DMA transfer method, DMA transfer apparatus, and program

Abstract

To suppress reduction of performance in data transfer of DMA transfer.SOLUTION: A DMA transfer apparatus 100 according to the present invention has an addition processing unit 101 for adding an entry representing DMA transfer instructions loaded on an instruction queue with additional information representing independence of the DMA transfer instructions corresponding to the entry from other DMA transfer instructions, and a transfer processing unit 102 for, when the DMA transfer corresponding to the DMA transfer instructions loaded on the instruction queue is successively carried out, carrying out the DMA transfer corresponding to the entry based on the additional information added to the entry, without waiting for completion of other DMA transfer instructions.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present disclosure relates to a DMA transfer method, a DMA transfer device, and a program. [Background technology]

[0002] Data transfer between memories and devices can be performed using DMA (Direct Memory Access) transfer, as disclosed in Patent Document 1. An example of DMA transfer will now be described with reference to FIGS.

[0003] First, Figure 1 shows one queue for DMA transfer. Because DMA transfer is a data transfer, it essentially involves reading from one location and writing to another. However, for the sake of convenience, a read from the PCI (Peripheral Component Interconnect) direction is defined as a read command, and a write to the PCI direction is defined as a write command. Note that the DMA in this disclosure is assumed to be implemented on a PCI card-type accelerator card found in general GPGPUs (General-purpose computing on graphics processing units). However, the scope of application of this disclosure is not limited to this and can be applied to general DMA transfers.

[0004] Figure 1 shows that DMA transfer requests are queued in the following order: (1) read instruction with SYNC, (2) write instruction, (3) write instruction with SYNC, (4) read instruction with SYNC, and (5) write instruction with SYNC. Note that instructions with SYNC require synchronization control, i.e., the completion of data transfer.

[0005] Figure 2 shows the execution of the transfer command in Figure 1. Because (1) is a read command with a SYNC, the write command (2) is made to wait. If this is the expected operation, i.e., if you want to wait for the preceding read command to complete before writing, there is no problem. However, there are cases where the read and write commands are not dependent on each other while being queued in the same command queue, and you do not want to wait for the SYNC. In such cases, performance degradation occurs when the writes (2) and (3) are made to wait. For example, in a situation where data transfer performance can be achieved in both directions on the PCI bus, the throughput becomes one-way, resulting in a performance degradation problem. Similarly, the read (4) waits for the preceding read (1), but there are also cases where you do not want to wait for the writes (2) and (3). This also results in a performance degradation problem. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-070259 Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, when performing DMA transfer, synchronization control such as a SYNC instruction may be necessary, but this can cause a problem of reduced data transfer performance.

[0008] Therefore, an object of the present disclosure is to solve the above-mentioned problem of degradation in data transfer performance in DMA transfer. [Means for solving the problem]

[0009] A DMA transfer method according to one embodiment of the present disclosure includes: Adding additional information to an entry representing a DMA transfer instruction stored in the instruction queue, which indicates that the DMA transfer instruction corresponding to the entry is independent of other DMA transfer instructions; When sequentially performing DMA transfers corresponding to the DMA transfer instructions stacked in the instruction queue, the DMA transfers corresponding to the entries are performed based on the additional information added to the entries without waiting for the completion of other DMA transfer instructions. The structure is as follows. Furthermore, a DMA transfer device according to an embodiment of the present disclosure includes: an additional processing unit that adds additional information to an entry representing a DMA transfer instruction stacked in the instruction queue, the additional information indicating that the DMA transfer instruction corresponding to the entry is independent of other DMA transfer instructions; a transfer processing unit that, when sequentially performing DMA transfers corresponding to the DMA transfer instructions stacked in the instruction queue, performs the DMA transfers corresponding to the entries based on the additional information added to the entries without waiting for the completion of other DMA transfer instructions; Equipped with The structure is as follows. Furthermore, a program according to an embodiment of the present disclosure includes: DMA transfer device, Adding additional information to an entry representing a DMA transfer instruction stored in the instruction queue, which indicates that the DMA transfer instruction corresponding to the entry is independent of other DMA transfer instructions; When sequentially performing DMA transfers corresponding to the DMA transfer instructions stacked in the instruction queue, the DMA transfers corresponding to the entries are performed based on the additional information added to the entries without waiting for the completion of other DMA transfer instructions. Execute the process, The structure is as follows. [Effects of the Invention]

[0010] With the above-described configuration, the present disclosure can suppress degradation in data transfer performance in DMA transfer. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram for explaining DMA transfer. [Figure 2]FIG. 1 is a diagram for explaining DMA transfer. [Figure 3] FIG. 1 is a diagram for explaining DMA transfer. [Figure 4] FIG. 2 is a diagram showing the state of data used in DMA transfer in the present disclosure. [Figure 5] 1 is a block diagram showing a configuration of a DMA transfer device according to the present disclosure. [Figure 6] FIG. 1 is a diagram illustrating a process according to the present disclosure. [Figure 7] FIG. 1 is a diagram illustrating a process according to the present disclosure. [Figure 8] FIG. 1 is a diagram illustrating a process according to the present disclosure. [Figure 9] FIG. 1 is a diagram illustrating a process according to the present disclosure. [Figure 10] FIG. 1 is a diagram illustrating a process according to the present disclosure. [Figure 11] FIG. 1 is a diagram illustrating a process according to the present disclosure. [Figure 12] 1 is a block diagram showing a configuration of a DMA transfer device according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] First Embodiment A first embodiment of the present disclosure will be described with reference to the drawings, which may be relevant to any embodiment.

[0013] [overview] First, an overview of the present disclosure will be described. As described above with reference to FIG. 2, when DMA transfer is performed while waiting for the completion of a SYNC instruction, performance in data transfer in both directions of the PCI may be degraded. In such cases, the present disclosure assumes that the PCI transfer status will be improved, for example, as shown in FIG. 3. Specifically, in the example of FIG. 3, the write instructions (2) and (3) can be started without waiting for the completion of the SYNC read instruction (1). Furthermore, the write instruction (5) can be started without waiting for the completion of the SYNC read instruction (4). This allows the PCI to achieve its throughput in both directions and demonstrate expected performance. Note that it is assumed that the fact that the instruction (4) is waiting for the completion of the SYNC read instruction (1) and the instruction (5) is waiting for the completion of the SYNC write instruction (3) are as expected.

[0014] Next, a further overview of the DMA transfer method disclosed herein will be provided. First, one DMA transfer method involves stacking entries, each specifying a transfer address and transfer volume, in a hardware queue and transferring them sequentially in the queue order. While transfers are typically simply performed in the order of entries, there are times during processing when the order of entries must be guaranteed (for example, when a flag must be written after data has been written). When multiple DMA engines are used, SYNC control is used to guarantee the order of entries. When SYNC control is required, subsequent entries must wait until the transfer of all entries prior to the entry for which SYNC is specified is complete before starting. However, if a transfer queue contains transfers that do not affect each other (transfers that do not need to wait for SYNC), the execution of this SYNC control will also halt the start of unrelated transfers. For example, in the case of PCI bidirectional control, SYNC control in one direction will halt transfer control in the opposite direction, resulting in a loss of the intended bidirectional bandwidth.

[0015] As a result of the above, in this invention, by using transfer group information known by software that does not affect each other and providing it as an identifier for the hardware, SYNC control that does not affect the transfer performance of other groups is realized, thereby achieving high-performance DMA transfer. In other words, as will be explained below, this invention achieves high-performance DMA transfer through cooperation between software and hardware.

[0016] Next, we will explain an example of the configuration and operation for achieving the above. First, a group field that can be specified by software is added to a DMA transfer entry. A specific example of an entry is shown in Figure 4. Figure 4 shows one entry for a DMA transfer stored in a descriptor queue. The entry contains the contents of a DMA transfer command and directs the DMA transfer. The entry contains the source address, destination address, transfer length, control bits, and other information. In this disclosure, a new "GRP" bit (group bit) (additional information) is added to the entry (bit 32 of Word 1). The software implemented as a DMA transfer device stores write and read commands in a descriptor queue. At this time, it can determine whether the read and write command sequences are independent. If they are independent, the read and write command sequences are grouped together. For example, a read command has a GRP bit of "0" and a write command has a GRP bit of "1." Then, the hardware that constitutes the DMA transfer device determines whether or not to wait for SYNC of the preceding DMA transfer in a DMA transfer based on the GRP bit in the entry, as will be described later.

[0017] 5 shows the configuration of the DMA transfer device in this embodiment. As will be described in detail later, this embodiment includes a register called Receive REG14 that stores entries, as well as another register called Overtake Receive REG15. By including the Overtake Receive REG15, it becomes possible to independently control each of the SYNC instructions whose GRP bits are (0,1), as will be described later. In other words, if the transfer following a SYNC instruction belongs to a different group than the preceding transfer, the subsequent transfer can begin without waiting for the preceding SYNC instruction to finish.

[0018] The effects of the present invention are shown in Figures 6 and 7. Note that Figure 7 shows a case where four DMA transfer engines are provided.

[0019] First, in Figure 6, a series of the same type of instructions is lined up, such as a read instruction sequence of four instructions, a write instruction sequence of three instructions, and a read instruction sequence of five instructions. When read instructions and write instructions are not lined up alternately like this, that is, when they are divided into read instruction groups and write instruction groups, the SYNC instruction is more likely to cause a performance degradation.

[0020] Figure 7 shows the execution of the present invention when applied to the command sequence shown in Figure 6. As shown in this figure, for example, the fourth, fifth, and sixth write commands can be executed without waiting for the preceding read command to complete, achieving the expected bidirectional PCI transfer performance.

[0021] [Example] Next, the configuration and operation of the present invention will be described in further detail using an embodiment. Figure 5 shows a DMA transfer device in this embodiment. In this embodiment, for example, an accelerator card such as the GPGPU described above is assumed, and a DMA transfer device (function) exists within the LSI of such an accelerator card. For example, the DMA transfer device is configured with electrical circuits, and includes an arithmetic circuit that performs arithmetic processing of data, an arithmetic unit with a program installed, and a storage device that stores data. Below, the configuration of DMA transfer device 1 will be described in order.

[0022] The control REG11 is a register that controls whether or not to execute a DMA transfer. When this register is instructed to execute, the transfer of the corresponding descriptor begins. There are, for example, eight control REG11s provided.

[0023] The descriptor 12 stores the actual transfer command. As an example, eight descriptors are provided. The descriptor 12 shown in the figure has 128 entries, each 32B (bytes). The contents of one 32B entry are in the format shown in FIG. 4, as described above, and indicate the specific transfer contents. The 128 entries store the command strings shown in FIG. 1 and FIG. 6.

[0024] The ReadPointer 13 indicates the read destination of the descriptor 12. Specifically, it indicates one of 128 entries, and the instruction is read from that entry, analyzed, and executed. As an example, eight ReadPointers 13 are provided.

[0025] The receiving REG14 is a register that receives and stores instructions read from the descriptor 12. The overtaking receiving REG15 is a register newly added in this invention. By having the overtaking receiving REG15, it becomes possible to control two SYNC waits, as will be described later. As an example, eight receiving REG14s and eight overtaking receiving REG15s are provided.

[0026] The arbiter 16 is an arbitration circuit. In this embodiment, it is assumed that there are multiple descriptors that enable instruction sequences, and the instructions arbitrated by the arbiter 16 are dispatched to the DMA engines 17 and 18.

[0027] The DMA engine consists of a read issuing function 17 and a write issuing function 18. A read and a write are paired to realize DMA transfer. There are four read issuing functions 17 and four write issuing functions 18.

[0028] Next, the operation of the above-mentioned DMA transfer device 1 will be described mainly with reference to the flowchart of FIG.

[0029] Step S1: When an execution instruction is given by the control REG 11, a DMA transfer instruction is taken out from the entry of the descriptor 12 pointed to by the ReadPointer 13.

[0030] Step S2: An entry is read from the descriptor 12, and the command corresponding to the entry is analyzed. In particular, here, it is determined whether the GRP bit (group bit) in the entry is "0" or "1." Note that the GRP bit is an independent command that is not affected by other SYNC commands when the software constituting the DMA transfer device 1 queues write commands and read commands in the descriptor, and "0" is added to the GRP bit if it is a read command, and "1" is added to the GRP bit if it is a write command. At this time, it is also determined whether the preceding receiving REG 14 and the overtaking receiving REG 15 are free. Then, based on this determination, the command corresponding to the read entry is allocated as follows: Group bit 0 & No preceding SYNC instruction in the receiving REG → Store in REG and update ReadPointer Group bit 0 & Receive REG has a preceding SYNC instruction → Do not update the ReadPointer and read the same entry next time. Group bit 1 & No preceding SYNC instruction in overtaking receiving REG → Store in overtaken REG, update ReadPointer Group bit 1 & Overtake receiving REG has a preceding SYNC instruction →The ReadPointer is not updated and the same entry is read next time.

[0031] Steps S3-1 / S3-2: Depending on the determination made in step S2, the command corresponding to the entry is stored in the receiving REG 14 or the overtaking receiving REG 15 as described above.

[0032] Steps S4-1 and S402: If the command in the receiving REG 14 or the overtaking receiving REG 15 has a SYNC, the receiving REG 14 or the overtaking receiving REG 15 is instructed to hold the command until the command is completed. Then, when the DMA engine reports the completion of the command with a SYNC, the command stored in the receiving REG 14 or the overtaking receiving REG 15 is released.

[0033] Step S5: The arbiter 16 arbitrates the instruction issue requests from the eight descriptors 12.

[0034] Step S6: The command arbitrated by the Arbiter 16 is dispatched to the DMA engine (Read issuing function 17 / Write issuing function 18).

[0035] Step S7: Execute the specified transfer. Specifically, read data from the source address for the specified transfer length and write that data to the destination address. When the transfer is complete, send a completion notification based on the transfer instruction.

[0036] In the above, steps S1 to S7 were explained focusing on the first entry (transfer command), but please note that in reality they operate continuously every clock cycle (each step operates simultaneously in a pipeline).

[0037] As described above, in this embodiment, the DMA transfer device 1 can specify additional information (group number) in the DMA transfer entry by software, and by performing SYNC control for each group based on that additional information, it is possible to improve the throughput of DMA transfer. In this case, in this embodiment, one queue can be logically treated as two queues, which improves queue utilization efficiency and achieves the above-mentioned functions with a small hardware configuration.

[0038] [Other Examples] Next, another embodiment of the present disclosure will be described. In the above embodiment, it has been explained that the performance degradation due to SYNC within the same descriptor can be suppressed. However, consider the case where READ / WRITE transfers are stacked in eight descriptors 12, as shown in Figure 9. In this case, since the descriptors are assigned to four DMA engines starting with the lowest number, it is possible that four DMA engines will be occupied in one direction. In such a case, there is room for further improvement in the throughput in both directions.

[0039] For this reason, the transfer directions of multiple instructions are aligned according to the value of the GRP bit (group bit) of the entry, and the instructions are assigned to four engines based on the transfer direction according to the value of the group bit. That is, by determining the transfer direction and dispatching instructions to the DMA engines according to that transfer direction, it is possible to eliminate imbalances in the DMA engines. In this case, the Arbiter 16 determines whether or not the dispatch imbalance occurs during arbitration. As a result, for example, the DMA transfer state shown in FIG. 10 can be changed to the DMA transfer state shown in FIG. 11. Specifically, in FIG. 11, different transfer directions are assigned to different DMA engines, allowing for uniform allocation to bidirectional transfers and improving overall transfer performance. As an example, two commands with different transfer directions, i.e., read commands and write commands, are assigned to each of the four engines, allowing the four engines to be used in both directions. As a result, as shown in FIG. 11, DMA transfers of multiple read and write commands with different transfer directions can be performed simultaneously, improving transfer performance.

[0040] <Second embodiment> Next, a second embodiment of the present disclosure will be described with reference to the drawings. This embodiment shows an outline of the configuration of the DMA transfer device described in the above embodiment. Note that FIG. 12 is a diagram for explaining the configuration, and this diagram may be relevant to any embodiment.

[0041] The DMA transfer device 100 shown in FIG. 12 is equipped with the following hardware configuration, as an example. ·CPU(Central Processing Unit) ROM (Read Only Memory) (storage device) RAM (Random Access Memory) (storage device) -Programs loaded into RAM -Storage device for storing programs Communication interface for connecting to external communication networks Input / output interface for data input / output Buses connecting each component

[0042] The DMA transfer device 100 can be equipped with the additional processing unit 101 and transfer processing unit 102 shown in Fig. 12 by having the CPU acquire and execute the programs. However, the additional processing unit 101 and transfer processing unit 102 may be constructed using dedicated electronic circuits for realizing such means.

[0043] The additional processing unit 101 adds additional information to an entry representing a DMA transfer instruction stored in the instruction queue, the additional information indicating that the DMA transfer instruction corresponding to the entry is independent of other DMA transfer instructions. When sequentially performing DMA transfers corresponding to the DMA transfer instructions stored in the instruction queue, the transfer processing unit 102 performs the DMA transfer corresponding to the entry based on the additional information added to the entry without waiting for the completion of other DMA transfer instructions.

[0044] With the above configuration, the present disclosure can execute a DMA transfer command that is independent of other DMA transfer commands without waiting for the other DMA transfer commands to complete, thereby achieving high-performance DMA transfers.

[0045] Although the present disclosure has been described above with reference to the above-described embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each of the above-described embodiments can be combined with other embodiments as appropriate.

[0046] <Additional Notes> Some or all of the above embodiments can also be described as follows: Below, we will explain the outline of the configuration of the DMA transfer method, DMA transfer device, and program according to the present disclosure. However, the present disclosure is not limited to the following configuration. (Appendix 1) Adding additional information to an entry representing a DMA transfer instruction stored in the instruction queue, which indicates that the DMA transfer instruction corresponding to the entry is independent of other DMA transfer instructions; When sequentially performing DMA transfers corresponding to the DMA transfer instructions stacked in the instruction queue, the DMA transfers corresponding to the entries are performed based on the additional information added to the entries without waiting for the completion of other DMA transfer instructions. DMA transfer method. (Appendix 2) 2. The DMA transfer method according to claim 1, adding the additional information corresponding to the transfer direction of the DMA transfer command to the entry; performing a DMA transfer corresponding to the entry according to the transfer direction in the additional information added to the entry without waiting for completion of a DMA transfer command of another transfer direction; DMA transfer method. (Appendix 3) 2. The DMA transfer method according to claim 1, adding the additional information indicating the type of the DMA transfer instruction, whether it is a read instruction or a write instruction, to the entry; performing a DMA transfer corresponding to the entry without waiting for completion of a different type of DMA transfer instruction, depending on whether the additional information added to the entry is the read instruction or the write instruction; DMA transfer method. (Appendix 4) 4. The DMA transfer method according to claim 3, storing the entry in a different register depending on whether the additional information added to the entry is the read instruction or the write instruction; arbitrating the entries stored in each of the registers and performing DMA transfer corresponding to the entries; DMA transfer method. (Appendix 5) 5. The DMA transfer method according to claim 4, performing a DMA transfer corresponding to the entry stored in another register without waiting for completion of a DMA transfer corresponding to the entry stored in a predetermined register; DMA transfer method. (Appendix 6) 5. The DMA transfer method according to claim 4, When the DMA transfer corresponding to the entry stored in the register is completed, the entry is released from the register. DMA transfer method. (Appendix 7) 3. The DMA transfer method according to claim 2, simultaneously performing DMA transfers corresponding to a plurality of DMA transfer instructions of different transfer directions according to the transfer directions in the additional information added to the entry; DMA transfer method. (Appendix 8) 2. The DMA transfer method according to claim 1, adding the additional information corresponding to the content of each DMA transfer instruction to a series of the entries representing a series of consecutive DMA transfer instructions that are independent of other DMA transfer instructions while the instructions are stacked in the instruction queue; performing DMA transfers corresponding to the series of entries based on the additional information added to each of the series of entries without waiting for completion of other DMA transfer instructions; DMA transfer method. (Appendix 9) an additional processing unit that adds additional information to an entry representing a DMA transfer instruction stacked in the instruction queue, the additional information indicating that the DMA transfer instruction corresponding to the entry is independent of other DMA transfer instructions; a transfer processing unit that, when sequentially performing DMA transfers corresponding to the DMA transfer instructions stacked in the instruction queue, performs the DMA transfers corresponding to the entries based on the additional information added to the entries without waiting for the completion of other DMA transfer instructions; A DMA transfer device equipped with (Appendix 10) DMA transfer device, Adding additional information to an entry representing a DMA transfer instruction stored in the instruction queue, which indicates that the DMA transfer instruction corresponding to the entry is independent of other DMA transfer instructions; When sequentially performing DMA transfers corresponding to the DMA transfer instructions stacked in the instruction queue, the DMA transfers corresponding to the entries are performed based on the additional information added to the entries without waiting for the completion of other DMA transfer instructions. A program that executes a process. [Explanation of symbols]

[0047] 1 DMA transfer device 11 Control REG 12 Descriptors 13 ReadPointer 14 Receiver REG 15 Overtaking REG 16 Arbiter 17 Read issuing function 18 Write issuing function 100 DMA Transfer Device 101 Additional processing unit 102 Transfer processing unit

Claims

1. adding additional information to an entry representing a DMA transfer command stored in the command queue, the additional information indicating that the DMA transfer command corresponding to the entry is independent of other DMA transfer commands; When sequentially performing DMA transfers corresponding to the DMA transfer commands stacked in the command queue, the DMA transfers corresponding to the entries are performed based on the additional information added to the entries without waiting for the completion of other DMA transfer commands. DMA transfer method.

2. 2. The DMA transfer method according to claim 1, adding the additional information corresponding to the transfer direction of the DMA transfer command to the entry; performing a DMA transfer corresponding to the entry according to the transfer direction in the additional information added to the entry, without waiting for the completion of a DMA transfer command for another transfer direction; DMA transfer method.

3. 2. The DMA transfer method according to claim 1, adding the additional information indicating the type of the DMA transfer command, whether it is a read command or a write command, to the entry; performing a DMA transfer corresponding to the entry without waiting for completion of a different type of DMA transfer command, depending on whether the additional information added to the entry is the read command or the write command; DMA transfer method.

4. 4. The DMA transfer method according to claim 3, storing the entry in a different register depending on whether the additional information added to the entry is the read instruction or the write instruction; arbitrating the entries stored in each of the registers and performing DMA transfer corresponding to the entries; DMA transfer method.

5. 5. The DMA transfer method according to claim 4, performing a DMA transfer corresponding to the entry stored in another register without waiting for completion of a DMA transfer corresponding to the entry stored in a predetermined register; DMA transfer method.

6. 5. The DMA transfer method according to claim 4, When the DMA transfer corresponding to the entry stored in the register is completed, the entry is released from the register. DMA transfer method.

7. 3. The DMA transfer method according to claim 2, simultaneously performing DMA transfers corresponding to a plurality of DMA transfer commands having different transfer directions according to the transfer directions in the additional information added to the entry; DMA transfer method.

8. 2. The DMA transfer method according to claim 1, adding the additional information corresponding to the content of each DMA transfer command to a series of the entries representing a series of consecutive DMA transfer commands that are independent of other DMA transfer commands while the commands are stacked in the command queue; performing DMA transfers corresponding to the series of entries based on the additional information added to each of the series of entries without waiting for completion of other DMA transfer commands; DMA transfer method.

9. an additional processing unit that adds additional information to an entry representing a DMA transfer command stored in the command queue, the additional information indicating that the DMA transfer command corresponding to the entry is independent of other DMA transfer commands; a transfer processing unit that, when sequentially performing DMA transfers corresponding to the DMA transfer commands stacked in the command queue, performs the DMA transfers corresponding to the entries based on the additional information added to the entries without waiting for the completion of other DMA transfer commands; A DMA transfer device comprising:

10. DMA transfer device, adding additional information to an entry representing a DMA transfer command stored in the command queue, the additional information indicating that the DMA transfer command corresponding to the entry is independent of other DMA transfer commands; When sequentially performing DMA transfers corresponding to the DMA transfer commands stacked in the command queue, the DMA transfers corresponding to the entries are performed based on the additional information added to the entries without waiting for the completion of other DMA transfer commands. A program that executes a process.

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