Silicon carbide device having trench and gate

Abstract

To provide a silicon carbide device having a trench gate.SOLUTION: A silicon carbide device (500) comprises a stripe-shaped trench-gate structure (150) extending from a first surface (101) in a silicon carbide body (100). A gate structure (150) has a gate length (L0) along a first direction (291) of a crosswise direction. A bottom face (158) of the gate structure (150), and a first gate side wall (151) in an active state are connected through a first bottom edge part (156) of the gate structure (150). The silicon carbide device (500) further includes at least one source region (110) of a first conductivity-type. A shield region (160) of a second conductivity type is in contact with the first bottom edge part (156) of the gate structure (150) over at least 20% of the gate length.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide devices, and more particularly to silicon carbide switches using transistor cells. [Background technology]

[0002] For example, in DC / AC converters, AC / AC converters, or AC / DC converters, or in electrical circuits driving inductive loads, such as motor driver circuits, electrical circuits for converting electrical energy may include power semiconductor devices as switches. Switching a heavy inductive load may trigger an LC oscillation. On the other hand, the breakdown field strength of silicon carbide (SiC) is high compared to silicon. SiC devices can be significantly thinner than comparable silicon devices for the same nominal blocking voltage capability, resulting in a significantly lower on-resistance for SiC devices. Summary of the Invention [Problem to be solved by the invention]

[0003] There is a need to expand the range of applications that can be achieved with silicon carbide devices. [Means for solving the problem]

[0004] One embodiment of the present disclosure relates to a silicon carbide device. The silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a first lateral direction. A bottom surface of the gate structure and a first gate sidewall are connected through a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type contacts the first bottom edge of the gate structure over at least 20% of the gate length.

[0005] The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of silicon carbide devices and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims. [Brief explanation of the drawings]

[0006] [Figure 1A] 1A-1C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device having a source region and a shield region, according to various embodiments. [Figure 1B] 1A-1C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device having a source region and a shield region, according to various embodiments. [Figure 1C] 1A and 1B show schematic vertical cross-sectional views of a portion of a silicon carbide device having a source region and a shield region, according to various embodiments. [Figure 1D] 1A and 1B show schematic vertical cross-sectional views of a portion of a silicon carbide device having a source region and a shield region, according to various embodiments. [Figure 2A] 1A-1C show schematic plan and side cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielded region including deep sub-sections arranged in rows and columns. [Figure 2B] 1A-1C show schematic plan and side cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielded region including deep sub-sections arranged in rows and columns. [Figure 2C] 1A-1C show schematic plan and side cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielded region including deep sub-sections arranged in rows and columns. [Figure 2D] 1A-1C show schematic plan and side cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielded region including deep sub-sections arranged in rows and columns. [Figure 3A]2A-2C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a stripe-shaped deep section. [Figure 3B] 2A-2C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a stripe-shaped deep section. [Figure 3C] 2A-2C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a stripe-shaped deep section. [Figure 3D] 2A-2C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a stripe-shaped deep section. [Figure 4A] 1A-1C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a lattice-shaped deep section. [Figure 4B] 1A-1C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a lattice-shaped deep section. [Figure 4C] 1A-1C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a lattice-shaped deep section. [Figure 4D] 1A-1C show schematic plan and vertical cross-sectional views of a portion of a silicon carbide device according to one embodiment having a shielding region including a lattice-shaped deep section. [Figure 5A] FIG. 10 shows a schematic perspective view of a portion of a silicon carbide device according to another embodiment having a shielding region including laterally separated deep subsections. [Figure 5B] FIG. 10 shows a schematic perspective view of a portion of a silicon carbide device according to another embodiment having a shielding region including laterally separated deep subsections. [Figure 6A] 1 shows a schematic cross-sectional top view of a portion of a silicon carbide device according to a further embodiment. [Figure 6B] 1 shows a schematic cross-sectional top view of a portion of a silicon carbide device according to a further embodiment. [Figure 6C] 1 shows a schematic cross-sectional top view of a portion of a silicon carbide device according to a further embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and which show, by way of illustration, specific embodiments in which silicon carbide devices may be implemented. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment can be used on or in conjunction with other embodiments to yield still further embodiments. The present disclosure includes such modifications and variations. Examples are described using specific language which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Unless otherwise noted, corresponding elements are designated by the same reference numerals in the various drawings.

[0008] Terms such as "having," "containing," "including," and "comprising" are not exclusive and indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a," "an," and "the" include the plural as well as the singular, unless the context clearly indicates otherwise.

[0009] The term "electrically connected" refers to a permanent, low-resistance connection between electrically connected elements, e.g., direct contact between the elements or a low-resistance connection via metal and / or heavily doped semiconductor material. The term "electrically coupled" includes that one or more intervening elements adapted for signal and / or power transmission may be connected between the electrically coupled elements, e.g., elements that are controllable to temporarily achieve a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. Ohmic contacts are non-rectifying electrical junctions that have a linear or nearly linear current / voltage characteristic.

[0010] In each diagram, the relative doping concentration is indicated by showing the doping type "n" or "p" next to a "-" or "+." For example, "n-" means a lower doping concentration than an "n" doped region, and an "n+" doped region is more doped than an "n" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions may have the same or different absolute doping concentrations.

[0011] Two adjacent doped regions of the same conductivity type but different dopant concentrations form a monopolar junction, e.g., an n / n+ or p / p+ junction, along the interface between the two doped regions. At the monopolar junction, the dopant concentration profile perpendicular to the monopolar junction may exhibit a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa.

[0012] Ranges given for physical dimensions are inclusive of the boundaries. For example, a range for a parameter y from a to b is interpreted as a≦y≦b. The same is true for ranges with a single boundary, such as "at most" and "at least."

[0013] The main components of a layer or structure made of a compound or alloy are the elements whose atoms form the compound or alloy, for example, nickel and silicon are the main components of a nickel silicide layer, and copper and aluminum are the main components of a copper aluminum alloy.

[0014] The term "above" should not be construed to mean "directly above." Rather, when one element is disposed "above" another element (e.g., a layer is "above" another layer or "above" a substrate), additional components (e.g., additional layers) may be disposed between the two elements (e.g., when a layer is "above" a substrate, another layer may be disposed between this layer and the substrate).

[0015] With respect to structures and doped regions formed in a silicon carbide body, a second region is "below" a first region if the smallest distance between the second region and a first surface on the front side of the silicon carbide body is greater than the largest distance between the first region and the first surface. A second region is "directly below" a first region when the perpendicular projections of the first and second regions onto the first surface overlap. This perpendicular projection is a projection orthogonal to the first surface.

[0016] Regions and / or structures may be laterally separated from one another within the same horizontal layer. Laterally separated regions and / or structures may also be vertically separated (i.e., located on different horizontal layers). In the latter case, the orthogonal projections of the separated regions and / or structures onto a horizontal projection plane are laterally separated. Regions and / or structures laterally overlap if their orthogonal projections onto a horizontal projection plane overlap laterally.

[0017] The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30V, e.g., 100V, 600V, 3.3kV or more, and having a nominal on-current or forward current of at least 1A, e.g., 10A or more.

[0018] According to one embodiment, a silicon carbide device may include a striped trench gate structure extending from the first surface into the silicon carbide body.

[0019] The silicon carbide body may have two substantially parallel major surfaces of the same shape and size, and an outer surface area connecting the edges of the two major surfaces. For example, the silicon carbide body may be a polygonal (e.g., rectangular or hexagonal) prism with or without rounded edges, or a cylinder. The silicon carbide body may have surface extensions along two horizontal directions and a thickness along a vertical direction perpendicular to the horizontal directions. This horizontal direction will hereinafter also be referred to as the lateral direction.

[0020] The silicon carbide body material may be, for example, 15R-SiC (15R-polytype silicon carbide) or a hexagonal polytype of silicon carbide, such as 2H-SiC, 4H-SiC, or 6H-SiC, for example. In addition to the primary components silicon and carbon, the silicon carbide body may also include dopant atoms, such as nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), and / or gallium (Ga). Additionally, the silicon carbide body may include unwanted impurities, such as hydrogen, fluorine, and / or oxygen.

[0021] A stripe-shaped trench gate structure may extend from a first surface on the front side of the silicon carbide body into the silicon carbide body. The gate structure has a gate length along a first lateral direction and a gate width along a second lateral direction orthogonal to the first direction. The gate structure may include a conductive gate electrode. The gate structure may further include a gate dielectric formed between the gate electrode and the silicon carbide body. The opposing first and second gate sidewalls may be vertical or slightly inclined relative to the vertical direction. The first and second gate sidewalls may be tapered or parallel.

[0022] Generally, at least the first gate sidewall may extend substantially along a crystal plane of the silicon carbide body having high charge carrier mobility (e.g., one of the {11-20} or {1-100} crystal planes). The first gate sidewall may be an active sidewall, i.e., the transistor channel may extend along the first gate sidewall. In some embodiments (e.g., in the case of parallel first and second gate sidewalls, such as in a vertical trench gate structure), this second gate sidewall may also be an active sidewall. In other embodiments (e.g., in the case of a tapered trench gate structure), this second gate sidewall may be an inactive sidewall. When viewed from the front side of the silicon carbide body, the first gate sidewall is on a first side of the gate structure, and the second gate sidewall is on an opposite second side of the gate structure.

[0023] A bottom surface at the lower end of the gate structure connects the first gate sidewall and the second gate sidewall via a first bottom edge and a second bottom edge. The bottom surface may include a horizontal portion. The first gate sidewall may include a straight section. The first bottom edge may connect the horizontal portion of the bottom surface with the straight section of the first gate sidewall. Accordingly, the second bottom edge may connect the horizontal portion of the bottom surface with the straight section of the second gate sidewall. The first bottom edge between the bottom surface and the first gate sidewall may be acute, rounded, and / or chamfered (e.g., at an obtuse angle). The second bottom edge between the bottom surface and the second gate sidewall may be acute, rounded, and / or chamfered (e.g., at an obtuse angle).

[0024] The silicon carbide device may further include at least one source region. The at least one source region may be a doped region of the first conductivity type. The source region may be in contact with the first gate sidewall of the gate structure, or may be in contact with the first gate sidewall of the further gate structure. That is, no source region may be formed along the first gate sidewall of the gate structure, or a single source region or multiple source regions may be formed along the first gate sidewall of the gate structure. If no source region is formed along the first gate sidewall of the gate structure, at least one source region may be formed along the further gate structure. Source regions formed along the same gate structure may be separated from each other along the first direction. The length of each source region along the first direction may be at least 500 nm, for example, at least 1 μm.

[0025] The silicon carbide device may further include a shielding region. The shielding region may be a doped region of a second conductivity type. The first conductivity type and the second conductivity type are complementary conductivity types. The first conductivity type may be n-type and the second conductivity type may be p-type. Alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0026] The shielding region contacts the first bottom edge over at least 20% of the gate length of the gate structure. For example, the shielding region may extend along the entire length of the gate structure. The shielding region may extend at least partially along the first gate sidewall. According to another example, the shielding region extends over at least 20% of the first gate sidewall. Along the first bottom edge, the shielding region may be absent for at least a vertical interval below the source region. When the shielding region contacts the first bottom edge, the shielding region may extend vertically along the first gate sidewall from the first surface to the first bottom edge.

[0027] According to another example, the shielding region may extend over at least 30% of the distance between adjacent source regions.

[0028] The shielding region may further contact the second gate sidewall, the second bottom edge, and / or the bottom surface of the gate structure. The shielding region may contact the second gate sidewall and the second bottom edge along the entire gate length of the gate structure. The shielding region may contact the fully shielded section of the bottom surface along the second bottom edge along the entire gate length of the gate structure. The shielding region may contact the partially shielded section of the bottom surface along the first bottom edge of each section between adjacent source regions.

[0029] With the shielding region in contact with a substantial section of the first bottom edge, a substantial portion of the gate structure may be completely embedded within the shielding region. The shielding region may shield the gate structure from potentials applied to the backside, e.g., the drain potential, such that an increased portion of the shielding region along the first gate sidewall reduces the gate-drain capacitance C GD The shielding region may be electrically connected to a front side potential, for example, the source potential. In this case, increasing the fraction of the shielding region relative to the source region reduces the gate-source capacitance C GS may increase. C GS increases, and C GD When r is reduced, the tendency to turn-off oscillation is significantly reduced.

[0030] Increasing the area of ​​the shielding region along the first surface may further increase the contact area between the shielding region and a front-side electrode formed on the first surface. The increased contact area may reduce the ohmic contact resistance between the front-side electrode and the shielding region. Furthermore, increasing the area of ​​the shielding region along the first surface may make it easier to form a reliable, low-resistance ohmic contact between the shielding region and the front-side electrode. As a result, the surge current robustness of a body diode formed with the shielding region in the drift structure may be significantly improved. The increased contact area and reduced ohmic resistance of the contact between the front-side electrode and the shielding portion may also contribute to reducing current overshoot during turn-on, reducing losses in the body diode, and / or reducing the tendency for oscillations during turn-off.

[0031] Shielding regions may be formed along the first gate sidewalls to reduce the area of ​​the source regions and, consequently, the overall width of the transistor channel. The reduced transistor channel width, along with improved shielding of the transistor channel from those portions of the shielding regions formed between each source region along the first direction, can contribute to reducing the saturation current of the transistor and, therefore, improving short-circuit robustness. Furthermore, the fully shielded portion of the bottom surface can be increased, effectively shielding the non-fully shielded portion of the bottom surface from all four sides. Both of these effects can further contribute to improving the reliability of the gate dielectric.

[0032] For high-voltage devices, e.g., devices with a voltage blocking capability of at least 600V, e.g., at least 3kV, the resistance of the voltage sustaining layer may dominate in on-state losses, potentially resulting in negligible, slightly increased transistor channel on-resistance. On the other hand, forming a shielding region along a substantial portion of the first gate sidewall may significantly smooth switching behavior, improve body diode characteristics, and / or enhance short-circuit robustness. In particular, high-voltage devices with a voltage blocking capability of at least 600V, e.g., at least 3kV, may benefit from a shielding region extending across a substantial portion of the first gate sidewall.

[0033] According to one embodiment, the shielding region may contact the first bottom edge over at least 30%, such as at least 50%, of the gate length. GD Further reduce C GS and / or the reliability of the device can be further improved.

[0034] According to one embodiment, the shielding region may comprise a top shielding portion and a deep shielding portion. The top shielding portion is disposed between the first surface and the deep shielding portion. The top shielding portion may be adjacent (e.g., directly adjacent) to the first surface. The vertical extension of the top shielding portion may be greater than the vertical extension of the gate structure. The top shielding portion may, for example, contact the first bottom edge at least in places.

[0035] The top shielding portion may contact the second bottom edge of the gate structure along the entire length of the gate structure, and the deep shielding portion may be formed in a layer of the silicon carbide body between the bottom edge of the gate structure and the second surface on the back side of the silicon carbide body.

[0036] The horizontal cross-sectional area of ​​the deep shielding portion may be the same as or substantially the same as the horizontal cross-section of the top shielding portion, and the same implant mask may be used to form the deep shielding portion and the top shielding portion. Alternatively, the horizontal cross-sectional area or the top and deep shielding portions may be significantly different. In the latter case, different implant masks may define the deep and top shielding portions.

[0037] The top and deep shielding portions may be directly connected to each other along the vertical direction, may overlap each other in the sense that one or more range edge peaks of the implant defining the deep shielding portion may be located within the top shielding portion, or may be contiguous along the vertical direction.

[0038] Deep shielding sections can improve the shielding effect on the transistor channel and on those portions of the gate dielectric that are not directly embedded in the shielding region. Improved shielding of the transistor channel may reduce drain-induced barrier lowering (DIBL).

[0039] This improved lateral shielding may facilitate sufficient shielding even for relatively short vertical extensions of the shielding regions, e.g., deep shielding portions. For example, improved lateral shielding may at least partially compensate for reduced vertical extensions of the deep shielding portions by eliminating implants with implant energies greater than 1.3 MeV. For example, the vertical distance between the bottom of the gate and the lower edge of the deep shielding portion may be reduced to at least 50 nm, e.g., at least 300 nm.

[0040] According to one embodiment, a first distance between the top shielding portion and the first gate sidewall may be less than a second distance between the deep shielding portion and the first gate sidewall. For example, a surface section of the top shielding portion may be directly adjacent to the source regions. The deep shielding portion may have a lateral distance relative to each source region along at least one lateral direction and / or may laterally overlap the source regions along at least one lateral direction.

[0041] According to one embodiment, the top shielding portion may include an isolation region. The isolation region may contact the first gate sidewall. The isolation region may extend downward from the first surface to the first bottom edge. The isolation region may laterally separate source regions formed along the first direction along the gate structure. In this case, the top shielding portion may shield each transistor channel from all four lateral sides.

[0042] According to one embodiment, the top shielding portion may include isolation sections. Each isolation section may be disposed between each source region. For example, the isolation sections may contact the first gate sidewall. Along the first surface, each isolation section and each source region may cover a continuous portion of the first gate sidewall of the gate structure along the first direction. Each isolation section and each source region may completely cover the first gate sidewall along the first surface.

[0043] Each isolation section and each source region may have the same width along the second direction. Along the first surface, each isolation section and each source region of the top shielding portion may be seamlessly complementary to one another in the first continuous area. The absence of additional doped regions along or near the first gate sidewall may facilitate the formation of the top shielding portion and the source region using a relatively simple photomask.

[0044] According to one embodiment, a silicon carbide device may comprise a first gate structure and an adjacent second gate structure. Each of the first gate structure and the second gate structure may be implemented as a gate structure described above. The first gate structure or the second gate structure may further correspond to a gate structure described above.

[0045] The top shield portion and source region assigned to the first gate structure may be disposed between a first gate sidewall of the first gate structure and a second gate sidewall of the second gate structure.

[0046] In particular, it is possible that a further doped region having the conductivity type of the source region and electrically connected to the voltage sustaining layer via an ohmic path is not adjacent to the first surface in the area between the first gate structure and the second gate structure.

[0047] At the first surface, the area between the first gate sidewall and the second gate sidewall may be filled with the top shielding portion and the source region. Specifically, the area between the first gate structure and the second gate structure may be completely filled with the exposed surfaces of the shielding portion and the source region.

[0048] That is, the top shielding portion and the source region may complement each other into a second continuous area along the first surface between the first gate sidewall of the first gate structure and the second gate sidewall of the second gate structure. The second continuous area includes the first continuous area and an additional stripe-shaped portion of the upper surface of the top shielding portion at the first surface. The absence of additional doped regions between adjacent gate structures may further facilitate formation of the top shielding portion and the source region.

[0049] According to one embodiment, the lateral dopant profile along the first direction through the transition between one of the isolation sections and one of the source regions may include a plateau section. This plateau section may represent that the openings in the implant mask for the source region implantation along the first direction can be narrower than the length of the mask columns in the implant mask for the top shielding portion implantation. The length of the plateau section corresponds to the difference between the extension of the mask columns for the top shielding portion implantation and the extension of the mask openings for the source region implantation along the first direction. The length of each plateau section may be at least 50 nm, 200 nm, or even 500 nm. For example, in the plateau section, the dopant concentration may vary by an order of magnitude or less over a distance of 50 nm, 200 nm, or even 500 nm. In the plateau section, the conductivity type may be the conductivity type of the isolation section, the conductivity type of the source region, or may be intrinsic. The plateau section may simplify the alignment of implant masks for forming the source regions and / or isolation sections.

[0050] According to one embodiment, a silicon carbide device may comprise a first gate structure and an adjacent second gate structure. The first gate structure and the second gate structure may be implemented as the gate structures described above. The first gate structure or the second gate structure may further correspond to the gate structures described above.

[0051] The deep shielding portion may include deep sections. Along the second direction, the deep sections may be laterally separated from the first gate sidewall of the first gate structure. Further, each deep section may laterally overlap with the second gate sidewall of the second gate structure.

[0052] For example, the silicon carbide device may include a plurality of gate structures. The deep shielding portion may include a plurality of deep sections separated from one another along at least a second direction. Along the second direction, each deep section may be laterally separated from a first gate sidewall of a first of two adjacent gate structures and may laterally overlap with a second gate sidewall of a second of the two adjacent gate structures.

[0053] According to one embodiment, the deep section may form a continuous stripe with a longitudinal axis parallel to the first direction, and may extend over at least 90% of the gate length, or over the entire gate length.

[0054] For example, a silicon carbide device may include multiple gate structures and multiple deep sections. The deep sections may be laterally separated along the second direction. The deep sections may form continuous stripes with longitudinal axes parallel to the first direction. For example, each deep section may extend across at least 90% of the gate length or across the entire gate length. Stripe-shaped deep sections may be successfully formed without fine-tuning a photomask along the first direction. Each stripe-shaped deep section may contribute to shielding transistor channels formed on opposite longitudinal sides of the stripe-shaped deep section.

[0055] According to another example, a deep section may include multiple deep subsections. The deep subsections may be separated laterally along a first direction. The deep subsections may be arranged in a matrix of rows and columns, with each row extending perpendicular to each column. Two of the deep subsections may be formed on either side of each source region along a second direction. In this manner, each transistor channel may be shielded by at least two deep subsections formed on either side of the deep subsections in the lateral direction.

[0056] When the source regions assigned to adjacent gate structures are offset from one another, for example, by half the center-to-center distance between the adjacent source regions, each transistor channel may be shielded by four deep subsections formed on four opposing sides. Deep subsections may not be present in regions where the shielding effect of the shielding regions is negligible or negligible. The deep subsections arranged in a matrix may maintain high lateral diffusion of on-current. The deep subsections arranged in a matrix may minimize any possible adverse effects of the deep subsections on other electrical characteristics of the silicon carbide device, such as on-resistance.

[0057] According to another embodiment, the horizontal cross-section of the deep shielding portion may comprise a grid with grid openings. Each grid opening may laterally surround at least a portion of one source region. For example, each grid opening may laterally surround one complete source region. According to another example, each grid opening may surround a channel sidewall section. For example, the horizontal cross-section of the deep shielding portion may be more or less identical to the horizontal cross-section of the top shielding portion below the multiple gate trenches and may be formed using the same implant mask. The grid-shaped deep shielding portion may facilitate high shielding effectiveness.

[0058] According to another embodiment, a silicon carbide device may comprise a first gate structure and an adjacent second gate structure. The first gate structure and the second gate structure may be implemented as the gate structures described above. The first gate structure or the second gate structure may also correspond to the gate structures described above.

[0059] The shielding region may contact the first bottom edge of the first gate structure over the gate length thereof, which may eliminate the need for alignment of the shielding region along the first direction, thereby making the manufacturing process more efficient.

[0060] According to one embodiment, the source region may extend along the gate length of the second gate structure, which may eliminate the need for alignment of the source region along the first direction, thus making the manufacturing process more efficient.

[0061] According to another embodiment, a silicon carbide device may include a body region of a second conductivity type and a current spreading region of a first conductivity type. The body region and the current spreading region may be formed in a silicon carbide body. The body region may separate the source region and the current spreading region.

[0062] In the on-state of a silicon carbide device, a transistor channel may be formed in the body region. This transistor channel may be an inversion layer formed along the gate structure. This inversion layer promotes the flow of unipolar charge carriers between the source region and the current spreading region in the on-state.

[0063] According to another embodiment, the silicon carbide device may comprise a drift structure between the gate structure and the second surface of the silicon carbide body. The drift structure may comprise a voltage sustaining structure. The voltage sustaining structure may include a lightly doped drift region having a vertical extension of at least 4 μm, 12 μm, 20 μm, or even at least 100 μm. The minimum vertical extension may depend on the desired blocking capability of the silicon carbide device. For example, at a desired blocking capability of 650 V (or 1.2 kV, or 1.7 V, or 3.3 kV, or 6.5 kV), the vertical extension of the drift region may be at least 4 μm (or at least 8 μm, or at least 12 μm, or at least 20 μm, or at least 40 μm, respectively). Alternatively, or in addition, the voltage sustaining structure may comprise a compensation structure, such as a superjunction structure.

[0064] The shielding region and the drift structure can form a p-n junction. The p-n junction can be effective as, or as part of, a body diode, which is in forward conduction mode when the silicon carbide device is reverse biased. A large contact area at the shielding region along the first surface can facilitate a low ohmic contact between the shielding region and the front electrode, improving the electrical characteristics of the body diode.

[0065] 1A-1D show a portion of a silicon carbide device 500 having a silicon carbide body 100. The silicon carbide device 500 may be or include, by way of example, an IGFET (insulated gate field effect transistor), such as a MOSFET (metal oxide semiconductor FET), or an MCD (MOS controlled diode), or an IGBT (insulated gate bipolar transistor).

[0066] Silicon carbide body 100 may comprise or consist of single crystal silicon carbide, e.g., a silicon carbide crystal containing primarily silicon and carbon. The silicon carbide crystal may include unwanted impurities such as hydrogen and / or oxygen, and / or intended impurities, e.g., dopant atoms. The polytype of the silicon carbide crystal may be 15R or may be hexagonal, e.g., 2H, 6H, or 4H. Silicon carbide body 100 may comprise or consist of a silicon carbide layer grown by epitaxy.

[0067] The first surface 101 on the front side of the silicon carbide body 100 may be planar or ribbed. The mean plane of the first surface 101 extends along the horizontal direction. The mean plane of the planar first surface 101 is the same as the planar first surface 101. In the case of a non-planar first surface 101, for example, a ribbed first surface 101, the mean plane may be a planar least-squares plane. The position and orientation of the planar least-squares plane are determined so that the sum of the squares of the deviations of each surface point of the ribbed first surface 101 from the planar least-squares plane has a minimum value. The vertical direction 104 is orthogonal to the horizontal direction, for example, parallel to the surface normal to the mean plane. This horizontal direction is also referred to as the lateral direction hereinafter.

[0068] The normal direction 104 may be aligned with the primary lattice direction or may be tilted at an off-axis angle relative to the primary lattice direction, which may be in the range of 2° to 8°, and specifically may be 4°. On the back side of the silicon carbide body 100, a second surface may extend parallel to the flat first surface 101 or parallel to a least-squares plane of the ribbed first surface 101.

[0069] The transistor cells TC are formed on the front side of the silicon carbide body 100. A drift structure 130 extends laterally through the silicon carbide body 100 between the transistor cells TC and the second surface. The drift structure 130 may comprise a voltage sustaining structure, such as a lightly doped drift region, and / or a compensation structure, such as a superjunction structure.

[0070] Each transistor cell TC includes a source region 110 of a first conductivity type and a body region 120 of a second conductivity type. The body region 120 and the drift structure 130 form a first pn junction pn1. The body region 120 and the source region 110 form a second pn junction pn2. The vertical extension of the body region 120 corresponds to the channel length of the transistor cell TC and may be in the range of 0.2 μm to 1.5 μm.

[0071] The stripe-shaped trench gate structures 150 extend along a lateral first direction 291. At least one gate structure 150 contacts the source region 110 and the body region 120 of the transistor cell TC. The gate structure 150 includes a conductive gate electrode 155, which may include or consist of a heavily doped polycrystalline silicon layer and / or a metal-containing layer. A gate dielectric 159 separates the gate electrode 155 from the silicon carbide body 100 along at least one side of the gate structure 150. The gate dielectric 159 may include or consist of thermally grown or deposited silicon oxide, silicon nitride, silicon oxynitride, another deposited dielectric material, or any combination thereof. The thickness of the gate dielectric 159 may be selected to obtain a transistor cell TC having a threshold voltage in the range of 1.0 V to 8 V. The gate structure 150 may comprise only the gate electrode 155 and the gate dielectric 159, or may comprise, in addition to the gate electrode 155 and the gate dielectric 159, further conductive and / or dielectric structures.

[0072] The gate structures 150 may be equally spaced and / or have a uniform gate width w0. The center-to-center distance between adjacent gate structures 150 may be in the range of 0.5 μm to 10 μm, for example, 1 μm to 5 μm. The gate length L0 of the gate structures 150 may be up to several millimeters. The vertical gate extension v0 of the gate structures 150 may be in the range of 0.3 μm to 5 μm, for example, 0.5 μm to 2 μm.

[0073] The opposing first and second gate sidewalls 151, 152 of each gate structure 150 may extend substantially along the vertical direction 104 or may be inclined at an inclination angle relative to the vertical direction 104. In the latter case, the gate structure 150 may have parallel first and second gate sidewalls 151, 152, or the gate structure 150 may taper with increasing distance from the first surface 101. The inclination angle between the gate sidewalls 151, 152 and the vertical direction 104 may be selected according to the alignment of the crystal axes and / or according to the off-axis angle.

[0074] For example, the absolute value of the tilt angle between the first gate sidewall 151 and the vertical direction 104 may differ from the absolute value of the off-axis angle by ±1° or less (e.g., for 4H—SiC, the tilt angle may range from at least 3° to at most 5°). However, the tilt angle may have an orientation different from the off-axis angle. The tilt angle between the second gate sidewall 152 opposite the first gate sidewall 151 and the vertical direction 104 may be oriented in the same direction as the tilt angle of the first gate sidewall 151 or in the opposite direction. As the tilt angle increases, the tapered gate structure 150 narrows from the first surface 101.

[0075] Generally, at least the first gate sidewall 151 may extend substantially along a crystal plane of the silicon carbide body 100 that has high charge carrier mobility (e.g., one of the {11-20} or {1-100} crystal planes). The first gate sidewall 151 may be an active sidewall, i.e., the transistor channel may extend along the first gate sidewall 151. In some embodiments (e.g., for a vertical trench gate structure 150), the second gate sidewall 152 may also be an active sidewall. In other embodiments (e.g., for a tapered trench gate structure 150), this second gate sidewall 152 may be an inactive sidewall.

[0076] A bottom surface 158 at the lower end of each gate structure 150 connects the first gate sidewall 151 and the second gate sidewall 152, or forms at least a portion of the connection between the first gate sidewall 151 and the second gate sidewall 152. This bottom surface 158 may include a horizontal portion. The bottom surface 158 and the first gate sidewall 151 of each gate structure 150 may be connected via a first bottom edge 156. The bottom surface 158 and the second gate sidewall 152 of each gate structure 150 may be connected via a second bottom edge 157. The first bottom edge 156 may be acute, rounded, and / or chamfered. The second bottom edge 157 may be acute, rounded, and / or chamfered.

[0077] 1A, a plurality of isolated (voneinander separierten in German) source regions 110 are formed in a portion of the silicon carbide body 100 between two adjacent gate structures 150. A lateral length L1 of the source regions 110 along a first direction 291 may be at least 500 nm, for example at least 1 μm.

[0078] The isolation sections 161 of the shielding regions 160 may laterally separate adjacent source regions 110 at the first surface 101 along the first direction 291. A lateral width w2 of the isolation sections 161 and a lateral width w1 of the source regions 110 may be equal. The isolation sections 161 and the source regions 110 formed between two identical gate structures 150 may complement each other into a first continuous area 410 in the plane of the first surface 101. The first continuous area 410 does not include any gaps.

[0079] 1B shows a single source region 110 formed between two adjacent gate structures 150. This source region 110 may extend uninterrupted along the entire gate length L0, i.e., the source region 110 may extend from one longitudinal end of the gate structure 150 to the opposite longitudinal end. Along another gate structure 150 without a source region 110, a shielding region 160 may extend uninterrupted along the entire gate length L0.

[0080] The shielding region 160 may extend along one or more further gate structures 150 from one longitudinal end of the gate structure 150 to the opposite longitudinal end.

[0081] A channel sidewall section 153 of the first gate sidewall 151 extends downward from the source region 110 to a first bottom edge 156 .

[0082] 1C and 1D , the shielding region 160 extends from the first surface 101 into the silicon carbide body 100. The shielding region 160 may be in direct contact with the inactive second gate sidewall 152 over the gate length L and over the vertical gate extension v. Along the second gate sidewall 152, the shielding region 160 extends from the first surface 101 to below the gate structure 150. The first vertical extension v of the shielding region 160 is greater than the vertical gate extension v. For example, the vertical distance v between the bottom gate surface 158 and the lower edge of the shielding region 160 may be at least 50 nm, e.g., at least 300 nm.

[0083] The shielding region 160 includes a section between the body region 120 and the inactive second gate sidewall 152. The body region 120 and the shielding region 160 may form a unipolar junction. The shielding region 160 may include an isolation section 161 separating adjacent source regions 110 along the first direction 291. The isolation section 161 is in direct contact with the first gate sidewall 151 outside the channel sidewall section 153.

[0084] The maximum dopant concentration in the shielding region 160 may be higher than the maximum dopant concentration in the body region 120. The vertical dopant concentration profile in the shielding region 160 may have a maximum below the gate structure 150. Along the second gate sidewall 152, the dopant concentration in the shielding region 160 may be relatively high, i.e., at least 10 times higher than the dopant concentration in the body region 120 along the first gate sidewall 151.

[0085] 2A-2D, the shielding region 160 comprises a top shielding portion 168 and a deep shielding portion 169. The deep shielding portion 169 and the top shielding portion 168 are connected to each other along the vertical direction 104.

[0086] The vertical extension v2 of the top shielding portion 168 is greater than the vertical gate extension v0. The deep shielding portion 169 includes a plurality of deep subsections 164 arranged along parallel columns and parallel rows, with each row extending perpendicular to each column. Along a horizontal second direction 292, each deep subsection 164 is formed between two adjacent source regions 110. The deep subsections 164 may be laterally separated from the source regions 110. Along a horizontal first direction 291, adjacent deep subsections 164 in the same row are laterally separated. The horizontal length of the deep subsections 164 along the first direction 291 may be equal to, shorter than, or longer than the length of the source regions 110 along the first direction 291.

[0087] For example, as shown, top shielding portion 168 may provide some improvement in lateral shielding of the gate dielectric and transistor channel, allowing deep subsection 164 to be extended symmetrically along first direction 291 relative to each edge of source region 110. In this case, the horizontal length of deep subsection 164 is less than the length of source region 110.

[0088] A first distance d 1 between the top shielding portion and the first gate sidewall 151 may be less than a second distance d 2 between the deep shielding portion 169 and the first gate sidewall 151 .

[0089] The drift structure 130 may include a drift region 131 of a first conductivity type. The drift region 131 forms a voltage sustaining structure, in which the vertical extension and dopant concentration within the drift region 131 may be selected to enable the silicon carbide device 500 to achieve a nominal blocking voltage capability in the off-state of the silicon carbide device 500. The drift region 131 may be formed in a layer grown by epitaxy. The average net dopant concentration in the drift region 131 may be, for example, 1E15 cm -3 ~5E16cm -3 According to another example, the drift structure 130 may include a compensation structure, such as a superjunction structure.

[0090] A heavily doped contact 139 may be formed between the drift structure 130 and a backside electrode directly adjacent the second surface 102 of the silicon carbide body 100. The heavily doped contact 139 and the backside electrode form a low resistance ohmic contact. The contact 139 may have the same conductivity type as the drift region 131, the opposite conductivity type, or may include regions of both conductivity types.

[0091] The drift structure 130 may include a current spreading region 137. This current spreading region 137 may be formed between the body region 120 and a voltage-sustaining structure, such as the drift region 131. The current spreading region 137 may be in contact with the body region 120. The current spreading region 137 may laterally separate adjacent deep subsections 164. Portions of the current spreading region 137 may be formed directly beneath deep shielding portions 169. The current spreading region 137 may have a higher average dopant concentration than the drift region 131, which may facilitate relatively better lateral spreading of the on-current.

[0092] The implantation mask defining the deep subsection 164 and / or the source region 110 may have rounded openings, e.g., elliptical or circular openings. Accordingly, the horizontal cross-sectional areas of the deep subsection 164 and / or the source region 110 may include circular segments, elliptical segments, circular and / or elliptical shapes. The implantation mask defining the top shielding portion 168 may include rounded pillars, e.g., elliptical or circular pillars. Accordingly, the horizontal cross-sectional areas of the openings in the top shielding portion 168 may be circular segments, elliptical segments, circular and / or elliptical shapes.

[0093] A first loading electrode 310 on the front side of the silicon carbide body 100 is electrically connected to the source region 110, the body region 120, and the shield region 160. A gate electrode 155 may be electrically connected to gate metallization on the front side of the silicon carbide body 100. This gate metallization forms or is electrically connected or coupled to the gate terminal.

[0094] Portions of the interlayer insulating film 210 separate the first loading electrode 310 and the gate electrode 155 in the gate structure 150. The first loading electrode 310 may form or be electrically connected or coupled to a first loading terminal, which may be the anode terminal of an MCD or the source terminal of a MOSFET.

[0095] The second loading electrode 320 forms a low resistance ohmic contact with the contact portion 139. The second loading electrode 320 may form or be electrically connected or coupled to a second loading terminal, which may be the cathode terminal of an MCD or the drain terminal of a MOSFET.

[0096] The illustrated silicon carbide device 500 is an n-channel SiC TMOSFET, with a first charging electrode 310 forming or electrically connected or coupled to a source terminal S and a second charging electrode 320 forming or electrically connected or coupled to a drain terminal D. The silicon carbide device 500 comprises a plurality of transistor cells TC and a plurality of gate structures 150. The transistor cells TC may be electrically connected in parallel.

[0097] 3A-3D, the deep sections 163 of the deep shielding portions 169 form continuous stripes with their longitudinal axes parallel to the horizontal first direction 291. In FIG.

[0098] 4A-4D, the horizontal cross-sectional area of ​​the deep shielding portion 169 forms a grid with grid openings 167. Each grid opening 167 is formed around a source region 110.

[0099] 5A-5B show perspective views of a silicon carbide device 500 having a source region 110 formed along a channel sidewall section 153 of a first gate sidewall 151. A deep shielding portion 169 includes a dot-shaped deep subsection 164. A shielding region 160 includes a heavily doped contact section 162 formed along the first surface 101.

[0100] 6A and 6B show a silicon carbide device 500 having a plurality of gate structures 150. A plurality of source regions 110 are formed along first gate sidewalls 151 of the gate structures 150. Along the first surface 101, the top shielding portion 168 of the shielding region and the source regions 110 complement each other in a second continuous area 400 between two adjacent gate structures 150.

[0101] 6A, the source regions 110 are arranged in a matrix of columns and rows, with each row extending perpendicular to each column, i.e., the source regions 110 are formed in the black and white portions of the checkerboard.

[0102] 6B, the source regions 110 of adjacent gate structures 150 are offset from one another along the first direction 291 by half the center-to-center distance between adjacent source regions 110. That is, source regions 110 may be formed only in the "white" portions of the checkerboard.

[0103] 6C , each source region 110 extends along the entire gate length of the first-type gate structure 150 and is completely absent along the first gate sidewall 151 of the second-type gate structure 150. The first-type gate structures 150 and the second-type gate structures 150 may form a regular pattern. For example, one, two, three, or more gate structures 150 of the first type (in contact with the source regions 110) may be formed between each pair of second-type gate structures 150 (not in contact with the source regions 110).

[0104] For purposes of illustration, various situations have been described with respect to silicon carbide devices, although similar techniques may be implemented in semiconductor devices based on other kinds and types of compound semiconductor materials for the semiconductor body, such as gallium nitride (GaN) or gallium arsenide (GaAs).

[0105] For illustrative purposes, various situations have been described with respect to silicon carbide devices that do not incorporate a Schottky diode. Some embodiments may incorporate a Schottky contact between a front electrode of a first conductivity type and a diode region. The diode region may extend from the first surface to the drift structure and between adjacent gate structures. Alternatively, or in addition, each isolation section may laterally separate the Schottky contact from the source region. For example, a p-doped isolation section may laterally separate an n-doped diode region from an n-doped source region. [Explanation of symbols]

[0106] 100 Silicon carbide body 101 First Surface 102 Second Surface 104 Vertical 110 Source Region 120 Body Region 130 Drift Structure 131 Drift Region 137 Current Diffusion Region 139 Contact part 150 Gate Structure 151 First Gate Sidewall 152 Second Gate Sidewall 153 Channel sidewall section 155 gate electrode 156 first bottom edge 157 Second bottom edge 158 bottom 159 Gate Dielectric 160 Covered area 161 Separation Section 162 Highly doped contact area 163 Deep Section 164 Deep Subsection 167 Lattice opening 168 Top shield part 169 Deep shielding part 210 Interlayer insulating film 291 First Direction 292 Second Direction 310 first loading electrode 320 second loading electrode 400 Second continuous area 410 First continuous area 500 Silicon Carbide Devices

Claims

1. a stripe-shaped trench gate structure (150) extending from a first surface (101) into the silicon carbide body (100), the gate structure (150) having a gate length (L0) along a lateral first direction (291), the bottom surface (158) of the gate structure (150) and a first gate sidewall (151) being connected via a first bottom edge (156) of the gate structure (150); at least one source region (110) of a first conductivity type; a shielding region (160) of second conductivity type contacting the first bottom edge (156) of the gate structure (150) over at least 20% of the gate length (L0); A silicon carbide device (500) comprising:

2. The silicon carbide device of claim 1, wherein the shielding region (160) contacts the first bottom edge (156) over at least 30% of the gate length (L0).

3. 3. The silicon carbide device of claim 1, wherein the shielding region (160) comprises a top shielding portion (168) and a deep shielding portion (169), the top shielding portion (168) being between the first surface (101) and the deep shielding portion (169), and the top shielding portion (168) being in contact with the first bottom edge (156).

4. 4. The silicon carbide device of claim 3, wherein a first distance (d1) between the top shielding portion (168) and the first gate sidewall (151) is less than a second distance (d2) between the deep shielding portion (169) and the first gate sidewall (151).

5. the top shielding portion (168) includes a separation section (161); the separation section (161) is in contact with the first gate sidewall (151); 5. The silicon carbide device of claim 3 or 4, wherein each isolation section (161) laterally separates source regions (110) formed along the first direction (291).

6. the top shielding portion (168) includes an isolation section (161) disposed between the source regions (110); 6. The silicon carbide device of claim 3, wherein along the first surface (101), the isolation zone (161) and the source region (110) cover a continuous portion of the first gate sidewall (151) of the gate structure (150).

7. the silicon carbide device comprises a first gate structure (150) and an adjacent second gate structure (150); the top shielding portion (168) and the source region (110) of the first gate structure (150) are disposed between the first gate sidewall (151) of the first gate structure (150) and the second gate sidewall (152) of the second gate structure (150); 7. The silicon carbide device of claim 3, wherein an area on the first surface (101) between the first gate sidewall (151) and the second gate sidewall (152) is filled with the top shielding portion (168) and the source region (110).

8. 8. The silicon carbide device of claim 3, wherein a lateral dopant profile along the first direction (291) through a transition between one of the isolation regions (161) and one of the source regions (110) includes a plateau region.

9. the silicon carbide device comprises a first gate structure (150) and an adjacent second gate structure (150); the deep shielding portion (169) comprises a deep section (163); along a second direction (292), the deep section (163) is laterally separated from the first gate sidewall (151) of the first gate structure (150); The silicon carbide device of any one of claims 3 to 8, wherein the deep section (163) laterally overlaps a second gate sidewall (152) of the second gate structure (150).

10. The silicon carbide device of claim 9, wherein the deep sections (163) form continuous stripes having longitudinal axes parallel to the first direction (291).

11. the deep section (163) comprises a plurality of deep subsections (164); The silicon carbide device of claim 9, wherein the deep subsections (164) are separated laterally along the first direction (291).

12. a horizontal cross section of the deep shielding portion (169) comprising a grid having grid openings (167); The silicon carbide device of any one of claims 3 to 8, wherein each grid opening (167) surrounds at least a portion of one of the source regions (110).

13. the silicon carbide device comprises a first gate structure (150) and an adjacent second gate structure (150); The silicon carbide device of any one of claims 1 to 8, wherein the shielding region (160) contacts the first bottom edge (156) of the first gate structure (150) over the gate length (L0).

14. The silicon carbide device of claim 13, wherein the source region (110) extends along the gate length (L0) of the second gate structure (150).

15. 15. The silicon carbide device of claim 1, wherein the silicon carbide body (100) comprises a body region (120) of the second conductivity type and a current spreading region (137) of the first conductivity type, the body region (120) separating the source region (110) and the current spreading region (137).

16. 16. The silicon carbide device of claim 1, wherein the silicon carbide body comprises a drift structure between the gate structure and the second surface of the silicon carbide body, the shielding region and the drift structure forming a pn junction.

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