Electronic circuit and test method for electronic circuit

Abstract

To provide an electronic circuit which performs high-quality data error detection based on CRC codes by detecting an error of a CRC circuit per se.SOLUTION: An electronic circuit comprises: a CRC arithmetic circuit which executes CRC arithmetic to input data; an error detection section which detects the presence / absence of error in output of the CRC arithmetic circuit; a data holding section which holds test data for a test of the CRC arithmetic circuit, initial value data for setting an initial value of the CRC arithmetic circuit to a plurality of shift registers, and expectation value data for setting an expectation value of output of the CRC arithmetic circuit to the error detection section; and a test control section which sets the initial value data to the plurality of shift registers and inputs the test data to the CRC arithmetic circuit when testing the CRC arithmetic circuit. The data holding section holds a plurality of sets of test data, initial value data and expectation value data.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to electronic circuits and methods for testing electronic circuits. [Background technology]

[0002] In communication paths, error detection circuits using CRC codes are commonly used to ensure the validity of data. However, error detection using CRC (Cyclic Redundancy Check) alone cannot distinguish between a problem on the communication path and a malfunction within the communication system (data generation circuit or CRC circuit). Even if there is a malfunction in the CRC circuit, it may be detected as an error even though accurate data is being transmitted. Furthermore, assuming a sudden error due to noise on the communication path, etc., data may be repeatedly resent between the sender and receiver, making it difficult to quickly determine whether a system abnormality exists.

[0003] Patent Document 1 discloses technology relating to an in-device monitoring system, particularly an in-device monitoring system with a self-diagnosis function used in digital multiplexing terminal equipment, etc. In general, in-device monitoring systems, a monitoring pattern signal is inserted on the transmitting side, and errors are detected on the receiving side via the transmission path, but the invention disclosed in Patent Document 1 has two monitoring pattern generation circuits installed in the transmitting device, and errors are detected by two error detection circuits in the receiving device, and the monitoring systems are arranged in parallel to prevent erroneous detection and improve the accuracy and reliability of the detection output. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 5-30071 Summary of the Invention [Problem to be solved by the invention]

[0005] However, with conventional technology, it took a long time to determine whether an error had occurred due to a malfunction of the CRC circuit inside the communication system.

[0006] The present disclosure has been made in consideration of the above points, and aims to provide an electronic circuit and a method for testing an electronic circuit that detects errors in the CRC circuit itself and performs data error detection using a high-quality CRC code. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, there is provided an electronic circuit comprising: a CRC calculation circuit consisting of a plurality of shift registers and performing a CRC calculation on input data; an error detection unit which detects the presence or absence of an error in the output of the CRC calculation circuit; a data holding unit which holds test data for testing the CRC calculation circuit, initial value data for setting initial values ​​of the CRC calculation circuit in the plurality of shift registers, and expected value data for setting an expected value of the output of the CRC calculation circuit in the error detection unit; and a test control unit which sets the initial value data in the plurality of shift registers when testing the CRC calculation circuit, and inputs the test data to the CRC calculation circuit, wherein the data holding unit holds a plurality of sets of the test data, the initial value data, and the expected value data.

[0008] The electronic circuit may include a plurality of the CRC calculation circuits and the error detection units.

[0009] According to another aspect of the present disclosure, there is provided a method for testing an electronic circuit comprising: a CRC calculation circuit consisting of a plurality of shift registers and performing a CRC calculation on input data; an error detection unit which detects the presence or absence of an error in the output of the CRC calculation circuit; a data holding unit which holds test data for testing the CRC calculation circuit, initial value data for setting initial values ​​of the CRC calculation circuit in the plurality of shift registers, and expected value data for setting an expected value of the output of the CRC calculation circuit in the error detection unit; and a test control unit which sets the initial values ​​in the plurality of shift registers and inputs the test data to the CRC calculation circuit when testing the CRC calculation circuit, wherein the data holding unit holds a plurality of sets of the test data, the initial value data, and the expected value data, the method including the steps of setting the initial values ​​in the plurality of shift registers, setting the expected value in the error detection unit, inputting the test data to the CRC calculation circuit, and outputting an error signal from the error detection unit when the output of the CRC calculation circuit does not match the expected value.

[0010] In the above-described method for testing an electronic circuit, the electronic circuit may include a plurality of the CRC calculation circuits and the error detection unit, and the step of inputting the test data to the CRC calculation circuits may include a step of inputting the test data to the CRC calculation circuits while any one of the CRC calculation circuits is performing a CRC calculation on data transmitted from outside. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to provide an electronic circuit and a test method for an electronic circuit that detects errors in the CRC circuit itself and performs data error detection using a high-quality CRC code. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a conventional transmission / reception system. [Figure 2] 10A and 10B are diagrams illustrating data processed by an I / F circuit and an error signal when an error occurs. [Figure 3] FIG. 2 is a diagram illustrating a data format of transmission data transmitted by the transmission system. [Figure 4] 2 is a diagram illustrating a method for testing a CRC calculation circuit using the receiving system shown in FIG. 1. FIG. [Figure 5] 1 is a diagram illustrating an example of the configuration of a transmission / reception system according to a first embodiment. [Figure 6] 10A and 10B are diagrams illustrating examples of test input data, shift register initial values, and expected values ​​stored in a test table. [Figure 7] 6 is a diagram for explaining a method of testing a CRC calculation circuit in the receiving system shown in FIG. 5. [Figure 8] 8 is a diagram illustrating steps 7 and 8 of the test method for the CRC calculation circuit in the receiving system shown in FIG. 7. [Figure 9] FIG. 1 is a diagram illustrating an example of the configuration of a conventional transmission / reception system. [Figure 10] 10A and 10B are diagrams illustrating data processed by an I / F circuit and an error signal when an error occurs. [Figure 11] FIG. 10 is a diagram illustrating an example of the configuration of a transmission / reception system according to a second embodiment. [Figure 12] 10A and 10B are diagrams illustrating data processed by an I / F circuit, an error signal when an error occurs, and a test control signal output by a test control unit. [Figure 13] FIG. 10 is a diagram illustrating an example of the configuration of a transmission / reception system according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] An example of an embodiment of the present disclosure will be described below with reference to the drawings. The same reference numerals are used throughout the drawings to designate identical or equivalent components and parts. The dimensional proportions of the drawings are exaggerated for illustrative purposes and may differ from the actual proportions.

[0014] (First embodiment) Before describing the first embodiment of the present disclosure, a conventional technique will be described. Fig. 1 is a diagram showing an example of the configuration of a conventional transmission and reception system. The transmission and reception system shown in Fig. 1 is a system in which data transmitted from a transmission system 20 on the transmitting side is received by a reception system 10 on the receiving side. The reception system 10 includes a CRC calculation circuit 11, a function circuit 14, an error detection unit 15, and an I / F circuit 16.

[0015] The CRC calculation circuit 11 is a circuit that performs CRC calculations, and the CRC generating polynomial is X 16 +X 12 +X 5 To perform a CRC calculation represented by +1, the circuit is equipped with 16 shift registers 12A, 12B, ..., 12P and adders 13A, 13B, and 13C. Adder 13A adds the input to CRC calculation circuit 11 and the output from shift register 12P, and outputs the result to shift register 12A, adder 13B, and adder 13C. Adder 13B adds the output of adder 13A and the output from shift register 12E, and outputs the result to shift register 12F. Adder 13C adds the output of adder 13A and the output from shift register 12L, and outputs the result to shift register 12M.

[0016] The functional circuit 14 is a circuit that executes processing based on data transmitted from the transmission system 20, and executes processing determined by the functions of the reception system 10.

[0017] The error detection unit 15 detects whether or not there is an error in the calculation result of the CRC calculation circuit 11 based on the calculation result of the CRC calculation circuit 11. The I / F circuit 16 receives data transmitted from the transmission system 20 and outputs the data portion to the functional circuit 14, and the data portion and CRC code portion (all received data) to the CRC calculation circuit 11. FIG. 2 is a diagram showing data processed by the I / F circuit 16 and an error signal when an error occurs. When the output of the shift registers 12A, 12B, 12C, ..., 12P is 16'h0000, the error detection unit 15 sets the error signal to L. When the output of the shift registers 12A, 12B, 12C, ..., 12P is other than 16'h0000, the error detection unit 15 toggles the error signal from L to H and outputs the error signal to the functional circuit 14 and to the outside of the receiving system 10.

[0018] The transmission system 20 adds a CRC code to the transmission data along with a control signal for the data communication format and transmits the data. Fig. 3 is a diagram showing the data format of the transmission data transmitted by the transmission system 20. The transmission system 20 transmits the transmission data consisting of N-bit data 21 and a 16-bit CRC code 22.

[0019] The receiving system 10 shown in FIG. 1 performs an error check using the output of the CRC calculation circuit 11 as follows.

[0020] Fig. 4 is a diagram illustrating a method for testing the CRC calculation circuit 11 by the receiving system 10 shown in Fig. 1. In step 1, an initial value is set in the CRC calculation circuit 11, and all 16 bits of the output from the shift registers 12A, 12B, ..., 12P are 1. In step 2, data "1" is input to the CRC calculation circuit 11, and by clock input and shift operation, the input to the CRC calculation circuit 11 and the output from the shift register 12P are added in the adder 13A, and the output from the adder 13A and the output from the shift register 12E are added in the adder 13B, and the value of the shift register 12F is set to 0.

[0021] Thereafter, the input of data to the CRC calculation circuit 11 is repeated, and in step 8 of Fig. 4, the value of the shift register 12L is set to 0. In other words, it takes another 6 cycles from step 2 until the value of the shift register 12L is set to 0.

[0022] Furthermore, the input of data to the CRC calculation circuit 11 is repeated, and in the procedure (N+16+1) of Fig. 4, the output of the shift registers 12A to 12P is normal if all 16 bits are 0. That is, after all the data transmitted from the transmission system 20 is input to the reception system 10, a cycle of N+CRC bits (16 bits) of data length is required until it becomes possible to check whether the calculation result of the CRC calculation circuit 11 is all 0. That is, depending on the data length, it may take some time to check whether the calculation result of the CRC calculation circuit 11 is all 0.

[0023] The receiving system according to the first embodiment of the present disclosure is characterized in that it can reduce the time required to check the CRC calculation results by performing a test using a minimum number of test patterns.

[0024] Fig. 5 is a diagram illustrating an example configuration of a transmission / reception system according to the first embodiment of the present disclosure. The transmission / reception system illustrated in Fig. 5 is a system in which data transmitted from a transmission system 20 on the transmitting side is received by a reception system 100 on the receiving side. The reception system 100 includes an I / F circuit 110, a CRC calculation circuit 111, a functional circuit 140, an error detection unit 150, a test control unit 160, a selector 161, and a test table 170. The test table 170 is an example of a data holding unit of the present disclosure, and is a table that stores test input data 171, which is an example of test data of the present disclosure, a shift register initial value 172, which is an example of initial value data of the present disclosure, and an expected value 173, which is an example of expected value data of the present disclosure.

[0025] The I / F circuit 110 receives data transmitted from the transmission system 20 and outputs the data portion to the function circuit 140 and the data portion and CRC code portion (all received data) to the CRC calculation circuit 111 .

[0026] The CRC calculation circuit 111 is an example of an electronic circuit of the present disclosure. The CRC calculation circuit 111 is a circuit that performs CRC calculations, and the CRC generating polynomial is X 16 +X 12 +X 5 To perform the CRC calculation represented by +1, the circuit is equipped with 16 shift registers 120A, 120B, ..., 120P and adders 130A, 130B, and 130C. Adder 130A adds the input to CRC calculation circuit 111 and the output from shift register 120P, and outputs the result to shift register 120A, adder 130B, and adder 130C. Adder 130B adds the output of adder 130A and the output from shift register 120E, and outputs the result to shift register 120F. Adder 130C adds the output of adder 130A and the output from shift register 120L, and outputs the result to shift register 120M.

[0027] The functional circuit 140 is a circuit that executes processing based on data transmitted from the transmission system 20, and executes processing determined by the functions of the reception system 100.

[0028] The error detection unit 150 detects whether or not there is an error in the calculation result of the CRC calculation circuit 111 based on the calculation result of the CRC calculation circuit 111 and the expected value 173 stored in the test table 170 .

[0029] The test control unit 160 sets an arbitrary initial value in the CRC calculation circuit 111 when testing the CRC calculation circuit 111. For example, in response to an instruction from outside the receiving system 100, the test control unit 160 reads test input data 171, shift register initial values ​​172, and expected values ​​173 corresponding to a test number (No.) from the test table 170. FIG. 6 is a diagram showing examples of the test input data 171, shift register initial values ​​172, and expected values ​​173 stored in the test table 170. As shown in FIG. 6, the test table 170 stores different test input data 171, shift register initial values ​​172, and expected values ​​173 for each test number. The shift register initial values ​​172 are set in each shift register of the CRC calculation circuit 111, and the test input data 171 is input to the CRC calculation circuit 111. The test control unit 160 also outputs a test control signal to the selector 161 for switching the test on and off. The test control signal is a signal for switching the selector 161 so that data from the I / F circuit 110 is input to the CRC calculation circuit 111 under normal circumstances, and so that test input data 171 is input to the CRC calculation circuit 111 when testing the CRC calculation circuit 111.

[0030] A method for testing the CRC calculation circuit 111 in the receiving system 100 shown in Fig. 5 will be described below. Fig. 7 is a diagram for explaining a method for testing the CRC calculation circuit 111 in the receiving system 100 shown in Fig. 5.

[0031] In step 1, the test control unit 160 reads the test input data 171, shift register initial value 172, and expected value 173 corresponding to test number 1 from the test table 170, and sets the read shift register initial value 172 in each shift register of the CRC calculation circuit 111.

[0032] In step 2, the test control unit 160 inputs test input data 171 corresponding to test number 1 to the CRC calculation circuit 111. The CRC calculation circuit 111 receives the test input data 171 and outputs the values ​​of each of the shift registers 120A to 120P resulting from the shifting. The error detection unit 150 compares the calculation result of the CRC calculation circuit 111 with the expected value 173 corresponding to test number 1, and if the two match, determines that the calculation result of the CRC calculation circuit 111 is normal, and if the two do not match, outputs a message indicating that there is an error in the calculation of the CRC calculation circuit 111.

[0033] In procedure 3, the test control unit 160 reads out test input data 171, shift register initial value 172, and expected value 173 corresponding to test number 2 from the test table 170, and sets the read shift register initial value 172 in each shift register of the CRC calculation circuit 111. In procedure 4, the test control unit 160 inputs the test input data 171 corresponding to test number 2 to the CRC calculation circuit 111, and the error detection unit 150 compares the calculation result of the CRC calculation circuit 111 with the expected value 173 corresponding to test number 2.

[0034] Similarly, in step 5, the test control unit 160 reads out test input data 171, shift register initial value 172, and expected value 173 corresponding to test number 3 from the test table 170, and sets the read shift register initial value 172 in each shift register of the CRC calculation circuit 111. In step 6, the test control unit 160 inputs the test input data 171 corresponding to test number 3 to the CRC calculation circuit 111, and the error detection unit 150 compares the calculation result of the CRC calculation circuit 111 with the expected value 173 corresponding to test number 3.

[0035] Similarly, in step 7, the test control unit 160 reads out test input data 171, shift register initial value 172, and expected value 173 corresponding to test number 4 from the test table 170, and sets the read shift register initial value 172 in each shift register of the CRC calculation circuit 111. In step 8, the test control unit 160 inputs the test input data 171 corresponding to test number 4 to the CRC calculation circuit 111, and the error detection unit 150 compares the calculation result of the CRC calculation circuit 111 with the expected value 173 corresponding to test number 4.

[0036] 8 is a diagram extracting steps 7 and 8 from the test method for the CRC calculation circuit 111 in the receiving system 100 shown in FIG. 7. The calculation result of the CRC calculation circuit 111 in step 8 is "0100_0101_0110_0101," but the expected value of test number 4 is "0100_0101_0111_0101," which are different. Therefore, the error detection unit 150 outputs a message indicating that there is an error in the calculation by the CRC calculation circuit 111.

[0037] On the other hand, if we focus only on shift register 120L (S

[11] ), we can see that the value changes from 1 to 0 when data for test number 4 is input, which confirms that the shift operation from 1 to 0 is being performed normally between the previous shift register 120M (S

[10] ) and shift register 120L (S

[11] ).

[0038] As described above, the receiving system 100 according to the first embodiment of the present disclosure is characterized in that it can reduce the time required to check the CRC calculation results by performing a test using a minimum number of test patterns.

[0039] (Second embodiment) Before describing the second embodiment of the present disclosure, a conventional technique will be described. Fig. 9 is a diagram showing an example of the configuration of a conventional transmission and reception system. The transmission and reception system shown in Fig. 9 is a system in which data transmitted from a transmission system 20 on the transmitting side is received by a reception system 10' on the receiving side. The reception system 10' includes CRC calculation circuits 11A and 11B, a function circuit 14, error detection units 15A and 15B, an I / F circuit 16, and a comparison unit 17.

[0040] The CRC calculation circuit 11A is a circuit that performs CRC calculation, and the CRC generating polynomial is X 16 +X 12 +X 5 To perform the CRC calculation represented by +1, the CRC calculation circuit 11A includes 16 shift registers 12A-A, 12B-A, ..., 12P-A and adders 13A-A, 13B-A, and 13C-A. The adder 13A-A adds the input to the CRC calculation circuit 11A and the output from the shift register 12P-A, and outputs the result to the shift register 12A-A and the adders 13B-A and 13C-A. The adder 13B-A adds the output of the adder 13A-A and the output from the shift register 12E-A, and outputs the result to the shift register 12F-A. The adder 13C-A adds the output of the adder 13A-A and the output from the shift register 12L-A, and outputs the result to the shift register 12M-A.

[0041] Similarly, the CRC calculation circuit 11B is a circuit that performs CRC calculations, and the CRC generating polynomial is X 16 +X 12 +X 5To perform the CRC calculation represented by +1, the CRC calculation circuit 11B includes 16 shift registers 12A-B, 12B-B, ..., 12P-B and adders 13A-B, 13B-B, and 13C-B. Adder 13A-B adds the input to CRC calculation circuit 11B and the output from shift register 12P-B, and outputs the result to shift register 12A-B and adders 13B-B and 13C-B. Adder 13B-B adds the output of adder 13A-B and the output from shift register 12E-B, and outputs the result to shift register 12F-B. Adder 13C-B adds the output of adder 13A-B and the output from shift register 12L-B, and outputs the result to shift register 12M-B.

[0042] The receiving system 10' shown in Figure 9 is configured such that CRC calculation circuits are arranged in parallel, the outputs from the CRC calculation circuits 11A and 11B are detected by error detection units 15A and 15B, respectively, the outputs from the error detection units 15A and 15B are compared by a comparison unit 17, and the comparison result is output.

[0043] 10 is a diagram showing data processed by I / F circuit 16 and an error signal when an error occurs. When the outputs of shift registers 12A-A to 12P-A are 16'h0000, error detection unit 15A sets the error signal to L, and when the outputs of shift registers 12A-A to 12P-A are other than 16'h0000, error detection unit 15A toggles the error signal from L to H and outputs the error signal to comparison unit 17. Similarly, when the outputs of shift registers 12A-B to 12P-B are 16'h0000, error detection unit 15B sets the error signal to L, and when the outputs of shift registers 12A-B to 12P-B are other than 16'h0000, error detection unit 15B toggles the error signal from L to H and outputs the error signal to comparison unit 17.

[0044] The comparison unit 17 compares the outputs of the error detection units 15A and 15B, and if at least one of the error signals output by the error detection unit 15A and the error detection unit 15B is H, it toggles the error signal from L to H and outputs the error signal to the outside of the functional circuit 14 and the receiving system 10'.

[0045] However, even with this configuration, as explained in the prior art of the first embodiment, depending on the data length, it may take some time to check whether the calculation results of the CRC calculation circuit 11 are all 0.

[0046] The receiving system according to the second embodiment of the present disclosure is characterized in that it can reduce the time required to check the CRC calculation results by performing a test using a minimum number of test patterns.

[0047] Fig. 11 is a diagram showing an example configuration of a transmission / reception system according to the second embodiment of the present disclosure. The transmission / reception system shown in Fig. 11 is a system in which data transmitted from a transmission system 20 on the transmission side is received by a reception system 100' on the reception side. The reception system 100' includes an I / F circuit 110, CRC calculation circuits 111A and 111B, a functional circuit 140, error detection units 150A and 150B, a test control unit 160, a selector 161, a test table 170, and a comparison unit 180. The test table 170 is a table that stores test input data 171, a shift register initial value 172, and an expected value 173.

[0048] The differences from the receiving system 100 in the first embodiment will be described.

[0049] The CRC calculation circuit 111A is an example of an electronic circuit of the present disclosure. The CRC calculation circuit 111A is a circuit that performs CRC calculations, and the CRC generating polynomial is X 16 +X 12 +X 5To perform the CRC calculation represented by +1, the CRC calculation circuit 111A includes 16 shift registers 120A-A, 120B-A, ..., 120P-A and adders 130A-A, 130B-A, and 130C-A. The adder 130A-A adds the input to the CRC calculation circuit 111A and the output from the shift register 120P-A, and outputs the result to the shift register 120A-A and the adders 130B-A and 130C-A. The adder 130B-A adds the output from the adder 130A-A and the output from the shift register 120E-A, and outputs the result to the shift register 120F-A. The adder 130C-A adds the output from the adder 130A-A and the output from the shift register 120L-A, and outputs the result to the shift register 120M-A.

[0050] Similarly, the CRC calculation circuit 111B is an example of an electronic circuit of the present disclosure. The CRC calculation circuit 111B is a circuit that performs CRC calculations, and the CRC generation polynomial is X 16 +X 12 +X 5 To perform the CRC calculation represented by +1, the CRC calculation circuit 111B includes 16 shift registers 120A-B, 120B-B, ..., 120P-B and adders 130A-B, 130B-B, and 130C-B. The adder 130A-B adds the input to the CRC calculation circuit 111B and the output from the shift register 120P-B, and outputs the result to the shift register 120A-B and the adders 130B-B and 130C-B. The adder 130B-B adds the output from the adder 130A-B and the output from the shift register 120E-B, and outputs the result to the shift register 120F-B. The adder 130C-B adds the output from the adder 130A-B and the output from the shift register 120L-B, and outputs the result to the shift register 120M-B.

[0051] The error detection unit 150A detects whether or not there is an error in the calculation result of the CRC calculation circuit 111A, based on the calculation result of the CRC calculation circuit 111A and the expected value 173 stored in the test table 170. Similarly, the error detection unit 150B detects whether or not there is an error in the calculation result of the CRC calculation circuit 111B, based on the calculation result of the CRC calculation circuit 111B and the expected value 173 stored in the test table 170.

[0052] The comparison unit 180 compares the outputs of the error detection units 150A and 150B, and if at least one of the error signals output by the error detection unit 150A and the error detection unit 150B is H, the comparison unit 180 toggles the error signal from L to H and outputs the error signal to the outside of the functional circuit 140 and the receiving system 100′.

[0053] Specifically, when the outputs of shift registers 120A-A to 120P-A are 16'h0000, error detection unit 150A sets the error signal to L, and when the outputs of shift registers 120A-A to 120P-A are other than 16'h0000, error detection unit 150A toggles the error signal from L to H and outputs the error signal to comparison unit 180. Similarly, when the outputs of shift registers 120A-B to 120P-B are 16'h0000, error detection unit 150B sets the error signal to L, and when the outputs of shift registers 120A-B to 120P-B are other than 16'h0000, error detection unit 150B toggles the error signal from L to H and outputs the error signal to comparison unit 180.

[0054] The comparison unit 180 compares the outputs of the error detection units 150A and 150B, and if at least one of the error signals output by the error detection unit 150A and the error detection unit 150B is H, the comparison unit 180 toggles the error signal from L to H and outputs the error signal to the outside of the functional circuit 140 and the receiving system 100′.

[0055] In the receiving system 100' according to this embodiment, first, the error detection units 150A and 150B determine whether or not there is an error in the CRC calculation of data transmitted from the transmitting system 20. If it is determined that there is an error, the comparison unit 180 instructs the test control unit 160 to execute a test on the CRC calculation circuits 111A and 111B if the determination results of the error detection units 150A and 150B do not match. Upon receiving the instruction from the comparison unit 180, the test control unit 160 outputs a test control signal to switch the selector 161 so as to input test input data 171 to the CRC calculation circuits 111A and 111B. The subsequent test procedure for the CRC calculation circuits 111A and 111B is the same as in the first embodiment, and therefore a detailed description thereof will be omitted.

[0056] 12 is a diagram showing data processed by the I / F circuit 110, an error signal when an error occurs, and a test control signal output by the test control unit 160. The receiving system 100' first performs a CRC calculation on the data transmitted from the transmitting system 20, and if one of the error detection units 150A, 150B determines that an error has occurred, it executes a test on the CRC calculation circuits 111A, 111B using data stored in the test table 170. If the test using the data stored in the test table 170 confirms that the CRC calculation circuit that determined there was no error is not faulty, the comparing unit 180 sets the error signal to L, and if it confirms that the CRC calculation circuit that determined there was no error is faulty, the comparing unit 180 toggles the error signal from L to H and outputs it.

[0057] By performing tests on the CRC calculation circuits 111A and 111B in this manner, the receiving system 100' of this embodiment can determine the failure of the CRC calculation circuit in a short time if a circuit failure occurs in either of the CRC calculation circuits 111A and 111B, and output an error determination result based on the calculation result from the normal CRC calculation circuit.

[0058] (Third embodiment) Fig. 13 is a diagram showing an example of the configuration of a transmission / reception system according to the third embodiment of the present disclosure. The transmission / reception system shown in Fig. 13 is a system in which data transmitted from transmission systems 20A and 20B on the transmission side is received by a reception system 100'' on the reception side. The reception system 100'' of the transmission / reception system shown in Fig. 13 also functions as the transmission side, and the transmission / reception system shown in Fig. 13 is a system in which data transmitted from the reception system 100'' is received by a reception system 20C on the reception side.

[0059] The receiving system 100'' includes I / F circuits 110A, 110B, and 110C, CRC calculation circuits 111A, 111B, and 111C, a test control unit 160, and test tables 170A, 170B, and 170C. The CRC calculation circuits 111A, 111B, and 111C are examples of electronic circuits of the present disclosure. The CRC calculation circuits 111A, 111B, and 111C are circuits that perform CRC calculations, and are configured to generate CRCs when the CRC generating polynomial is X 16 +X 12 +X 5 The receiving system 100'' performs a CRC calculation represented by +1. The receiving system 100'' further includes the functional circuit 140 and the error detection unit 150 shown in the first embodiment, but these are omitted from FIG.

[0060] The receiving system 100'' shown in FIG. 13 is characterized by enabling a test to be performed in a short time by utilizing a gap time during inactivity, such as when communication starts or stops. For example, when communication starts, the receiving system 100'' tests the CRC calculation circuit 111A using an internal test pattern stored in the test table 170A before data from the transmitting system 20A is input to the I / F circuit 110A, and transmits the determination result of the CRC calculation circuit 111A to the transmitting system 20A. Also, when communication stops, the receiving system 100'' tests the CRC calculation circuit 111C using an internal test pattern stored in the test table 170C after normal operation, and transmits the determination result of the CRC calculation circuit 111C to the receiving system 20C.

[0061] In this way, the receiving system 100'' according to the third embodiment can reduce the time required to check the calculation results in the CRC calculation circuits 111A, 111B, and 111C by the test control unit 160 executing tests on the CRC calculation circuits 111A, 111B, and 111C using the internal test patterns stored in the test tables 170A, 170B, and 170C. By reducing the time required to check the calculation results in the CRC calculation circuits 111A, 111B, and 111C, the receiving system 100'' according to the third embodiment can perform tests in a short time by utilizing the gap time during inactivity, such as when communication starts or stops.

[0062] Although the embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. The above-described embodiments are illustrative and do not limit the technical scope of the present disclosure. It is clear that a person skilled in the art of the present disclosure can conceive of various modifications or alterations within the scope of the technical idea described in the claims, and it is understood that these modifications or alterations also naturally fall within the technical scope of the present disclosure.

[0063] Furthermore, the effects described in the above embodiments are explanatory or exemplary and are not limited to those described in the above embodiments. In other words, the technology according to the present disclosure may achieve other effects that are obvious to a person skilled in the art of the present disclosure from the description in the above embodiments, in addition to or instead of the effects described in the above embodiments. [Explanation of symbols]

[0064] 100 Receiving System 110 I / F circuit 111 CRC calculation circuit 120A, 120B,..., 120P shift register 130A, 130B, 130C adders 140 Functional Circuits 150 Error detection unit 160 Test control section 161 Selector 170 Test Table

Claims

1. a CRC calculation circuit that is made up of a plurality of shift registers and that performs a CRC calculation on input data; an error detection unit that detects whether or not there is an error in the output of the CRC calculation circuit; a data holding unit that holds test data for testing the CRC calculation circuit, initial value data for setting initial values ​​of the CRC calculation circuit in the plurality of shift registers, and expected value data for setting expected values ​​of the output of the CRC calculation circuit in the error detection unit; a test control unit that sets the initial value data in the plurality of shift registers when testing the CRC calculation circuit and inputs the test data to the CRC calculation circuit; Equipped with The data holding unit holds a plurality of sets of the test data, the initial value data, and the expected value data.

2. The electronic circuit according to claim 1 , comprising a plurality of said CRC calculation circuits and said error detection units.

3. a CRC calculation circuit that is made up of a plurality of shift registers and that performs a CRC calculation on input data; an error detection unit that detects whether or not there is an error in the output of the CRC calculation circuit; a data holding unit that holds test data for testing the CRC calculation circuit, initial value data for setting initial values ​​of the CRC calculation circuit in the plurality of shift registers, and expected value data for setting expected values ​​of the output of the CRC calculation circuit in the error detection unit; a test control unit that sets the initial values ​​in the shift registers and inputs the test data to the CRC calculation circuit when testing the CRC calculation circuit; Equipped with a test method for an electronic circuit, wherein the data holding unit holds a plurality of sets of the test data, the initial value data, and the expected value data, setting the initial values ​​in the plurality of shift registers; setting the expected value in the error detection unit; inputting the test data into the CRC calculation circuit; outputting an error signal from the error detection unit when the output of the CRC calculation circuit does not match the expected value; A method for testing an electronic circuit, including:

4. the electronic circuit comprises a plurality of the CRC calculation circuits and the error detection unit, 4. The electronic circuit testing method according to claim 3, wherein the step of inputting the test data to the CRC calculation circuit includes the step of inputting the test data to the CRC calculation circuit while any of the CRC calculation circuits is performing a CRC calculation on data transmitted from an external source.

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