Semiconductor device and manufacturing method thereof

Abstract

To achieve good diode characteristics.SOLUTION: A semiconductor device includes a semiconductor substrate, a bottom electrode and a gate electrode. The semiconductor substrate has a p-type collector region, an n-type cathode region and an n-type specific region which are arranged between a buffer region and the bottom face of the semiconductor substrate. The semiconductor device includes a transistor part and a diode part. Current flows in the transistor part depending on gate voltage. Current flows in the diode part depending on forward bias voltage. The collector region is arranged in at least a part of the transistor part and at least a part of the collector region is exposed from the bottom face of the semiconductor substrate. The cathode region is arranged in at least a part of the diode part and is exposed from the bottom face of the semiconductor substrate. The specific region is arranged in at least a part of the diode part and is also arranged between the cathode region and the buffer region. A p-type impurity concentration in the specific region is lower than a p-type impurity concentration in the collector region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] The IGBT (insulated gate bipolar transistor) disclosed in Patent Document 1 has a p-type collector region and an n-type buffer region (field stop layer). The collector region is disposed in an area including the lower surface of the semiconductor substrate and is in contact with a lower electrode. The buffer region is in contact with the collector region from above. In Patent Document 1, the concentration of p-type impurities in the collector region is increased in a position near the buffer region, thereby improving the short-circuit resistance of the IGBT. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-043301 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device having a diode adjacent to an IGBT is known. This type of semiconductor device is sometimes called an RC-IGBT (reverse conducting IGBT). In an RC-IGBT, a cathode region (i.e., an n-type region) of the diode is provided adjacent to the collector region of the IGBT. To form the above-mentioned collector region in an RC-IGBT, for example, the following steps are performed. First, p-type impurities are implanted into the area corresponding to the collector region and the cathode region. Next, n-type impurities are implanted into the area corresponding to the cathode region at a higher concentration than the p-type impurities. This forms an n-type cathode region. However, this method may leave a p-type region between the cathode region and the buffer region. If a p-type region remains between the cathode region and the buffer region, the diode will not have the desired characteristics. This specification proposes a technology for achieving good diode characteristics in an RC-IGBT. [Means for solving the problem]

[0005] The semiconductor device (10) disclosed herein includes a semiconductor substrate (12), a lower electrode (14) in contact with the bottom surface (12b) of the semiconductor substrate, and a gate electrode (20). The semiconductor substrate includes an n-type buffer region (44), a drift region (46) that is an n-type region with a lower n-type impurity concentration than the buffer region and is in contact with the buffer region from above, p-type first regions (48, 50) in contact with the drift region, an n-type second region (52, 54) separated from the drift region by the first region, and a p-type collector region (40) disposed between the buffer region and the bottom surface of the semiconductor substrate, an n-type cathode region (42), and an n-type specific region (41) with a lower n-type impurity concentration than the cathode region. The gate electrode faces the first region via a gate insulating film. When viewed perpendicularly to the top surface of the semiconductor substrate, the semiconductor device includes a transistor portion (30) and a diode portion (32). The transistor portion is a portion through which a current flows in response to a gate voltage applied to the gate electrode. The diode portion is a portion through which a current flows in response to a forward bias voltage applied between the first region and the lower electrode. The collector region (40) is disposed in at least a portion of the transistor portion, and at least a portion of the collector region is exposed to the lower surface of the semiconductor substrate. The cathode region (42) is disposed in at least a portion of the diode portion, and is exposed to the lower surface of the semiconductor substrate. The specific region (41) is disposed in at least a portion of the diode portion, and is disposed between the cathode region and the buffer region. The p-type impurity concentration of the specific region is lower than the p-type impurity concentration of the collector region.

[0006] According to this configuration, a specific region can be disposed between the cathode region and the buffer region in at least a portion of the diode section. The specific region is a region in which the p-type impurity concentration is lower than the p-type impurity concentration of the collector region. The specific region is an n-type region. Therefore, an n-type specific region can be disposed in the depth range from the lower electrode to the buffer region. This makes it possible to realize a structure in which no p-type region exists between the cathode region and the buffer region in at least a portion of the diode section. This makes it possible to obtain good diode characteristics.

[0007] This specification also proposes a method for manufacturing a semiconductor device. The semiconductor device manufactured by this method includes a semiconductor substrate (12), a lower electrode (14) in contact with the bottom surface of the semiconductor substrate, and a gate electrode (20). The semiconductor substrate includes an n-type buffer region (44), an n-type drift region (46) having a lower n-type impurity concentration than the buffer region and in contact with the buffer region from above, p-type first regions (48, 50) in contact with the drift region, an n-type second region (52, 54) separated from the drift region by the first region, and a p-type collector region (40) disposed between the buffer region and the bottom surface of the semiconductor substrate, an n-type cathode region (42), and an n-type specific region (41) having a lower n-type impurity concentration than the cathode region. The gate electrode faces the first region via a gate insulating film. When viewed perpendicularly to the top surface of the semiconductor substrate, the semiconductor device includes a transistor portion (30) and a diode portion (32). The transistor portion is a portion through which a current flows in response to a gate voltage applied to the gate electrode. The diode portion is a portion through which a current flows in response to a forward bias voltage applied between the first region and the lower electrode. The collector region (40) is disposed in at least a portion of the transistor portion, and at least a portion of the collector region (40) is exposed to the lower surface of the semiconductor substrate. The cathode region (42) is disposed in at least a portion of the diode portion, and is exposed to the lower surface of the semiconductor substrate. The specific region (41) is disposed in at least a portion of the diode portion, and is disposed between the cathode region and the buffer region. The manufacturing method includes a first implantation step of selectively implanting p-type impurities into a range of the lower surface of the semiconductor substrate corresponding to the collector region, and a second implantation step of selectively implanting n-type impurities into a range of the lower surface of the semiconductor substrate corresponding to the cathode region. The depth of the n-type impurities implanted in the second implantation step from the lower surface of the semiconductor substrate is smaller than the depth of the p-type impurities implanted in the first implantation step from the lower surface of the semiconductor substrate.

[0008] The first injection step and the second injection step may be carried out in any order.

[0009] According to this configuration, a semiconductor device having good diode characteristics can be manufactured. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the lower surface 12b of the semiconductor substrate 12. [Figure 3] Concentration distribution curve along line III-III in Figure 1. [Figure 4] Concentration distribution curve along line IV-IV in Figure 1 [Figure 5] Concentration distribution curve at line VV in Figure 1. [Figure 6] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are explanatory diagrams of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] FIG. 10 is a plan view of a diode section 32 according to a second embodiment. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 8. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0011] (Structure of semiconductor device 10) FIG. 1 shows a cross-sectional view of a main portion of a semiconductor device 10 according to a first embodiment. FIG. 2 shows a plan view of a lower surface 12b of a semiconductor substrate 12. The lower electrode 14 is not shown in FIG. 1. FIG. 1 corresponds to a cross-sectional view taken along line II in FIG. 2. In the drawings of this specification, a direction along the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction along the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z-direction. A portion having a repeating structure may be described by assigning a reference symbol to a representative portion of multiple portions. The semiconductor device 10 mainly includes a semiconductor substrate 12, a lower electrode 14, and a gate electrode 20.

[0012] 1, the semiconductor substrate 12 has a collector region 40, a cathode region 42, a specific region 41, a buffer region 44, a drift region 46, a body region 48, an anode region 50, an emitter region 52, and a dummy emitter region 54. The semiconductor substrate 12 may be made of various materials, such as silicon or a wide-gap semiconductor (e.g., SiC or GaN). In this example, the semiconductor substrate 12 is made of silicon.

[0013] A plurality of trenches 16 are provided in the upper surface 12a of the semiconductor substrate 12. Each trench 16 extends linearly in the y direction on the upper surface 12a. The trenches 16 are spaced apart in the x direction. A plurality of trenches 16 are provided in each of the transistor section 30 and the diode section 32. The transistor section 30 and the diode section 32 will be described later. The inner surface of each trench 16 is covered with a gate insulating film 18. A gate electrode 20 is provided in each trench 16 in the transistor section 30. Each gate electrode 20 is insulated from the semiconductor substrate 12 by the gate insulating film 18. A dummy electrode 22 is provided in each trench 16 in the diode section 32. Each dummy electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 18. The upper surfaces of the gate electrodes 20 and the dummy electrodes 22 are covered with an interlayer insulating film 24.

[0014] An upper electrode 26 is provided on the upper part of the semiconductor substrate 12. The upper electrode 26 covers the upper surface of the interlayer insulating film 24 and the upper surface 12a of the semiconductor substrate 12. The dummy electrode 22 is connected to the upper electrode 26 at a position not shown. Therefore, the potential of the dummy electrode 22 is equal to the potential of the upper electrode 26. The gate electrode 20 is insulated from the upper electrode 26 and the dummy electrode 22. Therefore, the potential of the dummy electrode 22 is independent from the potential of the gate electrode 20. The gate electrode 20 is connected to a gate pad not shown. The potential of the gate electrode 20 is controlled by an external drive circuit via the gate pad.

[0015] The transistor section 30 and the diode section 32 will now be described. As shown in FIG. 2, the semiconductor device 10 is formed with a transistor section 30 and a diode section 32. The diode section 32 is a rectangle extending in the y direction. A plurality of diode sections 32 are repeatedly arranged in the x direction at predetermined intervals. This forms a striped structure in which the transistor sections 30 and diode sections 32 are alternately arranged in the x direction.

[0016] 1, when viewed from a direction perpendicular to the top surface 12a of the semiconductor substrate 12 (z direction), the semiconductor device 10 includes a transistor section 30 and a diode section 32. The transistor section 30 is a section where a channel is formed in response to a gate voltage applied to the gate electrode 20, and a current flows. The diode section 32 is a section where a current flows in response to a forward bias voltage applied between the anode region 50 and the lower electrode 14. The transistor section 30 and the diode section 32 can have various configurations as long as they satisfy the above requirements.

[0017] In the example of FIG. 1 , the transistor section 30 is a region in which the gate electrode 20 is disposed. The diode section 32 is a region in which the dummy electrode 22 is disposed. A boundary B1 exists between the transistor section 30 and the diode section 32. Note that the configurations of the transistor section 30 and the diode section 32 are not limited to the example configuration of FIG. 1 and may be various. For example, the diode section 32 may be a region that does not include a dummy emitter region 54. In this case, the diode section 32 may include the gate electrode 20.

[0018] A lower electrode 14 is provided on the lower surface 12b of the semiconductor substrate 12. The lower electrode 14 covers almost the entire lower surface 12b. A collector region 40 and a cathode region 42 are in ohmic contact with the lower electrode 14. A p-type collector region 40, an n-type cathode region 42, and an n-type specific region 41 are arranged between the buffer region 44 and the lower surface 12b of the semiconductor substrate 12. The specific region 41 has a lower n-type impurity concentration than the cathode region 42.

[0019] The cathode region 42 is disposed in the entire diode section 32 and in part of the transistor section 30. An end 42e of the cathode region 42 in the -x direction extends beyond the boundary B1 and into the transistor section 30. The entire cathode region 42 is exposed to the lower surface 12b of the semiconductor substrate 12. The specific region 41 is disposed in part of the diode section 32. The specific region 41 is disposed between the cathode region 42 and the buffer region 44.

[0020] In a planar direction parallel to the lower surface 12b of the semiconductor substrate 12 (i.e., the x direction), the semiconductor substrate 12 has a first section S1 to a third section S3. The first section S1 is a section in which the collector region 40 is exposed to the lower surface 12b of the semiconductor substrate 12. The second section S2 is a section in which the collector region 40 is disposed between the buffer region 44 and the cathode region 42. That is, in the second section S2, the collector region 40 is laminated on the upper surface of the cathode region 42. A section boundary SB exists between the first section S1 and the second section S2. The third section S3 is a section in which the specific region 41 is disposed between the buffer region 44 and the cathode region 42. That is, in the third section S3, the specific region 41 is laminated on the upper surface of the cathode region 42. An interface IF exists between the second section S2 and the third section S3.

[0021] The collector region 40 is disposed in the entire transistor section 30 and in part of the diode section 32. An end 40e of the collector region 40 in the +x direction is in contact with the specific region 41. An interface IF where the end 40e and the specific region 41 are in contact is located within the diode section 32. Here, the distance from the section boundary SB to the interface IF (i.e., the width of the second section S2) is defined as D1. The thickness of the collector region 40 in the direction perpendicular to the lower surface 12b (z direction) is defined as T1. The distance D1 is greater than the thickness T1.

[0022] The buffer region 44 is an n-type region having a lower n-type impurity concentration than the cathode region 42. The buffer region 44 is distributed across the transistor section 30 and the diode section 32. The buffer region 44 contacts the collector region 40 and the specific region 41 from above.

[0023] The drift region 46 is an n-type region having a lower n-type impurity concentration than the buffer region 44. The drift region 46 is distributed across the transistor section 30 and the diode section 32. The buffer region 44 contacts the buffer region 44 from above within the transistor section 30 and the diode section 32. The upper end of the drift region 46 is located above the lower end of each trench 16. The drift region 46 contacts the gate insulating film 18 on the side surface of each trench 16.

[0024] The body region 48 and the anode region 50 are p-type regions that contact the drift region 46 from above. The body region 48 and the anode region 50 are an example of a first region. The body region 48 is provided in the transistor section 30. The anode region 50 is provided in the diode section 32. In other words, of the p-type first region arranged above the drift region 46, the portion within the transistor section 30 is the body region 48, and the portion within the diode section 32 is the anode region 50.

[0025] The body region 48 has a low-concentration region 48a and a contact region 48b. The p-type impurity concentration of the low-concentration region 48a is lower than the p-type impurity concentration of the contact region 48b. The low-concentration region 48a contacts the drift region 46 from above. The low-concentration region 48a contacts the gate insulating film 18 above the drift region 46. The contact region 48b contacts the low-concentration region 48a from above. The contact region 48b is in ohmic contact with the upper electrode 26.

[0026] The anode region 50 has a low-concentration region 50a and a contact region 50b. The p-type impurity concentration of the low-concentration region 50a is lower than the p-type impurity concentration of the contact region 50b. The low-concentration region 50a contacts the drift region 46 from above. The low-concentration region 50a contacts the gate insulating film 18 above the drift region 46. The contact region 50b contacts the low-concentration region 50a from above. The contact region 50b is in ohmic contact with the upper electrode 26.

[0027] The emitter region 52 and the dummy emitter region 54 are an example of an n-type second region. The emitter region 52 is an n-type region, and a plurality of emitter regions 52 are arranged in the transistor section 30. Each emitter region 52 contacts a low-concentration region 48a from above. Each emitter region 52 is in ohmic contact with the upper electrode 26. Each emitter region 52 contacts the gate insulating film 18 above the low-concentration region 48a. Each emitter region 52 is separated from the drift region 46 by the low-concentration region 48a. Each gate electrode 20 faces the low-concentration region 48a located between the emitter region 52 and the drift region 46, with the gate insulating film 18 interposed therebetween.

[0028] The dummy emitter regions 54 are n-type regions, and a plurality of them are arranged in the diode section 32. Each dummy emitter region 54 contacts the low concentration region 50a from above. Each dummy emitter region 54 contacts the gate insulating film 18 above the low concentration region 50a. Each dummy emitter region 54 is separated from the drift region 46 by the low concentration region 50a. Each dummy emitter region 54 is in ohmic contact with the upper electrode 26. Note that the dummy emitter regions 54 do not necessarily have to be provided in the diode section 32.

[0029] (Impurity concentration distribution curve) 3 to 5 show concentration distribution curves of impurities in the lower part of the semiconductor substrate 12. FIG. 3 shows the concentration distribution curve along line III-III in FIG. 1. FIG. 4 shows the concentration distribution curve along line IV-IV in FIG. 1. FIG. 5 shows the concentration distribution curve along line VV in FIG. 1.

[0030] 3 shows the concentration distribution curves of the region where the cathode region 42 and the collector region 40 are stacked (i.e., the second section S2). The n-type concentration distribution curve DC1 and a portion of the p-type concentration distribution curve DC2 overlap. The region where the n-type impurity concentration is higher than the p-type impurity concentration functions as the n-type cathode region 42. The region where the p-type impurity concentration is higher than the n-type impurity concentration functions as the p-type collector region 40. The region where the n-type concentration distribution curve DC3 is located functions as the n-type buffer region 44. That is, an npn junction is formed in the second section S2.

[0031] 4 shows the concentration distribution curve of the region where the cathode region 42 and the specific region 41 are stacked in the diode section 32 (i.e., the third section S3). In the third section S3, the p-type concentration distribution curve DC2 is not formed. Therefore, a region where no impurities are ion-implanted is formed between the cathode region 42 and the buffer region 44. This region is n - The third section S3 functions as an n-type specific region 41. The n-type impurity concentration of the specific region 41 is the same as the n-type impurity concentration of the drift region 46. That is, no npn junction is formed in the third section S3.

[0032] The specific region 41 is a region located in an area where the p-type concentration distribution curve DC2 is not formed. The collector region 40 is a region located in an area where the p-type concentration distribution curve DC2 is formed. Therefore, the concentration relationship is established such that the p-type impurity concentration of the specific region 41 is lower than the p-type impurity concentration of the collector region 40.

[0033] 5 shows the concentration distribution curves of the region (i.e., the first section S1) in the transistor section 30 where the collector region 40 is located. In the first section S1, the n-type concentration distribution curve DC1 is not formed. Therefore, the region where the p-type concentration distribution curve DC2 is formed functions as the p-type collector region 40. That is, in the first section S1, a pn junction is formed by the collector region 40 and the buffer region 44.

[0034] The characteristics of the p-type concentration distribution curve DC2 will be described using Figure 5. The concentration distribution curve DC2 has a first peak PK1 and a second peak PK2. The second peak PK2 is located more inward (toward the +z direction) than the first peak PK1. The second peak PK2 is higher than the first peak PK1.

[0035] The concentration distribution curve DC2 also has a depth center position DP and an integral center position IP. The depth center position DP is located at a depth half the distance from the lower surface 12b to the depth-direction end DC2e of the concentration distribution curve DC2. The integral center position IP is located at a depth where the integral value of the entire section of the concentration distribution curve DC2 is half. The integral center position IP is located more inward (in the +z direction) than the depth center position DP. This is because, as described above, the second peak PK2, which has a high peak value, is located more inward than the first peak PK1, which has a lower peak value.

[0036] The effect will be explained below. Compared to a concentration distribution curve with a simple Gaussian distribution, the concentration distribution curve DC2 allows the peak position of the p-type impurity concentration distribution curve to be positioned deeper in the depth direction from the lower surface 12b toward the inside. When the transistor section 30 is short-circuited, holes can be injected from the p-type collector region 40, thereby improving the short-circuit resistance. Furthermore, because the peak position of the p-type impurity concentration distribution curve can be positioned deeper from the lower surface 12b, the tail current can be suppressed, and an increase in switching loss can be suppressed.

[0037] (Operation of the semiconductor device 10) Within the transistor section 30, an IGBT is formed by the emitter region 52, the body region 48, the drift region 46, the buffer region 44, the collector region 40, the gate electrode 20, and the gate insulating film 18. When the potential of the lower electrode 14 is higher than the potential of the upper electrode 26 and the potential of the gate electrode 20 is higher than the gate threshold, the IGBT turns on and a current flows within the transistor section 30 from the lower electrode 14 to the upper electrode 26.

[0038] Within the diode section 32, a diode is formed by the anode region 50, the drift region 46, the buffer region 44, the specific region 41, and the cathode region 42. When the potential of the upper electrode 26 is higher than the potential of the lower electrode 14, the diode is turned on, and a current flows within the diode section 32 from the upper electrode 26 to the lower electrode 14.

[0039] (Method of manufacturing the semiconductor device 10) A manufacturing method for semiconductor device 10 will be described with reference to Figures 6 and 7. Figures 6 and 7 are cross-sectional views of the same portion as Figure 1, showing only the underside of semiconductor substrate 12. Note that this manufacturing method is characterized by the steps of forming collector region 40, specific region 41, and cathode region 42, and therefore the following description will focus on these steps.

[0040] First, n - An n-type semiconductor substrate 12 is prepared. An n-type impurity is implanted into the entire lower surface 12b of the semiconductor substrate 12. As a result, a buffer region 44 is formed.

[0041] Next, a first implantation step is performed. The first implantation step is a step of selectively implanting p-type impurities into an area corresponding to the collector region 40 of the lower surface 12b of the semiconductor substrate 12. This will be explained in detail. First, as shown in FIG. 6, a first mask 71 is formed on the lower surface 12b. The first mask 71 covers at least a portion of the diode portion 32 described above. An end 71e of the first mask 71 is located within the diode portion 32.

[0042] Next, p-type impurities are implanted from the lower surface 12b through the first mask 71. As a result, a p-type collector region 40 is formed in the region corresponding to the openings of the first mask 71 (i.e., the first section S1 and the second section S2). The collector region 40 is formed in the region from the lower surface 12b to the buffer region 44. The p-type impurities implanted by this ion implantation have a concentration distribution curve DC2 as described in FIG. 5. Such a concentration distribution curve with multiple peaks can be achieved by multi-stage implantation using multiple ion implantation energies.

[0043] Next, a second implantation step is performed. The second implantation step is a step of selectively implanting n-type impurities into an area corresponding to the cathode region 42 of the lower surface 12b of the semiconductor substrate 12. This step will be described in detail. First, as shown in FIG. 7, a second mask 72 is formed on the lower surface 12b. The second mask 72 covers at least a portion of the transistor section 30 described above. An end 72e of the second mask 72 is located within the transistor section 30.

[0044] Next, n-type impurities are implanted from the lower surface 12b through the second mask 72. As a result, the cathode region 42 is formed in the region corresponding to the opening of the second mask 72 (i.e., the second section S2 and the third section S3). Specifically, in the second section S2, n-type impurities are counter-ion-implanted into the p-type collector region 40, thereby forming the n-type cathode region 42. In addition, in the third section S3, n - An n-type cathode region 42 is formed by implanting n-type impurities into the region.

[0045] The cathode region 42 is formed in a shallow range from the lower surface 12b to a thickness T2. The thickness T2 of the cathode region 42 is smaller than the thickness T1 of the collector region 40. That is, the depth from the lower surface 12b of the n-type impurities implanted in the second implantation step is smaller than the depth from the lower surface 12b of the p-type impurities implanted in the first implantation step. Such a cathode region 42 can be formed by using a lower impurity implantation energy in the second implantation step than in the first implantation step and implanting the n-type impurities shallower than in the first implantation step.

[0046] The position of the end 71e of the first mask 71 coincides with the position of the interface IF described above (see FIG. 6). The position of the end 72e of the second mask 72 coincides with the position of the section boundary SB described above (see FIG. 7). Therefore, the opening region of the first mask 71 and the opening region of the second mask 72 partially overlap each other. The overlapping region of the opening regions coincides with the second section S2 described above. The distance between the positions of the end 71e and the end 72e is the distance D1 described above. The implantation depth of the p-type impurity implanted in the first implantation step corresponds to the thickness T1 of the collector region 40. Therefore, the distance D1 is greater than the implantation depth of the p-type impurity.

[0047] (effect) If a p-type region is formed between the cathode region 42 and the buffer region 44 in the diode section 32, it becomes difficult for current to flow through the diode section 32, and the forward voltage drop of the diode section 32 becomes extremely high. Therefore, high loss occurs in the diode section 32. Therefore, in the technology of this embodiment, an n-type specific region 41 is disposed between the cathode region 42 and the buffer region 44 in the third section S3 of the diode section 32. This makes it possible to realize a structure in which no p-type region exists between the cathode region 42 and the buffer region 44 in the third section S3 of the diode section 32. Therefore, it is possible to suppress loss occurring in the diode section 32.

[0048] In the technique of this embodiment, the first mask 71 is used in the first implantation step, so that the p-type impurity can be selectively implanted only into the first section S1 and the second section S2. This makes it possible to form the n-type specific region 41 in a self-aligned manner in the third section S3 of the diode section 32.

[0049] In the technology of this embodiment, the end 40e of the collector region 40 is located within the diode section 32. That is, the collector region 40 has a structure that extends toward the diode section 32. This allows holes to be injected from the collector region 40 located on the diode section 32 side when the transistor section 30 is operating. Since hole injection can be promoted, it is possible to reduce the on-voltage of the transistor section 30. Furthermore, since the collector region 40 can be extended into the diode section 32, it is possible to reduce the on-resistance of the transistor section 30. [Example]

[0050] (Structure of diode section 32) Fig. 8 shows a plan view of the diode portion 32 of Example 2. Fig. 8 corresponds to an enlarged view of region R8 in Fig. 2. That is, Fig. 8 shows a part of the diode portion 32 exposed on the lower surface 12b of the semiconductor substrate 12. Portions common to Example 2 and Example 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0051] In the diode section 32 of Example 2, a plurality of cathode regions 42 are arranged at intervals from one another. A specific region 41 is arranged between adjacent cathode regions 42. A cross-sectional view taken along line II in FIG. 8 (i.e., a cross-sectional view passing through the cathode region 42) is shown in FIG. 1. A cross-sectional view taken along line IX-IX in FIG. 8 (i.e., a cross-sectional view passing through the specific region 41) is shown in FIG. 9. As shown in FIG. 1, in the region where the cathode region 42 is arranged, the specific region 41 is arranged between the cathode region 42 and the buffer region 44. On the other hand, as shown in FIG. 8, in the region where the cathode region 42 is not arranged, the specific region 41 is exposed to the lower surface 12b.

[0052] (effect) According to the configuration of Example 2, in the diode section 32, a structure can be achieved in which the lower electrode 14 is in contact with the n-type specific region 41 in the region between adjacent cathode regions 42. A structure can be achieved in which no p-type region exists between the lower electrode 14 and the buffer region 44, making it possible to suppress the recovery tail current. As a result, recovery loss can be reduced.

[0053] (Manufacturing method) A manufacturing method of the diode section 32 of Example 2 will be described. In the second implantation step described above, a second mask 72 is formed (see FIG. 7). Here, the shape of the second mask 72 formed in the diode section 32 may be a shape having an opening in a region corresponding to the cathode region 42 in FIG. 8. In other words, the second mask 72 may have a divided mask structure in which a plurality of regions covering the specific region 41 in FIG. 8 are arranged in the diode section 32 at intervals from each other.

[0054] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

[0055] (Variation) The boundary region between the collector region 40 and the cathode region 42 may have various structures. For example, the collector region 40 and the cathode region 42 may not overlap in the thickness direction (z direction). In this case, the specific region 41 may be disposed between the end 40e of the collector region 40 and the end 42e of the cathode region 42. Alternatively, the end 40e of the collector region 40 and the end 42e of the cathode region 42 may be in contact with each other. In this case, the positions of the end 40e and the end 42e in the x direction may coincide. In this case, the positions of the end 40e and the end 42e may coincide with the boundary B1.

[0056] The shape of the p-type concentration distribution curve DC2 described in Fig. 5 may vary, for example, it may have a curve shape with three or more concentration peaks.

[0057] In the above-described embodiment, the first implantation step was performed first, followed by the second implantation step. However, these steps may be performed in any order. In the above-described embodiment, the collector region and the cathode region were formed after the buffer region 44, but the impurity implantation into the buffer region 44 may be performed after the collector region and the cathode region.

[0058] In the above-described embodiment, the dummy electrode 22 having a potential independent of the gate electrode 20 is disposed in the trench 16 in the diode portion 32. However, an electrode that is electrically connected to the gate electrode 20 may be disposed in the trench 16 in the diode portion 32. Also, a trench may not be provided in the diode portion 32.

[0059] In the above-described embodiment, a trench type IGBT is formed in the transistor section, but a planar type IGBT may be formed in the transistor section.

[0060] The configurations of the techniques disclosed in this specification are listed below. [Configuration 1] A semiconductor device (10), A semiconductor substrate (12); a lower electrode (14) in contact with the lower surface (12b) of the semiconductor substrate; a gate electrode (20); and The semiconductor substrate is an n-type buffer region (44); a drift region (46) that is an n-type region having a lower n-type impurity concentration than the buffer region and that is in contact with the buffer region from above; a p-type first region (48, 50) in contact with the drift region; an n-type second region (52, 54) separated from the drift region by the first region; a p-type collector region (40), an n-type cathode region (42), and an n-type specific region (41) having a lower n-type impurity concentration than the cathode region, which are arranged between the buffer region and the lower surface of the semiconductor substrate; and the gate electrode faces the first region via a gate insulating film, When viewed from a direction perpendicular to an upper surface of the semiconductor substrate, the semiconductor device comprises a transistor portion (30) and a diode portion (32), the transistor portion is a portion through which a current flows in response to a gate voltage applied to the gate electrode, the diode portion is a portion through which a current flows in response to a forward bias voltage applied between the first region and the lower electrode, the collector region (40) is disposed in at least a portion of the transistor portion, and at least a portion of the collector region (40) is exposed on the lower surface of the semiconductor substrate; the cathode region (42) is disposed in at least a portion of the diode section and is exposed on the lower surface of the semiconductor substrate; the specific region (41) is disposed in at least a part of the diode section and is disposed between the cathode region and the buffer region, the p-type impurity concentration in the specific region is lower than the p-type impurity concentration in the collector region; Semiconductor device. [Configuration 2] In a plane direction parallel to the lower surface of the semiconductor substrate, the collector region comprises a first section (S1) exposed to the lower surface of the semiconductor substrate, and a second section (S2) disposed between the buffer region and the cathode region; The first section and the second section are continuous, 2. The semiconductor device according to configuration 1, wherein an end of the second section in the planar direction is in contact with the specific region. [Configuration 3] 3. The semiconductor device according to configuration 2, wherein an interface (IF) where the end of the second section and the specific region come into contact is located within the diode section. [Configuration 4] The semiconductor device according to structure 3, wherein a distance (D1) from the boundary (B1) between the first section and the second section to the interface is greater than a thickness (T1) of the collector region in a direction perpendicular to the underside of the semiconductor substrate. [Configuration 5] a plurality of the cathode regions are arranged in the diode portion at intervals, 5. The semiconductor device according to any one of configurations 1 to 4, wherein the specific region is exposed on the underside of the semiconductor substrate between the adjacent cathode regions. [Configuration 6] a concentration distribution curve of the p-type impurity in the collector region in a depth direction from the lower surface of the semiconductor substrate toward the inside has a depth center position (DP) and an integral center position (IP), the depth center position is a depth position that is half the distance from the lower surface to an end of the concentration distribution curve in the depth direction, the integration center position is a depth position where the integral value of the entire section of the concentration distribution curve becomes half, The integration center position is located on the inner side of the depth center position. The semiconductor device according to any one of the configurations 1 to 5. [Configuration 7] A method for manufacturing a semiconductor device, comprising: The semiconductor device includes: A semiconductor substrate (12); a lower electrode (14) in contact with the lower surface of the semiconductor substrate; a gate electrode (20); and The semiconductor substrate is an n-type buffer region (44); a drift region (46) that is an n-type region having a lower n-type impurity concentration than the buffer region and that is in contact with the buffer region from above; a p-type first region (48, 50) in contact with the drift region; an n-type second region (52, 54) separated from the drift region by the first region; a p-type collector region (40), an n-type cathode region (42), and an n-type specific region (41) having a lower n-type impurity concentration than the cathode region, which are arranged between the buffer region and the lower surface of the semiconductor substrate; and the gate electrode faces the first region via a gate insulating film, When viewed from a direction perpendicular to an upper surface of the semiconductor substrate, the semiconductor device comprises a transistor portion (30) and a diode portion (32), the transistor portion is a portion through which a current flows in response to a gate voltage applied to the gate electrode, the diode portion is a portion through which a current flows in response to a forward bias voltage applied between the first region and the lower electrode, the collector region (40) is disposed in at least a portion of the transistor portion, and at least a portion of the collector region (40) is exposed on the lower surface of the semiconductor substrate; the cathode region (42) is disposed in at least a portion of the diode section and is exposed on the lower surface of the semiconductor substrate; the specific region (41) is disposed in at least a part of the diode section and is disposed between the cathode region and the buffer region, The manufacturing method includes: a first implantation step of selectively implanting p-type impurities into an area of ​​the lower surface of the semiconductor substrate corresponding to the collector region; a second implantation step of selectively implanting n-type impurities into an area of ​​the lower surface of the semiconductor substrate corresponding to the cathode region; and a depth from the bottom surface of the semiconductor substrate of the n-type impurity implanted in the second implantation step is smaller than a depth from the bottom surface of the semiconductor substrate of the p-type impurity implanted in the first implantation step; Manufacturing method. [Configuration 8] The first injection step forming a first mask on a lower surface of the semiconductor substrate to cover at least a portion of the diode portion; implanting the p-type impurity through the first mask; It is equipped with The second injection step forming a second mask on the lower surface of the semiconductor substrate to cover at least a portion of the transistor portion; implanting the n-type impurity through the second mask; It is equipped with 8. The manufacturing method according to claim 7, wherein the opening region of the first mask and the opening region of the second mask partially overlap each other. [Configuration 9] 9. The manufacturing method according to claim 8, wherein the end position of the first mask is located within the diode portion. [Configuration 10] The manufacturing method according to Structure 8 or 9, wherein a distance (D1) between an end position of the first mask and an end position of the second mask is greater than an implantation depth (T1) of the p-type impurity implanted in the first implantation step. [Configuration 11] 11. The manufacturing method according to any one of configurations 8 to 10, wherein the second mask further includes a plurality of divided masks arranged in the diode portion at intervals from each other. [Configuration 12] the first implantation step is performed so that a concentration distribution curve (DC2) of the p-type impurity in the collector region in a depth direction from the lower surface of the semiconductor substrate toward the inside has a first peak (PK1) and a second peak (PK2) located more inward than the first peak; 12. The method according to any one of aspects 7 to 11, wherein the second peak is higher than the first peak.

[0061] According to the configuration 2, holes can be injected from the second section of the collector region as well when the transistor section is in operation. Since hole injection can be promoted, it is possible to reduce the on-voltage of the transistor section.

[0062] According to the configuration 3, the collector region can be extended into the diode portion, thereby reducing the on-resistance of the transistor portion.

[0063] According to the fourth configuration, hole injection from the second section of the collector region can be more effectively promoted when the transistor section is in operation.

[0064] According to configuration 5, a structure can be achieved in which the bottom electrode contacts a specific region between adjacent cathode regions. This structure eliminates the need for a p-type region between the bottom electrode and the buffer region, making it possible to suppress the recovery tail current. As a result, recovery loss can be reduced.

[0065] According to configuration 6, the peak position of the concentration distribution curve of the p-type impurity in the collector region can be positioned deeper in the depth direction from the bottom surface of the semiconductor substrate, thereby making it possible to increase the short-circuit resistance while suppressing deterioration of switching loss.

[0066] According to configuration 8, a structure can be formed in which a part of the collector region is disposed between the buffer region and the cathode region. Hole injection can be promoted, and therefore the on-voltage of the transistor portion can be reduced.

[0067] According to the ninth aspect, a part of the collector region can be formed so as to extend into the diode portion, thereby reducing the on-resistance of the transistor portion.

[0068] According to the configuration 10, hole injection from the collector region formed in the diode section can be more effectively promoted.

[0069] According to the eleventh aspect, a structure can be formed in which a plurality of cathode regions are arranged in the diode section at intervals, thereby reducing recovery loss.

[0070] According to the configuration 12, it is possible to increase the short-circuit resistance while suppressing the deterioration of switching loss. [Explanation of symbols]

[0071] 10: Semiconductor device 12: Semiconductor substrate 30: Transistor section 32: Diode section 40: Collector region 41: Specific region 42: Cathode region 44: Buffer region 46: Drift region

Claims

1. A semiconductor device (10), a semiconductor substrate (12); a lower electrode (14) in contact with the lower surface (12b) of the semiconductor substrate; a gate electrode (20); and The semiconductor substrate is an n-type buffer region (44); a drift region (46) which is an n-type region having a lower n-type impurity concentration than the buffer region and which is in contact with the buffer region from above; a p-type first region (48, 50) in contact with the drift region; an n-type second region (52, 54) separated from the drift region by the first region; a p-type collector region (40), an n-type cathode region (42), and an n-type specific region (41) having a lower n-type impurity concentration than the cathode region, which are arranged between the buffer region and the lower surface of the semiconductor substrate; and the gate electrode faces the first region via a gate insulating film, When viewed from a direction perpendicular to the top surface of the semiconductor substrate, the semiconductor device comprises a transistor portion (30) and a diode portion (32), the transistor portion is a portion through which a current flows in response to a gate voltage applied to the gate electrode, the diode portion is a portion through which a current flows in response to a forward bias voltage applied between the first region and the lower electrode, the collector region (40) is disposed in at least a part of the transistor portion, and at least a part of it is exposed on the lower surface of the semiconductor substrate; the cathode region (42) is disposed in at least a part of the diode portion and is exposed on the lower surface of the semiconductor substrate; the specific region (41) is disposed in at least a part of the diode section and is disposed between the cathode region and the buffer region, a p-type impurity concentration in the specific region is lower than a p-type impurity concentration in the collector region; Semiconductor device.

2. In a planar direction parallel to a lower surface of the semiconductor substrate, the collector region includes a first section (S1) exposed to the lower surface of the semiconductor substrate, and a second section (S2) disposed between the buffer region and the cathode region; the first section and the second section are continuous, The semiconductor device according to claim 1 , wherein an end of said second section in said planar direction is in contact with said specific region.

3. 3. The semiconductor device according to claim 2, wherein an interface (IF) where said end of said second section and said specific region come into contact is located within said diode portion.

4. 4. The semiconductor device according to claim 3, wherein a distance (D1) from a boundary (B1) between the first section and the second section to the interface is greater than a thickness (T1) of the collector region in a direction perpendicular to the lower surface of the semiconductor substrate.

5. a plurality of the cathode regions are arranged in the diode portion at intervals, 5. The semiconductor device according to claim 1, wherein the specific region is exposed on the underside of the semiconductor substrate between the adjacent cathode regions.

6. a concentration distribution curve of the p-type impurity in the collector region in a depth direction from the lower surface of the semiconductor substrate toward the inside has a depth center position (DP) and an integral center position (IP), the depth center position is a depth position that is half the distance from the lower surface to an end of the concentration distribution curve in the depth direction, the integration center position is a depth position where the integral value of the entire section of the concentration distribution curve becomes half, The integration center position is located on the inner side of the depth center position. The semiconductor device according to claim 1 .

7. A method for manufacturing a semiconductor device, comprising: The semiconductor device includes: a semiconductor substrate (12); a lower electrode (14) in contact with the lower surface of the semiconductor substrate; a gate electrode (20); and The semiconductor substrate is an n-type buffer region (44); a drift region (46) which is an n-type region having a lower n-type impurity concentration than the buffer region and which is in contact with the buffer region from above; a p-type first region (48, 50) in contact with the drift region; an n-type second region (52, 54) separated from the drift region by the first region; a p-type collector region (40), an n-type cathode region (42), and an n-type specific region (41) having a lower n-type impurity concentration than the cathode region, which are arranged between the buffer region and the lower surface of the semiconductor substrate; and the gate electrode faces the first region via a gate insulating film, When viewed from a direction perpendicular to the top surface of the semiconductor substrate, the semiconductor device comprises a transistor portion (30) and a diode portion (32), the transistor portion is a portion through which a current flows in response to a gate voltage applied to the gate electrode, the diode portion is a portion through which a current flows in response to a forward bias voltage applied between the first region and the lower electrode, the collector region (40) is disposed in at least a part of the transistor portion, and at least a part of it is exposed on the lower surface of the semiconductor substrate; the cathode region (42) is disposed in at least a part of the diode portion and is exposed on the lower surface of the semiconductor substrate; the specific region (41) is disposed in at least a part of the diode section and is disposed between the cathode region and the buffer region, The manufacturing method includes: a first implantation step of selectively implanting p-type impurities into an area of ​​the lower surface of the semiconductor substrate corresponding to the collector region; a second implantation step of selectively implanting n-type impurities into an area of ​​the lower surface of the semiconductor substrate corresponding to the cathode region; and a depth from the bottom surface of the semiconductor substrate of the n-type impurity implanted in the second implantation step is smaller than a depth from the bottom surface of the semiconductor substrate of the p-type impurity implanted in the first implantation step; Manufacturing method.

8. The first injection step includes: forming a first mask on a lower surface of the semiconductor substrate to cover at least a portion of the diode portion; implanting the p-type impurity through the first mask; It is equipped with The second injection step includes: forming a second mask on the lower surface of the semiconductor substrate to cover at least a portion of the transistor portion; implanting the n-type impurity through the second mask; It is equipped with The manufacturing method according to claim 7 , wherein the opening region of the first mask and the opening region of the second mask partially overlap each other.

9. The manufacturing method according to claim 8 , wherein an end position of the first mask is located within the diode portion.

10. 10. The manufacturing method according to claim 9, wherein a distance (D1) between an end position of the first mask and an end position of the second mask is greater than an implantation depth (T1) of the p-type impurity implanted in the first implantation step.

11. 11. The manufacturing method according to claim 8, wherein the second mask further comprises a plurality of divided masks arranged in the diode portion at intervals from each other.

12. the first implantation step is performed so that a concentration distribution curve (DC2) of the p-type impurity in the collector region in a depth direction from the lower surface of the semiconductor substrate toward the inside has a first peak (PK1) and a second peak (PK2) located more inward than the first peak; The manufacturing method according to claim 7 , wherein the second peak is higher than the first peak.

Images