Adjustment circuit, adjustment method using the same, current adjustment circuit, current adjustment method using the same, operational amplifier and offset adjustment method

Abstract

To provide a technique that can more reliably achieve desired circuit operation by cutting off an element to be cut off.SOLUTION: Adjustment circuits 151, 152, and 155 are arranged between a first node and a second node. The adjustment circuits have a plurality of elements to be cut F1 to F4, F7, and F8 connected in series, and are configured such that when none of the plurality of elements to be cut is cut, the first node and the second node are electrically connected via the adjustment circuits, and when at least one of the plurality of elements to be cut is cut, the adjustment circuits are open when viewed from the first node.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to an adjustment circuit, an adjustment method using the same, a current adjustment circuit, a current adjustment method using the same, an operational amplifier, and an offset adjustment method. [Background technology]

[0002] A fuse is provided in a circuit and is blown as needed to interrupt a circuit path and realize a specific function. For example, Patent Document 1 discloses an operational amplifier equipped with a differential circuit that has a function of adjusting the input offset voltage by blowing a fuse. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-318337

[0004] [overview] However, the present inventors have come to recognize the following problem: When the fuse described in Patent Document 1 is cut using, for example, a laser, the fuse may not be cut reliably due to inaccuracies in the laser device, etc. As a result, the path within the circuit may not be properly cut off, and the desired circuit operation may not be achieved.

[0005] The present disclosure has been made in light of these circumstances, and one of its exemplary purposes is to provide a technique that can more reliably achieve desired circuit operation by disconnecting an element to be disconnected.

[0006] One aspect of the present disclosure is an adjustment circuit disposed between a first node and a second node. The adjustment circuit has a plurality of disconnection target elements connected in series, and is configured such that when none of the plurality of disconnection target elements are disconnected, the first node and the second node are electrically connected via the adjustment circuit, and when at least one of the plurality of disconnection target elements is disconnected, the adjustment circuit is open as seen from the first node.

[0007] Another aspect of the present disclosure is also an adjustment circuit. The adjustment circuit is disposed between a first node and a second node. The adjustment circuit includes a signal generation circuit and a plurality of disconnection target elements, and is configured such that, when none of the plurality of disconnection target elements are disconnected, the signal generation circuit outputs a first voltage to the first node, and when at least one of the plurality of disconnection target elements is disconnected, the signal generation circuit outputs a second voltage to the first node.

[0008] Another aspect of the present disclosure is an adjustment method. The adjustment method uses an adjustment circuit arranged between a first node and a second node. The adjustment circuit has a plurality of elements to be cut off connected in series, and is configured so that when none of the plurality of elements to be cut off are cut off, the first node and the second node are electrically connected via the adjustment circuit, and when at least one element to be cut off among the plurality of elements to be cut off is cut off, the adjustment circuit is open as seen from the first node. The adjustment method includes a cutting step of cutting at least one element to be cut off among the plurality of elements to be cut off.

[0009] Another aspect of the present disclosure is also an adjustment method. The adjustment method uses an adjustment circuit arranged between a first node and a second node. The adjustment circuit has a signal generation circuit and a plurality of elements to be disconnected, and is configured so that when none of the plurality of elements to be disconnected is disconnected, the signal generation circuit outputs a first voltage to the first node, and when at least one element to be disconnected of the plurality of elements to be disconnected is disconnected, the signal generation circuit outputs a second voltage to the first node. The adjustment method includes a disconnection step of disconnecting at least one element to be disconnected of the plurality of elements to be disconnected.

[0010] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic block diagram of an operational amplifier according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a circuit diagram of an input stage according to the embodiment. [Figure 3] FIG. 3 is a circuit diagram of the current adjustment circuit according to the embodiment. [Figure 4] FIG. 4 is a diagram showing an example of the layout of two fuses connected in series in a connection path. [Figure 5] FIG. 5 is a circuit diagram for explaining an example of the operation of the current adjustment circuit after the fuse is cut. [Figure 6] FIG. 6 is a diagram for explaining the amount by which the input offset voltage can be adjusted by sinking current through each of the first current path, the second current path, the third current path, and the fourth current path. [Figure 7] FIG. 7 is a diagram showing the layout of fuses provided in connection paths according to the first modification. [Figure 8] FIG. 8 is a circuit diagram of a control circuit according to the second embodiment. [Figure 9]FIG. 9 is a circuit diagram of a current adjusting circuit according to the third embodiment. [Figure 10] FIG. 10 is a circuit diagram of a voltage generating circuit according to an application example.

[0012] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] An adjustment circuit according to one embodiment is disposed between a first node and a second node. The adjustment circuit has a plurality of elements to be disconnected connected in series, and is configured such that when none of the plurality of elements to be disconnected is disconnected, the first node and the second node are electrically connected via the adjustment circuit, and when at least one of the plurality of elements to be disconnected is disconnected, the adjustment circuit is open as viewed from the first node.

[0014] With this configuration, even if some of the disconnection target elements among the multiple disconnection target elements fail to be disconnected, the adjustment circuit can be opened as long as at least one of the disconnection target elements is disconnected. Therefore, by disconnecting the disconnection target elements, the connection state of the adjustment circuit can be accurately adjusted, making it possible to more reliably achieve the desired circuit operation.

[0015] In one embodiment, the plurality of elements to be cut may each be a fuse, and the plurality of fuses may be arranged side by side in the fuse width direction.

[0016] In one embodiment, the adjustment circuit may be configured so that when none of the multiple elements to be cut are cut, the voltage of the first node is a first voltage, and when at least one of the multiple elements to be cut is cut, the voltage of the first node is a second voltage.

[0017] According to one embodiment, an adjustment circuit is disposed between a first node and a second node, and includes a signal generation circuit and a plurality of disconnection target elements, and is configured such that, when none of the plurality of disconnection target elements is disconnected, the signal generation circuit outputs a first voltage to the first node, and when at least one of the plurality of disconnection target elements is disconnected, the signal generation circuit outputs a second voltage to the first node.

[0018] With this configuration, even if some of the disconnection target elements fail to be disconnected, as long as at least one of the disconnection target elements is disconnected, the voltage output by the adjustment circuit can be adjusted to the desired voltage. Therefore, by disconnecting the disconnection target elements, the generated signal can be accurately adjusted, making it possible to more reliably achieve the desired circuit operation.

[0019] In one embodiment, the signal generating circuit may be an OR circuit. The plurality of elements to be cut may include a first element to be cut and a second element to be cut. The first element to be cut may be disposed between a first input terminal of the OR circuit and a second node. The second element to be cut may be disposed between a second input terminal of the OR circuit and the second node.

[0020] A current adjustment circuit according to one embodiment may adjust the amount of current generated by a current generation circuit that flows through an active load circuit. The current adjustment circuit may include a sink circuit having a switching element that adjusts the amount of current by drawing a current from the current generation circuit in accordance with whether the switching element is on or off, and a control circuit having the adjustment circuit. A voltage corresponding to the voltage of a first node may be input to an input terminal of the switching element. A predetermined voltage may be supplied to the second node. The switching element may be turned on and off depending on whether the voltage of the first node is a first voltage or a second voltage.

[0021] An operational amplifier according to one embodiment may include a current generating circuit and the current adjusting circuit. The current generating circuit may be an input differential pair having a first MOS transistor to which a first input voltage is input and a second MOS transistor to which a second input voltage is input. The sink circuit may adjust the amount of one of the first drain current and the second drain current flowing in the active load circuit by absorbing one of the first drain current flowing in the first MOS transistor and the second drain current flowing in the second MOS transistor.

[0022] In one embodiment, the sink circuit may have two switching elements: a first switching element connected to the drain of the first MOS transistor and a second switching element connected to the drain of the second MOS transistor. The control circuit may have a plurality of adjustment circuits including a first adjustment circuit and a second adjustment circuit. A voltage corresponding to a voltage at a first node of the first adjustment circuit may be input to an input terminal of the first switching element. A voltage corresponding to a voltage at a first node of the second adjustment circuit may be input to an input terminal of the second switching element. The sink circuit may sink the first drain current or the second drain current via the switching element that is turned on, either the first switching element or the second switching element.

[0023] In one embodiment, the sink circuit may include a plurality of current paths each having a switching element and different current sink capabilities. A voltage corresponding to the voltage of the first node of the adjustment circuit may be input to an input terminal of a switching element provided in any one of the plurality of current paths. The sink circuit may be configured to sink one of the first drain current and the second drain current via a current path having an on-state switching element among the plurality of current paths.

[0024] In one embodiment, the switching elements may have priorities defined based on the current sinking capabilities of the corresponding current paths and the standard deviation of the input offset voltages of the operational amplifiers, and a voltage corresponding to the voltage at the first node of the regulation circuit may be input to an input terminal of a switching element having the highest priority among the plurality of switching elements.

[0025] An adjustment method according to one embodiment uses an adjustment circuit disposed between a first node and a second node. The adjustment circuit has a plurality of elements to be disconnected connected in series, and is configured such that when none of the plurality of elements to be disconnected is disconnected, the first node and the second node are electrically connected via the adjustment circuit, and when at least one of the plurality of elements to be disconnected is disconnected, the adjustment circuit is open as viewed from the first node. The adjustment method includes a disconnection step of disconnecting at least one of the plurality of elements to be disconnected.

[0026] With this configuration, even if some of the disconnection target elements among the multiple disconnection target elements fail to be disconnected, the adjustment circuit can be opened as long as at least one of the disconnection target elements is disconnected. Therefore, by disconnecting the disconnection target elements, the connection state of the adjustment circuit can be accurately adjusted, making it possible to more reliably achieve the desired circuit operation.

[0027] In one embodiment, the plurality of disconnection target elements may each be a fuse. The plurality of fuses may be arranged side by side in a width direction of the fuse. The disconnection step may include disconnecting at least one of the plurality of disconnection target elements along the width direction of the plurality of fuses.

[0028] In one embodiment, the adjustment circuit may be configured so that when none of the multiple elements to be cut are cut, the first node is at a first voltage, and when at least one of the multiple elements to be cut is cut, the first node is at a second voltage.

[0029] An adjustment method according to one embodiment uses an adjustment circuit disposed between a first node and a second node. The adjustment circuit includes a signal generating circuit and a plurality of elements to be disconnected, and is configured such that, when none of the plurality of elements to be disconnected is disconnected, the signal generating circuit outputs a first voltage to the first node, and when at least one element to be disconnected of the plurality of elements to be disconnected is disconnected, the signal generating circuit outputs a second voltage to the first node. The adjustment method includes a disconnection step of disconnecting at least one element to be disconnected of the plurality of elements to be disconnected.

[0030] With this configuration, even if some of the disconnection target elements fail to be disconnected, as long as at least one of the disconnection target elements is disconnected, the voltage output by the adjustment circuit can be adjusted to the desired voltage. Therefore, by disconnecting the disconnection target elements, the generated signal can be accurately adjusted, making it possible to more reliably achieve the desired circuit operation.

[0031] A current adjustment method according to one embodiment uses a current adjustment circuit to adjust the amount of current flowing through an active load circuit, out of the current generated by a current generation circuit. The current adjustment circuit may include a sink circuit having a switching element, which adjusts the amount of current by drawing a current from the current generation circuit in accordance with the on / off state of the switching element, and a control circuit having the adjustment circuit. A voltage corresponding to the voltage of a first node may be input to an input terminal of the switching element. A predetermined voltage may be supplied to the second node. The switching element may be controlled to be turned on or off depending on whether the voltage of the first node is a first voltage or a second voltage. The current adjustment method may include the disconnection step.

[0032] An offset adjustment method according to one embodiment is a method for adjusting an input offset voltage of an operational amplifier. The operational amplifier may include a current generation circuit and the current adjustment circuit. The current generation circuit may be an input differential pair having a first MOS transistor to which a first input voltage is input and a second MOS transistor to which a second input voltage is input. The sink circuit may be configured to adjust the amount of one of the first drain current and the second drain current flowing in the active load circuit by absorbing one of the first drain current flowing in the first MOS transistor and the second drain current flowing in the second MOS transistor. The offset adjustment method may include a disconnection step.

[0033] In one embodiment, the sink circuit may have two switching elements: a first switching element connected to the drain of the first MOS transistor; and a second switching element connected to the drain of the second MOS transistor. The control circuit may have a plurality of adjustment circuits, including a first adjustment circuit and a second adjustment circuit. A voltage corresponding to the voltage of a first node of the first adjustment circuit may be input to an input terminal of the first switching element. A voltage corresponding to the voltage of a first node of the second adjustment circuit may be input to an input terminal of the second switching element. The sink circuit may be configured to sink one of the first drain current and the second drain current via a switching element that is turned on, either the first switching element or the second switching element. The disconnecting step may include disconnecting an element to be disconnected included in one of the first adjustment circuit and the second adjustment circuit.

[0034] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0035] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0036] Similarly, "a state in which component C is connected (placed) between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0037] 1 is a schematic block diagram of an operational amplifier 1 according to an embodiment of the present disclosure. As shown in FIG. 1, the operational amplifier 1 according to this embodiment mainly includes an input stage 10, a current adjustment circuit 12, a gain stage 20, an output stage 30, a capacitor C1, a first input terminal INP (non-inverting input terminal), a second input terminal INN (inverting input terminal), and an output terminal OUT.

[0038] A positive power supply voltage VDD and a negative power supply voltage VSS (for example, 0 V) ​​are supplied to the operational amplifier 1. A first input voltage Vinp is input to the first input terminal INP, and a second input voltage Vinn is input to the second input terminal INN. The operational amplifier 1 according to this embodiment has an input offset voltage Vos. The operational amplifier 1 amplifies a voltage obtained by adding the input offset voltage Vos to the difference between the first input voltage Vinp and the second input voltage Vinn, to generate an output voltage Vout.

[0039] The input stage 10 generates a first signal S1 according to the difference between the first input voltage Vinp and the second input voltage Vinn and the input offset voltage Vos. Specifically, the input stage 10 has an input differential pair (current generating circuit) described later, and the input differential pair generates a differential current. The first signal S1 according to this differential current is input to the gain stage 20.

[0040] The current adjustment circuit 12 is configured to adjust the amount of current flowing from the input differential pair of the input stage 10 to the gain stage 20. Specifically, the current adjustment circuit 12 adjusts the amount of current flowing to the gain stage 20 by absorbing a portion of the differential current. This adjusts the input offset voltage Vos of the operational amplifier 1.

[0041] The gain stage 20 functions as an active load circuit for the input stage 10. Specifically, the gain stage 20 amplifies a first signal S1 to generate a second signal S2. The gain stage 20 is provided with a capacitor C1 for phase compensation. The output stage 30 generates an output signal Vout according to the second signal S2.

[0042] 2 is a circuit diagram of an input stage 10 according to this embodiment. The input stage 10 according to this embodiment has an input differential pair 100 composed of a transistor MP1 (first MOS transistor) to which a first input voltage Vinp is input and a transistor MP2 (second MOS transistor) to which a second input voltage Vinn is input. The transistors MP1 and MP2 according to this embodiment are each composed of a P-channel MOS (Metal Oxide Semiconductor) transistor. Note that, although this embodiment describes an example in which the input differential pair 100 is composed of two P-channel MOS transistors, the input differential pair 100 may also be composed of two N-channel MOS transistors.

[0043] The input stage 10 is configured so that a tail current Itail supplied from a current source (not shown) is supplied to the sources of the input differential pair 100 (specifically, the sources of the transistors MP1 and MP2). The base of the transistor MP1 is connected to the first input terminal INP, and the drain of the transistor MP1 is connected to the current adjustment circuit 12 and the gain stage 20. The base of the transistor MP2 is connected to the second input terminal INN, and the drain of the transistor MP2 is connected to the current adjustment circuit 12 and the gain stage 20.

[0044] In this embodiment, a portion of the drain current Ip of transistor MP1 or a portion of the drain current In of transistor MN2 is sunk into the current adjustment circuit 12. For example, when a portion of the drain current Ip of transistor MP1, a current Ip1, is sunk into the current adjustment circuit 12, the remaining drain current Ip2 (=Ip-Ip1) flows into the gain stage 20. When a portion of the drain current In of transistor MP2, a current In1, is sunk into the current adjustment circuit 12, the remaining drain current In2 (=In-In1) flows into the gain stage 20. In this way, the drain currents Ip2 and In2 flowing from the input differential pair 100 to the gain stage 20 are regulated.

[0045] 3 is a circuit diagram of the current adjustment circuit 12 according to this embodiment. The current adjustment circuit 12 adjusts the amount of current (drain current) generated by the input differential pair 100 that flows to the gain stage 20. The current adjustment circuit 12 according to this embodiment includes a sink circuit 120 and a control circuit 140.

[0046] The sink circuit 120 has a switching element and adjusts the amount of current flowing to the gain stage 20 by drawing a current from the input differential pair 100 according to the on / off state of the switching element. More specifically, the sink circuit 120 adjusts the amount of one of the first drain current Ip flowing through the first transistor P1 and the second drain current In flowing through the second transistor P2 by drawing one of the drain currents. The sink circuit 120 according to this embodiment has a switch unit 122 and a group of current paths 130. The group of current paths 130 is provided between the switch unit 122 and a ground node 150 to which ground (reference voltage VSS) is supplied.

[0047] The switch unit 122 is configured to determine the drain current to be absorbed by the sink circuit 120 from the drain current Ip and the drain current In in accordance with control by the control circuit 140. The switch unit 122 has a transistor MN1 (first switching element) and a transistor MN2 (second switching element). The transistors MN1 and MN2 are each formed of an N-channel MOS transistor. The drain of the transistor MN1 is connected to the drain of the transistor MP1, and the drain of the transistor MN2 is connected to the drain of the transistor MP2.

[0048] The sink circuit 120 sinks one of the first drain current Ip and the second drain current In through either the transistor MN1 or the transistor MN2 that is turned on. For example, when the transistor MN1 is on and the transistor MN2 is off, a current Ip1 that is a portion of the first drain current Ip is sinked into the sink circuit 120 (In1=0). On the other hand, when the transistor MN1 is off and the transistor MN2 is on, a current In1 that is a portion of the second drain current In is sinked into the sink circuit 120 (Ip1=0).

[0049] The current path group 130 is configured so that currents Ip1 and In1 flow to be sunk into the sink circuit 120. The current path group 130 according to this embodiment has a plurality of current paths with different current sunk capabilities, specifically, a first current path 132, a second current path 134, a third current path 136, and a fourth current path 138. Note that, although this embodiment describes an example in which the current path group 130 has four current paths, the number of current paths is not limited to four and may be three or less, or five or more.

[0050] The first current path 132 has a transistor MN3 configured as an N-channel MOS transistor and a current source 133. The drain of the transistor MN3 is connected to the source of the switch unit 122. The current source 133 is disposed between the source of the transistor MN3 and the ground node 150.

[0051] The second current path 134 has a transistor MN4 configured as an N-channel MOS transistor and a current source 135. The drain of the transistor MN4 is connected to the source of the switch unit 122. The current source 135 is disposed between the source of the transistor MN4 and the ground node 150.

[0052] The third current path 136 has a transistor MN5 configured as an N-channel MOS transistor and a current source 137. The drain of the transistor MN5 is connected to the source of the switch unit 122. The current source 137 is disposed between the source of the transistor MN5 and the ground node 150.

[0053] The fourth current path 138 has a transistor MN6 configured as an N-channel MOS transistor and a current source 139. The drain of the transistor MN6 is connected to the source of the switch unit 122. The current source 139 is disposed between the source of the transistor MN6 and a ground node 150.

[0054] The operation (on / off) of the transistors MN1 to MN6 is controlled by the control circuit 140, as will be described later.

[0055] The sink circuit 120 absorbs one of the drain currents, the first drain current Ip or the second drain current In, through a current path in which the on-state transistors MN3 to MN6 are provided, out of multiple current paths (first current path 132, second current path 134, third current path 136, and fourth current path 138).

[0056] First current path 132, second current path 134, third current path 136, and fourth current path 138 have different current sink capacities. Specifically, the current sink capacities of current sources 133, 135, 137, and 138 are a reference capacity S multiplied by a power of 2. Specifically, current source 133 has a current sink capacity of S, current source 135 has a current sink capacity of 2S, current source 137 has a current sink capacity of 4S, and current source 139 has a current sink capacity of 8S.

[0057] The transistors MN3 to MN6 may have priorities that are defined based on the current sinking capabilities of the corresponding current paths and the standard deviation σ of the input offset voltage Vos of the operational amplifier 1. As will be described in detail later, in this embodiment, the transistor MN5 has the highest priority.

[0058] The control circuit 140 has first to sixth connection paths 151 to 156 (adjustment circuits) and current sources 171 to 176. The first to sixth connection paths 151 to 156 are each disposed between a first node and a second node.

[0059] In this embodiment, the first connection path 151, the second connection path 152, and the fifth connection path 155 each have a plurality of elements to be cut that are connected in series, and are configured so that when none of the plurality of elements to be cut are cut, the first node and the second node are electrically connected via an adjustment circuit, and when at least one of the plurality of elements to be cut is cut, the adjustment circuit is open as seen from the first node. Furthermore, these connection paths are configured so that when none of the plurality of elements to be cut are cut, the voltage of the first node is a first voltage, and when at least one of the plurality of elements to be cut is cut, the voltage of the first node is a second voltage.

[0060] The first connection path 151 is arranged between a node 161 (first node) connected to the gate of the transistor MN1 and a ground node 150 (second node). The first connection path 151 is configured by, in order from the node 161 side, a first resistor R1, a first fuse F1, and a second fuse F2 connected in series. One end of the first resistor R1 opposite to the first fuse F1 is connected to the gate of the transistor MN1. One end of the second fuse F2 opposite to the first fuse F1 is connected to the ground node 150.

[0061] The second connection path 152 is arranged between a node 162 (first node) connected to the gate of the transistor MN2 and a ground node 150 (second node). The second connection path 152 is configured by, in order from the node 162 side, a second resistor R2, a third fuse F3, and a fourth fuse F4 connected in series. One end of the second resistor R2 opposite to the third fuse F3 is connected to the gate of the transistor MN2. One end of the fourth fuse F4 opposite to the third fuse F3 is connected to the ground node 150.

[0062] The third connection path 153 is arranged between a node 163 (first node) connected to the gate of the transistor MN3 and a ground node 150 (second node). The third connection path 153 is configured by, in this order from the node 163 side, a third resistor R3 and a fifth fuse F5 connected in series. One end of the third resistor R3 opposite to the fifth fuse F5 is connected to the gate of the transistor MN3. One end of the fifth fuse F5 opposite to the third resistor R3 is connected to the ground node 150.

[0063] The fourth connection path 154 is arranged between a node 164 (first node) connected to the gate of the transistor MN4 and the ground node 150 (second node). The fourth connection path 154 is configured by, in this order from the node 164 side, connecting a fourth resistor R4 and a sixth fuse F6 in series. One end of the fourth resistor R4 opposite to the sixth fuse F6 is connected to the gate of the transistor MN4. One end of the sixth fuse F6 opposite to the fourth resistor R4 is connected to the ground node 150.

[0064] The fifth connection path 155 is arranged between a node 165 (first node) connected to the gate of the transistor MN5 and the ground node 150 (second node). The fifth connection path 155 is configured by, in order from the node 165 side, a fifth resistor R5, a seventh fuse F7, and an eighth fuse F8 connected in series. One end of the fifth resistor R5 opposite to the seventh fuse F7 is connected to the gate of the transistor MN5. One end of the eighth fuse F8 opposite to the seventh fuse F7 is connected to the ground node 150.

[0065] The sixth connection path 154 is arranged between a node 166 (first node) connected to the gate of the transistor MN6 and a ground node 150 (second node). The sixth connection path 156 is configured by, in order from the node 166 side, connecting a sixth resistor R6 and a ninth fuse F9 in series. One end of the sixth resistor R6 opposite to the ninth fuse F9 is connected to the gate of the transistor MN6. One end of the ninth fuse F9 opposite to the sixth resistor R6 is connected to the ground node 150. The first to sixth resistors R1 to R6 are resistors for gate protection.

[0066] When none of the first to ninth fuses F1 to F9 is blown, the nodes 161 to 166 are electrically connected to the ground node 150 via the corresponding connection paths among the first to sixth connection paths 151 to 156, respectively.

[0067] The first to ninth fuses F1 to F9 may be cut by, for example, a laser. When any of the first to ninth fuses F1 to F9 is cut, the connection path having the cut fuse is interrupted. When at least one of the multiple fuses in a connection path having multiple fuses (first connection path 151, second connection path 152, and fifth connection path 155) is cut, the connection path becomes open as seen from the first node.

[0068] For example, when at least one of the first fuse F1 and the second fuse F2 is cut, the first connection path 151 is open when viewed from the node 161. When at least one of the third fuse F3 and the fourth fuse F4 is cut, the second connection path 152 is open when viewed from the node 162. When the fifth fuse F5 is cut, the third connection path 153 is open when viewed from the node 163. When the sixth fuse F6 is cut, the fourth connection path 154 is open when viewed from the node 164. When at least one of the seventh fuse F7 and the eighth fuse F8 is cut, the fifth connection path 155 is open when viewed from the node 165. When the ninth fuse F9 is cut, the sixth connection path 164 is open.

[0069] The current sources 171 to 176 are arranged between a power supply voltage node 170 to which a power supply voltage VDD is supplied and the first nodes of the corresponding connection paths among the first connection path 151 to the sixth connection path 156, respectively.

[0070] 4 is a diagram showing an example of the layout of two fuses F11 and F12 connected in series in a connection path. The fuses F11 and F12 shown in FIG. 4 may be the first fuse F1 and the second fuse F2 of the first connection path 151, the third fuse F3 and the fourth fuse F4 of the second connection path 152, or the seventh fuse F7 and the eighth fuse F8 of the fifth connection path 155.

[0071] In FIG. 4, the length direction of the fuses F11 and F12 is indicated by the x-axis, and the width direction of the fuses F11 and F12 is indicated by the y-axis, with the x-axis and y-axis being perpendicular to each other. As shown in FIG. 4, the fuses F11 and F12 are arranged side by side in the width direction (y-axis direction). This allows the fuses F11 and F12 to be simultaneously blown, for example, along the cut line CL1 indicated by the dashed line in FIG. 4. This eliminates the need to blow the fuses F11 and F12 individually, allowing the fuses F11 and F12 to be blown more efficiently. Note that FIG. 4 shows an example in which the fuses F11 and F12 are arranged parallel to each other, but the fuses F11 and F12 may also be arranged diagonally.

[0072] Here, we will explain an offset adjustment method (including a current adjustment method) for adjusting the input offset voltage Vos of the operational amplifier 1. The offset adjustment method (including a current adjustment method) according to this embodiment includes a cutting step of cutting at least one fuse among a plurality of fuses included in the adjustment circuit (first connection path 151, second connection path 152, and fifth connection path 155).

[0073] For example, the disconnection step may include disconnecting a fuse included in one of the connection circuits of the first connection path 151 and the second connection path 152. As a result, one of the transistors MN1 and MN2 is turned on and the other is turned off. As a result, one of the first drain current Ip and the second drain current In is drawn into the sink circuit 120.

[0074] The disconnecting step may also include disconnecting fuses included in the third to sixth connection paths 153 to 156 corresponding to the transistors MN3 to MN6. For example, at least one of the two fuses (the seventh fuse F7 and the eighth fuse F8) included in the fifth connection path 155 may be disconnected. This turns on the transistor MN5, allowing a current to flow through the third current path 136. Similarly, disconnecting the fuses of the corresponding connection paths allows a current to flow through the other current paths.

[0075] As a result of the current being drawn into the sink circuit 120, the amount of current flowing from the input differential pair 100 to the gain stage 20 is adjusted, affecting the stages subsequent to the input stage 10 (including the gain stage 20 and the output stage 30). As a result, the input offset voltage Vos of the operational amplifier 1 is adjusted. In more detail, the input offset voltage Vos of the entire circuit of the operational amplifier 1 appears to have been adjusted.

[0076] Furthermore, when multiple fuses are arranged side by side in the width direction, the cutting step may cut multiple cutting target elements along the width direction of the multiple fuses, thereby making it possible to reliably and easily cut at least one fuse out of the multiple fuses.

[0077] An example of the operation of the current adjustment circuit 12 according to this embodiment will be described below. Fig. 5 is a circuit diagram for explaining an example of the operation of the current adjustment circuit 12 after the fuses are cut. In the example shown in Fig. 5, the first fuse F1, the second fuse F2, the fifth fuse F5, and the seventh fuse F7 are cut.

[0078] A voltage corresponding to the first node of the corresponding connection path is input to the gates of transistors MN1 to MN6, and their operation is controlled according to that voltage. Specifically, transistors MN1 to MN6 are controlled to be on or off according to whether the voltage at the first node of the corresponding connection path is a first voltage or a second voltage. This adjusts the current drawn by sink circuit 120.

[0079] A first connection path 151 seen from the gate of transistor MN1, a third connection path 153 seen from the gate of transistor MN3, and a fifth connection path 155 seen from the gate of transistor MN5 are all open. In addition, the gate of transistor MN2 is electrically connected to ground node 150 via second connection path 152, the gate of transistor MN4 is electrically connected to ground node 150 via fourth connection path 154, and the gate of transistor MN6 is electrically connected to ground node 150 via sixth connection path 156.

[0080] Because the first connection path 151 is open, the voltage V1 at the node 161 becomes a high voltage (second voltage) corresponding to the power supply voltage VDD. Therefore, a high voltage is input to the gate of the transistor MN1, turning on the transistor MN1. As a result, the sink circuit 120 begins to absorb a current Ip1, which is a part of the drain current Ip from the transistor MP1, via the transistor MN1.

[0081] The resistance of the second connection path 152 is sufficiently small. Therefore, most of the power supply voltage VDD drops across the current source 172, and the voltage V2 at the node 162 becomes substantially the reference voltage VSS, i.e., a low voltage (first voltage). Therefore, a low voltage is input to the gate of the transistor MN2, and the transistor MN2 is turned off. As a result, the drain current In from the transistor MP2 does not flow through the transistor MN2 (In1=0).

[0082] Voltages V3 and V5 at nodes 163 and 165 are high, as is node 161. This turns on transistors MN3 and MN5. Voltages V4 and V6 at nodes 164 and 166 are low, as is node 162. This turns off transistors MN4 and MN6.

[0083] With the transistors MN3 and MN5 turned on, a current Ip11 flows through the first current path 132, and a current Ip13 flows through the third current path 136. On the other hand, since the transistors MN4 and MN6 are off, no current flows through the second current path 134 and the fourth current path 138 (Ip12=0, Ip14=0).

[0084] 5, the current Ip1 (=Ip11+Ip13) is sunk from the transistor MP1 into the sink circuit 120. The input offset voltage Vos of the operational amplifier 1 is adjusted to be smaller in accordance with the sunk current Ip1.

[0085] Here, transistor MN1 and transistor MN2 are switching elements that determine which of transistors MP1 and MP2 of input differential pair 100 will absorb the drain current, so their operation is important. Therefore, in this embodiment, first connection path 151 and second connection path 152 each have two fuses arranged in series. Therefore, even if one of the fuses fails to blow, the other fuse can be blown, so the connection path that should be opened can be opened more reliably. As a result, it is possible to more accurately control the operation of transistor MN1 and transistor MN2.

[0086] In this way, by adjusting the number of fuses in the corresponding connection paths depending on the importance of the transistors MN1 to MN6, it is possible to more reliably achieve appropriate current adjustment.

[0087] 6 is a diagram illustrating the amount by which the input offset voltage Vos can be adjusted (hereinafter also referred to as "adjustment voltage") by absorbing current through each of the first current path 132, the second current path 134, the third current path 136, and the fourth current path 138. FIG. 6 shows the distribution of the input offset voltage Vos of the operational amplifier 1. The distribution of the input offset voltage Vos shown in FIG. 6 is a normal distribution with 0 V as the mean.

[0088] 6 are respectively regulated voltages resulting from the current being sunk by any one of the first current path 132, the second current path 134, the third current path 136, and the fourth current path 138. Specifically, ΔV1 is the regulated voltage resulting from the first current path 132 sunk of the current Ip11, ΔV2 is the regulated voltage resulting from the second current path 134 sunk of the current Ip12, ΔV3 is the regulated voltage resulting from the third current path 136 sunk of the current Ip13, and ΔV4 is the regulated voltage resulting from the fourth current path 138 sunk of the current Ip14.

[0089] The larger the amount of current to be drawn, the larger the adjustment voltage. Therefore, in this embodiment, since 0 < Ip11 < Ip12 < Ip13 < Ip14, it follows that 0 < ΔV1 < ΔV2 < ΔV3 < ΔV4. Here, assuming that the standard deviation of the input offset voltage Vos is σ, it is assumed that ΔV1 < ΔV2 < σ < ΔV3 < 2σ < 3σ = ΔV4 holds.

[0090] Here, when it is desired to keep the input offset voltage Vos within ±σ, in most cases, the input offset voltage Vos can be kept within ±σ by the adjustment voltage of ΔV3. Therefore, by opening the fifth connection path 155 and passing the current Ip13 through the third current path 136, the input offset voltage Vos can often be kept within ±σ. For this reason, the chance of cutting the fuse of the fifth connection path 155 increases.

[0091] Therefore, in this embodiment, among the transistors MN3 to MN6, the transistor MN5 has the highest priority, and the fifth connection path 155 corresponding to the transistor MN5 is provided with two fuses (the seventh fuse F7 and the eighth fuse F8) arranged in series. For this reason, when cutting the fuse, even if the cutting of one fuse fails, it is only necessary to be able to cut the other fuse, so it is possible to more reliably open the fifth connection path 155. As a result, it becomes possible to more accurately keep the input offset voltage Vos within the target value.

[0092] For cutting the fuse, a cutting device using a laser is used. However, due to poor accuracy of the cutting device or the like, there may be cases where the fuse cannot be cut. The reason for the inability to cut the fuse is presumably due to insufficient laser output and cutting errors due to misalignment of the position where the laser is irradiated. As a result, the yield of the device (for example, an operational amplifier or the like) including the fuse to be cut may deteriorate.

[0093] The operational amplifier 1 according to this embodiment includes a first connection path 151 (adjustment circuit) disposed between a node 161 (first node) and a ground node 150 (second node). The first connection path 151 includes a first fuse F1 and a second fuse F2 (multiple disconnection target elements) connected in series. The first connection path 151 is configured such that, when neither the first fuse F1 nor the second fuse F2 is disconnected, the node 161 and the ground node 150 are electrically connected via the first connection path 151, and when at least one fuse (disconnection target element) of the first fuse F1 and the second fuse F2 is disconnected, the first connection path 151 is open as seen from the node 161.

[0094] According to this configuration, even if cutting either the first fuse F1 or the second fuse F2 fails, as long as the other fuse can be cut, the first connection path 151 can be opened as seen from the node 161. Therefore, by cutting the element to be cut, the connection state of the first connection circuit 151 can be accurately adjusted, and the desired circuit operation can be more reliably achieved. The second connection path 152 and the fifth connection path 155, which are configured similarly to the first connection path 151, can also achieve the same effect.

[0095] Moreover, the operational amplifier 1 according to this embodiment includes a current adjustment circuit 12 having a sink circuit 120 and a control circuit 140. The sink circuit 120 has transistors MN1 to MN6 (switching elements), and adjusts the amount of current flowing from the input differential pair 100 to the gain stage 20 (active load circuit) by drawing in a current corresponding to the on / off state of the switching elements from the input differential pair 100 (current generating circuit). The control circuit 140 has a first connection path 151 (adjustment circuit).

[0096] A voltage corresponding to the voltage of node 161 is input to the gate (input terminal of the switching element) of transistor MN1. A reference voltage VSS (predetermined voltage) is supplied to node 150. Transistor MN1 is controlled to be on or off depending on whether the voltage of node 150 is a low voltage (first voltage) or a high voltage (second voltage). Here, first connection circuit 151 is configured so that node 161 is at a low voltage (first voltage) when neither first fuse F1 nor second fuse F2 connected in series is cut, and so that node 161 is at a high voltage (second voltage) when at least one of first fuse F1 and second fuse F2 is cut.

[0097] According to this configuration, the first connection path 151 can be more reliably opened as described above, and therefore the voltage of the node 161 can be more accurately controlled. As a result, the amount of current absorbed by the current adjustment circuit can be more accurately adjusted.

[0098] The operational amplifier 1 according to this embodiment also includes an input differential pair 100 (current generating circuit) and a current adjusting circuit 12. The input differential pair 100 includes a transistor MP1 (first MOS transistor) to which a first input voltage Vinp is input and a transistor MP2 (second MOS transistor) to which a second input voltage Vinn is input. The sink circuit 120 adjusts the amount of one of the first drain current and the second drain current flowing in the gain stage 20 (active load circuit) by absorbing one of the first drain current flowing in the transistor MP1 and the second drain current flowing in the transistor MP2.

[0099] According to this configuration, the drain current is absorbed by the sink circuit 120, thereby adjusting the amount of current flowing through the gain stage 20, and affecting the stages subsequent to the input stage 10 (including the gain stage 20 and the output stage 30). This allows the input offset voltage Vos of the operational amplifier 1 to be adjusted.

[0100] (First Modification) FIG. 7 is a diagram showing the layout of fuses F13 to F16 provided in a connection path 180 according to a first modification. In FIG. 7, the x-axis and y-axis are axes perpendicular to each other. The connection path 180 according to the first modification includes fuses F13 to F16 connected in series. These fuses F13 to F16 are arranged side by side in the width direction (x-axis direction). However, these fuses F13 to F16 are arranged with a shift in the length direction (y-axis direction). Even if the fuses F13 to F16 are shifted in the length direction in this way, as long as the amount of shift is within an appropriate range, the fuses F13 to F16 can be cut along the widthwise cut line CL2 indicated by the dashed line.

[0101] (Second Modification) In the above embodiment, an example has been described in which the connection path constituting the adjustment circuit has two fuses connected in series. However, the adjustment circuit is not limited to this and may have three or more fuses connected in series.

[0102] (Third Modification) In the above embodiment, an example has been described in which N-channel MOS transistors (transistors MN1 to MN6) are used as switching elements. However, the switching elements are not limited to this, and may be analog switches that combine P-channel MOS transistors and N-channel MOS transistors, or may be P-channel MOS transistors.

[0103] (Fourth Modification) The regulation circuit may have different numbers of series-connected fuses depending on the priority of the switching elements. For example, let us assume that transistors MN1 and MN2 have the highest priority, followed by the switching elements provided in one of the multiple current paths. In this case, let us assume that the number of fuses in the two regulation circuits corresponding to transistors MN1 and MN2, respectively, is N1, the number of fuses in the regulation circuit corresponding to the switching element with the next highest priority is N2, and the number of fuses in the regulation circuit corresponding to the remaining switching elements is N3. Then, N3 <N2<N1としてもよい。

[0104] (Variation 5) In the above embodiment, the first node of the connection path is directly connected to the gate of the corresponding transistor. However, the first node of the connection path may be connected to the gate of the corresponding transistor via any circuit (such as an OR circuit).

[0105] (Second embodiment) 8 is a circuit diagram of a control circuit 200 according to the second embodiment. The control circuit 200 according to the second embodiment may be provided in the current adjustment circuit 12, instead of the control circuit 140 according to the first embodiment. The control circuit 200 according to the second embodiment differs from the control circuit 140 according to the first embodiment in that the switching element corresponding to the connection path in which the element to be disconnected is disconnected is turned off. The control circuit 200 according to the second embodiment has first to sixth connection paths 211 to 216 (adjustment circuits) and current sources 231 to 236.

[0106] The first connection path 211 is arranged between a node 221 (first node) connected to the gate of the transistor MN1 and a power supply voltage node 210 (second node). The first connection path 211 is configured by connecting a fuse F22 and a fuse F21 in series in this order from the node 221 side.

[0107] The second connection path 212 is arranged between a node 222 (first node) connected to the gate of the transistor MN2 and a power supply voltage node 210 (second node). The second connection path 212 is configured by connecting a fuse F24 and a fuse F23 in series in this order from the node 222 side.

[0108] The third connection path 213 is arranged between a node 223 (first node) connected to the gate of the transistor MN3 and the power supply voltage node 210 (second node). The third connection path 213 is formed by a fuse F25.

[0109] The fourth connection path 214 is arranged between a node 224 (first node) connected to the gate of the transistor MN4 and the power supply voltage node 210 (second node). The fourth connection path 214 is formed by a fuse F26.

[0110] The fifth connection path 215 is arranged between a node 225 (first node) connected to the gate of the transistor MN5 and the power supply voltage node 210 (second node). The fifth connection path 215 is configured by connecting a fuse F28 and a fuse F27 in series in this order from the node 225 side.

[0111] The sixth connection path 214 is arranged between a node 226 (first node) connected to the gate of the transistor MN6 and the power supply voltage node 210 (second node). The sixth connection path 216 is formed by a fuse F29.

[0112] When none of the fuses F21 to F29 is blown, the nodes 221 to 226 are electrically connected to the power supply voltage node 210 via the corresponding connection paths among the first connection path 211 to the sixth connection path 216, respectively.

[0113] When any of the fuses F21 to F29 is blown, the connection path having the blown fuse is open when viewed from the corresponding first node. When at least one of the fuses in a connection path having multiple fuses (the first connection path 211, the second connection path 212, and the fifth connection path 215) is blown, the connection path is open when viewed from the corresponding first node.

[0114] The current sources 231 to 236 are each arranged between the ground node 230 and the first node of the corresponding connection path among the first connection path 211 to the sixth connection path 216.

[0115] In the control circuit 200 according to the second embodiment, the transistors corresponding to the connection paths having blown fuses are turned off, and the transistors corresponding to the connection paths not having blown fuses are turned on.

[0116] For example, assume that neither the fuse F21 nor the fuse F22 of the first connection path 211 is blown. In this case, the voltage V11 of the node 221 becomes substantially the high voltage (first voltage) of the power supply voltage VDD. As a result, the transistor MN1 connected to the node 221 turns on.

[0117] On the other hand, assume that at least one of the fuses F21 and F22 of the first connection path 211 is blown. In this case, the voltage V11 of the node 221 becomes substantially the low voltage (second voltage) of the reference voltage VSS. As a result, the transistor MN1 connected to the node 221 is turned off.

[0118] The other transistors MN2 to MN6 are controlled in the same manner as the transistor MN1, depending on the blown state of the fuse.

[0119] The operational amplifier using the control circuit 200 according to this embodiment can also achieve the same effects as the operational amplifier 1 according to the first embodiment.

[0120] (Third embodiment) 9 is a circuit diagram of a current adjustment circuit 40 according to the third embodiment. In FIG. 9, components having substantially the same functions as those in the current adjustment circuit 12 according to the first embodiment are denoted by the same reference numerals, and their description will be omitted where appropriate. The current adjustment circuit 40 according to the third embodiment differs from the adjustment circuits according to the first or second embodiment mainly in the configuration of the adjustment circuit included in the control circuit 420. The current adjustment circuit 40 according to the third embodiment includes a sink circuit 400 and a control circuit 420.

[0121] The sink circuit 400 according to this embodiment includes a switch unit 122 and a current path group 410. The current path group 410 is provided between the switch unit 122 and a ground node 430. The current path group 410 according to this embodiment includes a first current path 132 and a second current path 134.

[0122] The control circuit 420 according to this embodiment includes a first adjustment circuit 431, a second adjustment circuit 432, a third adjustment circuit 433, a fourth adjustment circuit 434, and current sources 461-468.

[0123] The first adjustment circuit 431 is disposed between a node 451 (first node) connected to the gate of the transistor MN1 and a ground node 430 (second node). The first adjustment circuit 431 includes an OR circuit 441 (signal generating circuit) and a plurality of fuses F31 and F32 (elements to be cut). The OR circuit 441 outputs a voltage Vo1 according to the cut states of the fuses F31 and F32. The first adjustment circuit 431 is configured such that when neither the fuses F31 nor F32 is cut, the OR circuit 441 outputs a low voltage (first voltage) to the node 451, and when at least one of the fuses F31 and F32 is cut, the OR circuit 441 outputs a high voltage (second voltage) to the node 451.

[0124] An output terminal of the OR circuit 441 is connected to a node 451. A fuse F31 is disposed between a first input terminal of the OR circuit 441 and the ground node 430. A fuse F32 is disposed between a second input terminal of the OR circuit 441 and the ground node 430.

[0125] The second adjustment circuit 432, the third adjustment circuit 433, and the fourth adjustment circuit 434 are configured similarly to the first adjustment circuit 431.

[0126] The second adjustment circuit 432 is arranged between a node 452 (first node) connected to the gate of the transistor MN2 and a ground node 430 (second node). The second adjustment circuit 432 has an OR circuit 442 and a plurality of fuses F33 and F34. The OR circuit 442 outputs a voltage Vo2 according to the cut states of the fuses F33 and F34. The output terminal of the OR circuit 442 is connected to the node 452. The fuse F33 is arranged between a first input terminal of the OR circuit 442 and the ground node 430. The fuse F34 is arranged between a second input terminal of the OR circuit 442 and the ground node 430.

[0127] The third adjustment circuit 433 is arranged between a node 453 (first node) connected to the gate of the transistor MN3 and a ground node 430 (second node). The third adjustment circuit 433 has an OR circuit 443 and a plurality of fuses F35 and F36. The OR circuit 443 outputs a voltage Vo3 according to the cut states of the fuses F35 and F36. The output terminal of the OR circuit 443 is connected to the node 453. The fuse F35 is arranged between a first input terminal of the OR circuit 443 and the ground node 430. The fuse F36 is arranged between a second input terminal of the OR circuit 443 and the ground node 430.

[0128] The fourth adjustment circuit 434 is arranged between a node 454 (first node) connected to the gate of the transistor MN4 and a ground node 430 (second node). The fourth adjustment circuit 434 has an OR circuit 444 and a plurality of fuses F37 and F38. The OR circuit 444 outputs a voltage Vo4 according to the cut states of the fuses F37 and F38. The output terminal of the OR circuit 444 is connected to the node 454. The fuse F37 is arranged between a first input terminal of the OR circuit 444 and the ground node 430. The fuse F38 is arranged between a second input terminal of the OR circuit 444 and the ground node 430.

[0129] Current sources 461-468 are arranged between power supply voltage node 460 and one end (the end opposite to ground node 430) of the corresponding fuse among fuses F31-F38.

[0130] According to the control circuit 420 of this embodiment, for example, in the first adjustment circuit 431, when both of the multiple fuses F31 and F32 are cut, even if cutting one of the fuses fails, as long as the other fuse is cut, the OR circuit 441 can output the desired voltage (high voltage).

[0131] As described above, according to the control circuit 420 of this embodiment, even if some of the fuses F31 and F32 fail to blow, as long as at least one fuse is blown, the voltage generated by the first adjustment circuit 431 can be adjusted to the desired voltage. Therefore, by blowing the fuses, the generated signal can be accurately adjusted, and the desired circuit operation can be more reliably achieved. Furthermore, the second adjustment circuit 432, the third adjustment circuit 433, and the fourth adjustment circuit 434 can also achieve the same effects as the first adjustment circuit 431.

[0132] Furthermore, the current adjustment circuit 40 having the control circuit 420 and the operational amplifier including this current adjustment circuit 40 can respectively achieve the same effects as the current adjustment circuit 12 and the operational amplifier 1 according to the first embodiment.

[0133] In this embodiment, an example has been described in which an OR circuit is used as the signal generation circuit. However, the signal generation circuit may be a circuit that operates in response to three or more input signals. For example, the signal generation circuit may be configured to output different signals when at least one of the three or more input signals is high and when all of the three or more input signals are low. In this case, a disconnection target element corresponding to each of the three or more input signals may be provided, and the signal input to the signal generation circuit may change depending on the disconnection of the disconnection target element. Even in this case, it is possible to cause the signal generation circuit to generate the desired signal even if disconnection of one of the three or more disconnection target elements fails.

[0134] (Application example) An application example of the connection paths (adjustment circuits) described in the first and second embodiments will be described. Fig. 10 is a circuit diagram of a voltage generation circuit 50 according to the application example. The voltage generation circuit 50 is configured to generate a reference voltage Vref. The voltage generation circuit 50 includes resistors R11 to R14, a first connection path 501, a second connection path 502, a third connection path 503, a fourth connection path 504, and an output terminal OUT.

[0135] One end of the resistor R11 is connected to a power supply voltage node 512 (second node) to which a power supply voltage VDD is supplied, and the other end (first node) of the resistor R11 is connected to one end of a resistor R12. The other end of the resistor R12 is connected to the output terminal OUT and one end of a resistor R13. The other end of the resistor R13 is connected to one end (first node) of a resistor R14. The other end of the resistor R14 is connected to a ground node 514 (second node).

[0136] The first connection path 501 and the second connection path 502 are each arranged between the other end of the resistor R11 and a power supply voltage node 512. The first connection path 501 is configured by connecting a fuse F41 and a fuse F42 in series in this order from the power supply voltage node 512 side. The second connection path 502 is configured by connecting a fuse F43 and a fuse F44 in series in this order from the power supply voltage node 512 side.

[0137] The third connection path 503 and the fourth connection path 504 are each arranged between one end of the resistor R14 and a ground node 514. The third connection path 503 is configured by connecting a fuse F46 and a fuse F45 in series in this order from the ground node 514 side. The second connection path 502 is configured by connecting a fuse F48 and a fuse F47 in series in this order from the ground node 514 side.

[0138] The reference voltage Vref is adjusted by cutting the fuses F41 to F48. When none of the fuses F41 to F48 are cut, the reference voltage Vref is VDD / 2. When all of the fuses F41 to F44 of the first connection path 501 and the second connection path 502 are cut, the reference voltage Vref is VDD / 3. At this time, the fuses F41 and F42 or the fuses F43 and F44 are connected in series. Therefore, even if cutting one of the fuses F41 and F42 or one of the fuses F43 and F44 fails, the first connection path 501 and the second connection path 502 are open, so the desired reference voltage (VDD / 3) can be generated.

[0139] In this application example, the first connection path 501 and the second connection path 502, or the third connection path 503 and the fourth connection path 504, are connected in parallel. This makes it possible to reduce the combined resistance of the fuses F41 to F44 before they are cut and the fuses F45 to F48 before they are cut. In this application example, an example in which two connection paths are connected in parallel is shown, but the combined resistance of the fuses can be further reduced by connecting two or more connection paths in parallel. Furthermore, instead of connecting multiple connection paths in parallel, a single connection path may be connected in parallel to the resistor R11 or R14.

[0140] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0141] It is also possible to combine one or more elements of one embodiment with one or more elements of another embodiment. For example, some of the connection paths 151 to 156 according to the first embodiment may be replaced with the adjustment circuits according to the third embodiment.

[0142] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0143] (Item 1) an adjustment circuit disposed between a first node and a second node, the adjustment circuit has a plurality of elements to be cut that are connected in series, and when none of the plurality of elements to be cut are cut, the first node and the second node are electrically connected via the adjustment circuit, and when at least one element to be cut of the plurality of elements to be cut is cut, the adjustment circuit is configured to be open as seen from the first node. Adjustment circuit.

[0144] (Item 2) The plurality of disconnection target elements are each constituted by a fuse, The plurality of fuses are arranged side by side in a width direction of the fuses. Item 1. The adjustment circuit according to item 1.

[0145] (Item 3) the adjustment circuit is configured so that, when none of the plurality of elements to be cut off is cut off, the voltage of the first node becomes a first voltage, and, when at least one element to be cut off among the plurality of elements to be cut off is cut off, the voltage of the first node becomes a second voltage; 3. The adjustment circuit according to item 1 or 2.

[0146] (Item 4) an adjustment circuit disposed between a first node and a second node, the adjustment circuit has a signal generation circuit and a plurality of elements to be cut off, and is configured such that, when none of the plurality of elements to be cut off is cut off, the signal generation circuit outputs a first voltage to the first node, and when at least one element to be cut off among the plurality of elements to be cut off is cut off, the signal generation circuit outputs a second voltage to the first node. Adjustment circuit.

[0147] (Item 5) the signal generating circuit is an OR circuit, the plurality of elements to be cut include a first element to be cut and a second element to be cut, the first element to be disconnected is disposed between a first input terminal of the OR circuit and the second node; the second element to be disconnected is disposed between a second input terminal of the OR circuit and the second node; Item 4. The adjustment circuit according to item 4.

[0148] (Item 6) A current adjusting circuit that adjusts the amount of current flowing through an active load circuit out of the current generated by a current generating circuit, a sink circuit having a switching element and absorbing a current corresponding to the on / off state of the switching element from the current generating circuit to adjust the amount of the current; A control circuit having the adjustment circuit according to any one of items 3 to 5, a voltage corresponding to the voltage of the first node is input to an input terminal of the switching element; a predetermined voltage is supplied to the second node; the switching element is controlled to be turned on or off depending on whether the voltage of the first node is the first voltage or the second voltage; Current regulation circuit.

[0149] (Item 7) the current generating circuit; Item 6. The current adjusting circuit according to item 6, the current generating circuit is an input differential pair having a first MOS transistor to which a first input voltage is input and a second MOS transistor to which a second input voltage is input, the sink circuit adjusts the amount of one of the first drain current and the second drain current flowing in the active load circuit by absorbing one of the first drain current flowing in the first MOS transistor and the second drain current flowing in the second MOS transistor. Operational amplifier.

[0150] (Item 8) the sink circuit has two switching elements, a first switching element connected to the drain of the first MOS transistor and a second switching element connected to the drain of the second MOS transistor; the control circuit has a plurality of the adjustment circuits including a first adjustment circuit and a second adjustment circuit; a voltage corresponding to a voltage of a first node of the first adjustment circuit is input to an input terminal of the first switching element; a voltage corresponding to a voltage of a first node of the second adjustment circuit is input to an input terminal of the second switching element; the sink circuit sinks the first drain current or the second drain current via a switching element that is turned on out of the first switching element or the second switching element. The operational amplifier described in item 7.

[0151] (Item 9) the sink circuit includes a plurality of current paths each having a switching element and different current sink capabilities; a voltage corresponding to a voltage of a first node of the adjustment circuit is input to an input terminal of a switching element provided in any one of the plurality of current paths; the sink circuit is configured to sink one of the first drain current and the second drain current through a current path in which an on-state switching element is provided among the plurality of current paths. An operational amplifier as described in item 7 or 8.

[0152] (Item 10) the switching elements have priorities defined based on the sinking capabilities of the corresponding current paths and standard deviations of input offset voltages of the operational amplifiers; a voltage corresponding to a voltage at a first node of the adjustment circuit is input to an input terminal of a switching element having the highest priority among the plurality of switching elements; Item 9. An operational amplifier.

[0153] (Item 11) A regulation method using a regulation circuit disposed between a first node and a second node, comprising: the adjustment circuit has a plurality of elements to be cut that are connected in series, and when none of the plurality of elements to be cut are cut, the first node and the second node are electrically connected via the adjustment circuit, and when at least one element to be cut of the plurality of elements to be cut is cut, the adjustment circuit is open as seen from the first node; The adjustment method includes a cutting step of cutting at least one element to be cut out of the plurality of elements to be cut out. Adjustment method.

[0154] (Item 12) The plurality of disconnection target elements are each constituted by a fuse, The plurality of fuses are arranged side by side in a width direction of the fuses. the cutting step includes cutting at least one of the plurality of cutting target elements along a width direction of the plurality of fuses. The adjustment method described in item 11.

[0155] (Item 13) the adjustment circuit is configured so that, when none of the plurality of elements to be cut off is cut, the first node is at a first voltage, and, when at least one element to be cut off among the plurality of elements to be cut off is cut, the first node is at a second voltage; Item 13. The method for adjusting according to Item 11 or 12.

[0156] (Item 14) A regulation method using a regulation circuit disposed between a first node and a second node, comprising: the adjustment circuit includes a signal generation circuit and a plurality of elements to be cut off, and is configured such that, when none of the plurality of elements to be cut off is cut off, the signal generation circuit outputs a first voltage to the first node, and when at least one element to be cut off among the plurality of elements to be cut off is cut off, the signal generation circuit outputs a second voltage to the first node; The adjustment method includes a cutting step of cutting at least one element to be cut out of the plurality of elements to be cut out. Adjustment method.

[0157] (Item 15) A current adjustment method for adjusting an amount of current flowing through an active load circuit out of a current generated by a current generating circuit, using a current adjustment circuit, comprising: The current adjustment circuit a sink circuit having a switching element and absorbing a current corresponding to the on / off state of the switching element from the current generating circuit to adjust the amount of the current; a control circuit having the adjustment circuit according to item 13 or 14, a voltage corresponding to the voltage of the first node is input to an input terminal of the switching element; a predetermined voltage is supplied to the second node; the switching element is controlled to be turned on or off depending on whether the voltage of the first node is the first voltage or the second voltage; The current adjusting method includes the cutting step. Current adjustment method.

[0158] (Item 16) An offset adjustment method for adjusting an input offset voltage of an operational amplifier, comprising: The operational amplifier is the current generating circuit; Item 16. The current adjusting circuit according to item 15, the current generating circuit is an input differential pair having a first MOS transistor to which a first input voltage is input and a second MOS transistor to which a second input voltage is input, the sink circuit is configured to adjust the amount of one of the first drain current and the second drain current flowing in the active load circuit by absorbing one of a first drain current flowing in the first MOS transistor and a second drain current flowing in the second MOS transistor; the offset adjustment method includes the cutting step, Offset adjustment method.

[0159] (Item 17) the sink circuit has two switching elements, a first switching element connected to the drain of the first MOS transistor and a second switching element connected to the drain of the second MOS transistor; the control circuit has a plurality of the adjustment circuits including a first adjustment circuit and a second adjustment circuit; a voltage corresponding to a voltage of a first node of the first adjustment circuit is input to an input terminal of the first switching element; a voltage corresponding to a voltage of a first node of the second adjustment circuit is input to an input terminal of the second switching element; the sink circuit is configured to sink one of the first drain current and the second drain current via a switching element that is turned on out of the first switching element or the second switching element; the disconnection step includes disconnecting an element to be disconnected that is included in one of the first adjustment circuit and the second adjustment circuit. Item 17. The offset adjustment method according to item 16. [Explanation of symbols]

[0160] 1 operational amplifier, 10 input stage, 12, 40 current adjustment circuit, 20 gain stage, 30 output stage, 100 input differential pair, 120, 400 sink circuit, 122 switch section, 130, 410 current path group, 133, 135, 137, 139, 171 to 176, 231 to 236, 461 to 468 current source, 132 first current path, 134 second current path, 136 third current path, 138 fourth current path, 140, 200, 420 control circuit, 150, 230, 430 ground node, 151, 211 first connection path, 152, 212 second connection path, 153, 213 third connection path, 154, 214 fourth connection path, 155, 215 fifth connection path, 156, 216 6th connection path, 161 to 166, 221 to 226, 451 to 454 first nodes, 170, 460 power supply voltage nodes, 180 connection path, 431 first adjustment circuit, 432 second adjustment circuit, 433 third adjustment circuit, 434 fourth adjustment circuit, 441 to 444 OR circuits, MP1, MP2, MN1 to MN6 transistors, R1 to R6 first to sixth resistors, F1 to F9 first to ninth fuses, F11 to F16, F21 to F29, F31 to F38 fuses.

Claims

1. an adjustment circuit disposed between a first node and a second node, the adjustment circuit has a plurality of elements to be cut that are connected in series, and when none of the plurality of elements to be cut are cut, the first node and the second node are electrically connected via the adjustment circuit, and when at least one element to be cut of the plurality of elements to be cut is cut, the adjustment circuit is configured to be open as seen from the first node. Adjustment circuit.

2. The plurality of disconnection target elements are each constituted by a fuse, The plurality of fuses are arranged side by side in a width direction of the fuses.

2. The regulation circuit of claim 1.

3. the adjustment circuit is configured so that, when none of the plurality of elements to be cut off is cut, the voltage of the first node becomes a first voltage, and, when at least one element to be cut off among the plurality of elements to be cut off is cut, the voltage of the first node becomes a second voltage; 2. The regulation circuit of claim 1.

4. an adjustment circuit disposed between a first node and a second node, the adjustment circuit has a signal generation circuit and a plurality of elements to be cut off, and is configured such that, when none of the plurality of elements to be cut off is cut off, the signal generation circuit outputs a first voltage to the first node, and when at least one element to be cut off among the plurality of elements to be cut off is cut off, the signal generation circuit outputs a second voltage to the first node. Adjustment circuit.

5. the signal generating circuit is an OR circuit, the plurality of elements to be cut include a first element to be cut and a second element to be cut, the first element to be disconnected is disposed between a first input terminal of the OR circuit and the second node, the second element to be cut off is disposed between a second input terminal of the OR circuit and the second node; 5. The adjustment circuit of claim 4.

6. A current adjusting circuit that adjusts the amount of current flowing through an active load circuit out of the current generated by a current generating circuit, a sink circuit having a switching element and absorbing a current corresponding to the on / off state of the switching element from the current generating circuit to adjust the amount of the current; a control circuit having the adjustment circuit according to any one of claims 3 to 5, a voltage corresponding to the voltage of the first node is input to an input terminal of the switching element; a predetermined voltage is supplied to the second node; the switching element is controlled to be turned on or off depending on whether the voltage of the first node is the first voltage or the second voltage; Current regulation circuit.

7. the current generating circuit; a current adjusting circuit according to claim 6; the current generating circuit is an input differential pair having a first MOS transistor to which a first input voltage is input and a second MOS transistor to which a second input voltage is input, the sink circuit adjusts the amount of one of the first drain current and the second drain current flowing in the active load circuit by absorbing one of the first drain current flowing in the first MOS transistor and the second drain current flowing in the second MOS transistor. Operational amplifier.

8. the sink circuit has two switching elements, a first switching element connected to the drain of the first MOS transistor and a second switching element connected to the drain of the second MOS transistor; the control circuit has a plurality of the adjustment circuits including a first adjustment circuit and a second adjustment circuit; a voltage corresponding to a voltage of a first node of the first adjustment circuit is input to an input terminal of the first switching element; a voltage corresponding to a voltage of a first node of the second adjustment circuit is input to an input terminal of the second switching element; the sink circuit sinks the first drain current or the second drain current via a switching element that is turned on out of the first switching element or the second switching element.

8. The operational amplifier of claim 7.

9. the sink circuit includes a plurality of current paths each having a switching element and different current sink capabilities; a voltage corresponding to a voltage of a first node of the adjustment circuit is input to an input terminal of a switching element provided in any one of the plurality of current paths; the sink circuit is configured to sink one of the first drain current and the second drain current through a current path in which an on-state switching element is provided among the plurality of current paths.

8. The operational amplifier of claim 7.

10. the switching elements have priorities defined based on the sinking capabilities of the corresponding current paths and standard deviations of input offset voltages of the operational amplifiers; a voltage corresponding to a voltage at a first node of the adjustment circuit is input to an input terminal of a switching element having the highest priority among the plurality of switching elements; 10. The operational amplifier of claim 9.

11. A regulation method using a regulation circuit disposed between a first node and a second node, comprising: the adjustment circuit has a plurality of elements to be cut that are connected in series, and when none of the plurality of elements to be cut are cut, the first node and the second node are electrically connected via the adjustment circuit, and when at least one element to be cut of the plurality of elements to be cut is cut, the adjustment circuit is configured to be open as seen from the first node; The adjustment method includes a cutting step of cutting at least one element to be cut out of the plurality of elements to be cut out. Adjustment method.

12. The plurality of disconnection target elements are each constituted by a fuse, The plurality of fuses are arranged side by side in a width direction of the fuses. the cutting step includes cutting at least one of the plurality of cutting target elements along a width direction of the plurality of fuses, The adjusting method according to claim 11.

13. the adjustment circuit is configured so that, when none of the plurality of elements to be cut off is cut, the first node becomes a first voltage, and, when at least one element to be cut off among the plurality of elements to be cut off is cut, the first node becomes a second voltage; The adjusting method according to claim 11.

14. A regulation method using a regulation circuit disposed between a first node and a second node, comprising: the adjustment circuit includes a signal generation circuit and a plurality of elements to be cut off, and is configured such that, when none of the plurality of elements to be cut off is cut off, the signal generation circuit outputs a first voltage to the first node, and when at least one element to be cut off among the plurality of elements to be cut off is cut off, the signal generation circuit outputs a second voltage to the first node; The adjustment method includes a cutting step of cutting at least one element to be cut out of the plurality of elements to be cut out. Adjustment method.

15. A current adjustment method for adjusting an amount of current flowing through an active load circuit out of a current generated by a current generating circuit, using a current adjustment circuit, comprising: The current adjustment circuit a sink circuit having a switching element and absorbing a current corresponding to the on / off state of the switching element from the current generating circuit to adjust the amount of the current; a control circuit having the adjustment circuit according to claim 13 or 14, a voltage corresponding to the voltage of the first node is input to an input terminal of the switching element; a predetermined voltage is supplied to the second node; the switching element is controlled to be turned on or off depending on whether the voltage of the first node is the first voltage or the second voltage; The current adjusting method includes the cutting step. Current adjustment method.

16. An offset adjustment method for adjusting an input offset voltage of an operational amplifier, comprising: The operational amplifier is the current generating circuit; and a current regulation circuit according to claim 15, the current generating circuit is an input differential pair having a first MOS transistor to which a first input voltage is input and a second MOS transistor to which a second input voltage is input, the sink circuit is configured to adjust the amount of one of the first drain current and the second drain current flowing through the active load circuit by absorbing one of a first drain current flowing through the first MOS transistor and a second drain current flowing through the second MOS transistor; the offset adjustment method includes the cutting step, Offset adjustment method.

17. the sink circuit has two switching elements, a first switching element connected to the drain of the first MOS transistor and a second switching element connected to the drain of the second MOS transistor; the control circuit has a plurality of the adjustment circuits including a first adjustment circuit and a second adjustment circuit; a voltage corresponding to a voltage of a first node of the first adjustment circuit is input to an input terminal of the first switching element; a voltage corresponding to a voltage of a first node of the second adjustment circuit is input to an input terminal of the second switching element; the sink circuit is configured to sink one of the first drain current and the second drain current via a switching element that is turned on out of the first switching element and the second switching element; the disconnection step includes disconnecting an element to be disconnected that is included in one of the first adjustment circuit and the second adjustment circuit. The offset adjusting method according to claim 16.

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