Memory device

Abstract

To inhibit a memory device from consuming electric power.SOLUTION: A memory device is adapted to selectively execute any of first, second and third sequences based on at least one of stored data (SD) of a plurality of memory transistors and write command data (WD*) if receiving a write instruction including the write command data as data to be stored in the plurality of memory transistors. In the first sequence, erase operation only out of erase and write operations is executed for the plurality of memory transistors (S21). In the second sequence, write operation matched with the write command data is executed for the plurality of memory transistors without going through erase operation (S22 to S24). In the third sequence, write operation matched with the write command data is executed for the plurality of memory transistors after going through erase operation (S20).SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] The present disclosure relates to memory devices. [Background technology]

[0002] Non-volatile memory devices such as EEPROMs are widely used. When writing data to a non-volatile memory device, each stored value at the target address is erased first, and then the required data is written to the target address. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-101937

[0004] [overview] The operation of erasing each stored value in the target address and the operation of writing the necessary data to the target address each consume a certain amount of power, so reducing power consumption is beneficial.

[0005] a write circuit configured to perform an erase operation to write a first value to each memory transistor and a write operation to write a second value different from the first value to one or more memory transistors; a read circuit configured to perform a read operation to read data stored in each memory transistor; and a control circuit configured to, when receiving a write command including write command data that is data to be stored in the memory transistors, selectively execute one of a first, second, or third sequence based on at least one of the stored data of the memory transistors obtained through the read operation and the write command data, wherein in the first sequence, the control circuit executes only the erase operation of the erase operation and the write operation on the memory transistors; in the second sequence, the control circuit executes the write operation according to the write command data on the memory transistors without performing the erase operation; and in the third sequence, the control circuit executes the write operation according to the write command data on the memory transistors after performing the erase operation. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating the overall configuration of a system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a write command according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram illustrating a summary of a read command according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a configuration diagram of one unit memory circuit according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating a basic sequence executed in response to a write command according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing the structure of 8-bit write command data according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram showing the structure of 8-bit stored data according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating a read operation executed in response to a read command according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic waveform diagram of the output voltage of the boost circuit and the current consumption of the memory device according to the embodiment of the present disclosure. [Figure 10] FIG. 10 is an explanatory diagram of a write omission sequence according to a first embodiment of the present disclosure. [Figure 11] FIG. 11 is an explanatory diagram of an erase omission sequence according to a second example belonging to an embodiment of the present disclosure. [Figure 12] FIG. 12 is an explanatory diagram of an erase omission sequence according to a third example belonging to an embodiment of the present disclosure. [Figure 13] FIG. 13 is an explanatory diagram of an erase omission sequence according to a fourth example belonging to the embodiment of the present disclosure. [Figure 14] FIG. 14 is an explanatory diagram of an erase omission sequence according to a fourth example belonging to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a flowchart illustrating an operation of a memory device related to reception of a write command, according to a sixth example of the embodiment of the present disclosure. [Figure 16] FIG. 16 is a flowchart illustrating an operation of a memory device related to reception of a write command according to a seventh example of the embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and redundant descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the byte selection transistor referred to by "130" (see FIG. 4) described below may be written as byte selection transistor 130 or abbreviated as transistor 130, but these all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is transmitted or applied. A ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. A 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, the back gate of any MOSFET can be considered short-circuited to the source. Hereinafter, the on state and off state of any transistor may be simply referred to as on and off.

[0010] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring (line), node, etc., may be understood to refer to an electrical connection.

[0011] FIG. 1 shows the configuration of a system according to this embodiment. The system in FIG. 1 has a memory device 1, an MPU (Micro Processing Unit) 2, and a wiring group 3. The memory device 1 is a non-volatile memory device. The memory device 1 and the MPU 2 are each connected to ground. A power supply voltage VCC having a positive DC voltage value is supplied to each of the memory device 1 and the MPU 2 from a voltage source (not shown). The memory device 1 and the MPU 2 are each driven based on the power supply voltage VCC.

[0012] The memory device 1 performs bidirectional communication with an external device connected to it. The MPU 2 is an example of the external device. That is, the memory device 1 and the MPU 2 are connected to each other via a wiring group 3, and bidirectional communication is possible via the wiring group 3. Although the communication between the memory device 1 and the MPU 2 may be parallel communication, in this embodiment, the communication between the memory device 1 and the MPU 2 is serial communication. As an interface for serial communication, I 2 An interface based on an Inter-Integrated Circuit (IC) can be used. In this case, the wiring group 3 has clock wiring for transmitting clock signals and data wiring for transmitting data signals. 2 In the serial communication of C, the MPU2 functions as the master and the memory device 1 functions as the slave. The master is sometimes called a controller, and the slave is sometimes called a target. In the system of FIG. 1, a device other than the memory device 1 may be provided as another slave. The interface for serial communication between the memory device 1 and the MPU2 is I 2 The interface is not limited to C, but may be SPI (Serial Peripheral Interface) or Microwire.

[0013] The memory device 1 includes a memory array 10, a write circuit 20, a read circuit 30, a control circuit 40, and an internal power supply circuit 50.

[0014] The memory array 10 is an EEPROM (Electrically Erasable Programmable Read-Only Memory), a non-volatile storage area having a predetermined storage capacity. The storage capacity of the memory array 10 is arbitrary, for example, 1, 2, 4, 8, 16, 32, or 64 kilobits. 1 kilobit is 1024 bits. In the memory device 1, data can be written to the memory array 10 in word units, and data can be read from the memory array 10 in word units. In this embodiment, 1 word is 1 byte. However, multiple bytes may correspond to 1 word. 1 byte consists of 8 bits.

[0015] The memory array 10 is made up of first to nth unit memory circuits. Each unit memory circuit stores 8 bits of data (i.e., 1 byte of data) in a non-volatile manner. n is an integer value of 2 or greater according to the storage capacity of the memory array 10. For example, if the storage capacity of the memory array 10 is 1 kilobit (i.e., 128 bytes), then "n=128", and if the storage capacity of the memory array 10 is 16 kilobits, then "n=128×16".

[0016] In the memory device 1, a memory space is defined for the memory array 10, and a unique address is assigned to each byte in the memory space. That is, a unique address is assigned to each unit memory circuit. The address assigned to the ith unit memory circuit is the ith address, where i represents any integer.

[0017] The write circuit 20 can write data to a unit memory circuit at a target address in accordance with an instruction from the MPU 2. The read circuit 30 can read data stored in a unit memory circuit at a target address in accordance with an instruction from the MPU 2. The control circuit 40 controls the operations of the write circuit 20 and the read circuit 30 in accordance with various instructions received from the MPU 2. The control circuit 40 is connected to the wiring group 3, and has the function of receiving instructions from the MPU 2 via the wiring group 3 and transmitting necessary signals to the MPU 2. The internal power supply circuit 50 generates internal power supply voltages required for various operations within the memory device 1 based on the power supply voltage VCC. The internal power supply circuit 50 is provided with a boost circuit 51.

[0018] The MPU 2 can send a variety of commands to the memory device 1 in accordance with a communication protocol established between the memory device 1 and the MPU 2. The variety of commands includes a write command and a read command.

[0019] There can be multiple types of write commands. However, here, we assume that the write command is a command to write one byte of data to the write target address, and the write target address is specified in the write command. Figure 2 shows how a write command is sent from the MPU 2 to the memory device 1. The write command includes the write target address and write command data WD * In a write command, the write target address refers to the address to be written to. Write command data WD * represents one byte of data to be stored in the unit memory circuit to which the write target address is assigned.

[0020] When the control circuit 40 receives a write command from the MPU 2, it performs a write access to the memory array 10 using the write circuit 20. The write access is performed by sending write command data WD to the write target address. * This is an access to write the write command data WD to the write target address. * Specifically, writing the write command data WD into the memory array 10.* The write command data WD is sent to the unit memory circuit to which the write target address is assigned. * Write access basically consists of an erase operation and a write operation (details will be explained later).

[0021] There can be multiple types of read commands. However, here we assume that the read command is a command to read one byte of data stored in the read target address, and that the read target address is specified in the read command. Figure 3 shows how a read command is sent from MPU 2 to memory device 1, and then the read data is sent from memory device 1 to MPU 2. In the read command, the read target address refers to the address that is the target of reading.

[0022] When the control circuit 40 receives a read command from the MPU 2, it uses the read circuit 30 to perform a read access to the memory array 10. The read access is realized by a read operation by the read circuit 30. In the read operation in response to the reception of the read command, the read circuit 30 reads one byte of data stored in the read target address. Reading one byte of data stored in the read target address specifically refers to reading data from the memory array 10, that is, reading one byte of data stored in a unit memory circuit to which the read target address is assigned. The one byte of data read in the read operation is referred to as read data RD. When the control circuit 40 receives a read command from the MPU 2, it transmits the read data RD read by the read operation of the read circuit 30 to the MPU 2.

[0023] FIG. 4 shows a configuration related to one unit memory circuit of interest. One unit memory circuit has eight memory transistors 110 and eight bit select transistors 120. When it is necessary to distinguish the eight memory transistors 110 from one another, the eight memory transistors 110 are referred to as memory transistors 110[0] to 110[7]. When it is necessary to distinguish the eight bit select transistors 120 from one another, the eight bit select transistors 120 are referred to as bit select transistors 120[0] to 120[7]. A byte select transistor 130 is assigned in common to the eight memory transistors 110. Although not shown in FIG. 4, one byte select transistor 130 is provided in the memory array 10 for each unit memory circuit.

[0024] Eight bits of data are stored by memory transistors 110[0] to 110[7]. The eight bits consist of bits 1 to 8. Of the eight bits of data, the (i+1)th bit of data is stored in memory transistor 110[i]. Of the first to eighth bits, the eighth bit is the most significant bit, the first bit is the least significant bit, and the (i+1)th bit is one bit higher than the i-th bit. Therefore, of the eight bits of data, the most significant bit (eighth bit) of data is stored in memory transistor 110[7], and the least significant bit (first bit) of data is stored in memory transistor 110[0]. Memory transistor 110[i+1] stores data that is one bit higher than memory transistor 110[i].

[0025] Each of transistors 110, 120, and 130 is an N-channel MOSFET. However, while bit select transistor 120 and byte select transistor 130 are planar MOSFETs with a single gate, memory transistor 110 is a floating gate MOSFET. That is, memory transistor 110 has a control gate, a floating gate, a source, and a drain.

[0026] The control gate of each memory transistor 110 is connected to a gate line 181, and the source of the byte select transistor 130 is connected to the gate line 181. In each memory transistor 110, the floating gate is disposed between the control gate and the channel and is insulated from any elements, lines, and electrodes within the memory device 1. However, in each memory transistor 110, a tunnel oxide film is formed between the floating gate and the drain, and electrons can be exchanged between the floating gate and the drain through the tunnel oxide film. In each memory transistor 110, one bit of data corresponding to the charge state of the floating gate is stored in a nonvolatile manner. Each memory transistor 110 stores a first value or a second value in a nonvolatile manner as one bit of data. The first value and the second value may be any two different values, but here, the first value is "1" and the second value is "0."

[0027] A bit select transistor 120 is connected in series to each memory transistor 110. Specifically, the drain of memory transistor 110[i] is connected to the source of bit select transistor 120[i]. The drain of each bit select transistor 120 is connected to a corresponding bit line 140, which is a bit line provided in the memory array 10. The bit line 140 corresponding to memory transistor 110[i] and bit select transistor 120[i] is specifically referred to as bit line 140[i]. Therefore, the drains of bit select transistors 120[0] to 120[7] are connected to bit lines 140[0] to 140[7], respectively. The sources of memory transistors 110[0] to 110[7] are commonly connected to a source line 182. The gates of bit select transistors 120[0] to 120[7] and the gate of byte select transistor 130 are commonly connected to a drive line 183. The drain of byte select transistor 130 is connected to a drive line 184.

[0028] The drive circuit 150 is connected to the bit lines 140[0] to 140[7], the drive line 183, and the drive line 184, and supplies the necessary voltages to these lines. The sense circuit 160 is connected to the bit lines 140[0] to 140[7], and functions effectively in read operations. The selector 170 is connected to the source line 182. The selector 170 switches between a state in which the ground potential is applied to the source line 182 and a state in which the source line 182 is open.

[0029] 4 are provided in the memory device 1. Of the components shown in FIG. 4, each memory transistor 110, each bit selection transistor 120, and each byte selection transistor 130 are provided in the memory array 10. Each bit line 140, gate line 181, source line 182, drive line 183, and drive line 184 are also provided in the memory array 10. A drive circuit 150 is shared by the write circuit 20 and the read circuit 30. A sense circuit 160 is provided in the read circuit 30. A selector 170 is shared by the write circuit 20 and the read circuit 30.

[0030] In the following description, unless otherwise required, attention will be focused on only one unit memory circuit at the write target address or the read target address. Therefore, in the following description, the memory transistor 110, the bit selection transistor 120, the byte selection transistor 130, the bit line 140, the gate line 181, the source line 182, the drive line 183, and the drive line 184 correspond to the write target address or the read target address unless otherwise specified.

[0031] 5 shows the basic sequence executed in a write access. In response to receiving a write command, the control circuit 40 can execute the basic sequence. Receiving a write command specifically means that a write command from the MPU 2 is received by the memory device 1 (control circuit 40). In the basic sequence, the control circuit 40 causes the write circuit 20 to execute an erase operation, and then causes the write circuit 20 to execute a write operation. The address that is the target of the erase operation and the write operation is the write target address.

[0032] In the erase operation, the drive circuit 150 (see FIG. 4) supplies a voltage of 0 V to the bit lines 140[0] to 140[7], and supplies a high voltage VPP to the drive lines 183 and 184. Also, in the erase operation, the selector 170 supplies a voltage of 0 V to the source line 182. Therefore, in the erase operation, the bit selection transistors 120[0] to 120[7] and the byte selection transistor 130 are turned on, and a high voltage VPP is applied to the floating gates based on the drain potential at each of the memory transistors 110[0] to 110[7]. Thus, in the erase operation, electrons are injected from the drain to the floating gate of each memory transistor 110, and as a result, each memory transistor 110 has a relatively high gate threshold voltage Vth_H.

[0033] The gate threshold voltage of each memory transistor 110 becomes a relatively high voltage Vth_H or a relatively low voltage Vth_L. "0 < Vth_L < Vth_H" holds. If the gate threshold voltage of the memory transistor 110[i] was the voltage Vth_L before the execution of the erase operation, the gate threshold voltage of the memory transistor 110[i] rises to the voltage Vth_H by the execution of the erase operation. If the gate threshold voltage of the memory transistor 110[i] was the voltage Vth_H before the execution of the erase operation, the gate threshold voltage of the memory transistor 110[i] remains unchanged at the voltage Vth_H before and after the execution of the erase operation.

[0034] The state where the gate threshold voltage of the memory transistor 110[i] is the voltage Vth_H corresponds to the state where the value "1" is stored in the memory transistor 110[i]. The state where the gate threshold voltage of the memory transistor 110[i] is the voltage Vth_L corresponds to the state where the value "0" is stored in the memory transistor 110[i]. Therefore, in the erase operation, the value "1" is written to all of the memory transistors 110[0] to 110[7] of the write target address.

[0035] In a write operation, the drive circuit 150 (see FIG. 4) receives write command data WD * The selector 170 controls the states of the bit lines 140[0] to 140[7] in response to the bit lines 140[0] to 140[7], supplies a high voltage VPP to the drive line 183, and supplies a voltage of 0V to the drive line 184. In addition, in a write operation, the selector 170 sets the source line 182 to an open state. The open state of the source line 182 refers to a state in which current exchange through the source line 182 between each memory transistor 110 and other parts is cut off. However, in a write operation, a fixed potential high enough to consider the current flowing to the source of each memory transistor 110 to be zero may be applied to the source line 182.

[0036] In a write operation, the drive circuit 150 (see FIG. 4) receives write command data WD * Depending on the bit line 140[0] to 140[7], the bit lines 140[0] to 140[7] are individually set to a high voltage applied state or an open state. Setting the bit line 140[i] to a high voltage applied state means supplying a high voltage VPP to the bit line 140[i]. Setting the bit line 140[i] to an open state means blocking current flow between the bit select transistor 120[i] and other parts through the bit line 140[i].

[0037] During a write operation, the bit select transistors 120[0] to 120[7] and the byte select transistor 130 are on. Therefore, when a high voltage VPP is supplied to the bit line 140[i] during a write operation, a high voltage VPP is applied to the drain of the corresponding memory transistor 110[i] based on the floating gate potential. Therefore, when a high voltage VPP is supplied to the bit line 140[i] during a write operation, electrons are drawn from the floating gate of the corresponding memory transistor 110[i] toward the drain, resulting in the gate threshold voltage of each memory transistor 110[i] having a relatively low voltage Vth_L.

[0038] If the gate threshold voltage of memory transistor 110[i] is voltage Vth_H before the execution of a write operation, the gate threshold voltage of memory transistor 110[i] drops to voltage Vth_L when a write operation is executed in which high voltage VPP is supplied to bit line 140[i]. If the gate threshold voltage of memory transistor 110[i] is voltage Vth_L before the execution of a write operation in which high voltage VPP is supplied to bit line 140[i], the gate threshold voltage of memory transistor 110[i] remains unchanged at voltage Vth_L between before and after the execution of a write operation in which high voltage VPP is supplied to bit line 140[i].

[0039] When the bit line 140[i] is set to an open state during a write operation, no significant potential difference occurs between the floating gate and drain of the corresponding memory transistor 110[i], and therefore no electrons flow between the floating gate and drain of the corresponding memory transistor 110[i]. Therefore, when the bit line 140[i] is set to an open state during a write operation, the gate threshold voltage of the memory transistor 110[i] does not change before and after the write operation (i.e., the stored value of the memory transistor 110[i] does not change). In this way, during a write operation, a value of "0" can be written to one or more of the memory transistors 110[0] to 110[7] at the write target address.

[0040] Referring to Figure 6, the write command data WD * is bit data B * [0]~B * [7] Write command data WD * Each bit data in has a value of "1" or "0." Write command data WD * is 8-bit data consisting of bits 1 to 8, and the write command data WD * The (i+1)th bit of data in *As mentioned above, among the 1st to 8th bits, the 8th bit is the most significant bit, the 1st bit is the least significant bit, and the (i+1)th bit is one bit higher than the i-th bit. Therefore, bit data B * [0]~B * [7] Bit data B * [7] is the most significant bit (8th bit) data, and bit data B * [0] is the least significant bit (1st bit) data. Bit data B * [0]~B * [7] Bit data B * [i+1] is bit data B * This is data one bit higher than [i].

[0041] Bit Data B * [i] indicates the value to be written to memory transistor 110[i] in a write operation. * When [i]=1, write command data WD * commands memory transistor 110[i] to store a value of “1.” Conversely, “B * When [i]=0, write command data WD * commands memory transistor 110[i] to store a value of “0.” Therefore, in a write operation, driver circuit 150 * If "B[i]=1", the bit line 140[i] is set to an open state, and "B[i]=1" is set to an open state. * When [i]=0″, the bit line 140[i] is set to a high voltage applied state.

[0042] Write command data WD in the example of Figure 5 * is (B * [7],B * [6],B * [5],B * [4],B * [3],B * [2],B * [1],B *[0]) = (0,0,1,1,1,1,0,1). Therefore, in the write operation of the example of Figure 5, bit lines 140[7], 140[6], and 140[1] are set to a high voltage applied state, and bit lines 140[5] to 140[2] and 140[0] are set to an open state. Therefore, after the write operation of Figure 5, 0, 0, 1, 1, 1, 1, 0, and 1 are stored in memory transistors 110[7], 110[6], 110[5], 110[4], 110[3], 110[2], 110[1], and 110[0], respectively.

[0043] Referring to FIG. 7, 8 bits of data stored in one unit memory circuit are referred to as stored data SD. Each bit of data in the stored data SD has a value of "1" or "0." The stored data SD is 8 bits of data consisting of 1st to 8th bits, and the (i+1)th bit of data in the stored data SD is bit data B[i]. As described above, of the 1st to 8th bits, the 8th bit is the most significant bit, the 1st bit is the least significant bit, and the (i+1)th bit is one bit higher than the i-th bit. Therefore, of the bit data B[0] to B[7], the bit data B[7] is the most significant bit (8th bit) data, and the bit data B[0] is the least significant bit (1st bit) data. Of the bit data B[0] to B[7], the bit data B[i+1] is one bit higher than the bit data B[i].

[0044] 8 shows the read operation executed in read access. In response to receiving a read command, the control circuit 40 can execute the read access. In the read access in response to receiving a read command, the control circuit 40 causes the read circuit 30 to execute the read operation, and then transmits the read data RD read by the read circuit 30 to the MPU 2. In the read access in response to receiving a read command, the address that is the target of the read operation is the read target address.

[0045] In a read operation, the drive circuit 150 (see FIG. 4) supplies a read voltage Vreg1 to the bit lines 140[0] to 140[7] and a read voltage Vreg2 to the drive lines 183 and 184. In addition, in a read operation, the selector 170 supplies a voltage of 0V to the source line 182. The read voltages Vreg1 and Vreg2 have a predetermined positive DC voltage value. The read voltages Vreg1 and Vreg2 may be a common voltage or may be two types of voltages having different voltage values. The read voltage Vreg2 is higher than the gate threshold voltage of each bit select transistor 120. In addition, the read voltage Vreg2 is higher than the above-mentioned voltage Vth_L but lower than the above-mentioned voltage Vth_H.

[0046] Therefore, during a read operation, if a value of “1” is stored in memory transistor 110[i] (i.e., if the gate threshold voltage of memory transistor 110[i] is voltage Vth_H), memory transistor 110[i] is turned off, and no drain current is generated in memory transistor 110[i], or the drain current of memory transistor 110[i] is sufficiently small. Conversely, during a read operation, if a value of “0” is stored in memory transistor 110[i] (i.e., if the gate threshold voltage of memory transistor 110[i] is voltage Vth_L), memory transistor 110[i] is turned on, and a significant drain current is generated in memory transistor 110[i]. At least during a read operation, if a value of “0” is stored in memory transistor 110[i], the drain current of memory transistor 110[i] is larger than when a value of “1” is stored in memory transistor 110[i].

[0047] In a read operation, the sense circuit 160 detects whether a value of "0" or "1" is stored in each of the memory transistors 110[0] to 110[7] based on the magnitude of the drain current of the memory transistor 110, and thereby reads the stored data SD from the target address. In a read access in response to receiving a read command, the control circuit 40 transmits the stored data SD read from the read target address to the MPU 2 as read data RD (see FIG. 3).

[0048] The read voltages Vreg1 and Vreg2 are DC voltages generated by the internal power supply circuit 50 based on the power supply voltage VCC. The read voltages Vreg1 and Vreg2 may be the power supply voltage VCC itself. A boost circuit 51 (see FIG. 1) provided in the internal power supply circuit 50 generates a high voltage VPP from the power supply voltage VCC by boosting operation. Therefore, the high voltage VPP is higher than the power supply voltage VCC. A charge pump circuit can be used as the boost circuit 51.

[0049] Figure 9 shows the output voltage V BOOST 1 and 2 show the waveforms of the current consumption ICC of the memory device 1. The period during which an erase operation is performed is called an erase period, and the period during which a write operation is performed is called a write period. BOOST The control circuit 40 stops the boosting operation of the boost circuit 51 as a rule. The control circuit 40 starts the boosting operation of the boost circuit 51 immediately before the erase operation is performed, and the output voltage V BOOST The control circuit 40 raises the output voltage V of the boost circuit 51 from a sufficiently low voltage (for example, 0 V) ​​to a high voltage VPP during the erase period. BOOST The control circuit 40 causes the boost circuit 51 to continue boosting so that the output voltage V is maintained at the high voltage VPP, and stops the boost operation of the boost circuit 51 when the erase period ends. BOOSTThe control circuit 40 raises the output voltage V of the boost circuit 51 from a sufficiently low voltage (for example, 0 V) ​​to a high voltage VPP during the write period. BOOST The boosting operation of the booster circuit 51 is continued so that the voltage VPP is maintained at the high voltage VPP, and when the write period ends, the boosting operation of the booster circuit 51 is stopped.

[0050] The current ICC consumed by the memory device 1 when the boost circuit 51 is stopped (i.e., the boosting operation is stopped) is referred to as the steady-state current consumption. The current ICC consumed by the memory device 1 is the output voltage V of the boost circuit 51 due to the boosting operation of the boost circuit 51. BOOST The current consumption rises significantly from the steady-state current consumption during the process of increasing the current consumption, and is greater than the steady-state current consumption during the erase period and write period. Therefore, if the execution of the erase operation or write operation can be prevented, the power consumption of the memory device 1 can be reduced.

[0051] In a reference memory device different from the memory device 1 according to the present embodiment, the basic sequence is always executed whenever a write command is received. In contrast, when a write command is received from the MPU 2, the control circuit 40 according to the present embodiment determines whether the omission condition is met, and if the omission condition is met, executes a write omission sequence or an erase omission sequence, or does not execute both the erase operation and the write operation. In a write omission sequence, only an erase operation is performed in response to the reception of a write command, and the write operation is not executed. In an erase omission sequence, only a write operation is performed in response to the reception of a write command, without first performing an erase operation. When a write command is received from the MPU 2 and the omission condition is not met, the control circuit 40 executes the basic sequence. As explained with reference to FIG. 5, in the basic sequence, the erase operation is performed first, and then the write command data WD * A write operation is performed according to the

[0052] In the write-omit sequence, power consumption can be reduced by the amount corresponding to the write operation being executed compared to the basic sequence. In the erase-omit sequence, power consumption can be reduced by the amount corresponding to the erase operation being executed compared to the basic sequence. When both the erase operation and the write operation are not executed, power consumption can be reduced by the amount corresponding to the erase operation and the write operation being executed compared to the basic sequence.

[0053] In order to determine whether the omission condition is satisfied, the control circuit 40 can execute a read access to the write target address specified in the write command in response to receiving the write command. When a read access is executed to the write target address, the read circuit 30 performs a read operation to read one byte of data stored in the write target address. To be more specific, reading one byte of data stored in the write target address means reading data from the memory array 10, and reading one byte of data stored in the unit memory circuit to which the write target address is assigned (one byte of data stored in the memory transistors 110[0] to 110[7] of the unit memory circuit to which the write target address is assigned).

[0054] In the following description, unless otherwise specified, the stored data SD (see FIG. 7) refers to one byte of data stored at the write target address immediately before the write command is received (more specifically, one byte of data stored in the memory transistors 110[0] to 110[7] of the unit memory circuit to which the write target address is assigned). Therefore, when a read access is performed on the write target address in response to the reception of a write command, the stored data at the write target address is read as the stored data SD by the read operation of the read circuit 30. The control circuit 40 does not transmit the stored data SD read in response to the reception of a write command to the MPU 2.

[0055] When a write command is received from the MPU 2, the control circuit 40 outputs write command data WD *and stored data SD (that is, stored data at the write target address), it is determined whether the omission condition is met.

[0056] Below, several specific operational examples, application techniques, modified techniques, etc. related to the memory device 1 will be described among the multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple embodiments described below can also be applied to any other of the multiple embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0057] <<First Example>> A first embodiment will be described. The omissible condition according to the first embodiment includes the condition CND1. In the first embodiment, the omissible condition may be the condition CND1 itself. Alternatively, the omissible condition may be constituted by the logical sum of the condition CND1 and another condition. That is, in the first embodiment, the omissible condition may be satisfied when the condition CND1 or another condition is satisfied, and the other condition may be one or more of the conditions CND2 to CND5 described below.

[0058] Condition CND1 is the write command data WD * All bit data in B * [0]~B * The condition CND1 is satisfied when [7] has a value of "1". * commands that the value "1" be written to each of the memory transistors 110[0] to 110[7] at the write target address.

[0059] When a write command is received, the write command data WD * All bit data in B * [0]~B * When [7] has a value of "1", the condition CND1 is satisfied, so that the omission enabling condition is satisfied, and the control circuit 40 executes the write omission sequence.

[0060] An overview of the write skip sequence is shown in Figure 10. The erase operation in the write skip sequence writes a value of "1" to each of the memory transistors 110[0] to 110[7] at the write target address, so that the data specified by the write command is written to the write target address without performing a subsequent write operation.

[0061] The success or failure of the condition CND1 depends on the write command data WD * Therefore, the write command data WD * When it can be determined that the condition CND1 is satisfied based on the above, the control circuit 40 does not need to make the read circuit 30 perform a read operation to read out the stored data SD at the write target address.

[0062] <<Second Example>> A second embodiment will be described. The omissible condition according to the second embodiment includes the condition CND2. In the second embodiment, the omissible condition may be the condition CND2 itself. Alternatively, the omissible condition may be constituted by the logical OR of the condition CND2 and another condition. That is, in the second embodiment, the omissible condition may be satisfied when the condition CND2 or another condition is satisfied, and the other condition may be any one or more of the conditions CND1 and CND3 to CND5 described above or below.

[0063] Condition CND2 is the write command data WD * All bit data in B * [0]~B * The condition CND2 is satisfied when [7] has a value of "0". * commands that the value "0" be written to each of the memory transistors 110[0] to 110[7] at the write target address.

[0064] When a write command is received, the write command data WD * All bit data in B * [0]~B *When [7] has a value of "0", the condition CND2 is satisfied, so that the omission enabling condition is satisfied, and the control circuit 40 executes the erase omission sequence.

[0065] 11 shows an outline of the erase omission sequence when the condition CND2 is satisfied. When the condition CND2 is satisfied, the write command data WD * Therefore, the data specified by the write command is written to the write target address without performing an erase operation before the write operation.

[0066] The success or failure of the condition CND2 depends on the write command data WD * Therefore, the write command data WD * When it can be determined that the condition CND2 is satisfied based on the above, the control circuit 40 does not need to make the read circuit 30 perform a read operation to read out the stored data SD at the write target address.

[0067] <<Third Example>> A third embodiment will be described. The omissible condition according to the third embodiment includes the condition CND3. In the third embodiment, the omissible condition may be the condition CND3 itself. Alternatively, the omissible condition may be constituted by the logical OR of the condition CND3 and another condition. That is, in the third embodiment, the omissible condition may be satisfied when the condition CND3 or another condition is satisfied, and the other condition may be any one or more of the conditions CND1, CND2, CND4, and CND5 described above or below.

[0068] Condition CND3 is a condition that all bit data B[0] to B[7] in the storage data SD of the write target address have a value of “1.” The storage data SD that satisfies condition CND3 indicates that the value of “1” is stored in each of the memory transistors 110[0] to 110[7] of the write target address.

[0069] When a write command is received, the control circuit 40 acquires the stored data SD by causing the read circuit 30 to perform a read operation to read out the stored data SD at the write target address. When all bit data B[0] to B[7] in the stored data SD have the value "1", the condition CND3 is met, which means the omission possible condition is met, and the control circuit 40 executes the erase omission sequence.

[0070] 12 shows an outline of the erase skip sequence when the condition CND3 is satisfied. When the condition CND3 is satisfied, the write operation in the erase skip sequence sends write command data WD to each of the memory transistors 110[0] to 110[7] of the write target address. * A value according to the above is written. When the condition CND3 is satisfied, even if an erase operation is not performed, the state of the memory transistors 110[0] to 110[7] immediately before the write operation will be the same as the state immediately after the erase operation. Therefore, even if an erase operation is not performed before the write operation, the data specified by the write command will be written to the write target address.

[0071] Write command data WD in the example of FIG. 12 * is (B * [7],B * [6],B * [5],B * [4],B * [3],B * [2],B * [1],B * 12, the values ​​0, 0, 1, 1, 1, 1, 1, 0, 1 are stored in memory transistors 110[7], 110[6], 110[5], 110[4], 110[3], 110[2], 110[1], and 110[0], respectively, as specified by the write command.

[0072] <<Fourth Example>> A fourth embodiment will be described. The omissible condition according to the fourth embodiment includes condition CND4. In the fourth embodiment, the omissible condition may be condition CND4 itself. Alternatively, the omissible condition may be constituted by the logical OR of condition CND4 and another condition. That is, in the fourth embodiment, the omissible condition may be satisfied when condition CND4 or another condition is satisfied, and the other condition may be any one or more of conditions CND1, CND2, CND3, and CND5 described above or below.

[0073] The condition CND4 is that the value of a specific bit in the storage data SD is "1" and the write command data WD * The value of the specific bit in the bit is "0", and the value of the stored data SD and the write command data WD in the non-specific bit other than the specific bit are * The condition is that the value of the storage data SD and the value of the write command data WD match (see FIG. 13). The number of specific bits is 1 or more and is any number, and the number of non-specific bits is also 1 or more and is any number. If there are multiple non-specific bits, the value of the storage data SD and the write command data WD match (see FIG. 13). * The value of the storage data SD and the write command data WD match in each of the plurality of non-specific bits. * In the case where there are multiple specific bits, if the value of the specific bit in the stored data SD is "1" and the value of the write command data WD * The value of a specific bit in the storage data SD is "0" when the values ​​of multiple specific bits in the storage data SD are "1" and the write command data WD * This means that the values ​​of multiple specific bits in the .

[0074] When a write command is received, the control circuit 40 acquires the stored data SD by causing the read circuit 30 to perform a read operation to read out the stored data SD at the write target address. Thereafter, the control circuit 40 converts the acquired stored data SD into write command data WD. * By comparing each bit with the stored data SD and write command data WD, *If the condition CND4 is met, the omission enabling condition is met, and the control circuit 40 executes the erase omission sequence.

[0075] 13 shows an outline of the erase skip sequence when the condition CND4 is satisfied. When the condition CND4 is satisfied, the write operation in the erase skip sequence sends write command data WD to each of the memory transistors 110[0] to 110[7] of the write target address. * When condition CND4 is met, even if an erase operation is not performed, if a value of "0" is written to a specific bit in a write operation, the data specified by the write command will be written to the write target address.

[0076] In the example of FIG. 13, the stored data SD satisfies (B[7], B[6], B[5], B[4], B[3], B[2], B[1], B[0])=(1,1,1,1,1,1,1,0), while the write command data WD * is (B * [7],B * [6],B * [5],B * [4],B * [3],B * [2],B * [1],B * [0])=(1,1,1,1,0,1,1,0). That is, in the example of FIG. 13, the fourth bit is a specific bit, and the first to third and fifth to eighth bits are non-specific bits (see also FIGS. 6 and 7). In the example of FIG. 13, the drive circuit 150 uses the write command data WD *13, the write operation switches the memory value of the memory transistor 110[3] corresponding to the specific bit from "1" to "0", and after the write operation, the memory transistors 110[7], 110[6], 110[5], 110[4], 110[3], 110[2], 110[1], and 110[0] store the values ​​1, 1, 1, 1, 0, 1, 1, 0, respectively, as specified by the write command.

[0077] If condition CND4 is satisfied, the bit line 140 corresponding to the non-specific bit, for which a value of "0" is stored in the storage data SD, may be set to an open state during a write operation. That is, if condition CND4 is satisfied, the non-specific bit is classified as a first-type non-specific bit or a second-type non-specific bit. A value of "1" is stored in the first-type non-specific bit in the storage data SD, and a value of "0" is stored in the second-type non-specific bit in the storage data SD. If condition CND4 is satisfied, the drive circuit 150 may set the bit line 140 corresponding to the second-type non-specific bit to an open state during a write operation. In the example of FIG. 13, only the first bit, which is the least significant bit, corresponds to the second-type non-specific bit. Therefore, the drive circuit 150 according to the example of FIG. 13 may set the bit line 140[0] corresponding to the first bit to an open state during a write operation. This is because, in the example of FIG. 13, it is not necessary to change the stored value of the memory transistor 110[0] during a write operation.

[0078] Another example where the condition CND4 is satisfied is shown in Figure 14. In the example of Figure 14, the stored data SD satisfies (B[7], B[6], B[5], B[4], B[3], B[2], B[1], B[0]) = (1,1,1,1,1,1,0,0), while the write command data WD * is (B * [7],B * [6],B * [5],B * [4],B * [3],B* [2],B * [1],B * [0])=(1,1,1,1,0,0,0,0). That is, in the example of FIG. 14, the third and fourth bits are specific bits, and the first, second and fifth to eighth bits are non-specific bits (see also FIGS. 6 and 7). In the example of FIG. 14, the drive circuit 150 uses the write command data WD * 14, the high voltage VPP is supplied to the bit lines 140[3] to 140[0] and the bit lines 140[7] to 140[4] are set to an open state. Therefore, in the example of Figure 14, the write operation switches the stored values ​​of the memory transistors 110[3] and 110[2] corresponding to each specific bit from "1" to "0", and after the write operation, 1, 1, 1, 1, 0, 0, 0, 0 are stored in the memory transistors 110[7], 110[6], 110[5], 110[4], 110[3], 110[2], 110[1], and 110[0], respectively, as specified by the write command.

[0079] In the example of Fig. 14, the first and second bits correspond to the second type of non-specific bits. Therefore, the drive circuit 150 according to the example of Fig. 14 may set the bit lines 140[0] and 140[1] corresponding to the first and second bits to an open state during a write operation. This is because, in the example of Fig. 14, it is not necessary to change the stored values ​​of the memory transistors 110[0] and 110[1] during a write operation.

[0080] <<Fifth Example>> A fifth embodiment will be described. The omissible condition according to the fifth embodiment includes condition CND5. In the fifth embodiment, the omissible condition may be condition CND5 itself. Alternatively, the omissible condition may be constituted by the logical OR of condition CND5 and another condition. That is, in the fifth embodiment, the omissible condition may be satisfied when condition CND5 or another condition is satisfied, and the other condition may be any one or more of the above-mentioned conditions CND1 to CND4.

[0081] Condition CND5 is write command data WD *The condition is that the stored data SD matches the write command data WD. When a write command is received, the control circuit 40 acquires the stored data SD by having the read circuit 30 perform a read operation to read the stored data SD at the write target address. Thereafter, the control circuit 40 converts the acquired stored data SD into the write command data WD. * By comparing each bit with the stored data SD and write command data WD, * Determine whether condition CND5 is satisfied. Bit data B[0] to B[7] in the acquired memory data SD and write command data WD * Bit data B in * [0]~B * [7] and (B[7],B[6],B[5],B[4],B[3],B[2],B[1],B[0]) = (B * [7],B * [6],B * [5],B * [4],B * [3],B * [2],B * [1],B * [0]), the condition CND5 is met.

[0082] The omission condition is met when the condition CND5 is met. When a write command is received and the condition CND5 is met, the control circuit 40 does not execute either the erase operation or the write operation in response to the write command. The data (SD) stored before the write command is written as the write command data WD. * If the values ​​match, there is no need to change the stored values ​​of the memory transistors 110 of the write target address.

[0083] <<Sixth Example>> A sixth embodiment will be described. In the sixth embodiment, the flow of operations of the memory device 1 in response to reception of a write command will be described. In the sixth embodiment, the first to fifth embodiments described above are combined. Figure 15 is a flowchart showing the operation of the memory device 1 in response to reception of a write command according to the sixth embodiment.

[0084] First, in step S11, a write command from the MPU 2 is received by the memory device 1. In step S12 following step S11, the control circuit 40 reads the write command data WD * If the condition CND1 is satisfied (i.e., "WD * If the write command data WD is "FFh", the process proceeds from step S12 to step S21. If the condition CND1 is not satisfied, the process proceeds from step S12 to step S13. * In the notation representing the value of the stored data SD, the symbol "h" indicates that the numerical value preceding the symbol "h" is a hexadecimal value.

[0085] In step S13, the control circuit 40 determines whether the write command data WD * If the condition CND2 is satisfied (i.e., "WD * = 00h"), the process proceeds from step S13 to step S22. If the condition CND2 is not satisfied, the process proceeds from step S13 to step S14.

[0086] In step S14, the control circuit 40 acquires the stored data SD by having the read circuit 30 perform a read operation to read out the stored data SD at the write target address. By proceeding to step S14 and performing the read operation only when the conditions CND1 and CND2 are not satisfied, it is possible to prevent unnecessary read operations from being executed.

[0087] In step S15 following step S14, the control circuit 40 determines whether the condition CND3 is met based on the stored data SD acquired in step S14. If the condition CND3 is met (i.e., if "SD=FFh"), the process proceeds from step S15 to step S23. If the condition CND3 is not met, the process proceeds from step S15 to step S16.

[0088] In step S16, the control circuit 40 reads the stored data SD and the write command data WD. *If the condition CND4 is satisfied, the process proceeds from step S16 to step S24. If the condition CND4 is not satisfied, the process proceeds from step S16 to step S17.

[0089] In step S17, the control circuit 40 reads the stored data SD and the write command data WD. * The success or failure of the condition CND5 is judged by comparing the two. If the condition CND5 is met (i.e., "SD=WD" * If the condition CND5 is not satisfied, the process proceeds from step S17 to step S20.

[0090] In step S20, the control circuit 40 executes a basic sequence. In step S21, the control circuit 40 executes a write omission sequence. In each of steps S22 to S24, the control circuit 40 executes an erase omission sequence. If the process proceeds to any of steps S20 to S24, the control circuit 40 executes the corresponding sequence and then ends the series of operations triggered by receiving a write command. If the process proceeds to step S25, the control circuit 40 executes neither an erase operation nor a write operation. If the process proceeds to step S25, the control circuit 40 executes neither an erase operation nor a write operation in response to the write command, and ends the series of operations triggered by receiving a write command. After receiving the write command, the control circuit 40 transmits a signal (such as an acknowledge signal) according to the communication protocol to the MPU 2, separate from the operations shown in FIG. 15.

[0091] <<Seventh Example>> A seventh embodiment will now be described. As with the sixth embodiment, the seventh embodiment will describe the flow of operations of the memory device 1 in response to reception of a write command. The seventh embodiment combines the first to fifth embodiments described above. Figure 16 is a flowchart of the operation of the memory device 1 in response to reception of a write command according to the seventh embodiment.

[0092] First, in step S31, a write command from the MPU 2 is received by the memory device 1. In step S32 following step S31, the control circuit 40 acquires the stored data SD by having the read circuit 30 perform a read operation to read out the stored data SD at the write target address. That is, in the seventh embodiment, unlike the sixth embodiment (FIG. 15), a read operation is first performed in response to the reception of the write command. After step S32, the process proceeds to step S33.

[0093] In step S33, the control circuit 40 reads the stored data SD and the write command data WD. * The success or failure of the condition CND5 is judged by comparing the two. If the condition CND5 is met (i.e., "SD=WD" * If the condition CND5 is not satisfied, the process proceeds from step S33 to step S43. If the condition CND5 is not satisfied, the process proceeds from step S33 to step S34.

[0094] In step S34, the control circuit 40 outputs the write command data WD * If the condition CND1 is satisfied (i.e., "WD * If the condition CND1 is not satisfied, the process proceeds from step S34 to step S41. If the condition CND1 is not satisfied, the process proceeds from step S34 to step S35.

[0095] In step S35, the control circuit 40 receives the stored data SD and the write command data WD * The fulfillment of conditions CND2 to CND4 is determined based on at least one of the above. If any of conditions CND2 to CND4 is fulfilled, the process proceeds from step S35 to step S42. If none of conditions CND2 to CND4 is fulfilled, the process proceeds from step S35 to step S40.

[0096] In step S40, the control circuit 40 executes a basic sequence. In step S41, the control circuit 40 executes a write omission sequence. In step S42, the control circuit 40 executes an erase omission sequence. If the process proceeds to any of steps S40 to S42, the control circuit 40 executes the corresponding sequence and then ends the series of operations triggered by receiving a write command. If the process proceeds to step S43, the control circuit 40 executes neither an erase operation nor a write operation. If the process proceeds to step S43, the control circuit 40 executes neither an erase operation nor a write operation in response to the write command, and ends the series of operations triggered by receiving a write command. After receiving the write command, the control circuit 40 transmits a signal (such as an acknowledge signal) according to the communication protocol to the MPU 2, separate from the operations shown in FIG. 16.

[0097] <<Eighth Example>> An eighth embodiment will now be described. In the eighth embodiment, modified techniques or supplementary matters to the above-mentioned items will be described.

[0098] An electronic component may be configured that incorporates the memory device 1 and any other functional circuit. The electronic component in this case is, for example, a DC / DC converter, a motor driver, or an LED driver that incorporates the memory device 1. The functional circuit can adjust the content or parameters of the operation it should perform based on the data stored in the memory array 10 in the memory device 1. An electronic component may be configured that incorporates the memory device 1 and the MPU 2.

[0099] The technology of the present disclosure is also applicable to nonvolatile memories other than EEPROM.

[0100] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0101] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0102] A memory device (1) according to one aspect of the present disclosure includes a plurality of memory transistors (110[0] to 110[7]) configured to non-volatilely store a plurality of bits of data, a write circuit (20) configured to execute an erase operation to write a first value (e.g., 1) to each memory transistor and a write operation to write a second value (e.g., 0) different from the first value to one or more memory transistors, a read circuit (30) configured to execute a read operation to read data stored in each memory transistor, and, when a write command including write command data that is data to be stored in the plurality of memory transistors is received, the memory device (1) includes: a plurality of memory transistors (110[0] to 110[7]) configured to non-volatilely store a plurality of bits of data; and a control circuit (40) configured to be able to selectively execute any one of the first, second, and third sequences based on at least one of the write command data, wherein the control circuit is configured (first configuration) to execute only the erase operation of the erase operation and the write operation on the plurality of memory transistors in the first sequence (write-omitted sequence), to execute the write operation according to the write command data on the plurality of memory transistors without going through the erase operation in the second sequence (erase-omitted sequence), and to execute the write operation according to the write command data on the plurality of memory transistors after going through the erase operation in the third sequence (basic sequence).

[0103] This makes it possible to reduce the power consumption required to execute an erase or write operation under specific conditions.

[0104] In the memory device of the first configuration described above, when the write command is received, the control circuit may be configured (second configuration) to determine whether a specific condition (CND1, CND2, CND3 or CND4) is met based on at least one of the stored data and the write command data, and execute the first sequence or the second sequence when the specific condition is met, and execute the third sequence when the specific condition is not met.

[0105] In the memory device of the second configuration, when the write command is received and the write command data is data instructing each of the plurality of memory transistors to store the first value (e.g., 1), the specific condition is met and the control circuit may be configured to execute the first sequence (third configuration).

[0106] In the memory device of the second or third configuration, when the write command is received and the write command data is data instructing each of the plurality of memory transistors to store the second value (e.g., 0), the specific condition is met and the control circuit may be configured to execute the second sequence (fourth configuration).

[0107] In a memory device according to any of the second to fourth configurations, when the write command is received and the stored data indicates that the first value (e.g., 1) is stored in each of the plurality of memory transistors, the specific condition may be met and the control circuit may execute the second sequence (fifth configuration).

[0108] In a memory device according to any of the second to fifth configurations, when the write command is received, if the value of the specific bit in the stored data is the first value (e.g., 1), the value of the specific bit in the write command data is the second value (e.g., 0), and the value of the stored data and the value of the write command data match in non-specific bits other than the specific bit, the specific condition is met and the control circuit may be configured to execute the second sequence (sixth configuration).

[0109] In the memory device according to any one of the first to sixth configurations, when the write command is received and the write command data matches the stored data, the control circuit does not execute both the erase operation and the write operation. The seventh configuration may also be used.

[0110] This makes it possible to reduce the power consumption required to execute erase and write operations under specific conditions. [Explanation of symbols]

[0111] 1. Memory device 2 MPU 3 wiring group 10 Memory Array 20 Light Circuit 30 Lead Circuit 40 Control circuit 50 Internal power circuit 51 Boost circuit VCC power supply voltage 110[0]~110[7] Memory transistor 120[0]~120[7] Bit selection transistor 130 Byte Select Transistors 140[0]~140[7] Bit lines 150 Drive Circuit 160 Sense Circuit 170 Selector 181 Gate Line 182 Source Line 183, 184 Drive line VPP High Voltage Vreg1, Vreg2 Read voltage WD * Light command data SD memory data RD Read Data

Claims

1. a plurality of memory transistors configured to store a plurality of bits of data in a nonvolatile manner; a write circuit configured to perform an erase operation to write a first value to each memory transistor and a write operation to write a second value different from the first value to any one or more memory transistors; a read circuit configured to perform a read operation to read data stored in each memory transistor; a control circuit configured to selectively execute one of a first sequence, a second sequence, and a third sequence based on at least one of the stored data of the memory transistors obtained through the read operation and the write command data when a write command including write command data is received, the write command data being data to be stored in the memory transistors; The control circuit In the first sequence, only the erase operation is performed on the plurality of memory transistors out of the erase operation and the write operation; In the second sequence, the write operation is executed on the plurality of memory transistors in accordance with the write command data without the erase operation; In the third sequence, the erase operation is performed on the plurality of memory transistors, and then the write operation is performed in accordance with the write command data. , memory device.

2. When the write command is received, the control circuit determines whether a specific condition is met based on at least one of the stored data and the write command data, and executes the first sequence or the second sequence when the specific condition is met, and executes the third sequence when the specific condition is not met.

10. The memory device of claim 1.

3. When the write command is received and the write command data is data instructing each of the plurality of memory transistors to store the first value, the specific condition is met and the control circuit executes the first sequence.

3. The memory device of claim 2.

4. When the write command is received and the write command data is data instructing each of the plurality of memory transistors to store the second value, the specific condition is met and the control circuit executes the second sequence.

3. The memory device of claim 2.

5. When the write command is received and the stored data indicates that the first value is stored in each of the plurality of memory transistors, the specific condition is met and the control circuit executes the second sequence.

3. The memory device of claim 2.

6. When the write command is received, if the value of the specific bit in the stored data is the first value, the value of the specific bit in the write command data is the second value, and the value of the stored data and the value of the write command data match in non-specific bits other than the specific bit, the specific condition is met and the control circuit executes the second sequence.

3. The memory device of claim 2.

7. When the write command is received, if the write command data matches the stored data, the control circuit does not execute both the erase operation and the write operation.

7. The memory device according to claim 1.

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