Digital-analog conversion device, display driver, and display device

Abstract

PURPOSE: To provide a digital-analog conversion device, a display driver, and a display device capable of generating a high quality analog output voltage while suppressing noise.CONSTITUTION: The present invention includes: a gray code conversion circuit that converts an upper N bit in a digital data piece formed of a binary code into an N-bit gray code, and outputs a converted digital data piece formed of the N-bit gray code and a K-bit binary code in which the upper N bit is omitted from the digital data piece; a first decoder that selects two reference voltages based on the N-bit gray code in the converted digital data piece from a plurality of reference voltages having different voltage values; a second decoder that outputs (K+1) voltages each having one or the other of the two reference voltages based on the K-bit binary code in the converted digital data piece; and an amplifier circuit that generates an analog voltage by amplifying an average voltage of the (K+1) voltages.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a digital-to-analog conversion device, a display driver for driving a display panel, and a display device. [Background technology]

[0002] A known liquid crystal display device includes a display panel in which a plurality of data lines and a plurality of scanning lines are arranged at an intersection, with display cells that serve as pixels formed at each intersection, as well as a source driver and a gate driver that drive the display panel (see, for example, Patent Document 1).

[0003] The source driver includes a shift register, a level shifter, a data register latch, a DA (digital to analog) conversion unit, and an output amplifier unit.

[0004] The shift register generates a plurality of latch timing signals for selecting latches in synchronization with a clock signal and supplies them to the data register latches.

[0005] The data register latch takes in n pieces of display data, for example, 8 bits each, corresponding to each display cell based on the video signal, based on each latch timing signal supplied from the shift register. The level shifter performs level shift processing on each of the n pieces of display data to increase the amplitude of the signal level corresponding to each bit, and supplies each of the resulting level-shifted n pieces of display data to the DA conversion unit.

[0006] The DA conversion unit includes a gamma circuit and n selection circuits (decoders) provided corresponding to the n display data segments. The gamma circuit generates, for example, 256 voltages having different voltage values ​​as reference voltages and supplies them to each of the n selection circuits. Each selection circuit selects, from the 256 reference voltages, a reference voltage corresponding to the value indicated by the 8-bit display data segment it receives. With this configuration, the DA conversion unit supplies the n reference voltages selected by each of the n selection circuits to the output amplifier unit as n gradation voltages.

[0007] The output amplifier section amplifies each of the n gray scale voltages individually and supplies the amplified voltages as output voltages to the n data lines of the display panel. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-145492 Summary of the Invention [Problem to be solved by the invention]

[0009] In recent years, with the increase in the size and resolution of display panels, high display quality is required for the waveform of the output voltage that a source driver outputs to the display panel.

[0010] Display data fragments based on video signals are generally binary codes, so a change in the brightness level of the display data fragments supplied to the DA converter by just one gradation per horizontal scanning period can cause logic inversions in many of the bits that make up the display data fragments.

[0011] For example, if a display data fragment changes from a state representing a brightness level of "126" to a state representing "127," the 8-bit binary code of the display data fragment changes from [01111110] to [01111111]. In other words, for a brightness level change of "1," the number of bits changed in the binary code is also "1."

[0012] However, when the display data fragment changes from a state representing a brightness level of "127" to a state representing a brightness level of "128," the 8-bit binary code changes from [01111111] to [10000000]. In other words, the number of bits changing in the binary code for a brightness level change of "1" is "8."

[0013] In this way, in binary code, the Hamming distance between adjacent codes varies between "1" and the total number of bits (for example, 8). Therefore, even if the amount of change in brightness level is "1", the Hamming distance between the codes, that is, the total number of inversions of the logic level for each bit digit, is "8".

[0014] At this time, a current corresponding to the number of inversions of the logic level flows simultaneously in the data register latch and the DA conversion section, generating noise, which may distort the waveform of the output voltage.

[0015] Therefore, an object of the present invention is to provide a digital-to-analog conversion device that can suppress noise and generate a high-quality analog output voltage without distortion, and a display driver and display device that include the digital-to-analog conversion device. [Means for solving the problem]

[0016] The digital-to-analog conversion device of the present invention is a digital-to-analog conversion device that converts a digital data piece consisting of a binary code into an analog voltage, and includes: a Gray code conversion circuit that receives the digital data piece, converts the most significant N (N is an integer of 2 or more) bits of the digital data piece into an N-bit Gray code, and outputs a converted digital data piece consisting of the N-bit Gray code and a K (K is an integer of 2 or more)-bit binary code obtained by excluding the most significant N bits from the digital data piece; a first decoder that receives a plurality of reference voltages having mutually different voltage values ​​and selects two reference voltages from the plurality of reference voltages based on the N-bit Gray code in the converted digital data piece; a second decoder that outputs (K+1) voltages, each having one or the other of the two reference voltages, based on the K-bit binary code in the converted digital data piece; and an amplifier circuit that receives the (K+1) voltages and generates the analog voltage by amplifying the average voltage of the (K+1) voltages.

[0017] A display driver according to the present invention includes first to nth digital-to-analog conversion circuits that receive a series of pixel data pieces that represent the luminance level of each pixel based on a video signal in binary code, and convert each of n (n is an integer of 2 or more) pixel data pieces included in the series of pixel data pieces into first to nth output voltages having voltage values ​​corresponding to the luminance levels, and supply the output voltages to first to nth data lines of a display panel, and further includes a display driver that converts the most significant N (N is an integer of 2 or more) bits in the pixel data pieces into an N-bit Gray code, and combines the N-bit Gray code with a K (K is an integer of 2 or more)-bit binary code obtained by excluding the most significant N bits from the pixel data pieces. and a Gray code conversion circuit that outputs a converted pixel data piece consisting of an N-bit Gray code, and each of the first to nth digital-to-analog conversion circuits has a first decoder that receives a plurality of reference voltages having mutually different voltage values ​​and selects two reference voltages from the plurality of reference voltages based on the N-bit Gray code in the converted pixel data piece, a second decoder that outputs (K+1) voltages, each having one or the other of the two reference voltages, based on the K-bit binary code in the converted pixel data piece, and an amplifier circuit that receives the (K+1) voltages and generates the analog voltage by amplifying the average voltage of the (K+1) voltages.

[0018] A display device according to the present invention is a display device comprising: a display panel on which first to n-th (n is an integer of 2 or more) data lines are arranged, each having a plurality of display cells formed thereon; and a display driver including first to n-th digital-to-analog conversion circuits that receive a series of pixel data pieces that represent the luminance level of each pixel based on a video signal in binary code, and convert each of n (n is an integer of 2 or more) pixel data pieces included in the series of pixel data pieces into first to n-th output voltages having voltage values ​​corresponding to the luminance level, and supply the output voltages to the first to n-th data lines of the display panel, wherein the display driver converts the most significant N (N is an integer of 2 or more) bits in the pixel data pieces into an N-bit Gray code, and converts the N-bit Gray code and the pixel data into a first to n-th output voltage. and a Gray code conversion circuit that outputs a converted pixel data piece consisting of a K-bit (K is an integer greater than or equal to 2) binary code obtained by excluding the most significant N bits from the data piece, and each of the first to nth digital-to-analog conversion circuits has a first decoder that receives a plurality of reference voltages having mutually different voltage values ​​and selects two reference voltages from the plurality of reference voltages based on the N-bit Gray code in the converted pixel data piece, a second decoder that outputs (K+1) voltages, each having one or the other of the two reference voltages, based on the K-bit binary code in the converted pixel data piece, and an amplifier circuit that receives the (K+1) voltages and generates the analog voltage by amplifying the average voltage of the (K+1) voltages. [Effects of the Invention]

[0019] In the present invention, when each digital data piece consisting of binary code is converted into an analog voltage in sequence, only the upper bits of each digital data piece are converted into Gray code, and each converted digital data piece consisting of a mixture of Gray code and binary code is input into a DA conversion circuit.

[0020] This reduces the frequency of bit inversion between adjacent digital data pieces compared to when each piece of digital data, with all bits being binary code, is directly input into the DA conversion circuit, and therefore reduces the current flowing through the DA conversion circuit.

[0021] Therefore, according to the present invention, noise caused by such currents flowing all at once is suppressed, making it possible to output an analog voltage having a high-quality waveform without distortion. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 is a block diagram showing the configuration of a display device 200. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of a data driver 13. [Figure 3] FIG. 2 is a circuit diagram showing a configuration of a Gray code conversion circuit 130. [Figure 4] 10 is a diagram showing a Gray code conversion table used by the Gray code conversion circuit 130. FIG. 11 is a diagram showing an example of binary code-Gray code conversion. [Figure 5] 1 is a block diagram showing an example of the internal configuration of a DA conversion circuit DA1 selected from among the DA conversion circuits DA1 to DAn. [Figure 6] 3 is a diagram illustrating the operation of each of the first decoder DE1 and the second decoder DE2. FIG. [Figure 7] 2 is a circuit diagram showing an example of the internal configuration of an amplifier circuit AP1. FIG. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0023] FIG. 1 is a block diagram showing a schematic configuration of a display device 200 including a display driver according to the present invention.

[0024] As shown in FIG. 1, the display device 200 includes a display panel 10, a display controller 11, a scan driver 12, and a data driver 13 as a display driver.

[0025] The display panel 10 is made of, for example, a liquid crystal or organic EL panel, and includes horizontal scanning lines S1 to Sm (m is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, and data lines D1 to Dn (n is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen. At each intersection of the horizontal scanning lines and the data lines, a display cell PC which serves as a pixel is formed.

[0026] The display controller 11 receives the video signal VS and supplies the scan driver 12 with a scan timing signal that indicates the timing for sequentially selecting the horizontal scan lines S1 to Sm in accordance with the video signal VS.

[0027] Based on the video signal VS, the display controller 11 generates, for each pixel, a video data signal VD including a series of pixel data fragments that represent the brightness level of that pixel using, for example, an 8-bit binary code. Furthermore, the display controller 11 generates various control signals including a start pulse signal STP including a single pulse signal synchronized with the horizontal scanning synchronization signal included in the video signal VS, and a clock signal CLK. The display controller 11 supplies the various control signals including the video data signal VD, start pulse signal STP, and clock signal CLK to the data driver 13.

[0028] The scan driver 12 sequentially applies horizontal scan pulses to each of the horizontal scan lines S1 to Sm of the display panel 10 in response to a scan timing signal supplied from the display controller 11.

[0029] The data driver 13 takes in a series of pixel data pieces included in the video data signal VD in response to various control signals supplied from the display controller 11. Then, the data driver 13 converts each of the pixel data pieces, each consisting of, for example, 8 bits, into an analog voltage and supplies the converted voltages in groups of n to the data lines D1 to Dn of the display panel 10 as output voltages G1 to Gn.

[0030] FIG. 2 is a block diagram showing the internal configuration of the data driver 13. As shown in FIG.

[0031] As shown in FIG. 2, the data driver 13 includes a Gray code conversion circuit 130, a shift register 131, a data latch unit 132, and a DA (digital to analog) conversion unit 133.

[0032] The Gray code conversion circuit 130 receives the video data signal VD and converts the pixel data pieces, each consisting of an 8-bit binary code, contained in the video data signal VD into 8-bit pixel data pieces that are a mixture of Gray code and binary code.

[0033] FIG. 3 is a circuit diagram showing an example of the configuration of the Gray code conversion circuit 130. As shown in FIG.

[0034] FIG. 4 is a diagram showing a Gray code conversion table used by the Gray code conversion circuit 130. As shown in FIG.

[0035] As shown in FIG. 3, the Gray code conversion circuit 130 includes buffers B1 and B2, and exclusive OR circuits EX1 to EX6.

[0036] Here, the Gray code conversion circuit 130 sequentially receives a series of pixel data pieces included in the video data signal VD, each of which represents a luminance level in an 8-bit (d0 to d7) binary code.

[0037] Buffer B1 shown in Figure 3 receives bit d0, which is the least significant bit (LSB) in the pixel data fragment, and outputs this bit d0 as is as bit dx0. Buffer B2 receives bit d1 in the pixel data fragment and outputs this bit d1 as is as bit dx1.

[0038] The exclusive-OR circuit EX1 receives bits d2 and d3 in the pixel data piece and outputs bit dx2 at logic level 1 if the two bits indicate different logic levels and at logic level 0 if the two bits indicate the same logic level. The exclusive-OR circuit EX2 receives bits d3 and d4 in the pixel data piece and outputs bit dx3 at logic level 1 if the two bits indicate different logic levels and at logic level 0 if the two bits indicate the same logic level. The exclusive-OR circuit EX3 receives bits d4 and d5 in the pixel data piece and outputs bit dx4 at logic level 1 if the two bits indicate different logic levels and at logic level 0 if the two bits indicate the same logic level. The exclusive-OR circuit EX4 receives bits d5 and d6 in the pixel data piece and outputs bit dx5 at logic level 1 if the two bits indicate different logic levels and at logic level 0 if the two bits indicate the same logic level. The exclusive OR circuit EX5 receives bits d6 and d7 in the pixel data piece, and outputs bit dx6 at logic level 1 if the two bits indicate different logic levels, and at logic level 0 if the two bits indicate the same logic level. The exclusive OR circuit EX6 receives bit d7 and logic level 0 in the pixel data piece, and outputs bit dx7 at logic level 1 if bit d7 indicates logic level 1, and at logic level 0 if bit d7 indicates logic level 0.

[0039] In this way, the Gray code conversion circuit 130 converts the bits d7 to d2 of the most significant bit group of each pixel data piece expressed in an 8-bit binary code into Gray code bits dx7 to dx2, as shown in Fig. 4. Note that the Gray code conversion circuit 130 directly converts the bits d1 and d0 of the least significant bit group of bits d7 to d0 into bits dx1 and dx0, respectively.

[0040] In other words, the Gray code conversion circuit 130 converts each pixel data piece contained in the video data signal VD into an 8-bit (dx0 to dx7) pixel data piece that is a mixture of Gray code and binary code, with only the most significant 6 bits converted to Gray code.

[0041] The Gray code conversion circuit 130 then supplies the converted pixel data signal VDG, which represents a series of 8-bit converted pixel data pieces (dx0 to dx7) in a mixture of Gray code and binary code, converted as shown in FIG. 4, to the data latch unit 132.

[0042] 2 receives a start pulse signal STP, which is a single pulse signal, and shifts the signal in order in synchronization with a clock signal CLK to generate n latch timing signals SR1 to SRn, each of which produces a single pulse at a different timing. The shift register 131 supplies the latch timing signals SR1 to SRn to a data latch unit 132.

[0043] The data latch unit 132 includes data latches LC1 to LCn that individually receive latch timing signals SR1 to SRn. Data latch LC1 latches one converted pixel data piece from the series of converted pixel data pieces included in the converted pixel data signal VDG at the timing of a single pulse included in the latch timing signal SR1. Data latch LC2 latches one converted pixel data piece from the series of converted pixel data pieces at the timing of a single pulse included in the latch timing signal SR2. Similarly, each of data latches LC3 to LCn latches one converted pixel data piece from the series of converted pixel data pieces included in the converted pixel data signal VDG at the timing of a single pulse included in the latch timing signal SRj (j is an integer from 3 to n) that it receives.

[0044] Then, the data latches LC1 to LCn supply the n pieces of converted pixel data that they have latched to the DA conversion unit 133 as converted pixel data R1 to Rn.

[0045] The DA conversion unit 133 includes a reference voltage generation circuit RFG that generates a plurality of reference voltages V0 to V64 having different voltage values, and DA conversion circuits DA1 to DAn that are provided corresponding to the converted pixel data R1 to Rn, respectively.

[0046] The DA conversion circuits DA1 to DAn individually receive the corresponding converted pixel data R1 to Rn, and convert each of the converted pixel data R1 to Rn into an output voltage G1 to Gn having an analog voltage value using the above-mentioned reference voltages V0 to V64, and output the output voltage G1 to Gn. The DA conversion circuits DA1 to DAn have the same internal configuration.

[0047] FIG. 5 is a block diagram showing the internal configuration of the DA conversion circuit DA1 selected from the DA conversion circuits DA1 to DAn.

[0048] As shown in FIG. 5, the DA conversion circuit DA1 includes a decoder DEC and an amplifier circuit AP1.

[0049] The decoder DEC receives the reference voltages V0 to V64 supplied from the reference voltage generation circuit RFG, and the 8-bit converted pixel data R1 in a mixture of Gray code and binary code.

[0050] The decoder DEC includes a first decoder DE1 and a second decoder DE2.

[0051] The first decoder DE1 receives the most significant 6 bits consisting of bits dx7 to dx2 in the converted pixel data R1 as a most significant bit group MB. The first decoder DE1 defines 1st to 64th gradation groups, which are obtained by dividing all gradations from 0 to 255 that can be expressed by the converted pixel data R1 into 64 gradations that can be expressed using the 6-bit number of the most significant bit group MB.

[0052] Here, first, the first decoder DE1 selects the gradation group that includes the value indicated by the upper bit group MB from among the 1st to 64th gradation groups.

[0053] Next, the first decoder DE1 selects a pair of reference voltages having adjacent voltage values ​​corresponding to the lower and upper limit gradations of the selected gradation group from among the reference voltages V0 to V64. For example, when a first gradation group including the lowest gradation is selected, the first decoder DE1 selects, from among the reference voltages V0 to V64, a reference voltage V0 corresponding to the lower limit gradation of the first gradation group and a reference voltage V1 corresponding to the upper limit gradation. Also, for example, when a second gradation group that is one level higher than the first gradation group is selected, the first decoder DE1 selects, from among the reference voltages V0 to V64, a reference voltage V1 corresponding to the lower limit gradation of the second gradation group and a reference voltage V2 corresponding to the upper limit gradation.

[0054] Then, the first decoder DE1 supplies the selected pair of reference voltages to the second decoder DE2 as selected reference voltages L1 and L2.

[0055] The second decoder DE2 receives the selected reference voltages L1 and L2 as well as the lower two bits dx1 and dx0 in the converted pixel data R1 as a lower bit group LB.

[0056] The second decoder DE2 supplies three voltages, each having the selected reference voltage L1 or L2, as representative voltages T1 to T3 to the amplifier circuit AP1 based on the lower-order bit group LB. For example, when bits dx1 and dx0 indicate (0, 0), the second decoder DE2 supplies three voltages, each having the selected reference voltage L1, as representative voltages T1 to T3 to the amplifier circuit AP1. For example, when bits dx1 and dx0 indicate (0, 1), the second decoder DE2 supplies a voltage having the selected reference voltage L1 as representative voltage T1, a voltage having the selected reference voltage L2 as representative voltage T2, and a voltage having the selected reference voltage L1 as representative voltage T3 to the amplifier circuit AP1. For example, when bits dx1 and dx0 indicate (1, 1), the second decoder DE2 supplies three voltages, each having the selected reference voltage L2, as representative voltages T1 to T3 to the amplifier circuit AP1.

[0057] Figure 6 shows selected reference voltages L1 and L2 output by the first decoder DE1 based on the upper bit group MB (dx7 to dx2), and representative voltages T1 to T3 output by the second decoder DE2 based on the lower bit group LB (dx1, dx0).

[0058] In short, the first decoder DE1 selects two selected reference voltages L1 and L2 from the reference voltages V0 to V64 based on the Gray code of the upper 6 bits (dx7 to dx2) in the converted pixel data R1.

[0059] Then, the second decoder DE2 generates three voltages, each having one or the other of the two selected reference voltages L1 and L2, as representative voltages T1 to T3 based on the binary code of the lower two bits (dx1, dx0) obtained by omitting the upper six bits from the converted pixel data R1. Note that the number of representative voltages, "3," is the number obtained by subtracting 1 from the square of "2," which is the number of bits in the binary code in the converted pixel data R1.

[0060] The amplifier circuit AP1 is an operational amplifier with an interpolation function, with its output terminal connected to its inverting input terminal and three non-inverting input terminals +A1 to +A3 that receive representative voltages T1 to T3, respectively.

[0061] The amplifier circuit AP1 averages the three representative voltages T1 to T3 with a predetermined weighting ratio, thereby obtaining a linearly interpolated two selected reference voltages L1 and L2 selected by the first decoder DE1. K One of the voltages is output as the analog output voltage Vout. Note that "K" is an integer obtained by adding 1 to the number of bits of the binary code in the converted pixel data R1, "2."

[0062] FIG. 7 is a circuit diagram showing an example of the configuration of the amplifier circuit AP1.

[0063] As shown in FIG. 7, the amplifier circuit AP1 includes four N-channel differential pairs (11_1, 12_1) to (11_4, 12_4), current sources 13_1 to 13_4, a current mirror circuit 20, and an amplifier stage 30.

[0064] The current mirror circuit 20 includes P-channel transistors 21 and 22 having the same size and whose gates are connected to each other. A high-level power supply voltage VDDA is applied to the source of each of the transistors 21 and 22. The drain of the transistor 21 is connected to a node n11, and the gate and drain of the transistor 22 are connected to a node n12. The nodes n11 and n12 are connected to the output pairs of the differential pairs (11_1, 12_1) to (11_4, 12_4), respectively. With this configuration, the current mirror circuit 20 operates as a common load for the differential pairs (11_1, 12_1) to (11_4, 12_4).

[0065] The output voltage Vout is fed back to the inverting input terminals of the differential pairs (11_1, 12_1) to (11_4, 12_4), that is, to the gates of the N-channel transistors 12_1 to 12_4.

[0066] A representative voltage T3 is supplied to the non-inverting input terminal of each of the differential pairs (11_1, 12_1) and (11_2, 12_2), i.e., the gates of the N-channel transistors 11_1 and 11_2. A representative voltage T2 is supplied to the non-inverting input terminal of the differential pair (11_3, 12_3), i.e., the gate of the N-channel transistor 11_3. Furthermore, a representative voltage T1 is supplied to the non-inverting input terminal of the differential pair (11_4, 12_4), i.e., the gate of the N-channel transistor 11_4.

[0067] The transistors 11_1 to 11_4 have the same transistor characteristics, and their drains are commonly connected to a node n11. The transistors 12_1 to 12_4 have the same transistor characteristics, and their drains are commonly connected to a node n12. That is, the differential pairs (11_1, 12_1) to (11_4, 12_4) are connected in parallel with their output pairs commonly connected.

[0068] In addition, the sources of the transistor pairs of each of the differential pairs (11_1, 12_1) to (11_4, 12_4) are connected to each other.

[0069] Current sources 13_1 to 13_4 are individually connected between the sources of the differential pairs (11_1, 12_1) to (11_4, 12_4) and the low-level power supply voltage VSSA. The current sources 13_1 to 13_4 generate tail currents to be supplied to the sources of the differential pairs (11_1, 12_1) to (11_4, 12_4).

[0070] The amplifier stage 30 outputs the voltage generated at the output node n0 as the output voltage Vout by sending a current corresponding to the voltage generated at the node n11 to the output node n0.

[0071] With the configuration shown in FIG. 7, the amplifier circuit AP1 assigns preset weighting ratios to the non-inverting input terminals +A1 to +A3, for example, +A1:+A2:+A3=1:1:2 The average voltage of the representative voltages T1 to T3 is calculated, and the following output voltage Vout having a voltage value corresponding to this average voltage is output.

[0072] Vout=(T1+T2+2 T3) / 4 Therefore, according to the DA conversion circuit DA1 shown in Figure 5, by using 65 reference voltages V0 to V64 with different voltage values, it is possible to generate output voltages Vout for 256 gradations with different voltage values, as shown in Figure 6.

[0073] In the data driver 13, not only the DA conversion circuit DA1 but also the DA conversion circuits DA2 to DAn have the configuration shown in FIG.

[0074] Therefore, by using 65 reference voltages V0 to V64, it is possible to express 256 luminance levels, which makes it possible to reduce the circuit area of ​​the reference voltage generation circuit RFG.

[0075] In the data driver 13, before each pixel data piece consisting of an 8-bit binary code (d7 to d0) is taken into the data latch unit 132, the Gray code conversion circuit 130 converts it into a converted pixel data piece consisting of 8 bits that is a mixture of Gray code (upper 6 bits) and binary code (lower 2 bits).

[0076] The Gray code is a code in which the Hamming distance between adjacent codes is always "1".

[0077] Therefore, for example, as shown in Figure 4, if the upper 6 bits (dx7 to dx2) of the 8 bits of the converted pixel data piece are Gray code, the number of bits whose logic levels are inverted within the upper 6 bits between adjacent gradations will be a maximum of "1". Also, as shown in Figure 4, if the lower 2 bits (dx1, dx0) of the 8 bits of the converted pixel data piece are binary code, the number of bits whose logic levels are inverted within the lower 2 bits between adjacent gradations will be a maximum of "2". As a result, according to the 8-bit converted pixel data piece input to the data latch unit 132 and the DA conversion unit 133, the total number of bits whose logic is inverted between adjacent gradations will be a maximum of "3".

[0078] Therefore, in the data latch unit 132 and the DA conversion unit 133, the frequency of inversion of the logic level occurring at each bit is significantly reduced compared to when each receives pixel data pieces consisting of 8-bit binary codes.

[0079] For example, as shown in Figure 4, if a pixel data fragment is an 8-bit binary code and the brightness level represented by this pixel data fragment changes, for example, from 127th to 128th gradation, all 8 bits are logically inverted. Therefore, if the data latch unit 132 and the DA conversion unit 133 receive a pixel data fragment in which all 8 bits are binary coded, the circuits corresponding to each of the 8 bits will operate simultaneously within each unit, causing a sudden increase in current. At this time, the sudden increase in current flowing through the data latch unit 132 and the DA conversion unit 133 will generate noise and distort the waveform of the output voltage Vout.

[0080] In contrast, in the data driver 13, when the brightness level represented by the converted pixel data fragment input to the data latch unit 132 and the DA conversion unit 133 changes, for example, from the 127th gradation to the 128th gradation, the number of bits to be logically inverted is 3 bits, as shown in Figure 4.

[0081] Therefore, the number of bits to be logically inverted is 3 / 8 of that when pixel data pieces each consisting of a binary code of all 8 bits are input to the data latch unit 132 and the DA conversion unit 133. This significantly reduces the current flowing in the data latch unit 132 and the DA conversion unit 133, suppressing noise generation and resulting in a high-quality output voltage Vout without waveform distortion. Furthermore, as shown in FIG. 3, the Gray code conversion circuit 130 converts only a portion (6 bits) of the input pixel data pieces consisting of an 8-bit binary code (d7 to d0) into Gray code, making it possible to reduce the circuit scale compared to when all 8 bits are converted into Gray code.

[0082] In the above embodiment, the number of bits of each pixel data piece to be subjected to DA conversion is 8 bits, but it is not limited to 8 bits.

[0083] In addition, in the Gray code conversion circuit 130, the number of upper bits to be converted into Gray code is set to "6", so the number of remaining lower bits is "2", and accordingly, the second decoder DE2 outputs three representative voltages T1 to T3, which are "2" plus 1.

[0084] However, in the Gray code conversion circuit 130, the number of upper bits to be converted into Gray code is not limited to "6", and furthermore, the number of lower bits to be left as binary code is not limited to "2".

[0085] In the above embodiment, the Gray code conversion circuit 130 and the DA conversion circuits DA1 to DAn included in the data driver 13 can also be mounted on electronic devices other than the data driver 13.

[0086] It is also possible to configure a single digital-to-analog conversion device with no specific application using the Gray code conversion circuit 130 shown in Fig. 3 and the DA conversion circuit DA1 shown in Fig. 7. In short, a digital-to-analog conversion device that converts digital data pieces consisting of binary codes into analog voltages may include the following Gray code conversion circuit, first and second decoders, and an amplifier circuit.

[0087] That is, the Gray code conversion circuit (130) receives a digital data piece and converts the most significant N (N is an integer equal to or greater than 2) bits (e.g., dx7 to dx2) of the digital data piece into an N-bit Gray code. The Gray code conversion circuit (130) then outputs a converted digital data piece (R1) consisting of the N-bit Gray code and a K (K is an integer equal to or greater than 2)-bit (e.g., dx1, dx0) binary code obtained by omitting the most significant N bits from the digital data piece.

[0088] The first decoder (DE1) receives a plurality of reference voltages (e.g., V0 to V64) having different voltage values, and selects two reference voltages (L1, L2) from the plurality of reference voltages based on the N-bit Gray code in the converted digital data piece.

[0089] The second decoder (DE2) outputs (K+1) voltages (e.g., T1 to T3), each having one or the other of the two reference voltages (L1, L2), based on the K-bit (e.g., 2-bit) binary code in the converted digital data piece.

[0090] The amplifier circuit (AP1) receives the (K+1) voltages and amplifies the average voltage to generate an analog voltage (Vout). [Explanation of symbols]

[0091] 13 Data Driver 130 Gray code conversion circuit 133 DA conversion section AP1 amplifier circuit DA1~DAn DA conversion circuit DE1 First decoder DE2 Second decoder RFG reference voltage generation circuit

Claims

1. A digital-to-analog conversion device that converts a digital data piece consisting of a binary code into an analog voltage, a Gray code conversion circuit that receives the digital data piece, converts the most significant N (N is an integer of 2 or more) bits in the digital data piece into an N-bit Gray code, and outputs a converted digital data piece consisting of the N-bit Gray code and a K (K is an integer of 2 or more)-bit binary code obtained by omitting the most significant N bits from the digital data piece; a first decoder for receiving a plurality of reference voltages having different voltage values ​​and selecting two reference voltages from the plurality of reference voltages based on the N-bit Gray code in the converted digital data piece; a second decoder for outputting (K+1) voltages, each having one or the other of the two reference voltages, based on the K-bit binary code in the converted digital data piece; an amplifier circuit that receives the (K+1) voltages and generates the analog voltage by amplifying an average voltage of the (K+1) voltages.

2. 2. The digital-to-analog conversion device according to claim 1, wherein the first decoder selects a pair of adjacent reference voltages having a magnitude corresponding to the Gray code as the two reference voltages from among the plurality of reference voltages.

3. the amplifier circuit is an operational amplifier having an interpolation function, its output terminal and inverting input terminal being connected to each other and having (K+1) non-inverting input terminals that individually receive the (K+1) voltages; The (K+1) voltages are averaged with a predetermined weighting ratio to obtain a linearly interpolated two reference voltages. Ｋ 3. The digital-to-analog conversion device according to claim 1, wherein one of the voltages is output as the analog voltage.

4. a display driver including first to n-th digital-to-analog conversion circuits that receive a series of pixel data pieces that represent, in binary code, a luminance level of each pixel based on a video signal, and convert each of n (n is an integer of 2 or more) pixel data pieces included in the series of pixel data pieces into first to n-th output voltages having voltage values ​​corresponding to the luminance levels, and supply the output voltages to first to n-th data lines of a display panel; a Gray code conversion circuit that converts the most significant N (N is an integer of 2 or more) bits in the pixel data fragment into an N-bit Gray code, and outputs a converted pixel data fragment consisting of the N-bit Gray code and a K (K is an integer of 2 or more)-bit binary code obtained by excluding the most significant N bits from the pixel data fragment; Each of the first to n-th digital-to-analog conversion circuits a first decoder that receives a plurality of reference voltages having different voltage values ​​and selects two reference voltages from the plurality of reference voltages based on the N-bit Gray code in the converted pixel data piece; a second decoder for outputting (K+1) voltages, each having one or the other of the two reference voltages, based on the K-bit binary code in the converted pixel data piece; an amplifier circuit that receives the (K+1) voltages and amplifies an average voltage of the (K+1) voltages to generate the analog voltage.

5. a display panel on which first to n-th (n is an integer of 2 or more) data lines are arranged, each of which has a plurality of display cells formed thereon; a display driver including first to n-th digital-to-analog conversion circuits that receive a series of pixel data pieces that represent, in binary code, a luminance level of each pixel based on a video signal, and convert each of n (n is an integer of 2 or more) pixel data pieces included in the series of pixel data pieces into first to n-th output voltages having voltage values ​​corresponding to the luminance levels, and supply the output voltages to the first to n-th data lines of the display panel, The display driver a Gray code conversion circuit that converts the most significant N (N is an integer of 2 or more) bits in the pixel data fragment into an N-bit Gray code, and outputs a converted pixel data fragment consisting of the N-bit Gray code and a K (K is an integer of 2 or more)-bit binary code obtained by excluding the most significant N bits from the pixel data fragment; Each of the first to n-th digital-to-analog conversion circuits a first decoder that receives a plurality of reference voltages having different voltage values ​​and selects two reference voltages from the plurality of reference voltages based on the N-bit Gray code in the converted pixel data piece; a second decoder for outputting (K+1) voltages, each having one or the other of the two reference voltages, based on the K-bit binary code in the converted pixel data piece; an amplifier circuit that receives the (K+1) voltages and amplifies an average voltage of the (K+1) voltages to generate the analog voltage.

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