Active matrix substrate and liquid crystal display device

Abstract

To provide an active matrix substrate in which a decrease in transmittance caused by a contact hole formed in a flattened layer.SOLUTION: An active matrix substrate includes: first TFTs arranged in pixel regions, respectively; a first flattened layer covering the first TFTs; pixel electrodes provided in the first flattened layer; and first connection electrodes located under the first flattened layer, each electrically connecting an oxide semiconductor layer and each pixel electrode. The first flattened layer has pixel contact holes formed so as to expose portions of the first connection electrodes. The active matrix substrate further includes second connection electrodes, each of the second connection electrodes electrically connecting each of the first connection electrodes and each of the pixel electrodes, and being in contact with each of the first connection electrodes in each of the pixel contact holes, and second flattened layers formed such that the pixel contact holes are filled with, respectively. An equivalent circle diameter d1 of a bottom surface of each of the pixel contact holes is three times or more and five times or less than an equivalent circle diameter d2 of an upper surface of each of the second flattened layers.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to an active matrix substrate and a liquid crystal display device. [Background technology]

[0002] Currently, liquid crystal display devices equipped with active matrix substrates are widely used for various applications. Active matrix substrates have switching elements for each pixel area. Active matrix substrates that have thin film transistors (TFTs) as switching elements are called TFT substrates.

[0003] The TFT substrate has TFTs and pixel electrodes provided for each pixel region, gate wiring that supplies gate signals to the TFTs, and source wiring that supplies source signals to the TFTs. The gate electrodes, source electrodes, and drain electrodes of the TFTs are electrically connected to the gate wiring, source wiring, and pixel electrodes, respectively. The TFTs are covered with an interlayer insulating layer.

[0004] A planarization layer (organic insulating film) may be formed on the interlayer insulating layer to flatten the surface. Forming the planarization layer can also reduce load capacitance (parasitic capacitance) and power consumption. Photosensitive resin materials are often used as the material for the planarization layer. When a planarization layer is formed, the pixel electrode is provided on the planarization layer and connected to the drain electrode of the TFT through a contact hole formed in the planarization layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-187714 Summary of the Invention [Problem to be solved by the invention]

[0006] To achieve sufficient planarization and load capacitance reduction effects, the photosensitive resin material is applied thickly (for example, several micrometers thick) when forming the planarization layer. Therefore, to form contact holes that reliably expose the layer below the planarization layer, it is necessary to provide the photosensitive resin material with sufficient exposure energy during exposure so that it is fully exposed in the depth direction. Specifically, exposure is performed by extending the exposure time or increasing the size of the mask pattern so that the area to be removed by photolithography is more reliably exposed. Therefore, to form contact holes reliably (so that the layer below is more reliably exposed), the finished diameter of the contact hole must be increased.

[0007] Contact holes cause light leakage due to the disturbance of the alignment state of liquid crystal molecules near the contact holes, resulting in a decrease in contrast ratio and display quality. Providing a light-shielding layer that blocks light from the vicinity of the contact holes can prevent the decrease in contrast ratio and display quality, but the area contributing to display in the pixel region is reduced by the amount of the light-shielding layer, resulting in a decrease in transmittance (light utilization efficiency). In high-resolution (e.g., 1000 ppi or higher) liquid crystal display devices such as those used in head-mounted displays, the proportion of the pixel region occupied by contact holes becomes large, resulting in a significant decrease in transmittance as described above.

[0008] Patent Document 1 discloses a configuration that can make shallow contact holes formed in a planarization layer (organic insulating film). In the configuration disclosed in Patent Document 1, an electrode (called a "metal portion" in Patent Document 1) that electrically connects a polysilicon semiconductor layer, which is the active layer of a TFT, to a pixel electrode is raised by a structure called a "pedestal" provided directly below it, which makes it possible to make shallow contact holes formed in the planarization layer.

[0009] However, if a complex structure such as that disclosed in Patent Document 1 is actually formed within a pixel, there is a concern about light leakage, and it is therefore considered necessary to shield the area near the pedestal by some method. Therefore, even if the configuration disclosed in Patent Document 1 is adopted, it is difficult to significantly improve the transmittance (significantly improve the aperture ratio). Furthermore, the addition of various processes to form the pedestal increases the process load, which also creates the problem of increasing the manufacturing costs of the TFT substrate.

[0010] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an active matrix substrate in which a decrease in transmittance caused by contact holes formed in a planarizing layer is suppressed. [Means for solving the problem]

[0011] This specification discloses an active matrix substrate and a liquid crystal display device described in the following items.

[0012] [Item 1] a display area defined by a plurality of pixel areas; A substrate; a first TFT supported by the substrate and disposed in each of the plurality of pixel regions; a first planarization layer covering the first TFT; a pixel electrode provided on the first planarization layer and electrically connected to the first TFT; Equipped with The first TFT is a lower gate electrode provided on the substrate; a lower gate insulating layer covering the lower gate electrode; an oxide semiconductor layer provided on the lower gate insulating layer, the oxide semiconductor layer including a channel region facing the lower gate electrode via the lower gate insulating layer, and a source contact region and a drain contact region located on both sides of the channel region; an upper gate insulating layer provided on the channel region of the oxide semiconductor layer; an upper gate electrode provided on the upper gate insulating layer and facing the channel region of the oxide semiconductor layer via the upper gate insulating layer, a first connection electrode located under the first planarization layer for electrically connecting the drain contact region of the oxide semiconductor layer and the pixel electrode; the first planarization layer has a pixel contact hole formed so as to expose a portion of the first connection electrode; when viewed from a normal direction of the substrate, a bottom surface of the pixel contact hole at least partially overlaps with at least the lower gate metal layer of a lower gate metal layer including the lower gate electrode and an upper gate metal layer including the upper gate electrode; the first connection electrode is made of a transparent conductive material, The active matrix substrate comprises: a second connection electrode formed of a transparent conductive material and electrically connecting the first connection electrode and the pixel electrode, the second connection electrode being in contact with the first connection electrode at the pixel contact hole; a second planarization layer formed to fill the pixel contact hole and cover a part of the second connection electrode; Furthermore, an active matrix substrate, wherein a ratio of a circle-equivalent diameter d2 of the upper surface of the second planarization layer to a circle-equivalent diameter d1 of the bottom surface of the pixel contact hole is 3 or more and 5 or less;

[0013] [Item 2] In a cross section parallel to the normal direction of the substrate, an axis perpendicular to the normal direction of the substrate is defined as an x-axis, an axis parallel to the normal direction of the substrate is defined as a y-axis, and the lowest point of the side surface of the pixel contact hole is located on the x-axis in a range of x>0, the side surface of the pixel contact hole has a shape approximated by the following formula (1): y=A*ln(x)+B (1) 2. The active matrix substrate according to claim 1, wherein the units of the x-axis and y-axis are each μm, 0.70≦A≦0.80, and B>0.

[0014] [Item 3] When a region of the upper surface of the first planarization layer in which the pixel contact hole is not formed is called a flat region, 3. The active matrix substrate according to item 1 or 2, wherein the difference in height between the highest part of the upper surface of the second planarization layer and the flat region is 0.5 μm or less.

[0015] [Item 4] the pixel electrode is in contact with a portion of the second connection electrode that is not covered with the second planarization layer, 4. The active matrix substrate according to any one of items 1 to 3, wherein the pixel electrode includes a portion located on the second planarization layer.

[0016] [Item 5] 5. The active matrix substrate according to any one of items 1 to 4, wherein, when viewed from a normal direction of the substrate, a bottom surface of the pixel contact hole at least partially overlaps with at least the lower gate electrode of the lower gate electrode and the upper gate electrode.

[0017] [Item 6] the lower gate metal layer includes a lower gate wiring electrically connected to the lower gate electrode, the upper gate metal layer includes an upper gate wiring electrically connected to the upper gate electrode, 5. The active matrix substrate according to any one of items 1 to 4, wherein, when viewed from a normal direction of the substrate, a bottom surface of the pixel contact hole at least partially overlaps at least the lower gate wiring out of the lower gate wiring and the upper gate wiring.

[0018] [Item 7] 5. The active matrix substrate according to any one of items 1 to 4, wherein, when viewed from a normal direction of the substrate, a bottom surface of the pixel contact hole at least partially overlaps both the lower gate metal layer and the upper gate metal layer.

[0019] [Item 8] 8. The active matrix substrate according to item 7, wherein, when viewed from the normal direction of the substrate, the bottom surface of the pixel contact hole at least partially overlaps both the lower gate electrode and the upper gate electrode.

[0020] [Item 9] the lower gate metal layer includes a lower gate wiring electrically connected to the lower gate electrode, the upper gate metal layer includes an upper gate wiring electrically connected to the upper gate electrode, 8. The active matrix substrate according to item 7, wherein, when viewed from the normal direction of the substrate, the bottom surface of the pixel contact hole at least partially overlaps both the lower gate line and the upper gate line.

[0021] [Item 10] 5. The active matrix substrate according to any one of items 1 to 4, wherein, when viewed from the normal direction of the substrate, the entire bottom surface of the pixel contact hole overlaps both the lower gate metal layer and the upper gate metal layer.

[0022] [Item 11] Item 11. The active matrix substrate according to item 10, wherein the entire bottom surface of the pixel contact hole overlaps both the lower gate electrode and the upper gate electrode when viewed from the normal direction of the substrate.

[0023] [Item 12] the lower gate metal layer includes a lower gate wiring electrically connected to the lower gate electrode, the upper gate metal layer includes an upper gate wiring electrically connected to the upper gate electrode, Item 11. The active matrix substrate according to item 10, wherein the entire bottom surface of the pixel contact hole overlaps both the lower gate wiring and the upper gate wiring when viewed from the normal direction of the substrate.

[0024] [Item 13] the first TFT has a source electrode electrically connected to the source contact region; 13. The active matrix substrate according to any one of items 1 to 12, wherein, when viewed from the normal direction of the substrate, the bottom surface of the pixel contact hole at least partially overlaps the source metal layer including the source electrode.

[0025] [Item 14] the source metal layer includes an island electrode provided separately from the source electrode, Item 14. The active matrix substrate according to item 13, wherein the bottom surface of the pixel contact hole at least partially overlaps the island electrode when viewed from the normal direction of the substrate.

[0026] [Item 15] the source metal layer includes a source wiring electrically connected to the source electrode, Item 14. The active matrix substrate according to item 13, wherein the bottom surface of the pixel contact hole at least partially overlaps the source line when viewed from the normal direction of the substrate.

[0027] [Item 16] 16. The active matrix substrate according to any one of items 1 to 15, wherein a portion of the first connection electrode is in contact with the drain contact region of the oxide semiconductor layer.

[0028] [Item 17] 17. The active matrix substrate according to any one of items 1 to 16, wherein the second connection electrode and the pixel electrode are formed from the same transparent conductive material.

[0029] [Item 18] Item 18. The active matrix substrate according to item 17, wherein the second connection electrode and the pixel electrode are formed from indium zinc oxide.

[0030] [Item 19] a non-display area located around the display area, Item 19. The active matrix substrate of any one of items 1 to 18, further comprising a second TFT provided in the non-display area and supported by the substrate, the second TFT including a crystalline silicon semiconductor layer.

[0031] [Item 20] the second TFT includes a gate electrode provided on an insulating layer covering the crystalline silicon semiconductor layer, the gate electrode facing the crystalline silicon semiconductor layer via the insulating layer; Item 20. The active matrix substrate according to item 19, wherein the gate electrode of the second TFT is formed in the same layer as the lower gate electrode of the first TFT.

[0032] [Item 21] 21. The active matrix substrate according to any one of items 1 to 20, wherein the oxide semiconductor layer includes an In—Ga—Zn—O-based semiconductor.

[0033] [Item 22] An active matrix substrate according to any one of items 1 to 21, an opposing substrate provided opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A liquid crystal display device comprising: [Effects of the Invention]

[0034] According to an embodiment of the present invention, it is possible to provide an active matrix substrate in which a decrease in transmittance caused by contact holes formed in a planarizing layer is suppressed. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a schematic diagram showing an example of a planar structure of an active matrix substrate 100 according to an embodiment of the present invention. [Figure 2] FIG. 1 is a plan view schematically showing an active matrix substrate 100. [Figure 3] 3A is a cross-sectional view schematically showing the active matrix substrate 100, taken along line 3A-3A' in FIG. [Figure 4] FIG. 1 is a plan view schematically showing an active matrix substrate 900 of a comparative example. [Figure 5] 5A is a cross-sectional view schematically showing an active matrix substrate 900, taken along line 5A-5A' in FIG. [Figure 6] 9A and 9B are diagrams for explaining the reason why transmittance decreases in the active matrix substrate 900. FIG. [Figure 7] 1 is a diagram for explaining why transmittance is improved in the active matrix substrate 100. FIG. [Figure 8A] 10A to 10C are diagrams for explaining a series of steps for filling the pixel contact hole CHP with the second planarization layer 17. FIG. [Figure 8B] 10A to 10C are diagrams for explaining a series of steps for filling the pixel contact hole CHP with the second planarization layer 17. FIG. [Figure 8C] 10A to 10C are diagrams for explaining a series of steps for filling the pixel contact hole CHP with the second planarization layer 17. FIG. [Figure 8D] 10A to 10C are diagrams for explaining a series of steps for filling the pixel contact hole CHP with the second planarization layer 17. FIG. [Figure 8E] 10A to 10C are diagrams for explaining a series of steps for filling the pixel contact hole CHP with the second planarization layer 17. FIG. [Figure 9] 2 is a cross-sectional view showing a pixel contact hole CHP of the active matrix substrate 100 and its vicinity. FIG. [Figure 10] This figure shows a state in which, in a cross section parallel to the normal direction of the substrate 1, the lowest point p1 of the side surface 16s of the pixel contact hole CHP is the origin, the axis that passes through the origin and is perpendicular to the normal direction of the substrate 1 is the x-axis, and the axis that passes through the origin and is parallel to the normal direction of the substrate 1 is the y-axis. [Figure 11A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 11B]1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 11C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 11D] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 12A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 12B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 12C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 13A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 13B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 13C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 14A] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 14B] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 14C] 1A to 1C are cross-sectional views showing the manufacturing process of the active matrix substrate 100. [Figure 15] This figure shows the shape of the second planarization layer 17 when the thermal history of post-baking during formation of the second planarization layer 17 is sufficiently long, with the upper, middle, and lower rows showing the cases of under-exposure, proper exposure, and over-exposure, respectively. [Figure 16A] 10 is a scatter diagram (graph) plotting the side surface shapes of pixel contact holes CHP in the example, showing the case where there is no misalignment of the multi-tone photomask. [Figure 16B]10 is a scatter diagram (graph) plotting the side surface shape of the pixel contact hole CHP of the example, showing the case where the alignment of the multi-tone photomask is shifted in the negative direction (to the left in the diagram). [Figure 16C] 10 is a scatter diagram (graph) plotting the side surface shape of the pixel contact hole CHP of the example, showing the case where the alignment of the multi-tone photomask is shifted in the positive direction (to the right in the diagram). [Figure 17A] 10 is a scatter diagram (graph) plotting the side surface shapes of pixel contact holes CHP in Reference Example 1, showing the case where there is no misalignment of the multi-tone photomask. [Figure 17B] 1 is a scatter diagram (graph) plotting the side surface shapes of pixel contact holes CHP in Reference Example 1, showing the case where the alignment of the multi-tone photomask is shifted in the negative direction (to the left in the diagram). [Figure 17C] 1 is a scatter diagram (graph) plotting the side surface shapes of pixel contact holes CHP in Reference Example 1, showing the case where the alignment of the multi-tone photomask is shifted in the positive direction (to the right in the diagram). [Figure 18A] 10 is a scatter diagram (graph) plotting the side surface shapes of pixel contact holes CHP in Reference Example 2, showing the case where there is no misalignment of the multi-tone photomask. [Figure 18B] 10 is a scatter diagram (graph) plotting the side surface shapes of pixel contact holes CHP in Reference Example 2, showing the case where the alignment of the multi-tone photomask is shifted in the negative direction (to the left in the diagram). [Figure 18C] 10 is a scatter diagram (graph) plotting the side surface shapes of pixel contact holes CHP in Reference Example 2, showing the case where the alignment of the multi-tone photomask is shifted in the positive direction (to the right in the diagram). [Figure 19] 10 is a schematic diagram created based on cross-sectional observation of a pixel contact hole CHP of Reference Example 2. FIG. [Figure 20] 10 is a schematic diagram created based on a cross-sectional observation of a pixel contact hole CHP in an example. FIG. [Figure 21]2 is a cross-sectional view schematically showing a spacer receiving portion rp provided on the active matrix substrate 100. FIG. [Figure 22] FIG. 10 is a plan view schematically showing another active matrix substrate 200 according to an embodiment of the present invention. [Figure 23] 23A is a cross-sectional view schematically showing the active matrix substrate 200, taken along line 23A-23A' in FIG. 22. FIG. [Figure 24] FIG. 10 is a plan view schematically showing still another active matrix substrate 300 according to an embodiment of the present invention. [Figure 25] 25A is a cross-sectional view schematically showing an active matrix substrate 300, taken along line 25A-25A' in FIG. 24. FIG. [Figure 26] 26A is a cross-sectional view schematically showing an active matrix substrate 300, taken along line 26A-26A' in FIG. 24. FIG. [Figure 27] FIG. 10 is a cross-sectional view schematically showing still another active matrix substrate 400 according to an embodiment of the present invention. [Figure 28] FIG. 1 is a cross-sectional view that schematically shows a liquid crystal display device 1000 that includes an active matrix substrate 100 (200, 300, 400) according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0036] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following, an active matrix substrate for a liquid crystal display device will be exemplified as an embodiment of the present invention, but the present invention is not limited to the following embodiment.

[0037] [Embodiment 1] An active matrix substrate 100 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing an example of the planar structure of the active matrix substrate 100.

[0038] As shown in FIG. 1, the active matrix substrate 100 has a display region DR and a non-display region (also called a "frame region") FR. The display region DR is defined by a plurality of pixel regions P. The pixel regions P are arranged in a matrix having a plurality of rows and a plurality of columns. The pixel regions P correspond to the pixels of the liquid crystal display device, and may also be simply called "pixels." The non-display region FR is located on the periphery of the display region DR and does not contribute to display.

[0039] In the display region DR, a plurality of gate lines GL extending in the row direction and a plurality of source lines SL extending in the column direction are formed. Each pixel region P is, for example, a region surrounded by a pair of adjacent gate lines GL and a pair of adjacent source lines SL.

[0040] Peripheral circuits are arranged in the non-display region FR. Here, a gate driver GD that drives the gate lines GL is integrally (monolithically) formed in the non-display region FR, and a source driver SD that drives the source lines SL is also implemented. Note that a source shared driving (SSD) circuit that drives the source bus lines SL in a time-division manner may also be arranged in the non-display region FR, or the SSD circuit may be integrally formed like the gate driver GD.

[0041] Each pixel region P of the display region DR is provided with a thin film transistor (TFT) 10 and a pixel electrode 18 electrically connected to the TFT 10. The TFT 10 arranged in each pixel region P is sometimes referred to as a "pixel TFT." The TFT 10 is supplied with a gate signal (scanning signal) from the corresponding gate line GL and a source signal (display signal) from the corresponding source line SL. For simplicity of explanation, FIG. 1 illustrates one gate line GL for each pixel row; however, as described below, a lower gate line and an upper gate line may be provided for each pixel row, and each TFT 10 may be supplied with a gate signal from the lower gate line and the upper gate line.

[0042] Next, a more specific configuration of the active matrix substrate 100 will be described with reference to Figures 2 and 3. Figure 2 is a plan view schematically showing the active matrix substrate 100. Figure 3 is a cross-sectional view schematically showing the active matrix substrate 100, showing a cross section taken along line 3A-3A' in Figure 2.

[0043] As shown in Figures 2 and 3, the active matrix substrate 100 comprises a substrate 1, a TFT 10 supported on the substrate 1, a planarization layer 16 covering the TFT 10, and a pixel electrode 18 provided on the planarization layer 16.

[0044] The substrate 1 is transparent and insulating, and is, for example, a glass substrate or a plastic substrate.

[0045] The TFT 10 is disposed in each pixel region P. The TFT 10 has a lower gate electrode 2, a lower gate insulating layer 3, an oxide semiconductor layer 4, an upper gate insulating layer 5, an upper gate electrode 6, and a source electrode 7. In other words, the TFT 10 has a double-gate structure.

[0046] The lower gate electrode 2 is provided on the substrate 1. The lower gate electrode 2 is electrically connected to the corresponding lower gate wiring GLA. In the illustrated example, a part of the lower gate wiring GLA (specifically, the part facing the oxide semiconductor layer 4) functions as the lower gate electrode 2. In this specification, the lower gate electrode 2 and wiring and / or electrodes formed in the same layer as the lower gate electrode 2 (by patterning the same conductive film) are collectively referred to as the "lower gate metal layer." Here, the lower gate metal layer includes the lower gate electrode 2 and the lower gate wiring GLA. The lower gate insulating layer 3 covers the lower gate electrode 2.

[0047] The oxide semiconductor layer 4 is provided on the lower gate insulating layer 3. The oxide semiconductor layer 4 includes a channel region 4c facing the lower gate electrode 2 with the lower gate insulating layer 3 interposed therebetween, and a source contact region 4s and a drain contact region 4d located on both sides of the channel region 4c.

[0048] The upper gate insulating layer 5 is provided on the channel region 4c of the oxide semiconductor layer 4. The upper gate electrode 6 is provided on the upper gate insulating layer 5 and faces the channel region 4c of the oxide semiconductor layer 4 via the upper gate insulating layer 5. The upper gate electrode 6 is electrically connected to the corresponding upper gate wiring GLB. In the illustrated example, a part of the upper gate wiring GLB (specifically, the part facing the oxide semiconductor layer 4) functions as the upper gate electrode 6. In this specification, the upper gate electrode 6 and wiring and / or electrodes formed in the same layer as the upper gate electrode 6 (by patterning the same conductive film) are collectively referred to as the "upper gate metal layer." Here, the upper gate metal layer includes the upper gate electrode 6 and the upper gate wiring GLB. The upper gate electrode 6 may be given the same potential as the lower gate electrode 2, or may be given a different potential for threshold control. When the upper gate electrode 6 and the lower gate electrode 2 are given the same potential, the upper gate wiring GLB and the lower gate wiring GLA may be electrically connected. Furthermore, when the upper gate electrode 6 and the lower gate electrode 2 are given the same potential, one of the upper gate electrode 6 and the lower gate electrode 2 may be an island electrode electrically connected to the other.

[0049] A first interlayer insulating layer 8 is provided so as to cover the upper gate electrode 6 and the oxide semiconductor layer 4. The source electrode 7 is provided on the first interlayer insulating layer 8. A source contact hole CH is formed in the first interlayer insulating layer 8 so as to expose a part of the source contact region 4s of the oxide semiconductor layer 4. Sare formed. The source electrode 7 is in contact with the source contact region 4s through the source contact hole and is electrically connected to the source contact region 4s. The source electrode 7 is electrically connected to the corresponding source wiring SL. In the illustrated example, a part of the source wiring SL (specifically, the part facing the oxide semiconductor layer 4) functions as the source electrode 7. In this specification, the source electrode 7 and wiring and / or electrodes formed in the same layer as the source electrode 7 (by patterning the same conductive film) are collectively referred to as the "source metal layer." Here, the source metal layer includes the source electrode 7 and the source wiring SL.

[0050] A second interlayer insulating layer 9 is provided to cover the TFT 10, and a planarization layer 16 is formed on the second interlayer insulating layer 9. The planarization layer 16 is made of, for example, a photosensitive resin material. A pixel electrode 18 is provided on the planarization layer 16. The pixel electrode 18 is electrically connected to the TFT 10.

[0051] The active matrix substrate 100 shown as an example is used in a FFS (Fringe Field Switching) mode liquid crystal display device, and further includes, although not shown here, a dielectric layer provided so as to cover the pixel electrodes 18, and a common electrode provided on the dielectric layer and facing the pixel electrodes 18. At least one slit is formed in the common electrode for each pixel region P.

[0052] The active matrix substrate 100 includes a connection electrode 14 located under the planarization layer 16, for electrically connecting the drain contact region 4d of the oxide semiconductor layer 4 to the pixel electrode 18. The connection electrode 14 is made of a transparent conductive material and is provided on the second interlayer insulating layer 9. The first interlayer insulating layer 8 and the second interlayer insulating layer 9 have a drain contact hole CH formed therein so that a part of the drain contact region 4d of the oxide semiconductor layer 4 is exposed. D A part of the connection electrode 14 is formed through the drain contact hole CH D , it contacts the drain contact region 4d.

[0053] The planarization layer 16 has a pixel contact hole CH formed so as to expose a part of the connection electrode 14. P A part of the pixel electrode 18 is formed through a pixel contact hole CH P In this case, the pixel contact hole CH P The top and bottom surfaces 16b are both substantially circular.

[0054] When viewed from the normal direction of the substrate 1, the pixel contact hole CH P The bottom surface 16b of the pixel contact hole CH at least partially overlaps both the lower gate metal layer and the upper gate metal layer. P The bottom surface 16b of the pixel contact hole CH at least partially overlaps both the lower gate electrode 2 and the upper gate electrode 6. In the illustrated example, P The entire bottom surface 16 b of the gate electrode 16 overlaps both the lower gate metal layer and the upper gate metal layer, more specifically, both the lower gate electrode 2 and the upper gate electrode 6 .

[0055] 3, the active matrix substrate 200 of this embodiment includes, in addition to the connection electrode 14 and planarization layer 16 already described, a further connection electrode 15 and a further planarization layer 17. In the following description, the connection electrode 14 and the planarization layer 16 will be referred to as the "first connection electrode" and the "first planarization layer," respectively, and the further connection electrode 15 and the further planarization layer 17 will be referred to as the "second connection electrode" and the "second planarization layer," respectively.

[0056] The second connection electrode 15 is made of a transparent conductive material and electrically connects the first connection electrode 14 and the pixel electrode 18. The second connection electrode 15 is formed through the pixel contact hole CH P The first connection electrode 14 is in contact with the first connection electrode 14 at this point.

[0057] The second planarization layer 17 is formed by the pixel contact hole CH PThe second planarization layer 17 is formed so as to fill the gap between the second connection electrode 15 and the second connection electrode 15. The second planarization layer 17 is formed of, for example, a photosensitive resin material. Here, both the top surface 17t and the bottom surface of the second planarization layer 17 are approximately circular.

[0058] The pixel electrode 18 is in contact with the portion of the second connection electrode 15 that is not covered with the second planarization layer 17. The pixel electrode 18 includes a portion that is located on the second planarization layer 17.

[0059] Here, the second connection electrode 15 and the pixel electrode 18 are formed from the same transparent conductive material. The second connection electrode 15 and the pixel electrode 18 are formed from, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0060] As described above, in the active matrix substrate 100 of this embodiment, the pixel contact holes CH formed in the first planarization layer 16 P The bottom surface 16b of the oxide semiconductor layer 4 at least partially overlaps both the lower gate electrode 2 and the upper gate electrode 6. The first connection electrode 14 for electrically connecting the drain contact region 4d of the oxide semiconductor layer 4 and the pixel electrode 18 is made of a transparent conductive material. The active matrix substrate 100 has such a configuration, which can improve the transmittance. The reason for this will be explained below.

[0061] 4 and 5 show an active matrix substrate 900 as a comparative example. Fig. 4 is a plan view schematically showing the active matrix substrate 900. Fig. 5 is a cross-sectional view schematically showing the active matrix substrate 900, showing a cross section taken along line 5A-5A' in Fig. 4.

[0062] The active matrix substrate 900 of the comparative example includes a TFT 10 with a double gate structure, similar to the liquid crystal display device 100. However, in the active matrix substrate 900 of the comparative example, the pixel contact hole CH PWhen viewed from the normal direction of the substrate 1, the pixel contact hole CH does not overlap with either the lower gate electrode 2 or the upper gate electrode 6, but overlaps with the drain contact region 4d of the oxide semiconductor layer 4. P When viewed from the normal direction of the substrate 1, the drain contact hole CH formed in the first interlayer insulating layer 8 and the second interlayer insulating layer 9 is D is the pixel contact hole CH P A part of the pixel electrode 18 is disposed so as to be located within the drain contact hole CH D 1, the pixel electrode 18 is in contact with the drain contact region 4d of the oxide semiconductor layer 4, thereby electrically connecting the pixel electrode 18 to the oxide semiconductor layer 4. Therefore, the active matrix substrate 900 of the comparative example does not include the first connection electrode 14 and the second connection electrode 15.

[0063] In addition, in the active matrix substrate 900 of the comparative example, when viewed from the normal direction of the substrate 1, the pixel contact holes CH P The light-shielding layer 11 is formed on the substrate 1, and a base coat layer 12 is provided to cover the light-shielding layer 11. The TFT 10 is formed on the base coat layer 12.

[0064] In the active matrix substrate 900 of the comparative example, in order to reliably electrically connect the pixel electrode 18 and the oxide semiconductor layer 4, the drain contact hole CH D and pixel contact hole CH P However, if the positions of the two are too close, the drain contact hole CH D There is a concern that the photosensitive resin material constituting the planarization layer 16 will remain at the bottom of the drain contact hole CH, which may cause a conduction failure. D The pixel contact hole CH P The opening diameter of the pixel contact hole CH must be large enough. P Therefore, it is necessary to set the exposure time when forming the pixel contact hole CH Pis the pixel contact hole CH P The drain contact hole CH D It is difficult to reduce the size of the pixel contact hole CH with respect to the opening diameter of the pixel contact hole CH. P This disturbs the alignment of the liquid crystal molecules, which causes a decrease in the contrast ratio and display quality due to light leakage in the liquid crystal display device. P It is necessary to shield the vicinity from light, but in that case, as shown in FIG. 6, the light from the backlight is blocked by the light-shielding layer 11 and the black matrix, resulting in a decrease in transmittance.

[0065] Furthermore, as already explained, Patent Document 1 discloses a configuration that can make shallow contact holes formed in a planarization layer (organic insulating film). In the configuration disclosed in Patent Document 1, the electrode (metal portion) that electrically connects the polysilicon semiconductor layer, which is the active layer of the TFT, to the pixel electrode is raised by a pedestal portion provided directly below it, thereby making it possible to make shallow contact holes formed in the planarization layer.

[0066] However, when a complex structure such as that disclosed in Patent Document 1 is actually formed within a pixel, there is a concern about light leakage. For example, a phenomenon in which the edges of island-shaped metal parts shine (a phenomenon known as streaks) may occur. To prevent light leakage due to such streaks, it is considered necessary to shield the vicinity of the metal parts (the vicinity of the pedestal) with a light-shielding layer on the active matrix substrate or a black matrix on the opposing substrate. Therefore, while the configuration disclosed in Patent Document 1 allows shallow contact holes to be formed, it is difficult to significantly improve transmittance (significantly improve aperture ratio).

[0067] In contrast, in the active matrix substrate 100 of this embodiment, when viewed from the normal direction of the substrate 1, the pixel contact holes CH PThe bottom surface 16b of the pixel contact hole CH at least partially overlaps both the lower gate electrode 2 and the upper gate electrode 6. This allows the thickness of the photosensitive resin material to be increased to the thickness of the pixel contact hole CH when the photosensitive resin material is exposed to light. P In the region where the pixel contact hole CH is formed, the pixel contact hole CH is reduced by the thickness of the lower gate electrode 2 and the upper gate electrode 6, and the exposure light is reflected by the lower gate electrode 2 and / or the upper gate electrode 6. Therefore, the pixel contact hole CH can be formed with a shorter exposure time and a smaller mask pattern. P Therefore, the pixel contact hole CH P The opening diameter of the pixel contact hole CH can be reduced. P Since the diameter of the opening can be reduced, the lower gate electrode 2 and the upper gate electrode 6 can sufficiently block light without forming a light-shielding layer, thereby improving transmittance. The active matrix substrate 100 of this embodiment does not require the formation of a separate structure such as the pedestal disclosed in Patent Document 1.

[0068] In the active matrix substrate 100 of this embodiment, the first connection electrode 14 for electrically connecting the drain contact region 4d of the oxide semiconductor layer 4 to the pixel electrode 18 is made of a transparent conductive material. Therefore, as shown in FIG. 7, the periphery of the drain contact region 4d (the drain contact hole CH D This allows the surrounding area to contribute to the display, and the aperture ratio can be increased to further improve the transmittance.

[0069] In addition, when a polysilicon semiconductor layer is used as the active layer of the TFT as in Patent Document 1, the junction between the polysilicon semiconductor and a material exhibiting n-type semiconductor characteristics, such as ITO or IZO, used as a transparent conductive material, is a heterojunction between different semiconductors with significantly different energy levels, and does not form an ohmic contact, making direct contact impossible. Therefore, the connection electrode for electrically connecting the polysilicon semiconductor layer to the pixel electrode must be made of a metal material. In contrast, when the active layer of the TFT 10 is an oxide semiconductor layer 4, as in this embodiment, the oxide semiconductor layer 4 has similar components and electrical properties to transparent conductive materials (e.g., ITO or IZO), so the first connection electrode 14 can be made of a transparent conductive material. If the first connection electrode 14 is made of a transparent conductive material, striations do not occur, and the drain contact hole CH D The periphery can also contribute to the display.

[0070] In addition, the pixel contact hole CH P When viewed from the normal direction of the substrate 1, the bottom surface 16b of the pixel contact hole CH is at least partially overlapped with at least the lower gate electrode 2 of the lower gate electrode 2 and the upper gate electrode 6. P However, from the viewpoint of further improving the transmittance, it is necessary to reduce the opening diameter of the pixel contact hole CH P The bottom surface 16b of the pixel contact hole CH preferably at least partially overlaps both the lower gate electrode 2 and the upper gate electrode 6. P It is more preferable that the entire bottom surface 16 b overlaps both the lower gate electrode 2 and the upper gate electrode 6 .

[0071] As described above, in the active matrix substrate 100 of this embodiment, the pixel contact holes CH P The decrease in transmittance caused by the above is suppressed.

[0072] In addition, in the active matrix substrate 100 of this embodiment, the pixel contact holes CH PThe second planarization layer 17 is formed to fill the pixel contact hole CH P 3 shows an example in which the size of the second connection electrode 15 is smaller than the size of the pixel electrode 18, the size of the second connection electrode 15 may be substantially the same as the size of the pixel electrode 18.

[0073] The second planarization layer 17 can be formed by, for example, applying a photosensitive resin material, exposing it to light, developing it, and baking it (post-baking). During the exposure, a multi-tone photomask is used as a photomask, so that the pixel contact holes CH are formed by the second planarization layer 17. P The inside of the mask can be filled with precision. Specifically, gray-tone masks and half-tone masks can be used as multi-tone photomasks. Gray-tone masks have slits formed in them that are smaller than the resolution of the exposure machine, and intermediate exposure is achieved by blocking part of the light through these slits. On the other hand, half-tone masks use a semi-transparent film to achieve intermediate exposure.

[0074] As described above, the pixel contact hole CH P By adopting a configuration in which the pixel contact hole CH is filled with the second planarization layer 17, P However, according to the study by the inventors of the present invention, the pixel contact hole CH P However, it has been found that in a configuration in which the gap is filled with the second planarization layer 17, a new problem may arise, as will be explained below.

[0075] In the manufacturing process of an active matrix substrate for a display device, planarization techniques such as chemical mechanical polishing (CMP) are not generally used. Therefore, pixel contact holes CH are formed by a photolithography process. P Therefore, it is important to flatten the surface as accurately as possible.

[0076] However, in reality, it is necessary to provide a design margin to accommodate deviations due to alignment variations during photolithography and variations in the finished width. P 10A to 10C are diagrams for explaining a series of steps for filling the gap with a second planarization layer 17.

[0077] FIG. 8A shows the pixel contact hole CH P 8B, a photosensitive resin material 17' (here, a positive type) is applied to the first planarization layer 16 and the second connection electrode 15 in this state, as shown in FIG. 8B. Subsequently, exposure is performed using a multi-tone photomask 40. The multi-tone photomask 40 has a transmissive region 41 that transmits light, a light-shielding region 42 that substantially blocks light, and a semi-transmissive region 43 that transmits light with a transmittance lower than that of the transmissive region 41. When the multi-tone photomask 40 is a half-tone mask, the semi-transmissive region 43 is made of a semi-transmissive film. When the multi-tone photomask 40 is a gray-tone mask, the semi-transmissive region 43 has a slit formed therein that is equal to or smaller than the resolution of the exposure machine. Hereinafter, the light-shielding region 42 and the semi-transmissive region 43 may be collectively referred to as a "light-adjusting region." Alternatively, the semi-transmissive region 43 may be divided into multiple regions, and the transmittance of each of these regions may be adjusted as desired. In this case, the multi-tone photomask 40 does not need to include the light-shielding region 42 .

[0078] Thereafter, development and post-baking are performed to form the pixel contact holes CH P The pixel contact hole CH is filled with the second planarization layer 17. However, as already explained, a design margin is provided in the design, so the second planarization layer 17 is P Not only does it fill the gap, but it also has a width W that corresponds to the design margin. M Pixel contact hole CH P Therefore, the pixel contact hole CH PIn order to avoid the formation of the step st1, it is possible to increase the exposure amount, but in that case, as shown in FIG. 8D, the second planarization layer 17 is thinned more than necessary, and the pixel contact hole CH P A step st2 is formed within the second planarization layer 17. The shape of the second planarization layer 17 is not limited to the example shown in FIG. 8C. The shape of the second planarization layer 17 can be appropriately controlled by changing the arrangement of the light-shielding regions 42 and the semi-transmitting regions 43 in the multi-tone photomask 40. For example, if the light-shielding regions 42 and the semi-transmitting regions 43 in the multi-tone photomask 40 shown in FIG. 8B are swapped, a second planarization layer 17 with a slightly recessed center is obtained, as shown in FIG. 8E.

[0079] The inventors of the present invention have P As a result of extensive investigation into the structure of the pixel contact hole CH, a structure suitable for suppressing the formation of a step was found. P A preferred structure of the compound will be described.

[0080] Pixel contact hole CH P The ratio of the diameter dB of the top surface 17t of the second planarization layer 17 to the diameter dA of the bottom surface 16b of the second planarization layer 17 is preferably 3 or more and 5 or less. In other words, the diameter dB is preferably 3 or more and 5 or less times the diameter dA. The fact that the diameter dB is 3 or more and 5 or less times the diameter dA means that the pixel contact hole CH P This means that the side surface 16s has a relatively gentle tapered shape. As will be described later in detail, if the diameter dB is between three and five times the diameter dA, even if exposure variations occur during the formation of the second planarization layer 17, the variations are reflected mainly as lateral size variations of the second planarization layer 17, and therefore size variations in the height direction of the second planarization layer 17 can be suppressed.

[0081] In addition, the pixel contact hole CH PThe shape of the bottom surface 16b of the pixel contact hole CH and the top surface 17t of the second planarization layer 17 is not limited to a substantially circular shape, but may be various shapes such as a substantially elliptical shape, a substantially rectangular shape, or a substantially regular polygonal shape. P The size of the bottom surface 16b of the second planarization layer 17 and the top surface 17t of the second planarization layer 17 can be expressed as a circle equivalent diameter. P This can be generalized as "a structure in which the ratio of the circle-equivalent diameter d2 of the top surface 17t of the second planarizing layer 17 to the circle-equivalent diameter d1 of the bottom surface 16b is 3 or more and 5 or less."

[0082] In addition, the pixel contact hole CH P 10, in a cross section parallel to the normal direction of the substrate 1, an axis perpendicular to the normal direction of the substrate 1 is defined as an x-axis, an axis parallel to the normal direction of the substrate 1 is defined as a y-axis, and the pixel contact hole CH P When the lowest point p1 of the side surface 16s is located on the x-axis in the range of x>0, the pixel contact hole CH P The side surface 16s has a shape that is approximated by the following formula (1) (for example, approximated by curve fitting using regression analysis). y=A*ln(x)+B (1)

[0083] Here, the units of the x-axis and y-axis are μm. In Equation (1), A is a value within the range of 0.75±0.05 (i.e., 0.70≦A≦0.80). B is an arbitrary constant greater than 0 (i.e., B>0).

[0084] The upper surface of the first planarization layer 16 is covered with the pixel contact hole CH PWhen the region F (see FIG. 9) where no pixel contact hole CH is formed is referred to as a "flat region," the highest part of the upper surface of the second planarization layer 17 may be substantially the same height as the flat region F, or may be slightly higher or lower than the flat region F. However, it is preferable that the difference between the height h1 of the highest part of the upper surface of the second planarization layer 17 and the height h2 of the flat region F is 0.5 μm or less. As long as the height h1 and the height h2 satisfy this relationship, the pixel contact hole CH P The circle-equivalent diameter d3 of the upper surface of the second planarization layer 17 may be substantially the same as the circle-equivalent diameter d2 of the upper surface 17t of the second planarization layer 17, or may be larger or smaller than the circle-equivalent diameter d2 of the upper surface 17t of the second planarization layer 17.

[0085] 11A to 14C, an example of a method for manufacturing the active matrix substrate 100 of this embodiment will be described. 11A to 14C are cross-sectional views showing the manufacturing process of the active matrix substrate 100.

[0086] 11A, a lower gate electrode 2 and a lower gate wiring GLA (i.e., a lower gate metal layer) are formed on a substrate 1. For example, a conductive film is deposited by a sputtering method, and then the conductive film is patterned by a photolithography process, thereby forming the lower gate electrode 2 and the lower gate wiring GLA.

[0087] The substrate 1 can be, for example, a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (resin substrate). The conductive film (lower gate metal film) for forming the lower gate electrode 2 and the lower gate wiring GLA can be made of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or an alloy thereof, or a film containing a metal nitride thereof. A laminated film obtained by laminating a plurality of these films may also be used. Here, a film obtained by laminating a tantalum nitride (TaN) film and a W film in this order is used as the lower gate metal film. The thickness of the lower gate metal film is, for example, 100 nm or more and 500 nm or less.

[0088] Next, as shown in FIG. 11B, a lower gate insulating layer 3 is formed to cover the lower gate electrode 2 and the lower gate wiring GLA. For example, the lower gate insulating layer 3 can be formed by a CVD method. The lower gate insulating layer 3 can be formed from a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, a silicon nitride oxide (SiNxOy;x>y) layer, or the like, as appropriate. The lower gate insulating layer 3 may have a laminated structure. For example, a SiNx layer may be formed as a lower layer on the substrate 1 side to prevent the diffusion of impurities from the substrate 1, and a SiO2 layer may be formed as an upper layer thereon to ensure insulation. The thickness of the lower gate insulating layer 3 is, for example, 150 nm or more and 400 nm or less.

[0089] Subsequently, as shown in FIG. 11C , an oxide semiconductor layer 4 is formed on the lower gate insulating layer 3. For example, an oxide semiconductor film is deposited by sputtering, and then the oxide semiconductor film is patterned by a photolithography process to form an island-shaped oxide semiconductor layer 4. The oxide semiconductor layer 4 is formed so as to face the lower gate electrode 2 with the lower gate insulating layer 3 interposed therebetween. Here, an In-Ga-Zn-O-based semiconductor layer having a composition ratio of In:Ga:Zn=1:1:1 is formed as the oxide semiconductor layer 4. The thickness of the oxide semiconductor layer 4 is, for example, 10 nm or more and 200 nm or less.

[0090] Next, as shown in FIG. 11D, an upper gate insulating layer 5 is deposited to cover the oxide semiconductor layer 4. The upper gate insulating layer 5 is deposited by, for example, a CVD method. Then, the oxide semiconductor layer 4 is subjected to an oxidation treatment (for example, baking or peroxidation treatment). For example, an insulating layer similar to the lower gate insulating layer 3 (exemplified as the lower gate insulating layer 3) can be used as the upper gate insulating layer 5. Here, a silicon oxide (SiO2) layer is formed as the upper gate insulating layer 5. When an oxide layer such as a silicon oxide layer is used as the upper gate insulating layer 5, oxygen vacancies occurring in the channel region 4c of the oxide semiconductor layer 4 can be reduced by the oxide layer, thereby preventing the resistance of the channel region from decreasing. The thickness of the upper gate insulating layer 5 is, for example, 50 nm to 150 nm.

[0091] Next, as shown in FIG. 12A, an upper gate electrode 6 and an upper gate wiring GLB (i.e., an upper gate metal layer) are formed on the upper gate insulating layer 5. For example, a conductive film (upper gate metal film) is deposited by sputtering, and then the upper gate metal film is patterned by a photolithography process to form the upper gate electrode 6 and the upper gate wiring GLB. The upper gate insulating layer 5 is then patterned. The upper gate insulating layer 5 can also be patterned together with the upper gate metal film. The upper gate metal film can be, for example, a film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or an alloy thereof, or a metal nitride thereof. Here, a film formed by stacking a Ti film, an Al film, and a Ti film in this order is used as the upper gate metal film. The thickness of the upper gate metal film is, for example, 100 nm to 400 nm.

[0092] Thereafter, the oxide semiconductor layer 4 may be subjected to a resistance-reducing treatment using the upper gate insulating layer 5 and the upper gate electrode 6 as a mask. For example, plasma treatment can be used as the resistance-reducing treatment. As a result of the resistance-reducing treatment, the regions of the oxide semiconductor layer 4 that do not overlap with the upper gate insulating layer 5 and the upper gate electrode 6 (regions that will become the source contact region 4s and the drain contact region 4d) become low-resistance regions with lower resistivity than the regions of the oxide semiconductor layer 4 that overlap with the upper gate insulating layer 5 and the upper gate electrode 6 (regions that will become the channel region 4c). The low-resistance regions may be conductive regions (e.g., sheet resistance: 200 Ω / □ or less). The plasma treatment may be performed using the upper gate electrode 6 as a mask without patterning the upper gate insulating layer 5. In this case, the photolithography process for the upper gate insulating layer 5 can be omitted, thereby shortening the manufacturing process. The resistance-reducing treatment method is not limited to plasma treatment. For example, the exposed regions of the oxide semiconductor layer 4 can be reduced by contacting them with a reducing insulating film that can reduce the oxide semiconductor. Alternatively, the resistance can be reduced by an ion implantation process such as ion doping into the oxide semiconductor layer 4. In this case, the ion implantation process can be performed through the upper gate insulating layer 5, so that the process can be shortened.

[0093] Next, as shown in FIG. 12B, a first interlayer insulating layer 8 is formed to cover the oxide semiconductor layer 4 and the upper gate electrode 6. For example, the first interlayer insulating layer 8 can be formed by a CVD method. The first interlayer insulating layer 8 can be a single layer or a stack of inorganic insulating layers such as a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, or a silicon nitride oxide (SiNxOy;x>y) layer. The thickness of the first interlayer insulating layer 8 is, for example, 200 nm or more and 700 nm or less. Here, a silicon oxide layer is used as the first interlayer insulating layer 8.

[0094] Next, a source contact hole CH is formed in the first interlayer insulating layer 8 so as to expose a part of the source contact region 4s of the oxide semiconductor layer 4. SForm a source contact hole CH S can be formed by patterning the first interlayer insulating layer 8 by a photolithography process, for example.

[0095] Next, the source electrode 7 and the source wiring SL (i.e., the source metal layer) are formed on the first interlayer insulating layer 8. For example, the source electrode 7 and the source wiring SL can be formed by depositing a conductive film by sputtering and then patterning the conductive film by a photolithography process. As the conductive film (source metal film) for forming the source electrode 7 and the source wiring SL, a film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), chromium (Cr), or titanium (Ti), or an alloy thereof, or a metal nitride thereof can be appropriately used. A laminated film in which a plurality of these films are stacked may also be used. Here, a film in which a Ti film, an Al film, and a Ti film are stacked in this order is used as the source metal film. The thickness of the source metal film is, for example, 200 nm to 700 nm.

[0096] Next, as shown in FIG. 12C, a second interlayer insulating layer 9 is formed to cover the TFT 10. For example, the second interlayer insulating layer 9 can be formed by a CVD method. The second interlayer insulating layer 9 can be a single layer or a stack of inorganic insulating layers such as a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, or a silicon nitride oxide (SiNxOy;x>y) layer. The thickness of the second interlayer insulating layer 9 is, for example, 100 nm or more and 600 nm or less. Here, a silicon nitride layer is used as the second interlayer insulating layer 9.

[0097] Next, as shown in FIG. 13A, a drain contact hole CH is formed in the first interlayer insulating layer 8 and the second interlayer insulating layer 9 so as to expose a part of the drain contact region 4d of the oxide semiconductor layer 4. D Drain contact hole CH is formed. Dcan be formed by patterning the first interlayer insulating layer 8 and the second interlayer insulating layer 9 by a photolithography process, for example.

[0098] Next, as shown in FIG. 13B, the first connection electrode 14 is formed on the second interlayer insulating layer 9. For example, the first connection electrode 14 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the first connection electrode 14 include indium tin oxide (ITO) and indium zinc oxide (IZO). In this example, indium zinc oxide is used. The thickness of the first connection electrode 14 is, for example, 30 nm or more and 100 nm or less.

[0099] 13C, a first planarization layer 16 is formed to cover the second interlayer insulating layer 9 and the first connection electrode 14. For example, a photosensitive resin material is applied, and then exposure, development, and post-baking are sequentially performed to form a pixel contact hole CH so that a part of the first connection electrode 14 is exposed. P The first planarization layer 16 is obtained on which the photosensitive resin material is formed. For example, a photosensitive acrylic resin can be used as the photosensitive resin material. The thickness t of the first planarization layer 16 in the flat portion (the portion not overlapping with the lower gate electrode 2 and the upper gate electrode 6) is, for example, about 2.5 μm to 3.0 μm. When the thickness of the lower gate electrode 2 and the upper gate electrode 6 is each about 300 nm, the pixel contact hole CH P The depth d is, for example, about 2.2 μm.

[0100] Next, as shown in FIG. 14A, the first planarization layer 16 and the pixel contact hole CH PThe second connection electrode 15 is formed within the second connection electrode 15. For example, the second connection electrode 15 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. As the transparent conductive material for forming the second connection electrode 15, for example, indium tin oxide or indium zinc oxide can be used. The thickness of the second connection electrode 15 is, for example, 30 nm or more and 100 nm or less.

[0101] If misalignment occurs in the photolithography process when forming the second connection electrode 15, there is a risk of variations in the finished second connection electrode 15. If the second connection electrode 15 and the pixel electrode 18 are formed from the same transparent conductive material, even if a part of the second connection electrode 15 protrudes from the region where the pixel electrode 18 is formed, the protruding part is removed when the transparent conductive film for the pixel electrode 18 is patterned (etched). In other words, the second connection electrode 15 can be patterned in a self-aligned manner to the same size as the mask pattern of the pixel electrode 18.

[0102] As already explained, indium tin oxide or indium zinc oxide can be used as the material for the second connection electrode 15. However, indium tin oxide crystallizes due to the thermal history during the process and becomes difficult to dissolve. In contrast, indium zinc oxide tends to maintain an amorphous state even when subjected to thermal history, and can be easily dissolved with a PAN-based etchant. Therefore, it is preferable to use indium zinc oxide as the material for the second connection electrode 15 (hereinafter referred to as the "first measure").

[0103] When indium tin oxide is used as the material for the second connection electrode 15, it is preferable to make the size of the second connection electrode 15 smaller than the size of the pixel electrode 18 by at least the value of the process margin (hereinafter referred to as the "second measure"). This makes it possible to prevent a part of the second connection electrode 15 from protruding from the region where the pixel electrode 18 is formed, even if misalignment occurs between the second connection electrode 15 and the pixel electrode 18.

[0104] Since the sum of the areas of the second connection electrode 15 and the pixel electrode 18 functions as an effective pixel electrode (simply referred to as pixel electrode here), both the first and second measures can prevent the pixel electrode area from becoming larger than necessary. That is, not only can the parasitic capacitance between the source electrode 7 and the pixel electrode be reduced, but also variations in parasitic capacitance caused by variations in the positions of the second connection electrode 15 and the source electrode 7 can be avoided (this is because the pixel electrode 18 is larger than or equal to the second connection electrode 15. When misalignment occurs, the second connection electrode 15 protrudes from the pixel electrode 18 and moves closer to the source electrode 7, preventing an increase in parasitic capacitance).

[0105] Next, as shown in FIG. 14B, the pixel contact hole CH P A second planarization layer 17 is formed to fill the pixel contact holes CH. For example, a photosensitive resin material is applied, and then exposure, development, and post-baking are performed in sequence to obtain the second planarization layer 17. For example, a photosensitive acrylic resin can be used as the photosensitive resin material. As already explained, by using a multi-tone photomask as a photomask during exposure, the pixel contact holes CH are formed by the second planarization layer 17. P The inside can be filled with precision Next, as shown in FIG. 14C, a pixel electrode 18 is formed on the first planarization layer 16, the second planarization layer 17, and the second connection electrode 15. For example, the pixel electrode 18 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the pixel electrode 18 include indium tin oxide and indium zinc oxide. In this example, indium zinc oxide is used. The thickness of the pixel electrode 18 is, for example, 30 nm or more and 100 nm or less.

[0106] Next, a dielectric layer is formed to cover the pixel electrodes. For example, the dielectric layer can be formed by a CVD method. For example, an inorganic insulating layer similar to the first interlayer insulating layer 8 and the second interlayer insulating layer 9 can be used as the dielectric layer. Here, a silicon nitride layer is used as the dielectric layer. The thickness of the dielectric layer is, for example, 50 nm or more and 300 nm or less.

[0107] A common electrode is then formed on the dielectric layer. For example, the common electrode can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the common electrode include indium tin oxide and indium zinc oxide. In this example, indium zinc oxide is used. The thickness of the common electrode is, for example, 30 nm or more and 100 nm or less. In this manner, the active matrix substrate 100 is obtained.

[0108] If the pixel pitch is large enough to provide a sufficient gap between the source electrode 7 and the first connection electrode 14, the first connection electrode 14 may be provided in the same layer as the source electrode 7 (i.e., on the first interlayer insulating layer 8). In this case, the second interlayer insulating layer 9 can be omitted, simplifying the manufacturing process.

[0109] As already explained, in the active matrix substrate 100 of this embodiment, the pixel contact holes CH P The side surface 16s of the pixel contact hole CH has a relatively gentle tapered shape. P The shape of the side surface 16s of the pixel contact hole CH can be controlled by adjusting, for example, the temperature and time of post-baking (hereinafter, these are collectively referred to as "thermal history"). Specifically, the smaller the thermal history, the steeper the tapered shape can be, and the longer the thermal history, the gentler the tapered shape can be. Therefore, by sufficiently increasing the thermal history of post-baking, it is possible to obtain a pixel contact hole CH having a side surface 16s with a relatively gentle tapered shape. PFurthermore, by increasing the heat history sufficiently, it is possible to prevent the shape of the side surface 16s from changing after that.

[0110] When the exemplified photosensitive acrylic resin is used as the material for the first planarization layer 16, from the viewpoint of making the tapered shape of the side surface 16s sufficiently gentle, it is preferable that the post-baking be performed, for example, at 200° C. or higher for 30 minutes or longer. Furthermore, by increasing the thermal history sufficiently, the moisture contained in the photosensitive resin material is also removed, which suppresses film lifting when a film is formed on the first planarization layer 16 in the subsequent process, thereby improving adhesion.

[0111] The thermal history required to make the tapered shape sufficiently gentle varies depending on the photosensitive resin material used as the material of the first planarization layer 16. P In order to make the tapered shape of the side surface 16s gentler, it is also preferable to use a photosensitive resin material that is relatively susceptible to shape changes due to post-baking as the material for the first planarization layer 16. When using a material that is relatively susceptible to shape changes due to post-baking, the thermal history may be outside the above-mentioned preferred range (200°C or higher for 30 minutes or longer).

[0112] In the past, in active matrix substrates for high-definition liquid crystal display devices, if the side surface of the pixel contact hole had a gentle taper, the effective opening diameter would be large, so it was preferred to form the pixel contact hole so that the side surface had a steep taper. P By intentionally making the tapered shape of the side surface 16s gentle, the above-mentioned effect can be obtained.

[0113] The shape of the upper surface 17t of the second planarization layer 17 can also be controlled by adjusting the thermal history (temperature and time) of post-baking when forming the second planarization layer 17. Specifically, the upper surface 17t of the second planarization layer 17 can be made flatter as the thermal history increases.

[0114] 15 shows an example of the cross-sectional shape of the second planarization layer 17 when the thermal history of the post-baking when forming the second planarization layer 17 is sufficiently long. The upper, middle, and lower rows of FIG. 15 show the cases of underexposure, proper exposure, and overexposure, respectively. As can be seen from FIG. 15, by sufficiently longing the thermal history, the second planarization layer 17 becomes thicker than the pixel contact hole CH. P Since the shape of the second planarization layer 17 changes to match the tapered shape of the side surface 16s of the pixel contact hole CH, the upper surface 17t of the second planarization layer 17 becomes flatter, and even if the exposure amount varies, the step ( P The step st1 and the pixel contact hole CH P Therefore, the step st2) formed in the groove can be reduced.

[0115] It is also preferable to use, as the material for the second planarization layer 17, a photosensitive resin material that is relatively susceptible to deformation due to post-baking.

[0116] 16A, 16B, and 16C show the pixel contact holes CH of an active matrix substrate 100 of this embodiment that was actually fabricated as a prototype (hereinafter referred to as an "example"), P 16A is a scatter diagram (graph) plotting the tapered shape of the side surface 16s of the multi-tone photomask. Fig. 16A shows a case where there is no misalignment of the multi-tone photomask. Fig. 16B shows a case where the alignment of the multi-tone photomask is misaligned in the negative direction (left side in the figure), and Fig. 16C shows a case where the alignment of the multi-tone photomask is misaligned in the positive direction (right side in the figure).

[0117] 17A, 17B, and 17C show that the side surface 16s has a steep tapered shape (the circle-equivalent diameter d2 of the upper surface 17t of the second planarization layer 17 is larger than the pixel contact hole CHP The pixel contact hole CH is formed so that the diameter thereof is less than three times the circle equivalent diameter d1 of the bottom surface 16s of the pixel contact hole CH. P 17A and 17B are scatter plots (graphs) plotting the side profile of a multi-tone photomask (hereinafter referred to as Reference Example 1). Fig. 17A shows a case where there is no misalignment of the multi-tone photomask. Fig. 17B shows a case where the alignment of the multi-tone photomask is misaligned in the negative direction (left side in the figure), and Fig. 17C shows a case where the alignment of the multi-tone photomask is misaligned in the positive direction (right side in the figure).

[0118] By forming the second planarization layer 17 using a multi-tone photomask, if there is no misalignment of the multi-tone photomask, the pixel contact hole CH P Therefore, it is possible to prevent the second planarization layer 17 from being reduced more than necessary.

[0119] On the other hand, when the alignment of the multi-tone photomask is shifted in the negative direction, in Reference Example 1, as shown in FIG. 17B, the pixel contact hole CH P There is a large step inside (pixel contact hole CH P In contrast to this, in the embodiment, as shown in FIG. 16B, the pixel contact hole CH P The step formed inside is small.

[0120] When the alignment of the multi-tone photomask is shifted in the positive direction, as shown in FIGS. 16C and 17C, in both the example and the reference example 1, the second planarization layer 17 is in contact with the pixel contact hole CH. P However, on the opposite side to the illustrated side, the same phenomenon occurs as when the alignment is shifted in the negative direction. P In the embodiment, a large step is formed in the pixel contact hole CH P The step formed inside is small.

[0121] As can be seen from the explanation given with reference to Figures 16A to 17C, the change in height (depth) (change in y direction) corresponding to the misalignment of the multi-tone photomask (change in x direction) occurs at the edge of the light adjusting region of the multi-tone photomask, which can result in a step. At such a position, the height change due to misalignment, i.e., the differential change, is significantly different between a tapered shape approximated by a logarithmic curve as shown in Figures 16A to 16C and a tapered shape approximated by a straight line with a much larger slope as shown in Figures 17A to 17C. This results in the above-mentioned difference between the working example and Reference Example 1.

[0122] Although an example of misalignment of a multi-tone photomask has been shown here, the pixel contact hole CH due to exposure variations may also be used. P The same effect can be obtained with respect to the influence of changes in the opening diameter of the second planarization layer 17 and changes in the diameter of the second planarization layer 17. Therefore, by employing a structure such as that of the active matrix substrate 100 of this embodiment, it is possible to reduce variations in the finished shape of the second planarization layer 17 that may occur due to process variations when forming the second planarization layer 17.

[0123] In addition, the pixel contact hole CH having a steeply tapered side surface 16s P In the pixel contact hole CH P To prevent steps from occurring inside the building, the following measures can be considered:

[0124] (A) By setting the width of the light adjusting region of the multi-tone photomask to be larger than the finished width that may occur due to process variations when forming the first planarization layer 16 and the second planarization layer 17, the second planarization layer 17 does not overlap the pixel contact hole CH in any case. P Make sure that the sides 16s are not completely covered.

[0125] (B) By making the upper surface 17t of the second planarization layer 17 sufficiently higher than the flat region F of the first planarization layer 16, the pixel contact hole CH PEven if a step occurs in the second planarization layer 17, the second planarization layer 17 is deformed during post-baking so that the step is filled in.

[0126] (C) Use measures (A) and (B) together.

[0127] If measure (A) can be easily realized, it would be acceptable. However, the inventors of the present application have actually conducted an investigation and found that measure (A) alone makes it difficult to stably form the second planarization layer 17 such that the upper surface 17t is at the same height as the flat region F due to the influence of process variations, and measure (C) is therefore necessary. In other words, when the pixel contact hole CH has a steeply tapered side surface 16s, P In the pixel contact hole CH P When attempting to suppress the formation of inward steps, the height of the upper surface 17t of the second planarization layer 17 tends to increase (that is, the protruding height of the second planarization layer 17 from the first planarization layer 16 tends to increase).

[0128] 18A, 18B, and 18C show pixel contact holes CH P 18A is a scatter diagram (graph) plotting the side profile of a sample to which countermeasure (C) was applied (hereinafter referred to as Reference Example 2) was applied. Fig. 18A shows a case in which there is no misalignment of the multi-tone photomask. Fig. 18B shows a case in which the alignment of the multi-tone photomask is misaligned in the negative direction (left side in the figure), and Fig. 18C shows a case in which the alignment of the multi-tone photomask is misaligned in the positive direction (right side in the figure).

[0129] In Reference Example 2, as shown in FIGS. 18A, 18B, and 18C, in all cases where there is no misalignment, where there is a misalignment in the negative direction, and where there is a misalignment in the positive direction, the pixel contact hole CH P Although no step is formed inside the second planarization layer 17, the protruding height of the second planarization layer 17 from the first planarization layer 16 becomes large.

[0130] FIG. 19 shows the pixel contact hole CH of Reference Example 2.P As can be seen from FIG. 19, the pixel contact hole CH P The tapered shape of the side surface 16s is extremely steep. Due to misalignment during the formation of the second planarization layer 17, the second planarization layer 17 is shifted slightly to the left in the figure, resulting in the left convexity of the two convexities of the second planarization layer 17 being higher than the right convexity. In this configuration, it can be seen that the thickness of the alignment film 31 differs between around the step and in the flat region F. Specifically, it can be seen that the alignment film 31 is relatively thin on the convexities and on the flat region F of the second planarization layer 17, whereas near the base ends of the convexities of the second planarization layer 17, the alignment film 31 is relatively thick due to accumulation of alignment film material. Thus, if the thickness of the alignment film 31 is uneven, the alignment state of the liquid crystal layer changes, which can have adverse effects on optical characteristics, such as image retention and unevenness.

[0131] Although a cross-sectional observation image is not shown here, as shown in FIG. 8D, when the second planarization layer 17 is reduced more than necessary (that is, when the upper surface 17t of the second planarization layer 17 is lower than the flat region F), the pixel contact hole CH P A large amount of alignment film material flows into the alignment film 31, and the difference in thickness of the alignment film 31 becomes even larger.

[0132] FIG. 20 shows the pixel contact hole CH P As can be seen from FIG. 20, the pixel contact hole CH P The tapered shape of the side surface 16s of the second planarization layer 17 is gentle. Also, it can be seen that the shape of the upper surface 17t of the second planarization layer 17 is almost the same on the left and right, and there is almost no difference in height between the left and right. This is because the pixel contact hole CH P This is because the second planarization layer 17 is formed to follow the tapered shape of the side surface 16s, and it is believed that there is a positive correlation between the magnitude of the inclination of the tapered shape and the magnitude of the change in size in the height direction of the second planarization layer 17 due to misalignment. Also, in the example, since the step is small, it can be seen that the thickness of the alignment film 31 is relatively uniform.

[0133] When forming the second planarization layer 17, the photosensitive resin material may be left in islands or strips on the first planarization layer 16 to form structures (hereinafter referred to as "spacer receiving portions") rp for receiving columnar spacers (also called "photospacers" or "PS") 50, as shown in FIG. 21 . The columnar spacers 50 are provided on the liquid crystal layer 30 side of the counter substrate 500 (described later). The spacer receiving portions rp are disposed in regions corresponding to the columnar spacers 50. Although not shown here, a dielectric layer and a common electrode may be formed on the spacer receiving portions rp. Furthermore, by changing the settings for the intermediate exposure described above during mask design, it is possible to mix spacer receiving portions rp of different heights, which enables optimization of the cell thickness and improvement of strength and display quality during compression tests.

[0134] [Embodiment 2] An active matrix substrate 200 according to this embodiment will be described with reference to Fig. 22 and Fig. 23. Fig. 22 is a plan view schematically showing the active matrix substrate 200. Fig. 23 is a cross-sectional view schematically showing the active matrix substrate 200, taken along line 23A-23A' in Fig. 22. The following description will focus on differences between the active matrix substrate 200 and the active matrix substrate 100 according to the first embodiment.

[0135] 22 and 23, in the active matrix substrate 200 of this embodiment, island electrodes 21 are provided in the same layer as the source electrodes 7 (by patterning the same conductive film) and separated from the source electrodes 7. That is, the source metal layer includes the island electrodes 21 in addition to the source electrodes 7 and source lines SL.

[0136] When viewed from the normal direction of the substrate 1, the pixel contact hole CH P The bottom surface 16b of the pixel contact hole CH at least partially overlaps both the lower gate metal layer and the upper gate metal layer (more specifically, both the lower gate electrode 2 and the upper gate electrode 6).P The bottom surface 16b of the pixel contact hole CH also at least partially overlaps the source metal layer. P The bottom surface 16b of the pixel contact hole CH at least partially overlaps the island-shaped electrode 21. P The entire bottom surface 16b of the electrode 16 overlaps the island-shaped electrode 21.

[0137] As described above, in the active matrix substrate 200 of this embodiment, the pixel contact holes CH formed in the planarization layer 16 P The bottom surface 16b of the pixel contact hole CH at least partially overlaps not only the lower gate electrode 2 and the upper gate electrode 6 but also the island-shaped electrode 21. P The opening diameter can be further reduced.

[0138] [Embodiment 3] An active matrix substrate 300 according to this embodiment will be described with reference to Figures 24, 25, and 26. Figure 24 is a plan view schematically showing the active matrix substrate 300. Figures 25 and 26 are cross-sectional views schematically showing the active matrix substrate 300, taken along lines 25A-25A' and 26A-26A' in Figure 24, respectively. The following description will focus on differences between the active matrix substrate 300 and the active matrix substrate 100 according to the first embodiment.

[0139] In the active matrix substrate 300 of this embodiment, when viewed from the normal direction of the substrate 1, the pixel contact holes CH P The bottom surface 16b of the pixel contact hole CH at least partially overlaps both the lower gate line GLA and the upper gate line GLB. P The entire bottom surface 16b of the gate electrode 16a overlaps both the lower gate wiring GLA and the upper gate wiring GLB.

[0140] In this way, the pixel contact hole CH PThe bottom surface 16b of the pixel contact hole CH at least partially overlaps both the lower gate line GLA and the upper gate line GLB. P The aperture diameter can be reduced, and the transmittance can be improved.

[0141] In addition, the pixel contact hole CH P When viewed from the normal direction of the substrate 1, the bottom surface 16b of the pixel contact hole CH is at least partially overlapped with at least the lower gate line GLA out of the lower gate line GLA and the upper gate line GLB. P However, from the viewpoint of further improving the transmittance, it is necessary to reduce the opening diameter of the pixel contact hole CH P The bottom surface 16b of the pixel contact hole CH preferably at least partially overlaps both the lower gate line GLA and the upper gate line GLB. P It is more preferable that the entire bottom surface 16b of the gate electrode 16 overlaps both the lower gate wiring GLA and the upper gate wiring GLB.

[0142] In the active matrix substrate 300 of this embodiment, when viewed from the normal direction of the substrate 1, the pixel contact holes CH P The bottom surface 16b of the pixel contact hole CH also overlaps at least partially (in the illustrated example, entirely) with the source line SL. P The opening diameter can be further reduced.

[0143] [Embodiment 5] An active matrix substrate 400 according to this embodiment will be described with reference to Fig. 27. Fig. 27 is a cross-sectional view schematically showing the active matrix substrate 400. A part of the display region DR is shown on the right side of Fig. 27, and a part of the non-display region FR is shown on the left side of Fig. 27. The following description will focus on the differences between the active matrix substrate 400 and the active matrix substrate 100 according to the first embodiment.

[0144] 27, the active matrix substrate 400 includes a first TFT 10 and a second TFT 60 supported on a substrate 1. The first TFT 10 is a pixel TFT arranged in each pixel region P of the display region DR, and is an oxide semiconductor TFT including an oxide semiconductor layer 4 as an active layer. The structure of the display region DR of the active matrix substrate 100 is substantially the same as the structure of the display region DR of the active matrix substrate 100 of Embodiment 1 (or the structure of the display region DR of the active matrix substrates 200 and 300 of Embodiments 2 and 3).

[0145] The second TFT 60 is provided in the non-display area. The second TFT 60 is a crystalline silicon TFT including a crystalline silicon semiconductor layer 61 as an active layer. The second TFT 60 is a circuit TFT that constitutes a peripheral circuit, such as a GDM (Gate Driver Monolithic) circuit or an SSD (Source Shared Driving) circuit. In addition to the crystalline silicon semiconductor layer 61, the second TFT 60 has a gate electrode 62, a source electrode 63, and a drain electrode 64.

[0146] In this embodiment, the crystalline silicon semiconductor layer 61 is a polycrystalline silicon layer (for example, a low-temperature polysilicon (LTPS) layer). In the example shown in the figure, a base coat layer (underlayer) 12 is provided on the substrate 1, and the crystalline silicon semiconductor layer 61 is provided on the base coat layer 12.

[0147] The gate electrode 62 is provided on the insulating layer 13 that covers the crystalline silicon semiconductor layer 61, and faces the crystalline silicon semiconductor layer 61 via the insulating layer 13. The gate electrode 62 is formed in the same layer as the lower gate electrode 2 of the first TFT 10 (that is, by patterning the same conductive film). The insulating layer 13 is made of the same inorganic insulating material as the lower gate insulating layer 3, etc.

[0148] The source electrode 63 and the drain electrode 64 are formed in the same layer as the source electrode 7 of the first TFT 10 (that is, by patterning the same conductive film). Therefore, the source electrode 63 and the drain electrode 64 are provided on the first interlayer insulating layer 8. The source electrode 63 and the drain electrode 64 are connected to the first interlayer insulating layer 8, the lower gate insulating layer 3, and the insulating layer 13 through a source contact hole CH S ' and drain contact hole CH D ', which is connected to the crystalline silicon semiconductor layer 61.

[0149] As described above, the second TFT 60 has a top-gate structure. The channel region (the region facing the gate electrode 62) of the crystalline silicon semiconductor layer 61 of the second TFT 60 is shielded from light by the light-shielding layer 11 formed under the base coat layer 12.

[0150] As in the present embodiment, it is possible to improve driving capability while reducing power consumption by using an oxide semiconductor TFT with excellent off-leakage characteristics as the pixel TFT 10 and a crystalline silicon TFT with excellent mobility as the circuit TFT 60. As illustrated, the gate electrode 62 of the circuit TFT 60 is formed in the same layer as the lower gate electrode 2 of the pixel TFT 10, thereby preventing an increase in the number of manufacturing steps.

[0151] [About oxide semiconductors] The oxide semiconductor contained in the oxide semiconductor layer 4 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axes are oriented approximately perpendicular to the layer surface.

[0152] The oxide semiconductor layer 4 may have a stacked structure of two or more layers. The oxide semiconductor layer 4 having a stacked structure may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer, or may include multiple crystalline oxide semiconductor layers with different crystal structures. Furthermore, the oxide semiconductor layer 4 having a stacked structure may include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer 4 has a stacked structure, the energy gaps of the layers may be different from each other.

[0153] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a stacked structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described, for example, in JP 2014-007399 A. The entire disclosure of JP 2014-007399 A is incorporated herein by reference.

[0154] The oxide semiconductor layer 4 may contain at least one metal element selected from the group consisting of In, Ga, and Zn. In the above-described embodiment, the oxide semiconductor layer 4 contains, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer 4 may be formed from an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

[0155] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline, and a crystalline In-Ga-Zn-O based semiconductor with its c-axis oriented generally perpendicular to the layer plane is preferred as the crystalline In-Ga-Zn-O based semiconductor.

[0156] The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed, for example, in the aforementioned Japanese Patent Application Laid-Open Nos. 2014-007399, 2012-134475, and 2014-209727. The disclosures of Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-209727 are incorporated herein by reference in their entirety. TFTs having an In-Ga-Zn-O-based semiconductor layer have high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one-hundredth that of an a-Si TFT). Therefore, they are suitable for use as driver TFTs (e.g., TFTs included in a driver circuit provided on the same substrate as a display area, around a display area including multiple pixels) and pixel TFTs (TFTs provided in pixels).

[0157] The oxide semiconductor layer 4 may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, it may contain an In-Sn-Zn-O-based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer 11 may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, or the like.

[0158] (Liquid crystal display device) The active matrix substrates 100, 200, 300 and 400 according to the embodiments of the present invention can be suitably used in a liquid crystal display device. An example of a liquid crystal display device is shown in FIG.

[0159] The liquid crystal display device 1000 shown in Figure 28 includes an active matrix substrate 100 (or active matrix substrates 200, 300, 400), a counter substrate 600 arranged opposite to the active matrix substrate 100, and a liquid crystal layer 30 arranged between the active matrix substrate 100 and the counter substrate 600.

[0160] The active matrix substrate 100 includes a TFT 10 (not shown) disposed in each pixel region P, a pixel electrode 18 electrically connected to the TFT 10, a dielectric layer 19 provided to cover the pixel electrode 18, and a common electrode 20 provided on the dielectric layer 19 and facing the pixel electrode 18. At least one slit 20a is formed in the common electrode 20 for each pixel region P.

[0161] Alignment films 31 and 32 are provided on the outermost surfaces of the active matrix substrate 100 and the counter substrate 600 facing the liquid crystal layer 30. The counter substrate 600 typically has a color filter layer and a black matrix (neither of which are shown).

[0162] The thickness (cell gap) of the liquid crystal layer 30 is determined by columnar spacers 50 (not shown in FIG. 20) provided on the liquid crystal layer 30 side of the counter substrate 600. Spacer receiving portions rp as shown in FIG. 21 may be provided on the active matrix substrate side.

[0163] Although the liquid crystal display device 1000 shown here is an FFS mode liquid crystal display device, which is a type of lateral electric field mode, the active matrix substrate according to the embodiment of the present invention may be used in liquid crystal display devices of other display modes. In a liquid crystal display device of a vertical electric field mode, such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, the common electrode is provided on the opposing substrate side. [Industrial Applicability]

[0164] According to an embodiment of the present invention, it is possible to provide an active matrix substrate in which a decrease in transmittance caused by contact holes formed in a planarizing layer is suppressed. The active matrix substrate according to an embodiment of the present invention is suitable for use in high-resolution (e.g., 1000 ppi or higher) liquid crystal display devices such as liquid crystal display devices for head-mounted displays. [Explanation of symbols]

[0165] 1 board 2. Bottom gate electrode 3 Lower gate insulating layer 4. Oxide semiconductor layer 4c Channel region 4s Source Contact Area 4d Drain contact area 5. Top gate insulating layer 6 Upper gate electrode 7. Source electrode 8 First interlayer insulating layer 9 Second interlayer insulating layer 10 TFT(1st TFT) 11 Light blocking layer 12 Base coat layer 13 Insulating layer 14 First connection electrode 15 Second connection electrode 16 First planarization layer 17 Second planarization layer 18 pixel electrode 19 Dielectric Layer 20 common electrode 21 Island electrode 30 Liquid crystal layer 31, 32 Alignment film 50 Pillar spacer 60 2nd TFT 61 Crystalline silicon semiconductor layer 62 gate electrode 63 Source electrode 64 Drain electrode 100, 200, 300, 400 Active matrix substrate 600 Opposing substrate 1000 lcd display device DR display area FR hidden area P pixel area GL gate wiring GLA lower gate wiring GLB upper gate wiring SL Source wiring GD Gate driver SD Source Driver CH P Pixel Contact Hole CHS, CHS' source contact holes CHD, CHD' drain contact holes rp Spacer receiving part

Claims

1. a display area defined by a plurality of pixel areas; A substrate; a first TFT supported by the substrate and disposed in each of the plurality of pixel regions; a first planarization layer covering the first TFT; a pixel electrode provided on the first planarization layer and electrically connected to the first TFT; Equipped with The first TFT is a lower gate electrode provided on the substrate; a lower gate insulating layer covering the lower gate electrode; an oxide semiconductor layer provided on the lower gate insulating layer, the oxide semiconductor layer including a channel region facing the lower gate electrode via the lower gate insulating layer, and a source contact region and a drain contact region located on both sides of the channel region; an upper gate insulating layer provided on the channel region of the oxide semiconductor layer; an upper gate electrode provided on the upper gate insulating layer and facing the channel region of the oxide semiconductor layer via the upper gate insulating layer, a first connection electrode located under the first planarization layer for electrically connecting the drain contact region of the oxide semiconductor layer and the pixel electrode; the first planarization layer has a pixel contact hole formed so as to expose a portion of the first connection electrode; when viewed from a normal direction of the substrate, a bottom surface of the pixel contact hole at least partially overlaps with at least the lower gate metal layer of a lower gate metal layer including the lower gate electrode and an upper gate metal layer including the upper gate electrode; the first connection electrode is made of a transparent conductive material, The active matrix substrate comprises: a second connection electrode formed of a transparent conductive material and electrically connecting the first connection electrode and the pixel electrode, the second connection electrode being in contact with the first connection electrode in the pixel contact hole; a second planarization layer formed to fill the pixel contact hole and cover a part of the second connection electrode; Furthermore, an active matrix substrate, wherein a ratio of a circle-equivalent diameter d2 of the upper surface of the second planarization layer to a circle-equivalent diameter d1 of the bottom surface of the pixel contact hole is 3 or more and 5 or less.

2. In a cross section parallel to the normal direction of the substrate, an axis perpendicular to the normal direction of the substrate is defined as an x-axis, an axis parallel to the normal direction of the substrate is defined as a y-axis, and the lowest point of the side surface of the pixel contact hole is located on the x-axis in a range of x>0, the side surface of the pixel contact hole has a shape approximated by the following formula (1): y=A*ln(x)+B (1) 2. The active matrix substrate according to claim 1, wherein the units of the x-axis and y-axis are each μm, 0.70≦A≦0.80, and B>0.

3. When a region of the upper surface of the first planarization layer in which the pixel contact hole is not formed is called a flat region, 3. The active matrix substrate according to claim 1, wherein the difference in height between the highest part of the upper surface of said second planarization layer and the flat region is 0.5 [mu]m or less.

4. the pixel electrode is in contact with a portion of the second connection electrode that is not covered with the second planarization layer, The active matrix substrate according to claim 1 , wherein the pixel electrode includes a portion located on the second planarization layer.

5. 3. The active matrix substrate according to claim 1, wherein, when viewed from a normal direction of the substrate, a bottom surface of the pixel contact hole at least partially overlaps with at least the lower gate electrode of the lower gate electrode and the upper gate electrode.

6. the lower gate metal layer includes a lower gate wiring electrically connected to the lower gate electrode, the upper gate metal layer includes an upper gate wiring electrically connected to the upper gate electrode, 3. The active matrix substrate according to claim 1, wherein, when viewed from a normal direction of the substrate, a bottom surface of the pixel contact hole at least partially overlaps at least the lower gate wiring out of the lower gate wiring and the upper gate wiring.

7. 3. The active matrix substrate according to claim 1, wherein, when viewed from a normal direction of the substrate, the bottom surface of the pixel contact hole at least partially overlaps both the lower gate metal layer and the upper gate metal layer.

8. 8. The active matrix substrate according to claim 7, wherein, when viewed from a normal direction of the substrate, the bottom surface of the pixel contact hole at least partially overlaps both the lower gate electrode and the upper gate electrode.

9. the lower gate metal layer includes a lower gate wiring electrically connected to the lower gate electrode, the upper gate metal layer includes an upper gate wiring electrically connected to the upper gate electrode, 8. The active matrix substrate according to claim 7, wherein, when viewed from a normal direction of the substrate, the bottom surface of the pixel contact hole at least partially overlaps both the lower gate wiring and the upper gate wiring.

10. 3. The active matrix substrate according to claim 1, wherein the entire bottom surface of the pixel contact hole overlaps both the lower gate metal layer and the upper gate metal layer when viewed from the normal direction of the substrate.

11. 11. The active matrix substrate according to claim 10, wherein the entire bottom surface of the pixel contact hole overlaps both the lower gate electrode and the upper gate electrode when viewed from the normal direction of the substrate.

12. the lower gate metal layer includes a lower gate wiring electrically connected to the lower gate electrode, the upper gate metal layer includes an upper gate wiring electrically connected to the upper gate electrode, 11. The active matrix substrate according to claim 10, wherein the entire bottom surface of the pixel contact hole overlaps both the lower gate wiring and the upper gate wiring when viewed from the normal direction of the substrate.

13. the first TFT has a source electrode electrically connected to the source contact region; 3. The active matrix substrate according to claim 1, wherein the bottom surface of the pixel contact hole at least partially overlaps a source metal layer including the source electrode when viewed from a normal direction of the substrate.

14. the source metal layer includes an island electrode provided separately from the source electrode, 14. The active matrix substrate according to claim 13, wherein a bottom surface of the pixel contact hole at least partially overlaps the island electrode when viewed from a normal direction of the substrate.

15. the source metal layer includes a source wiring electrically connected to the source electrode, 14. The active matrix substrate according to claim 13, wherein a bottom surface of the pixel contact hole at least partially overlaps the source line when viewed from a normal direction of the substrate.

16. The active matrix substrate according to claim 1 , wherein a portion of the first connection electrode is in contact with the drain contact region of the oxide semiconductor layer.

17. 3. The active matrix substrate according to claim 1, wherein the second connection electrode and the pixel electrode are made of the same transparent conductive material.

18. 18. The active matrix substrate according to claim 17, wherein the second connection electrode and the pixel electrode are made of indium zinc oxide.

19. a non-display area located around the display area, 3. The active matrix substrate according to claim 1, further comprising a second TFT provided in the non-display area and supported by the substrate, the second TFT including a crystalline silicon semiconductor layer.

20. the second TFT includes a gate electrode provided on an insulating layer covering the crystalline silicon semiconductor layer, the gate electrode facing the crystalline silicon semiconductor layer via the insulating layer; 20. The active matrix substrate according to claim 19, wherein the gate electrode of the second TFT is formed in the same layer as the lower gate electrode of the first TFT.

21. 3. The active matrix substrate according to claim 1, wherein the oxide semiconductor layer includes an In--Ga--Zn--O based semiconductor.

22. The active matrix substrate according to claim 1 or 2; an opposing substrate provided opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A liquid crystal display device comprising:

Images