Information processing device and information processing method

Abstract

To obtain an information processing device with which FA measures can be strengthened by a simple technique.SOLUTION: The information processing device comprises an arithmetic circuit having a first arithmetic circuit and a second arithmetic circuit, a control circuit, a counter circuit, and a comparison circuit. The control circuit sequentially processes each bit of inputted confidential information consisting of a plurality of bits, as the bit to be processed, causing the arithmetic circuit to execute a first arithmetic operation by the first arithmetic circuit and a second arithmetic operation by the second arithmetic circuit when the logic of the bit to be processed is 1, or causing the arithmetic circuit to execute only the second arithmetic operation among the first and second arithmetic operations when the logic of the bit to be processed is 0. The counter circuit outputs a counter value based on the number of the bits to be processed on which only the second arithmetic operation among the first and second arithmetic operations was performed by the arithmetic circuit, and the comparison circuit compares the counter value with the expected value of the counter value based on the confidential information.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing device and an information processing method. [Background technology]

[0002] With the recent development of IoT technology, various information processing devices are now connected to networks, which increases the threat of secret information being stolen from the devices through physical attacks. One type of physical attack is a fault attack (hereinafter referred to as "FA"). FA is an attack that intentionally induces a calculation error by applying a physical stimulus to an information processing device that is processing secret information, and then analyzes the behavior to steal the secret information.

[0003] Patent Document 1 discloses an IC card with FA countermeasures according to the background art. In a signature creation process using RSA, one of the public key cryptosystems, a coprocessor installed in the IC card simultaneously calculates and stores an error detection code for the data generated in the calculation process. When creating a digital signature, the coprocessor recalculates the error detection code for the data and compares it with the stored error detection code. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 11-8616 Summary of the Invention [Problem to be solved by the invention]

[0005] A Safe Error Attack is known as a type of FA. A Safe Error Attack steals secret information by analyzing whether or not the final output changes when an error is injected into each bit of the secret information. The background art disclosed in Patent Document 1 cannot prevent the theft of secret information through a Safe Error Attack, and is therefore insufficient as a countermeasure against FA.

[0006] Exponent blinding, one of the countermeasures against FA, conceals confidential information using random numbers. However, this method requires the generation of random numbers and the encryption of confidential information using the random numbers, which makes the process complicated.

[0007] The present invention has been made in view of the above circumstances, and has an object to provide an information processing device and an information processing method that are capable of strengthening FA countermeasures using a simple technique. [Means for solving the problem]

[0008] An information processing device according to a first aspect of the present invention comprises an arithmetic circuit having a first arithmetic circuit and a second arithmetic circuit, a control circuit, a counter circuit, and a comparison circuit, wherein the control circuit processes each bit of input multi-bit secret information as a processing target bit in sequence, and when the logic of the processing target bit is "1", causes the arithmetic circuit to perform a first operation by the first arithmetic circuit and a second operation by the second arithmetic circuit, and when the logic of the processing target bit is "0", causes the arithmetic circuit to perform only the second operation of the first operation and the second operation, the counter circuit outputs a counter value based on the number of processing target bits for which the arithmetic circuit has performed only the second operation of the first operation and the second operation, and the comparison circuit compares the counter value with an expected value of the counter value based on the secret information.

[0009] According to the first aspect, FA can be detected by detecting a mismatch between the counter value and the expected value. As a result, FA countermeasures can be strengthened by a simple method of comparing the counter value and the expected value using a comparator circuit.

[0010] A second aspect of the present invention is an information processing device according to the first aspect, wherein the arithmetic circuit is a modular exponentiation circuit, the first arithmetic circuit is a multiplication circuit, and the second arithmetic circuit is a squaring circuit.

[0011] According to the second aspect, it is possible to easily detect FA that targets an attack on a modular exponentiation circuit.

[0012] An information processing device according to a third aspect of the present invention is an information processing device according to the first aspect, wherein the arithmetic circuit is a scalar multiplication circuit defined on an elliptic curve, the first arithmetic circuit is a point addition circuit, and the second arithmetic circuit is a point doubling circuit.

[0013] According to the third aspect, it is possible to easily detect FA that targets a scalar multiplication circuit as an attack target.

[0014] In the information processing device according to a fourth aspect of the present invention, in addition to the first aspect, the first arithmetic circuit and the second arithmetic circuit are configured using the same circuit that can switch between executing the first arithmetic and the second arithmetic.

[0015] According to the fourth aspect, the first arithmetic circuit and the second arithmetic circuit are configured using the same circuit, and therefore the circuit scale can be reduced compared to when they are configured using different circuits.

[0016] An information processing device according to a fifth aspect of the present invention is any one of the first to fourth aspects, wherein the counter value indicates the total number of processing target bits on which the arithmetic circuit has performed only the second operation of the first and second operations.

[0017] According to the fifth aspect, FA can be detected by a simple process of comparing the total number of processing target bits for which only the second operation of the first and second operations has been performed with an expected value.

[0018] An information processing device according to a sixth aspect of the present invention is any one of the first to fourth aspects, wherein the counter value indicates the sum of weight values ​​set according to the bit positions of the processing target bits for which the arithmetic circuit has performed only the second operation out of the first operation and the second operation.

[0019] According to the sixth aspect, the detection accuracy of FA can be improved even when the number of processing target bits whose logic has been inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic has been inverted from "1" to "0" by error injection.

[0020] An information processing device according to a seventh aspect of the present invention is any one of the first to fourth aspects, wherein the counter values ​​include a first counter value indicating the total number of processing target bits for which the arithmetic circuit has performed only the second operation of the first operation and the second operation, and a second counter value indicating the sum of weight values ​​set according to the bit positions of the processing target bits for which the arithmetic circuit has performed only the second operation of the first operation and the second operation.

[0021] According to the seventh aspect, even if the first counter value and the expected value of the first counter value become equal due to the bit position or number of error injections, FA can be detected because the second counter value and the expected value of the second counter value are different. Also, even if the second counter value and the expected value of the second counter value become equal due to the bit position or number of error injections, FA can be detected because the first counter value and the expected value of the first counter value are different. As a result, FA can be detected with higher accuracy.

[0022] An information processing device according to an eighth aspect of the present invention is an information processing device according to the sixth or seventh aspect, wherein the plurality of bits are k bits, with the least significant bit being bit 0 and the most significant bit being bit k-1, and the weight value set at the bit position of the nth bit (n is an integer between 0 and k-1) is 2 n is.

[0023] According to the eighth aspect, even if the number of processing target bits whose logic is inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic is inverted from "1" to "0" by error injection, FA can be detected with high accuracy. n This makes it possible to update the counter value by a simple process of bit shifting and exclusive ORing.

[0024] An information processing device according to a ninth aspect of the present invention is an information processing device according to the eighth aspect, wherein the counter circuit has a plurality of registers, and the counter circuit distributes and stores the counter value among the plurality of registers according to the order of appearance of the processing target bits on which the arithmetic circuit has performed only the second operation out of the first operation and the second operation.

[0025] According to the ninth aspect, by storing the counter value in a plurality of registers in a distributed manner, the amount of information contained in each register can be reduced and leakage of confidential information from the counter circuit can be prevented.

[0026] The information processing device according to a tenth aspect of the present invention is the information processing device of the eighth aspect, further comprising a setting circuit that sets an initial value of the counter value using a random number.

[0027] According to the tenth aspect, the counter value can be concealed by setting the initial value of the counter value using a random number. As a result, leakage of confidential information from the counter circuit can be prevented. Furthermore, this can be realized at a lower cost than when the confidential information itself is concealed using a random number.

[0028] An information processing device according to an eleventh aspect of the present invention is any one of the first to tenth aspects, wherein when the logic of the bit to be processed is "0", the counter circuit updates the counter value by calculation using the first calculation circuit.

[0029] According to the eleventh aspect, even when the logic of the processing target bit is "0", the operation is performed using the first operation circuit, so that SPA resistance can be imparted.

[0030] An information processing device according to a twelfth aspect of the present invention is, in the eleventh aspect, such that the counter circuit performs a bit shift of the counter value when the arithmetic circuit performs only the second operation of the first operation and the second operation, and the counter value indicates the total number of bit shifts.

[0031] According to the twelfth aspect, FA can be detected by a simple process of comparing the number of digits of the expected value with the number of digits of the counter value.

[0032] An information processing device according to a thirteenth aspect of the present invention is the information processing device of the twelfth aspect, wherein a shift width of the bit shift is set according to the number of times the processing target bit is processed.

[0033] According to the thirteenth aspect, the detection accuracy of FA can be improved even when the number of processing target bits whose logic has been inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic has been inverted from "1" to "0" by error injection.

[0034] An information processing device according to a 14th aspect of the present invention is, in the 12th aspect, an information processing device in which the shift width of the bit shift is set according to the number of consecutive processing target bits on which the arithmetic circuit has performed the first operation and the second operation before a processing target bit on which the arithmetic circuit has performed only the second operation of the first operation and the second operation.

[0035] According to the fourteenth aspect, the detection accuracy of FA can be improved even when the number of processing target bits whose logic has been inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic has been inverted from "1" to "0" by error injection.

[0036] An information processing device according to a 15th aspect of the present invention is, in the 11th aspect, the counter circuit performs point addition of the counter value when the arithmetic circuit performs only the second operation of the first operation and the second operation, and the counter value indicates point coordinates.

[0037] According to the fifteenth aspect, FA can be detected by a simple process of comparing the point coordinates of the expected value with the point coordinates of the counter value.

[0038] An information processing device according to a 16th aspect of the present invention is the 15th aspect, wherein the number of times of point addition is set in accordance with the number of times the processing target bit is processed.

[0039] According to the 16th aspect, the detection accuracy of FA can be improved even when the number of processing target bits whose logic has been inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic has been inverted from "1" to "0" by error injection.

[0040] An information processing method according to a seventeenth aspect of the present invention includes an information processing device that acquires multiple bits of secret information, processes each bit of the multiple bits in order as a processing target bit, and performs a first operation and a second operation if the logic of the processing target bit is "1", and performs only the second operation of the first operation and the second operation if the logic of the processing target bit is "0", counts a counter value based on the number of processing target bits for which only the second operation of the first operation and the second operation has been performed, and compares the counter value with an expected value of the counter value based on the secret information.

[0041] According to the seventeenth aspect, FA can be detected by detecting a mismatch between the counter value and the expected value. As a result, it is possible to strengthen FA countermeasures by using a simple method in which the counter value and the expected value are compared by a comparator circuit. [Effects of the Invention]

[0042] According to the present invention, it is possible to strengthen FA countermeasures using a simple method. [Brief explanation of the drawings]

[0043] [Figure 1] 1 is a diagram showing a simplified configuration of an information processing apparatus according to an embodiment of the present invention; [Figure 2]FIG. 2 is a diagram illustrating a first configuration example of an arithmetic circuit. [Figure 3] 10 is a flowchart showing a process executed by the information processing device in the first configuration example. [Figure 4] FIG. 10 is a diagram illustrating a second configuration example of the arithmetic circuit. [Figure 5] 10 is a flowchart showing a process executed by the information processing device in the second configuration example. [Figure 6] FIG. 10 is a diagram showing a simplified example of setting weight values. [Figure 7] FIG. 10 is a diagram showing a simplified configuration of an information processing device according to a second modified example. [Figure 8] FIG. 10 is a diagram showing a simplified example of setting weight values. [Figure 9] FIG. 10 is a diagram showing a simplified configuration of an information processing device according to a fourth modified example. [Figure 10] FIG. 10 is a simplified diagram illustrating an example of secret information. [Figure 11] FIG. 10 is a simplified diagram illustrating an example of a counter value of a register. [Figure 12] FIG. 13 is a diagram showing a simplified configuration of an information processing device according to a fifth modified example. [Figure 13] FIG. 13 is a diagram showing a simplified configuration of an information processing device according to a sixth modified example. [Figure 14] FIG. 10 is a diagram showing a simplified example of setting a shift width. [Figure 15] FIG. 10 is a simplified diagram showing an example of setting a point addition value. [Figure 16] FIG. 13 is a diagram showing a simplified configuration of an information processing device according to an eighth modification. [Figure 17] FIG. 10 is a simplified diagram illustrating a counter value update process performed by a counter circuit. DETAILED DESCRIPTION OF THE INVENTION

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Elements with the same reference numerals in different drawings indicate the same or corresponding elements.

[0045] 1 is a simplified diagram showing the configuration of an information processing device 1 according to an embodiment of the present invention. The information processing device 1 includes an arithmetic circuit 11, a control circuit 12, a counter circuit 13, a comparison circuit 14, a setting circuit 15, a memory circuit 16, and selection circuits 17 and 18. The arithmetic circuit 11 includes a first arithmetic circuit 21 and a second arithmetic circuit 22.

[0046] FIG. 2 is a diagram illustrating a first configuration example of the arithmetic circuit 11. In the first configuration example, the arithmetic circuit 11 is a modular exponentiation circuit 11A, the first arithmetic circuit 21 is a multiplication circuit 21A, and the second arithmetic circuit 22 is a squaring circuit 22A. In the first configuration example, the information processing device 1 is applied to RSA encryption, which is a type of public key encryption. The multiplication circuit 21A and the squaring circuit 22A may be configured as separate circuits, or may be configured using the same circuit that can switch between multiplication and squaring by inputting a control parameter. In RSA encryption, the computational cost of modular exponentiation is dominant and critical. The modular exponentiation circuit 11A performs modular exponentiation at high speed using the binary algorithm. Note that the application of the information processing device 1 is not limited to RSA encryption, and may also be any public key encryption that uses modular exponentiation.

[0047] FIG. 3 is a flowchart showing the process executed by the information processing device 1 in the first configuration example.

[0048] First, in step S01, the information processing device 1 acquires secret information D1. The secret information D1 may be a secret key of multiple k bits indicating the value of an exponent. k is, for example, 2048, but is not limited to this. The value of each bit of the secret information D1 is "0" or "1" in binary logic. The information processing device 1 also acquires ciphertext D2. The ciphertext D2 may be data encrypted using a public key or the like. The secret information D1 is input to the control circuit 12 and the setting circuit 15. The ciphertext D2 is input to the modular exponentiation circuit 11A. The modular exponentiation circuit 11A has a T register (not shown) that stores a variable T and an S register (not shown) that stores a variable S. The modular exponentiation circuit 11A stores the ciphertext D2 in the T register and an initial value "1" in the S register.

[0049] Next, in step S02, the setting circuit 15 sets an expected value D3 based on the secret information D1. In this embodiment, the setting circuit 15 sets the total number of bits whose logic is "0" in the k-bit secret information D1 as the expected value D3.

[0050] Next, in step S03, the setting circuit 15 stores in the memory circuit 16 the expected value D3 set in step S02.

[0051] After step S01, in step S04, the counter circuit 13 resets the counter value to an initial value, which in this embodiment is "0."

[0052] The control circuit 12 processes each bit of the k-bit secret information D1 as a processing target bit (hereinafter sometimes abbreviated as "target bit") in order. In the example of this embodiment, the information processing device 1 performs the modular exponentiation operation using a rightward binary algorithm. In the rightward binary algorithm, processing of each bit proceeds rightward from the most significant bit to the least significant bit of the k bits. Note that the information processing device 1 may also perform the modular exponentiation operation using a leftward binary algorithm. In the leftward binary algorithm, processing of each bit proceeds leftward from the least significant bit to the most significant bit of the k bits.

[0053] Next, in step S05, the control circuit 12 determines whether the logic of the target bit is "0." The control circuit 12 inputs a control signal D4 corresponding to the logic of the target bit to the modular exponentiation circuit 11A. The control signal D4 is also input to the counter circuit 13.

[0054] If the logic of the target bit is "1" (step S05: NO), in step S08A, the control circuit 12 causes the modular exponentiation circuit 11A to perform multiplication by the multiplication circuit 21A (i.e., the first operation by the first operation circuit 21) and squaring by the squaring circuit 22A (i.e., the second operation by the second operation circuit 22) using the control signal D4 indicating the logic "1".

[0055] Multiplication and squaring in modular exponentiation are expressed by the following formulas using modulus p and variables S and T. Multiplication: ST mod p Squaring: T 2 mod p

[0056] The multiplication circuit 21A stores the multiplied value in the S register, and the squaring circuit 22A stores the multiplied value in the T register.

[0057] On the other hand, if the logic of the target bit is "0" (step S05: YES), in step S06A, the control circuit 12 causes the modular exponentiation circuit 11A to perform only the squaring by the squaring circuit 22A out of the multiplication by the multiplication circuit 21A and the squaring by the squaring circuit 22A, using the control signal D4 indicating the logic "0".

[0058] The squaring circuit 22A stores the squared value in the T register.

[0059] Furthermore, in step S07, the counter circuit 13 updates the counter value D5 when the control signal D4 indicating a logic "0" is input, i.e., when the modular exponentiation circuit 11A executes only the squaring by the squaring circuit 22A out of the multiplication by the multiplication circuit 21A and the squaring by the squaring circuit 22A. In this embodiment, the counter circuit 13 increments the counter value D5 by "1" each time the control signal D4 indicating a logic "0" is input. When the control signal D4 indicating a logic "1" is input, i.e., when the modular exponentiation circuit 11A executes both the multiplication by the multiplication circuit 21A and the squaring by the squaring circuit 22A, the counter circuit 13 does not update the counter value D5. The counter circuit 13 outputs the counter value D5. The counter value D5 is input to the comparison circuit 14.

[0060] In step S09 following step S07 or step S08A, the information processing device 1 determines whether or not the processing for all k bits as target bits has been completed.

[0061] If an unprocessed target bit exists (step S09: NO), in step S10 the information processing device 1 updates the target bit by shifting it one bit to the right. The information processing device 1 repeatedly executes the processes from step S05 onwards for the new target bit after the update.

[0062] If processing of all target bits is completed (step S09: YES), in step S11, the comparator circuit 14 compares the expected value D3 input from the memory circuit 16 with the counter value D5 input from the counter circuit 13 to determine whether the expected value D3 and the counter value D5 are the same. If the logic of the control signal D4 is inverted by FA to the modular exponentiation circuit 11A, the counter value D5 will not match the expected value D3. This allows FA to be detected. The comparator circuit 14 outputs data D6 indicating the comparison result. The data D6 is input to the selection circuit 18.

[0063] If the expected value D3 and the counter value D5 are the same (step S11: YES), in step S12 the modular exponentiation circuit 11A outputs data D9 indicating the operation result, and the selection circuit 18 outputs the data D9. The data D9 includes plaintext data obtained by decrypting the ciphertext D2.

[0064] If the expected value D3 and the counter value D5 are not the same (step S11: NO), the selection circuit 18 outputs dummy data D10 in step S13. The dummy data D10 is data unrelated to the ciphertext D2. Note that instead of outputting the dummy data D10, other error handling may be performed, such as outputting an alert or not outputting any data.

[0065] FIG. 4 is a diagram illustrating a second configuration example of the arithmetic circuit 11. In the second configuration example, the arithmetic circuit 11 is a scalar multiplication circuit 11B, the first arithmetic circuit 21 is a point addition circuit 21B, and the second arithmetic circuit 22 is a point doubling circuit 22B. In the second configuration example, the information processing device 1 is applied to elliptic curve cryptography, which is included in public key cryptography. The point addition circuit 21B and the point doubling circuit 22B may be configured as separate circuits, or may be configured using the same circuit that can switch between point addition and point doubling by inputting a control parameter. In elliptic curve cryptography, the computational cost of scalar multiplication defined on an elliptic curve is dominant and critical. The scalar multiplication circuit 11B performs scalar multiplication at high speed using the binary algorithm.

[0066] 5 is a flowchart showing the processing executed by the information processing device 1 in the second configuration example. The following description will focus on the differences from the flowchart shown in FIG.

[0067] In step S01, the information processing device 1 acquires secret information D1. The secret information D1 may be a secret key of multiple k bits indicating a scalar value, where k is, for example, 256, but is not limited to this.

[0068] In step S02, the setting circuit 15 sets an expected value D3 based on the secret information D1.

[0069] In step S03, the setting circuit 15 stores in the memory circuit 16 the expected value D3 set in step S02.

[0070] In step S04, the counter circuit 13 resets the counter value to an initial value.

[0071] In step S05, the control circuit 12 determines whether the logic of the target bit is "0" or not.

[0072] If the logic of the target bit is "1" (step S05: NO), in step S08B, the control circuit 12 causes the scalar multiplication circuit 11B to execute point addition by the point addition circuit 21B (i.e., the first operation by the first operation circuit 21) and point doubling by the point doubling circuit 22B (i.e., the second operation by the second operation circuit 22) using the control signal D4 indicating logic "1". Point addition in scalar multiplication means addition of points on an elliptic curve. Point doubling in scalar multiplication means doubling of a point on an elliptic curve.

[0073] On the other hand, if the logic of the target bit is "0" (step S05: YES), in step S06B, the control circuit 12 causes the scalar multiplication circuit 11B to perform only the point doubling by the point doubling circuit 22B, out of the point addition by the point addition circuit 21B and the point doubling by the point doubling circuit 22B, using the control signal D4 indicating the logic "0".

[0074] Furthermore, in step S07, the counter circuit 13 updates the counter value D5 when the control signal D4 indicating a logic "0" is input, i.e., when the scalar multiplication circuit 11B executes only the point doubling by the point doubling circuit 22B out of the point addition by the point addition circuit 21B and the point doubling by the point doubling circuit 22B. In this embodiment, the counter circuit 13 increments the counter value D5 by "1" each time the control signal D4 indicating a logic "0" is input. The counter circuit 13 does not update the counter value D5 when the control signal D4 indicating a logic "1" is input, i.e., when the scalar multiplication circuit 11B executes both the point addition by the point addition circuit 21B and the point doubling by the point doubling circuit 22B. The counter circuit 13 outputs the counter value D5. The counter value D5 is input to the comparison circuit 14.

[0075] In step S09 following step S07 or step S08B, the information processing device 1 determines whether or not the processing for all k bits as target bits has been completed.

[0076] If there is an unprocessed target bit (step S09: NO), in step S10 the information processing device 1 updates the target bit by shifting it one bit to the right.

[0077] If processing of all target bits is completed (step S09: YES), in step S11, the comparator circuit 14 compares the expected value D3 input from the memory circuit 16 with the counter value D5 input from the counter circuit 13, and determines whether the expected value D3 and the counter value D5 are the same. The comparator circuit 14 outputs data D6 indicating the comparison result. The data D6 is input to the selector circuit 18.

[0078] If the expected value D3 and the counter value D5 are the same (step S11: YES), the scalar multiplication circuit 11B outputs data D9 indicating the operation result in step S12, and the selection circuit 18 outputs data D9.

[0079] If the expected value D3 and the counter value D5 are not the same (step S11: NO), the selection circuit 18 outputs dummy data D10 in step S13.

[0080] According to this embodiment, FA can be detected by detecting a mismatch between the counter value D5 and the expected value D3. As a result, FA countermeasures can be strengthened by a simple method in which the comparator circuit 14 compares the counter value D5 and the expected value D3.

[0081] Furthermore, according to this embodiment, it is possible to easily detect FA that targets the modular exponentiation circuit 11A as an attack target.

[0082] Furthermore, according to this embodiment, it is possible to easily detect FA that targets the scalar multiplication circuit 11B as an attack target.

[0083] Furthermore, according to this embodiment, FA can be detected by a simple process of comparing the total number of processing target bits for which only the second operation of the first and second operations has been performed with the expected value D3.

[0084] Various modifications of the above embodiment will be described below.

[0085] (First Modification) In the embodiment, the counter value D5 may indicate the sum of weight values ​​set according to the bit positions of the processing target bits for which the arithmetic circuit 11 has performed only the second arithmetic operation out of the first arithmetic operation and the second arithmetic operation.

[0086] 6 is a simplified diagram showing an example of setting weight values. The weight value differs depending on the bit position of the bit to be processed. For example, a weight value of "1" is set to the 0th bit (least significant bit) of the secret information D1, a weight value of "2" is set to the 1st bit, and a weight value of "3" is set to the 2nd bit.

[0087] The setting circuit 15 calculates an expected value D3 according to the secret information D1 based on the weight setting rule. The expected value D3 indicates the sum of weights set according to the bit positions of bits whose logic is "0" among the multiple bits of the secret information D1.

[0088] According to this modified example, the detection accuracy of FA can be improved even when the number of processing target bits whose logic has been inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic has been inverted from "1" to "0" by error injection.

[0089] (Second Modification) In the first modified example, the counter value may further include the counter value in the above embodiment. That is, the counter value D5 may include both the counter value in the above embodiment and the counter value in the first modified example.

[0090] 7 is a simplified diagram showing the configuration of an information processing device 1 according to a second modification. The counter circuit 13 outputs a first counter value D5A and a second counter value D5B as the counter value D5. The first counter value D5A indicates the total number of processing target bits for which the arithmetic circuit 11 has performed only the second operation of the first and second operations. The second counter value D5B indicates the sum of weight values ​​set according to the bit positions of processing target bits for which the arithmetic circuit 11 has performed only the second operation of the first and second operations.

[0091] The setting circuit 15 calculates a first expected value D3A and a second expected value D3B as the expected value D3. The first expected value D3A indicates the total number of bits whose logic is "0" among the multiple bits of the secret information D1, and corresponds to the expected value of the first counter value D5A. The second expected value D3B indicates the sum of weight values ​​set according to the bit positions of the bits whose logic is "0" among the multiple bits of the secret information D1, and corresponds to the expected value of the second counter value D5B.

[0092] The comparator circuit 14 compares the first expected value D3A with the first counter value D5A and compares the second expected value D3B with the second counter value D5B. If the first expected value D3A and the first counter value D5A match and the second expected value D3B and the second counter value D5B match, the comparator circuit 14 outputs data D6 indicating a comparison result that an FA has not been detected. If the first expected value D3A and the first counter value D5A do not match or if the second expected value D3B and the second counter value D5B do not match, the comparator circuit 14 outputs data D6 indicating a comparison result that an FA has been detected.

[0093] According to this modification, even if the first counter value D5A and the first expected value D3A become equal due to the bit position or number of error injections, FA can be detected because the second counter value D5B and the second expected value D3B are different. Also, even if the second counter value D5B and the second expected value D3B become equal due to the bit position or number of error injections, FA can be detected because the first counter value D5A and the first expected value D3A are different. As a result, FA can be detected with higher accuracy.

[0094] (Third Modification) In the first or second modification, the weight value is 2 n That is, the secret information D1 is a plurality of k bits, with the least significant bit being bit 0 and the most significant bit being bit k-1, and the weight value set at the bit position of the nth bit (n is an integer between 0 and k-1) is 2 n It may be.

[0095] FIG. 8 is a simplified diagram showing an example of setting weight values. The weight value differs depending on the bit position of the bit to be processed. For example, the 0th bit of the secret information D1 is set to "2 0 The weight value is set to "2 1 The weight value is set to "2 2 " weight value is set.

[0096] The setting circuit 15 calculates an expected value D3 according to the secret information D1 based on the weight setting rule. The expected value D3 indicates the sum of weights set according to the bit positions of bits whose logic is "0" among the multiple bits of the secret information D1.

[0097] According to this modification, the weight value is set to 2 n By setting the weighting value to 2, FA can be reliably detected. For example, even if the number of processing target bits whose logic is inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic is inverted from "1" to "0" by error injection, FA can be reliably detected. n By doing so, when the control signal D4 indicating the logic "0" is input, the most significant bit of the counter value D5 is inverted and then the counter value D5 is circularly shifted to the left, and when the control signal D4 indicating the logic "1" is input, the counter value D5 is circularly shifted to the left without inverting the most significant bit of the counter value D5, thereby making it possible to update the counter value D5 through a simple process.

[0098] (Fourth Modification) In a third variant, the counter circuit 13 may be equipped with multiple registers, and the counter circuit 13 may store the counter value D5 in a distributed manner in the multiple registers according to the order of appearance of the processing target bits for which the arithmetic circuit 11 performed only the second operation of the first and second operations.

[0099] 9 is a diagram showing a simplified configuration of an information processing device 1 according to the fourth modification. The counter circuit 13 has a plurality of registers R1 to R4 (four in the example shown in FIG. 9).

[0100] Fig. 10 is a simplified diagram showing an example of the secret information D1. In the example shown in Fig. 10, the secret information D1 has a bit sequence of "0110001110000110".

[0101] Counter circuit 13 updates the counter value of register R1 in response to the first occurrence of "0", updates the counter value of register R2 in response to the second occurrence of "0", updates the counter value of register R3 in response to the third occurrence of "0", updates the counter value of register R4 in response to the fourth occurrence of "0", and repeats the same updating process thereafter.

[0102] 11 is a simplified diagram showing an example of the counter values ​​of registers R1 to R4. The arithmetic circuit 11 performs only the second operation of the first and second operations in response to the bit positions of "0" in the secret information D1, and the counter value of one of registers R1 to R4 becomes "1" depending on the order in which the "0" bits to be processed appear.

[0103] According to this modification, by storing the counter value D5 in a plurality of registers R1 to R4 in a distributed manner, the amount of information contained in each of the registers R1 to R4 can be reduced and leakage of the secret information D1 from the counter circuit 13 can be prevented.

[0104] (Fifth Modification) For example, in the third modification, the initial value of the counter value D5 may be set randomly using a random number. Note that the fifth modification can also be applied to the above embodiment or other modifications.

[0105] FIG. 12 is a simplified diagram showing the configuration of an information processing device 1 according to a fifth modified example. The information processing device 1 includes a setting circuit 30 that sets an initial value of a counter value D5 using a random number. The setting circuit 30 includes, for example, a pseudo-random number generation circuit. The setting circuit 30 generates and outputs an initial value D20, which is a random number value. The initial value D20 is input to the counter circuit 13 and the setting circuit 15. In step S02 of the flowchart shown in FIGS. 3 and 5, the setting circuit 15 sets an expected value D3 based on the secret information D1 and the initial value D20. In addition, in step S04 of the flowchart shown in FIGS. 3 and 5, the counter circuit 13 resets the counter value D5 to the initial value D20.

[0106] According to this modification, the counter value D5 can be concealed by setting the initial value D20 of the counter value D5 using a random number. As a result, it is possible to prevent the secret information D1 from leaking from the counter circuit 13. Furthermore, this can be achieved at a lower cost than when the secret information D1 itself is concealed using a random number.

[0107] (Sixth Modification) In the embodiment, the counter circuit 13 may update the counter value D5 through calculation using the first calculation circuit 21.

[0108] 13 is a simplified diagram showing the configuration of an information processing device 1 according to a sixth modification. The counter circuit 13 is configured using the first arithmetic circuit 21 of the arithmetic circuit 11, and updates the counter value D5 through calculation using the first arithmetic circuit 21.

[0109] As shown in FIG. 2, when the first arithmetic circuit 21 is a multiplication circuit 21A, the counter circuit 13 sets the initial value of the counter value D5 to "1." The counter circuit 13 multiplies the current counter value D5 by "2" using the multiplication circuit 21A corresponding to the processing target bit on which the arithmetic circuit 11 has performed only the second arithmetic operation of the first and second arithmetic operations. That is, the counter value D5 is shifted one bit to the left, thereby adding one digit to the counter value D5. The comparison circuit 14 compares the number of digits of the expected value D3 according to the secret information D1 with the final number of digits of the counter value D5. FA can be detected by the simple process of comparing the number of digits of the expected value D3 with the number of digits of the counter value D5.

[0110] 4, when the first arithmetic circuit 21 is the point addition circuit 21B, the counter circuit 13 sets the initial value of the counter value D5 to a predetermined point coordinate on the elliptic curve. The counter circuit 13 adds a base point G to the current counter value D5 using the point addition circuit 21B, corresponding to the processing target bit on which the arithmetic circuit 11 has performed only the second operation of the first and second operations. The comparison circuit 14 compares the point coordinate of the expected value D3 calculated in advance according to the secret information D1 with the final point coordinate of the counter value D5.

[0111] According to this modification, even when the logic of the bit to be processed is "0", an operation is performed using the first operation circuit 21, so that in addition to FA resistance, resistance to simple power analysis attacks (SPA resistance) can be imparted.

[0112] Furthermore, according to this modification, FA can be detected by a simple process of comparing the number of digits of the expected value D3 with the number of digits of the counter value D5.

[0113] Furthermore, according to this modification, FA can be detected by a simple process of comparing the point coordinates of the expected value D3 with the point coordinates of the counter value D5.

[0114] (Seventh Modification) In the sixth modification, the shift width of the bit shift may be set according to the number of times the processing target bit is processed.

[0115] 14 is a simplified diagram showing an example of setting the shift width. The shift width differs depending on the number of times the bit to be processed is processed (i.e., the bit position of the bit to be processed). For example, the shift width is set to 1 bit for the first processing, 2 bits for the second processing, and 3 bits for the third processing.

[0116] In the sixth modification, the point addition value may be set according to the number of times the processing target bit is processed.

[0117] 15 is a simplified diagram showing an example of setting the point addition value. The point addition value differs depending on the number of times the bit to be processed is processed (i.e., the bit position of the bit to be processed). For example, the point addition value is set to 1G for the first processing, 2G for the second processing, and 3G for the third processing.

[0118] According to this modified example, the detection accuracy of FA can be improved even when the number of processing target bits whose logic has been inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic has been inverted from "1" to "0" by error injection.

[0119] (Eighth Modification) In the sixth variant, the shift width of the bit shift may be set according to the number of consecutive processing target bits on which the arithmetic circuit 11 has performed the first and second operations before the processing target bit on which the arithmetic circuit 11 has performed only the second operation of the first and second operations.

[0120] 16 is a simplified diagram showing the configuration of an information processing device 1 according to the eighth modification. The counter circuit 13 has an XOR circuit 40 that performs an exclusive OR (XOR) operation.

[0121] FIG. 17 is a simplified diagram showing the process of updating the counter value D5 by the counter circuit 13.

[0122] As shown in (A), the confidential information is 6-bit data "101110" consisting of bits B1 to B6, and the initial value of the counter value D5 is set to "000000."

[0123] As shown in (B), when processing bit B2, which is "0," counter circuit 13 counts the number of consecutive "1"s immediately preceding bit B2. In the example shown in FIG. 17, the consecutive number corresponds to bit B1, which is "1." Counter circuit 13 bit-shifts the current counter value D5 to the left by one bit to correspond to the consecutive number "1." Counter circuit 13 generates one-bit data D31, "1," indicating the consecutive number "1." Counter circuit 13 updates counter value D5 by performing an XOR operation on the bit-shifted counter value D5 and data D31 using XOR circuit 40. The updated counter value D5 becomes "000001."

[0124] As shown in (C), when processing bit B6, which is "0," counter circuit 13 counts the number of consecutive "1"s immediately preceding bit B6. In the example shown in FIG. 17, the consecutive number is "3," corresponding to bits B3 to B5. Counter circuit 13 bit-shifts the current counter value D5 three bits to the left to correspond to the consecutive number "3." Counter circuit 13 generates 3-bit data D32 "100" indicating the consecutive number "3." Counter circuit 13 updates counter value D5 by using XOR circuit 40 to perform an XOR operation on the bit-shifted counter value D5 and data D32. The updated counter value D5 becomes "001100."

[0125] According to this modified example, the detection accuracy of FA can be improved even when the number of processing target bits whose logic has been inverted from "0" to "1" by error injection is equal to the number of processing target bits whose logic has been inverted from "1" to "0" by error injection.

[0126] The functions of the elements disclosed herein may be implemented using circuitry or processing circuitry, including general-purpose processors, special-purpose processors, integrated circuits, ASICs ("application-specific integrated circuits"), conventional circuitry, and / or combinations thereof, configured to perform the disclosed elements or programmed to perform the disclosed functions. A processor is considered to be processing circuitry or circuitry when it includes transistors and other circuitry therein. In this disclosure, a circuitry, unit, or means is hardware that performs the recited function or hardware programmed to perform the function. The hardware may be any hardware disclosed herein or other known hardware that is programmed to perform or configured to perform the recited function. When the hardware is a processor, which may be considered as a type of circuitry, the circuitry, means, or unit is a combination of hardware and software, software used to configure the hardware, and / or processor. [Explanation of symbols]

[0127] 1. Information processing equipment 11 Arithmetic circuit 11A Modular exponentiation circuit 11B Scalar multiplication circuit 12 Control circuit 13 Counter Circuit 14 Comparison circuit 15,30 Setting circuit 21 1st arithmetic circuit 21A Multiplier Circuit 21B-point adding circuit 22 Second arithmetic circuit 22A squaring circuit 22B point doubling circuit 40 XOR circuit

Claims

1. an arithmetic circuit having a first arithmetic circuit and a second arithmetic circuit; a control circuit; A counter circuit; a comparison circuit; Equipped with The control circuit Each bit of the input secret information is processed in order as a processing target bit, when the logic of the bit to be processed is "1", causing the arithmetic circuits to perform a first arithmetic operation by the first arithmetic circuit and a second arithmetic operation by the second arithmetic circuit; when the logic of the bit to be processed is "0", causing the arithmetic circuit to perform only the second operation of the first operation and the second operation; the counter circuit outputs a counter value based on the number of processing target bits for which the arithmetic circuit has performed only the second arithmetic operation of the first arithmetic operation and the second arithmetic operation; the comparison circuit compares the counter value with an expected value of the counter value based on the secret information; Information processing device.

2. the arithmetic circuit is a modular exponentiation arithmetic circuit, the first arithmetic circuit is a multiplication circuit, the second arithmetic circuit is a squaring circuit; The information processing device according to claim 1 .

3. the arithmetic circuit is a scalar multiplication circuit defined on an elliptic curve, the first arithmetic circuit is a point adding circuit, the second arithmetic circuit is a point doubling circuit; The information processing device according to claim 1 .

4. the first arithmetic circuit and the second arithmetic circuit are configured using the same circuit that can switch between executing the first arithmetic operation and the second arithmetic operation; The information processing device according to claim 1 .

5. the counter value indicates the total number of processing target bits for which the arithmetic circuit has performed only the second operation of the first operation and the second operation. The information processing device according to claim 1 .

6. the counter value indicates a total value of weight values ​​set according to the bit positions of the processing target bits for which the arithmetic circuit has performed only the second arithmetic operation out of the first arithmetic operation and the second arithmetic operation. The information processing device according to claim 1 .

7. The counter value is a first counter value indicating the total number of processing target bits for which the arithmetic circuit has performed only the second operation of the first operation and the second operation; a second counter value indicating the sum of weights set in accordance with the bit positions of the processing target bits for which only the second operation of the first operation and the second operation has been performed by the arithmetic circuit; Including, The information processing device according to claim 1 .

8. The plurality of bits are k bits, with the least significant bit being bit 0 and the most significant bit being bit k-1, The weight value set to the bit position of the nth bit (n is an integer between 0 and k-1) is 2 ｎ That is, 8. The information processing device according to claim 6 or 7.

9. the counter circuit has a plurality of registers; the counter circuit distributes and stores the counter values ​​among the plurality of registers according to an order of appearance of processing target bits on which the arithmetic circuit has performed only the second operation out of the first operation and the second operation. The information processing device according to claim 8 .

10. further comprising a setting circuit for setting an initial value of the counter value using a random number; The information processing device according to claim 8 .

11. the counter circuit updates the counter value by calculation using the first calculation circuit. The information processing device according to claim 1 .

12. the counter circuit performs a bit shift on the counter value when the arithmetic circuit has performed only the second arithmetic operation of the first arithmetic operation and the second arithmetic operation; The counter value indicates the total number of bit shifts. The information processing device according to claim 11.

13. The shift width of the bit shift is set according to the number of times the processing target bits are processed. The information processing device according to claim 12.

14. a shift width of the bit shift is set according to the number of consecutive processing target bits on which the arithmetic circuit has performed the first operation and the second operation, before the processing target bit on which the arithmetic circuit has performed only the second operation out of the first operation and the second operation. The information processing device according to claim 12.

15. the counter circuit performs point addition of the counter value when the arithmetic circuit performs only the second arithmetic operation of the first arithmetic operation and the second arithmetic operation; The counter value indicates a point coordinate. The information processing device according to claim 11.

16. The number of times of point addition is set according to the number of times the processing target bit is processed. The information processing device according to claim 15.

17. The information processing device Obtain multiple bits of secret information, processing each bit of the plurality of bits as a processing target bit in order; If the logic of the bit to be processed is "1", a first operation and a second operation are performed; When the logic of the bit to be processed is "0", only the second operation of the first operation and the second operation is performed; counting a counter value based on the number of processing target bits for which only the second operation of the first operation and the second operation has been performed; comparing the counter value with an expected value of the counter value based on the secret information; Information processing methods.

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