Liquid crystal device, wavelength selection switch unit, and method for detecting fault of liquid crystal device

Abstract

To provide a liquid crystal device, a wavelength selection switch unit, and a method for detecting a fault of the liquid crystal device, with which it is possible to detect a fault with good accuracy.SOLUTION: A liquid crystal device according to the present disclosure comprises: a shift register unit for sequentially taking in a video signal as much as the number of pixel rows in synchronism with a clock signal; a latch unit for outputting the plurality of video signals taken in by the shift register unit, simultaneously in synchronism with a trigger signal; a plurality of comparators for comparing each of the plurality of video signals outputted from the latch unit with a grayscale signal and, when matched, activating the respective match signals; an analog switch unit for supplying, to a plurality of data lines, a plurality of analog signals corresponding to timing at which the respective match signals of the plurality of comparators are activated; a fault detection circuit for latching the respective match signals of the plurality of comparators in synchronism with a trigger signal, and outputting a fault detection result in synchronism with the clock signal.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to a liquid crystal device, a wavelength selective switch device, and a method for detecting a fault in a liquid crystal device, and more particularly to a liquid crystal device, a wavelength selective switch device, and a method for detecting a fault in a liquid crystal device that are suitable for detecting a fault with high accuracy. [Background technology]

[0002] The liquid crystal display device disclosed in Patent Document 1 includes a plurality of pixels arranged in a matrix, a plurality of sets of data lines provided corresponding to each column of the plurality of pixels, a plurality of gate lines provided corresponding to each row of the plurality of pixels, a plurality of switches for supplying positive and negative polarity video signals to the plurality of sets of data lines in sequence on a set-by-set basis, and a driving means for driving the plurality of switches and the plurality of gate lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-223289 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in order to improve reliability, liquid crystal display devices are required to accurately detect failures due to aging, etc. However, Patent Document 1 does not disclose specific details of how to detect failures, and the liquid crystal display device disclosed in Patent Document 1 has the problem that it cannot accurately detect failures.

[0005] The present disclosure has been made in consideration of the above points, and an object of the present disclosure is to provide a liquid crystal device, a wavelength selective switch device, and a method for detecting a fault in a liquid crystal device, which are capable of detecting a fault with high accuracy. [Means for solving the problem]

[0006] a latch unit that simultaneously outputs the plurality of video signals acquired by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal whose potential changes monotonically and activates a corresponding match signal when the plurality of video signals match; an analog switch unit that supplies a plurality of analog voltages to the plurality of data lines in accordance with the timing at which the match signal of each of the plurality of comparators becomes active; and a fault detection circuit that acquires the respective match signals of the plurality of comparators in synchronization with the trigger signal, and shifts the acquired match signals in synchronization with the clock signal and outputs them as fault detection results.

[0007] a latch unit that simultaneously outputs the plurality of video signals acquired by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a gradation signal whose potential transitions monotonically and activates a corresponding match signal when the plurality of video signals match; an analog switch unit that supplies a plurality of analog voltages to the plurality of data lines according to the timing at which the match signals of each of the plurality of comparators become active; and a fault detection circuit, wherein the fault detection circuit acquires the respective match signals of the plurality of comparators in synchronization with the trigger signal, and the fault detection circuit shifts the acquired match signals in synchronization with the clock signal and outputs them as fault detection results. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a liquid crystal device, a wavelength selective switch device, and a method for detecting a fault in a liquid crystal device, which are capable of detecting a fault with high accuracy. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a wavelength selective switch according to the present disclosure as viewed from the x-axis direction. [Figure 2] 2 is a diagram showing a wavelength selective switch according to the present disclosure as viewed from the y-axis direction. FIG. [Figure 3] FIG. 10 is a diagram illustrating an example of wavelength channels focused on a reflective liquid crystal element applied to a wavelength selective switch according to the present disclosure. [Figure 4] FIG. 1 is a diagram showing an example of the configuration of a liquid crystal device at the conceptual stage. [Figure 5] 5 is an enlarged view of a horizontal driver and an analog switch section provided in the liquid crystal device shown in FIG. 4. FIG. [Figure 6] 5 is a diagram showing a specific example of the configuration of a pixel provided in the liquid crystal device shown in FIG. 4. FIG. [Figure 7] 5 is a timing chart for explaining a method of driving pixels by the liquid crystal device shown in FIG. [Figure 8] 10A and 10B are diagrams for explaining voltage levels from black to white of a positive polarity video signal and a negative polarity video signal written to a pixel. [Figure 9] 5 is a timing chart showing the operation of the liquid crystal device shown in FIG. 4 in an image display mode. [Figure 10] FIG. 1 is a diagram illustrating a configuration example of a liquid crystal device according to a first embodiment. [Figure 11] 11 is an enlarged view of a horizontal driver, an analog switch section, and a failure detection circuit provided in the liquid crystal device shown in FIG. 10. FIG. [Figure 12] 11 is a diagram showing a specific example of a failure detection circuit provided in the liquid crystal device shown in FIG. [Figure 13] FIG. 10 is a diagram illustrating a configuration example of a part of a liquid crystal device according to a second embodiment. [Figure 14]14 is a timing chart showing an example of a method for detecting a fault in the liquid crystal device shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Description of a wavelength selective switch to which a liquid crystal device according to the present disclosure is applied> 1 is a diagram illustrating an example of the configuration of a wavelength selective switch (WSS) array 100 according to the present disclosure, as viewed from the x-axis direction.

[0011] In recent years, optical communication networks have been developed to meet the demand for higher speeds and larger capacities in telecommunications and data networks. Optical communication networks generally employ optical wavelength division multiplexing (WDM) technology, which utilizes as much of the optical spectrum as possible. In optical WDM, as in wireless WDM, data is modulated onto multiple carrier waves with different wavelengths. These multiple carrier waves are called channels (wavelength channels). Compared to wireless WDM, optical WDM uses light waves instead of radio waves, and different wavelength channels correspond to different frequencies (wavelengths) of light. Optical communication typically uses channels within or around the wavelength range of 1 to 2 μm.

[0012] In many optical communication networks, optical nodes corresponding to branch points of the optical communication network are used. Each optical node uses, for example, a reconfigurable optical add-drop multiplexer (ROADM) device with reconfigurable add-drop functionality. Generally speaking, the ROADM functionality allows each optical node to drop or add one or more wavelength channels.

[0013] The WSS array 100 may be used for routing any wavelength channel in a ROADM system. In this case, the WSS array 100 may use an optical beam deflection device, such as a spatial light modulator, which may select a wavelength for deflection to a desired output port. For example, deflecting a wavelength channel to a drop port results in the channel being dropped from the WDM signal. Furthermore, the WSS array 100 may use a spatial light modulator using reflective liquid crystal elements.

[0014] Here, the ROADM function uses a Broadcast-and-Select (BS) scheme, which requires a WSS and an optical splitter at each node. However, future devices may use a Route-and-Select (RS) scheme with multiple WSS devices instead of optical splitters.

[0015] The WSS array 100 according to the present disclosure comprises at least two WSS devices within a single package. While the at least two WSS devices share most of the optical components, the at least two WSS devices are configured to operate independently. This not only reduces the size and optical complexity of the WSS array 100, but also allows for the same independent processing capabilities as larger, more costly devices. The WSS array 100 configured in this manner is suitable for use in optical communication networks, for example, as a reconfigurable optical ROADM, and as a component within a branching node using a route-and-select (RS) architecture. The WSS array 100 also incorporates a liquid crystal device according to the present disclosure as a reflective liquid crystal element.

[0016] As shown in Figure 1, the WSS array 100 includes two independent WSS devices 100a and 100b, each capable of operating as an independent WSS device. As used herein, the term "independent" refers to the ability of one WSS device 100a or 100b to independently process one or more WDM signals independently of the other. As used herein, the term "processing" is used broadly to include, for example, modulating, attenuating, blocking, redirecting, and switching the individual wavelength channels that make up each WDM signal.

[0017] The WSS array 100 includes an input section 110, an optical system 120, and a reflective liquid crystal element .

[0018] The optical system 120 is configured to beam shape each WDM signal beam, spectrally disperse (demultiplex) each WDM signal into its constituent wavelength channels or groups thereof, and spectrally combine (multiplex) the dispersed wavelength channels or groups thereof into one or more WDM signals. The reflective liquid crystal element 130 optically processes the dispersed wavelength channels or groups thereof, for example, to redirect the individual wavelength channels along predetermined paths within the WSS array 100.

[0019] The WSS array 100 is configured to be symmetrical about a symmetry axis Z1 extending in the z-axis direction. This allows a single optical system 120 and a single reflective liquid crystal element 130 to be shared by multiple WSS devices (WSS devices 100a and 100b in this example). While the WSS array 100 allows the WSS devices 100a and 100b to share most of the optical components, the WSS devices 100a and 100b are configured to operate independently. This not only reduces the size and optical complexity of the WSS array 100, but also allows it to have the same independent processing capabilities as larger, more costly devices.

[0020] The input unit 110 has input ports and output ports for transmitting one or more WDM signals to each of the WSS devices 100a and 100b. Each input port and each output port may be, for example, an optical fiber or a planar waveguide, but in this embodiment, an optical fiber will be used as an example. Therefore, hereinafter, each input port will also be referred to as an input fiber, and each output port will also be referred to as an output fiber.

[0021] Specifically, the input unit 110 includes an input fiber FI1 and n (n is an integer equal to or greater than 1) output fibers FO1_1 to FO1_n for the WSS device 100a, and an input fiber FI2 and n output fibers FO2_1 to FO2_n for the WSS device 100b. In the input unit 110, the optical fibers FI1, FO1_1 to FO1_n that make up the fiber stack for the WSS device 100a and the optical fibers FI2, FO2_1 to FO2_n that make up the fiber stack for the WSS device 100b are arranged along the y-axis direction.

[0022] The input unit 110 further includes collimating lenses LI1, LO1_1 to LO1_n corresponding to the optical fibers FI1, FO1_1 to FO1_n for the WSS device 100a, and collimating lenses LI2, LO2_1 to LO2_n corresponding to the optical fibers FI2, FO2_1 to FO2_n for the WSS device 100b. The collimating lenses LI1, LO1_1 to LO1_n and the collimating lenses LI2, LO2_1 to LO2_n form a microlens array. In the input unit 110, each collimating lens is disposed closer to the optical system 120 than each optical fiber. Each collimating lens is any optical element capable of guiding or changing the direction of light rays and focusing a set of light rays.

[0023] In the input section 110, the optical fibers FI1, FO1_1 to FO1_n and collimating lenses LI1, LO1_1 to LO1_n constitute the input section of the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n and collimating lenses LI2, LO2_1 to LO2_n constitute the input section of the WSS device 100b.

[0024] In the example of FIG. 1, the WSS array 100 employs a microlens array, but other types of arrays may be employed without departing from the spirit of the invention.

[0025] 1, the optical axes of the collimating lenses LI1, LO1_1 to LO1_n are displaced relative to the optical axes of the optical fibers FI1, FO1_1 to FO1_n, respectively. Due to this relative positional shift between the collimating lenses LI1, LO1_1 to LO1_n and the optical fibers FI1, FO1_1 to FO1_n, the input beam for the WSS device 100a is input to the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100a is output from the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100a are inclined in the negative direction of the y-axis by the angle θ1 with respect to the axis of symmetry Z1 from the input unit 110 to the optical system 120.

[0026] Similarly, the optical axes of the collimating lenses LI2, LO2_1 to LO2_n are displaced relative to the optical axes of the optical fibers FI2, FO2_1 to FO2_n, respectively. Due to this relative positional shift between the collimating lenses LI2, LO2_1 to LO2_n and the optical fibers FI2, FO2_1 to FO2_n, the input beam for the WSS device 100b is input to the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100b is output from the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100b are tilted in the positive direction of the y-axis by the angle θ2 with respect to the axis of symmetry Z1 from the input unit 110 to the optical system 120.

[0027] In the WSS array 100, a first WDM signal input from the outside is supplied to an input fiber FI1. The input fiber FI1 outputs a first WDM signal parallel to the symmetry axis Z1. The first WDM signal output from the input fiber FI1 passes through a collimating lens LI1, whereby the first WDM signal is tilted in the negative direction of the y-axis by an angle θ1, and is then supplied to an optical system 120. The first WDM signal supplied to the optical system 120 forms a WDM signal beam BI1 that travels along the y-z plane in the optical system 120. In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, the lens 121 does not affect the shaping of the WDM signal beam BI1 when viewed from the x-axis direction (in other words, when viewed from the y-z plane).

[0028] The WDM signal beam BI1 that has passed through the lens 121 is incident on the lens 122. The lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of the lens 122 depends on a reflective liquid crystal element 130 that is positioned on the focal plane of the lens 122. Furthermore, the center of the lens 122 is located on the symmetry axis Z1.

[0029] In the WSS array 100, a second WDM signal input from the outside is supplied to an input fiber FI2. The input fiber FI2 outputs a second WDM signal parallel to the symmetry axis Z1. The second WDM signal output from the input fiber FI2 is tilted in the positive direction of the y-axis by an angle θ2 by passing through a collimating lens LI2 and is then supplied to the optical system 120. The second WDM signal supplied to the optical system 120 forms a WDM signal beam BI2 that travels along the y-z plane in the optical system 120. In the optical system 120, the WDM signal beam BI2 is incident on a lens 121 that shapes the WDM signal beam BI2 in the x-axis direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, the lens 121 does not affect the shaping of the WDM signal beam BI2 when viewed from the x-axis direction (in other words, when viewed from the y-z plane).

[0030] The WDM signal beam BI2 that has passed through the lens 121 is incident on the lens 122. The lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of the lens 122 depends on a reflective liquid crystal element 130 that is positioned on the focal plane of the lens 122. Furthermore, the center of the lens 122 is located on the symmetry axis Z1.

[0031] Here, since reflective liquid crystal element 130 is positioned on the focal plane of lens 122, any pair of light rays reflected from positions having the same distance in the y-axis direction with respect to axis of symmetry Z1 among the light rays reflected by reflective liquid crystal element 130 will be emitted as a pair of parallel light rays from lens 122. Conversely, any pair of parallel light rays incident on lens 122 from the input unit 110 side will be focused in reflective liquid crystal element 130 at positions having the same distance in the y-axis direction with respect to axis of symmetry Z1.

[0032] 1, any incident beam (WDM signal beam BI1 in this example) traveling at an angle θ1 with respect to axis of symmetry Z1 is directed by lens 122 toward position LC1 on reflective liquid crystal element 130. Conversely, light rays (output beams BO1_1 to BO1_n in this example) originating from position LC1 on reflective liquid crystal element 130 are directed by lens 122 as parallel light rays traveling at an angle θ1 with respect to axis of symmetry Z1.

[0033] Similarly, any incident beam (WDM signal beam BI2 in this example) traveling at an angle θ2 with respect to axis of symmetry Z1 is directed by lens 122 toward position LC2 on reflective liquid crystal element 130. Conversely, light rays (output beams BO2_1 to BO2_n in this example) originating at position LC2 on reflective liquid crystal element 130 are directed by lens 122 as parallel light rays traveling at an angle θ2 with respect to axis of symmetry Z1.

[0034] FIG. 2 is a view of the WSS array 100 as seen from the y-axis direction. FIG. 3 is a diagram showing an example of wavelength channels focused on the reflective liquid crystal element 130. As shown in FIG.

[0035] 2 and 3, the WDM signal beam BI1 passes through the lens 122 and then through the dispersive element 124 provided between the lenses 122 and 123. The dispersive element 124 is a transmissive optical component such as a diffraction grating or a prism, and angularly disperses the wavelength channels of the WDM signal beam BI1. The wavelength channels dispersed by the dispersive element 124 pass through the lens 123. The lens 123 is a cylindrical lens, for example, and focuses the wavelength channels dispersed by the dispersive element 124 at a position LC1 on the reflective liquid crystal element 130.

[0036] Similarly, after passing through lens 122, WDM signal beam BI2 passes through dispersive element 124 provided between lenses 122 and 123. Dispersive element 124 angularly disperses the wavelength channels of WDM signal beam BI2. The wavelength channels dispersed by dispersive element 124 pass through lens 123. Lens 123 focuses the wavelength channels dispersed by dispersive element 124 at position LC2 on reflective liquid crystal element 130.

[0037] The reflective liquid crystal element 130 is a two-dimensional pixelated optical element, such as a pixelated spatial light modulator, that may reflect or redirect one or more of the dispersed wavelength channels so that they are routed to any one of the output fibers, as described in more detail below.

[0038] In the WSS device 100a, all light rays originating from a position LC1 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and are directed as parallel light rays tilted at an angle θ1. Thus, when the deflection angles are appropriately set, the output light rays reflected at the reflective liquid crystal element 130 (e.g., the reflected output light rays corresponding to a group of light rays, each of which may include one or more of the wavelength channels of the WDM signal beam BI1) can be routed to the output fibers FO1_1 through FO1_n, respectively. Here, because the output light rays reflected at the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO1_1 through LO1_n, they can be recombined into the output fibers FO1_1 through FO1_n with improved efficiency.

[0039] Similarly, in WSS device 100b, all light rays originating from position LC2 on reflective liquid crystal element 130 are displaced by lens 122 by an amount corresponding to the deflection angle from reflective liquid crystal element 130 and directed as parallel light rays tilted at angle θ2. Thus, when the deflection angles are appropriately set, output light rays reflected at reflective liquid crystal element 130 (e.g., reflected output light rays corresponding to a group of light rays that may each include one or more wavelength channels of WDM signal beam BI2) can be routed to output fibers FO2_1 through FO2_n, respectively. Here, because the output light rays reflected at reflective liquid crystal element 130 are displaced by the same amount by collimating lenses LO2_1 through LO2_n, they can be recombined into output fibers FO2_1 through FO2_n with improved efficiency.

[0040] Thus, the combination of input section 110 and lens 122 results in a WSS array 100 device that transmits a predetermined set of beams along a predetermined angle (e.g., angle θ1 for WSS device 100a and angle θ2 for WSS device 100b) and then directs these beams toward a position on reflective liquid crystal element 130 that depends only on the input angle (e.g., position LC1 for WSS device 100a and position LC2 for WSS device 100b). As a result, in WSS array 100, the light beams of WSS device 100a and the light beams of WSS device 100b are each processed by a common optical system 120 and reflective liquid crystal element 130, while each wavelength channel is processed separately by the processing capabilities of WSS array 100, as described in more detail below with reference to FIGS.

[0041] Next, the WSS array 100 will be described with reference to Figures 2 and 3. As already explained, Figure 2 is a view of the WSS array 100 as viewed from the y-axis direction. As already explained, Figure 3 is a view showing an example of wavelength channels focused on the reflective liquid crystal element 130. Of the WSS devices 100a and 100b, the following will mainly describe the WSS device 100a, but the same can be said for the WSS device 100b.

[0042] As shown in FIG. 2, in the WSS device 100a, a WDM signal beam BI1 that has passed through an input fiber FI1 is incident on an optical system 120. In the example of FIG. 2, the WDM signal beam BI1 propagates along a plane perpendicular to the paper (the yz plane) at an angle θ1. The WDM signal beam BI1 includes multiple wavelength channels. The multiple wavelength channels range from a longest wavelength λ1 to a shortest wavelength λn. Note that the WDM signal beam BI1 may include multiple wavelength channels, such as 96 wavelength channels spaced at 50 or 100 GHz on a fixed grating. In another example, the WSS device 100a may use a frequency spacing of 12.5 GHz and be used in an adaptive grating system having, for example, 130 or more wavelength channels (i.e., 97 or more wavelength channels).

[0043] In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 expands the WDM signal beam BI1, for example, so that the WDM signal beam BI1 has a diameter suitable for achieving a desired beam size in the dispersive element 124. Note that the collimating lens provided in the input unit 110 and the lens 121 provided in the optical system 120 may function as a beam expansion telescope.

[0044] In the optical system 120, the dispersive element 124 angularly disperses the wavelength channels of the WDM signal beam BI1. The wavelength channels λ1 to λn dispersed by the dispersive element 124 are each focused on the reflective liquid crystal element 130 by the lens 123. As a result, the wavelength channels λ1 to λn are spatially dispersed on the reflective liquid crystal element 130 in the wavelength dispersion direction (x-axis direction).

[0045] FIG. 3 illustrates an example of the distribution of wavelength channels in the pixel area of ​​the reflective liquid crystal element 130. Note that only wavelength channels λ1 to λ3 are shown in the example of FIG. 3 among the wavelength channels λ1 to λn. More generally, the wavelength channels can be arranged as long strips or elliptical spots on the two-dimensional surface of the reflective liquid crystal element 130. Simply put, each wavelength channel is treated as a discrete wavelength signal that can be independently acted upon by the reflective liquid crystal element 130. However, the reflective liquid crystal element 130 need not be limited to acting on individual wavelength channels but may also act upon groups of wavelength channels. Furthermore, as shown in FIG. 3, the wavelength channels or groups of wavelength channels themselves do not need to have fixed bandwidths because the reflective liquid crystal element 130 can be implemented in the WSS array 100 as a dynamically fully reconfigurable spatial light modulator. Therefore, the WSS array 100 can be used in systems with both conventional fixed-grid architectures and conventional or future-developed adaptive grid architectures.

[0046] As shown in FIG. 2, the reflective liquid crystal element 130 may then redirect wavelength channels λ1 to λn selected from the multiple wavelength channels toward output fibers FO1_1 to FO1_n, respectively. In the example of FIG. 2, the redirection by the reflective liquid crystal element 130 occurs along a plane (yz plane) perpendicular to the paper surface. The wavelength channels redirected by being reflected by the reflective liquid crystal element 130 are incident on the lens 123. The lens 123 redirects the incident wavelength channels so that they are recombined in the dispersive element 124. For example, the dispersive element 124 recombines the multiple wavelength channels to form a single beam (output beam). The output beams BO_1 to BO_n formed in the dispersive element 124 are redirected by the lens 122 and the collimating lens of the input unit 110 to become parallel beams, and are then output to the outside as processed signals via the output fibers FO1_1 to FO1_n.

[0047] For example, consider a case where a WDM signal beam BI1 includes three wavelength channels (hereinafter referred to as wavelength channels λ1 to λ3) having wavelengths λ1, λ2, and λ3 and channel bandwidths δλ1, δλ2, and δλ3, respectively. In this case, in the example of FIG. 1, the WDM signal beam BI1 is incident on the optical system 120 with a tilt angle of θ1. The light rays of the WDM signal beam BI1 traveling with a tilt angle of θ1 pass through the center of the lens 122, and therefore maintain the tilt angle of θ1. The WDM signal beam BI1 that has passed through the lens 122 is dispersed by the dispersive element 124 into multiple wavelength channels including the above-mentioned three wavelength channels along a plane (zx plane) perpendicular to the paper surface of FIG. 1. However, all of the multiple wavelength channels that have passed through the dispersive element 124 maintain the tilt angle of θ1 in a plane (yz plane) parallel to the paper surface of FIG. 1. The above three dispersed wavelength channels are then focused by a lens 123 onto different positions on the pixel area of ​​a reflective liquid crystal element 130, as shown in FIG.

[0048] It should be noted that several different routing functions may be combined in the routing function of the device. For example, consider the case where all three wavelength channels λ1-λ3 described above are routed to a common output fiber FO_n. After being reflected from reflective liquid crystal element 130, wavelength channels λ1-λ3 are deflected by lens 123 and focused before reaching dispersive element 124, where they are then recombined (multiplexed) to form a single output beam BO1_n. After passing through dispersive element 124, output beam BO1_n is redirected by lens 122 at an angle θ1.

[0049] The output beam BO1_n that has passed through the lens 122 travels along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, passes through the lens 121, and is then incident on the collimating lens LO1_n. The collimating lens LO1_n changes the direction of the output beam BO1_n so that it is parallel to the axis of symmetry Z1. The output beam BO1_n that has passed through the collimating lens LO1_n is emitted outside the WSS array 100 via the output fiber FO1_n.

[0050] Note that the present invention is not limited to the case where multiple wavelength channels are routed to a common output fiber, and multiple wavelength channels may be routed to different output fibers. For example, consider the case where the above-mentioned three wavelength channels λ1 to λ3 are routed to different output fibers FO1_1 to FO1_3, respectively. Wavelength channels λ1 to λ3 reflected by reflective liquid crystal element 130 are deflected by lens 123 and then redirected by dispersive element 124 to form fan-shaped output beams BO1_1 to BO1_3. After passing through dispersive element 124, the fan-shaped output beams BO1_1 to BO1_3 are redirected by lens 122 so that they are each tilted by angle θ.

[0051] After passing through lens 122, the parallel output beams BO1_1 to BO1_3 travel along the yz plane at an angle θ1 with respect to the axis of symmetry Z1. After passing through lens 121, they are incident on collimating lenses LO1_1 to LO1_3, respectively. The collimating lenses LO1_1 to LO1_3 redirect the output beams BO1_1 to BO1_3 so that they are parallel to the axis of symmetry Z1. After passing through collimating lenses LO1_1 to LO1_3, the output beams BO1_1 to BO1_3 are emitted outside the WSS array 100 via output fibers FO1_1 to FO1_3, respectively. That is, in the WSS device 100a, wavelength channels λ1 to λ3 are routed from input fiber FI1_1 to each of output fibers FO1_1 to FO1_3 via the reflective liquid crystal element 130.

[0052] As described above, any wavelength channel of a WDM signal in WSS device 100a can be routed to one or more of the multiple output fibers as needed. The same can be said for any wavelength channel of a WDM signal in WSS device 100b. That is, any wavelength channel of a WDM signal in WSS device 100b can be routed to one or more of the multiple output fibers as needed. This is because, in WSS array 100, optical system 120 and reflective liquid crystal element 130 are configured to be symmetrical about axis of symmetry Z1, and the wavelength channels dispersed in WSS device 100a and the wavelength channels dispersed in WSS device 100b are focused at different positions on reflective liquid crystal element 130.

[0053] 1 to 3, a case where one input port (input fiber) and n output ports (output fibers) are provided for each WSS device has been described, but this is not limited thereto, and any number of input ports and any number of output ports may be provided for each WSS device. Furthermore, some or all of the n output ports may be reconfigured as input ports, and one input port may be reconfigured as an output port. Furthermore, in the example of FIGS. 1 to 3, a case where the WSS array 100 is configured with two WSS devices 100a and 100b has been described, but this is not limited thereto, and the WSS array 100 may be configured with three or more WSS devices.

[0054] Next, the reflective liquid crystal element 130 applied to the WSS array 100 will be described in detail.

[0055] <Preliminary study of liquid crystal devices> First, a liquid crystal device 50 previously studied by the present inventor will be described. The liquid crystal device 50 can also be used as the reflective liquid crystal element 130 of the WSS array 100.

[0056] (Configuration of liquid crystal device 50 at the concept stage) FIG. 4 is a diagram showing an example of the configuration of an active matrix liquid crystal device 50 at the conceptual stage.

[0057] 4, the liquid crystal device 50 includes an image display unit 11, a timing generator 13, a polarity switching control circuit 14, a vertical shift register & level shifter 15, a horizontal driver 16, an analog switch unit 17, and AND circuits ADA1 to ADAn and ADB1 to ADBn. The horizontal driver 16, together with the analog switch unit 17, forms a data line driving circuit and includes a shift register circuit 161, a one-line latch circuit 162, a comparator unit 163, and a gradation counter 164. Note that FIG. 4 also shows a ramp signal generator 40 that is connected to the liquid crystal device 50 during normal operation.

[0058] 5 is an enlarged view of the horizontal driver 16 and the analog switch section 17 provided in the liquid crystal device 50. The comparator section 163 includes m comparators 163_1 to 163_m corresponding to m (m is an integer of 2 or more) columns of pixels 12. The analog switch section 17 includes m sets of switch elements SW1+, SW1- to SWm+, SWm- corresponding to m columns of pixels 12.

[0059] Wired in the pixel arrangement region of the image display unit 11 are n rows (n is an integer of 2 or more) of row scanning lines G1 to Gn and n rows of readout switch selection lines TG1 to TGn extending in the horizontal direction (I-axis direction), and m columns of data lines D1+, D1- to Dm+, Dm- extending in the vertical direction (J-axis direction). Also wired in the pixel arrangement region of the image display unit 11 are gate control signal lines S+, S- and gate control signal line B.

[0060] The image display unit 11 has a plurality of regularly arranged pixels 12. Here, the plurality of pixels 12 are arranged in a two-dimensional matrix at n×m intersections in total where n row scanning lines G1 to Gn extending in the horizontal direction (I-axis direction) intersect with m sets of data lines D1+, D1− to Dm+, Dm− extending in the vertical direction (J-axis direction).

[0061] The row scanning line Gj (j is any integer from 1 to n) and the read switch selection line TGj are commonly connected to each of the m pixels 12 arranged in the jth row. Furthermore, the data lines Di+, Di- (i is any integer from 1 to m) are commonly connected to each of the n pixels 12 arranged in the i-th column. Furthermore, the gate control signal lines S+, S- and the gate control signal line B are all commonly connected to all of the pixels 12. However, the gate control signal lines S+, S- and the gate control signal line B may each be provided individually for each row.

[0062] Based on the timing signal generated by the timing generator 13, the polarity switching control circuit 14 outputs a gate control signal for positive polarity (hereinafter referred to as gate control signal S+) to the gate control signal line S+, outputs a gate control signal for negative polarity (hereinafter referred to as gate control signal S-) to the gate control signal line S-, and further outputs a gate control signal (hereinafter referred to as gate control signal B) to the gate control signal line B.

[0063] The vertical shift register & level shifter 15 outputs scan pulses for n rows, one row at a time, from the first row to the nth row, in a cycle of one horizontal scan period HST. The AND circuits ADA1 to ADAn each control whether or not to output the n scan pulses sequentially outputted row by row from the vertical shift register & level shifter 15 to the row scan lines G1 to Gn, based on a mode switching signal MD supplied from the outside. The AND circuits ADB1 to ADBn each control whether or not to output the n scan pulses sequentially outputted row by row from the vertical shift register & level shifter 15 to the read switch selection lines TG1 to TGn, based on a mode switching signal MD supplied from the outside.

[0064] For example, in the case of an operation in which a video signal is written to the pixels 12 (image writing operation), an H-level mode switching signal MD is supplied from the outside. In this case, the AND circuits ADA1 to ADAn output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the row scanning lines G1 to Gn, respectively. On the other hand, the AND circuits ADB1 to ADBn do not output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the read switch selection lines TG1 to TGn, respectively. Therefore, all of the read switch selection lines TG1 to TGn are fixed to the L level.

[0065] On the other hand, in the case of an operation for reading out the video signals written to the pixels 12 (image readout operation), an L-level mode switching signal MD is supplied from the outside. In this case, the AND circuits ADB1 to ADBn output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the readout switch selection lines TG1 to TGn, respectively. On the other hand, the AND circuits ADA1 to ADAn do not output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the row scanning lines G1 to Gn, respectively. Therefore, all of the row scanning lines G1 to Gn are fixed to the L level.

[0066] (Specific configuration example of pixel 12) 6 is a diagram showing a specific configuration example of the pixel 12. Here, the pixel 12 provided in the j-th row and the i-th column of the pixels 12 arranged in n rows and m columns will be described.

[0067] As shown in FIG. 6, the pixel 12 has N-channel MOS transistors (hereinafter simply referred to as transistors) Tr1, Tr2, Tr5, Tr6, and Tr9, and P-channel MOS transistors (hereinafter simply referred to as transistors) Tr3, Tr4, Tr7, and Tr8.

[0068] The transistor Tr1 and the storage capacitor Cs1 constitute a sample-and-hold circuit that samples and holds a positive-polarity video signal supplied via the data line Di+. Specifically, the source of the transistor Tr1 is connected to one data line Di+ of the pair of data lines, the drain is connected to the gate of the transistor Tr3, and the gate is connected to the row scanning line Gj. The storage capacitor Cs1 is provided between the gate of the transistor Tr3 and the ground voltage terminal Vss.

[0069] The transistor Tr2 and the storage capacitor Cs2 form a sample-and-hold circuit that samples and holds a negative video signal supplied via the data line Di-. Specifically, the source of the transistor Tr2 is connected to the other data line Di- of the data line pair, the drain is connected to the gate of the transistor Tr4, and the gate is connected to the row scanning line Gj. The storage capacitor Cs2 is provided between the gate of the transistor Tr3 and the ground voltage terminal Vss. The storage capacitors Cs1 and Cs2 are provided independently of each other and store positive and negative video signals in parallel, respectively.

[0070] The transistors Tr3 and Tr7 form a source follower buffer (impedance conversion buffer) that outputs the voltage held in the holding capacitor Cs1. Specifically, the drain of the source follower transistor Tr3 is connected to the ground voltage line Vss, and the source is connected to the node Na. The transistor Tr7, which is used as a bias-controllable constant current load, has its source connected to the power supply voltage line Vdd, its drain connected to the node Na, and its gate connected to the gate control signal line B.

[0071] The transistors Tr4 and Tr8 form a source-follower buffer that outputs the voltage held in the holding capacitor Cs2. Specifically, the source-follower transistor Tr4 has its drain connected to the ground voltage line Vss and its source connected to node Nb. The transistor Tr8, used as a bias-controllable constant-current load, has its source connected to the power supply voltage line Vdd, its drain connected to node Nb, and its gate connected to the gate control signal line B.

[0072] Transistors Tr5 and Tr6 configure a polarity switch. Specifically, transistor Tr5 has a source connected to node Na, a drain connected to pixel drive electrode PE, and a gate connected to one gate control signal line S+ of the pair of gate control signal lines. Transistor Tr6 has a source connected to node Nb, a drain connected to pixel drive electrode PE, and a gate connected to the other gate control signal line S− of the pair of gate control signal lines.

[0073] The liquid crystal display element LC is composed of a pixel drive electrode (reflective electrode) PE that has light-reflecting properties, a common electrode CE that is optically transparent and arranged opposite the pixel drive electrode at a distance, and liquid crystal LCM that fills the space between them. A common voltage Vcom is applied to the common electrode CE. The transistor Tr9 is provided between the pixel drive electrode PE and the data line Di+ and is switched on and off by the read switch selection line TGj.

[0074] The pair of data lines Di+ and Di- are supplied with video signals of mutually opposite polarities sampled by the analog switch unit 17. When a scanning pulse output from the vertical shift register & level shifter 15 is supplied to the row scanning line Gj, the transistors Tr1 and Tr2 are simultaneously turned on. As a result, the voltages of the positive and negative video signals are accumulated and held in the storage capacitors Cs1 and Cs2, respectively.

[0075] The input resistance of each of the positive and negative source follower buffers is almost infinite, so the charge stored in each of the storage capacitors Cs1 and Cs2 is retained without leaking until one vertical scanning period has elapsed and a new video signal is written.

[0076] Transistors Tr5 and Tr6, which constitute the polarity switching switch, are switched on and off in response to gate control signals S+ and S-, alternately selecting the output voltage of the positive-side source follower buffer (positive-polarity video signal voltage) and the output voltage of the negative-side source follower buffer (negative-polarity video signal voltage) and outputting this to the pixel drive electrode PE. This causes a video signal voltage whose polarity periodically inverts to be applied to the pixel drive electrode PE. Because the pixels themselves have a polarity inversion function, this liquid crystal device enables high-frequency AC driving, regardless of the vertical scanning frequency, by quickly switching the polarity of the video signal voltage supplied to the pixel drive electrode PE in each pixel.

[0077] (Explanation of AC driving method for pixel 12) 7 is a timing chart for explaining a method of AC driving the pixels 12 by the liquid crystal device 50. Here, the AC driving method for the pixel 12 provided in the jth row and the ith column of the pixels 12 arranged in n rows and m columns will be explained.

[0078] In FIG. 7, VST represents a vertical synchronization signal that is the reference for vertical scanning of the video signal. B represents a gate control signal supplied to each gate of transistors Tr7 and Tr8 used as constant current loads for two types of source follower buffers. S+ represents a gate control signal supplied to the gate of transistor Tr5 on the positive side of the polarity changeover switch. S- represents a gate control signal supplied to the gate of transistor Tr6 on the negative side of the polarity changeover switch. VPE represents a voltage applied to the pixel drive electrode PE. Vcom represents a voltage applied to the common electrode CE. VLC represents an AC voltage applied to the liquid crystal LCM.

[0079] 8 is a diagram illustrating the voltage levels, from black to white, of the positive and negative video signals written to the pixel 12. In the example of FIG. 8, the positive video signal represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. In contrast, the negative video signal represents the white level when the voltage level is minimum and the black level when the voltage level is maximum. However, the positive video signal may represent the white level when the voltage level is minimum and the black level when the voltage level is maximum. Also, the negative video signal may represent the black level when the voltage level is minimum and the white level when the voltage level is maximum. The dashed dotted lines in the diagram indicate the inversion centers of the positive and negative video signals.

[0080] In pixel 12, transistor Tr9 remains off because the read switch selection line TGj is fixed at the L level. On the other hand, transistors Tr1 and Tr2 are temporarily turned on when a scan pulse is supplied to row scan line Gj. When transistors Tr1 and Tr2 are turned on, the voltages of the positive and negative video signals are accumulated and held in storage capacitors Cs1 and Cs2, respectively.

[0081] As shown in Figure 7, while the gate control signal S+ is at the H level, the positive-side transistor Tr5 is on. At this time, by setting the gate control signal B to the L level, transistor Tr7 is on, activating the positive-side source follower buffer. This charges the pixel drive electrode PE to the voltage level of the positive video signal. Setting the gate control signal B to the L level also turns on transistor Tr8, activating the negative-side source follower buffer. However, because the negative-side transistor Tr6 is off, the pixel drive electrode PE is not charged to the voltage level of the negative video signal. Once the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S+ is switched from the H level to the L level. This causes the pixel drive electrode PE to enter a floating state, maintaining a positive drive voltage across the liquid crystal capacitance.

[0082] Meanwhile, while the gate control signal S- is at the H level, the negative-side transistor Tr6 is turned on. At this time, by setting the gate control signal B to the L level, the negative-side transistor Tr8 is turned on, activating the negative-side source follower buffer. This charges the pixel drive electrode PE to the voltage level of the negative video signal. Setting the gate control signal B to the L level also turns on the transistor Tr7, activating the positive-side source follower buffer. However, because the positive-side transistor Tr5 is off, the pixel drive electrode PE is not charged to the voltage level of the positive video signal. Once the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S- is switched from the H level to the L level. This causes the pixel drive electrode PE to enter a floating state, maintaining a negative drive voltage across the liquid crystal capacitance.

[0083] By alternately repeating the above-mentioned positive and negative side operations, an AC driving voltage VPE is applied to the pixel driving electrode PE using the voltages of the positive and negative video signals.

[0084] In addition, the charges held in the storage capacitors Cs1 and Cs2 are not transferred directly to the pixel drive electrode PE but are transferred via a source follower buffer. Therefore, even when the pixel drive electrode PE is repeatedly charged and discharged with positive and negative video signal voltages, the charges are not neutralized and pixel drive without attenuation of the voltage level can be achieved.

[0085] 7, the voltage level of the voltage Vcom applied to the common electrode CE is switched to the opposite level to that of the applied voltage VPE in synchronization with the switching of the voltage level of the voltage VPE applied to the pixel drive electrode PE. Note that the voltage Vcom applied to the common electrode CE has an inversion reference voltage that is approximately equal to the inversion reference voltage of the voltage VPE applied to the pixel drive electrode PE.

[0086] Here, the substantial AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the voltage VPE applied to the pixel drive electrode PE and the voltage Vcom applied to the common electrode CE, and therefore an AC voltage VLC containing no DC component is applied to the liquid crystal LCM. In this way, by switching the voltage Vcom applied to the common electrode CE to be in opposite phase to the voltage VPE applied to the pixel drive electrode PE, the amplitude of the voltage to be applied to the pixel drive electrode PE can be reduced, thereby reducing the breakdown voltage and power consumption of the transistors that make up the pixel circuitry.

[0087] Even if the current steadily flowing through the source follower buffer per pixel is as small as 1 μA, the current steadily flowing through all pixels of the liquid crystal device may be large enough to be significant. For example, in a 2-megapixel liquid crystal device for full high-definition television, the current consumption may reach 2 A. Therefore, in pixel 12, transistors Tr7 and Tr8 used as constant current loads are not always on, but are only on for a limited period of time while the positive and negative transistors Tr5 and Tr6, respectively, are on. This allows the operation of one source follower buffer to be stopped while the other is operating, thereby suppressing an increase in current consumption.

[0088] The AC drive frequency of the liquid crystal display element LC can be freely adjusted by adjusting the pixel inversion control period, regardless of the vertical scanning frequency. For example, assume that the vertical scanning frequency is 60 Hz, the frequency used for general television video signals, and that the number of vertical scanning lines (n) in full high-definition television is 1,125 lines. Furthermore, assume that the polarity switching for each pixel occurs every 15 lines. In other words, assume that the number of lines (r) per polarity switching period for each pixel is 30 lines. In this case, the AC drive frequency of the liquid crystal is 60 Hz × 1,125 / (15 × 2) = 2.25 kHz. In other words, the liquid crystal device 50 can dramatically increase the AC drive frequency of the liquid crystal. This significantly improves the reliability, stability, and display quality of images displayed on the LCD screen, which were previously problematic when the AC drive frequency of the liquid crystal was low.

[0089] Next, the operation of the liquid crystal device 50 in each operation mode will be described.

[0090] (Operation of the liquid crystal device 50 in the image display mode) First, the operation of the liquid crystal device 50 in the image display mode (pixel writing mode) will be described with reference to Fig. 9. Fig. 9 is a timing chart showing the operation of the liquid crystal device 50 in the image display mode.

[0091] 9, when a pulse signal of the horizontal synchronization signal HST is supplied, the shift register circuit 161 sequentially captures m columns of video signals each having an N-bit width (N is an integer equal to or greater than 2) in synchronization with the clock signal HCK. The one-line latch circuit 162 simultaneously outputs the m columns of video signals captured by the shift register circuit 161 when the trigger signal REG_S temporarily becomes active.

[0092] The gradation counter 164 counts the number of rising edges of the clock signal CNT_CK and outputs a gradation signal Cout with a gradation level corresponding to the count value. Here, the gradation counter 164 outputs a gradation signal Cout with a minimum level at the start of one horizontal ramp period R (a transition period of the ramp signal within one horizontal scanning period) (at the rising edge of the horizontal synchronization signal HST), increases the gradation level of the gradation signal Cout as the count value increases, and outputs a gradation signal Cout with a maximum level at the end of one horizontal ramp period R (the time S before the next rising edge of the horizontal synchronization signal HST). The count value of the gradation counter 164 is initialized to "0" when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST, for example.

[0093] The m columns of comparators 163_1 to 163_m provided in the comparator section 163 operate in synchronization with the clock signal CMP_CK, and activate (for example, to L level) the match signals P1 to Pm at the timing when the gradation signal Cout output from the gradation counter 164 matches each of the m columns of video signals (line data) output simultaneously from the 1-line latch circuit 162.

[0094] Of the m sets of switch elements SW1+, SW1- to SWm+, and SWm- provided in the analog switch unit 17, the positive-side switch elements SW1+ to SWm+ are provided between the data lines D1+ to Dm+ and the common wiring Dcom+, respectively. Also, the negative-side switch elements SW1- to SWm- are provided between the data lines D1- to Dm- and the common wiring Dcom-, respectively. The m sets of switch elements SW1+, SW1- to SWm+, and SWm- are switched on and off by match signals P1 to Pm from the comparators 163_1 to 163_m, respectively.

[0095] The common wiring Dcom+ is supplied with a reference ramp voltage Ref_R+, which is a positive ramp signal output from the ramp signal generator 40. The common wiring Dcom- is supplied with a reference ramp voltage Ref_R-, which is a negative ramp signal output from the ramp signal generator 40.

[0096] The reference ramp voltage Ref_R+ is a sweep signal whose image level changes from black to white from the start to the end of each horizontal scanning period. The reference ramp voltage Ref_R- is a sweep signal whose image level changes from white to black from the start to the end of each horizontal scanning period. Therefore, the reference ramp voltage Ref_R+ relative to the common voltage Vcom and the reference ramp voltage Ref_R- relative to the common voltage Vcom are inversely related to each other.

[0097] The switch elements SW1+, SW1- to SWm+, and SWm- are simultaneously turned on when the start signal SW_Start becomes active (for example, H level) at the start of the horizontal ramp period R. Thereafter, the switch elements SW1+, SW1- to SWm+, and SWm- are switched from on to off when the match signals P1 to Pm output from the comparators 163_1 to 163_m become active (for example, L level). After the horizontal ramp period R ends, the start signal SW_Start becomes inactive (for example, L level).

[0098] In the example of FIG. 9, a waveform SPk indicates the timing of switching on and off the switch elements SWq+ and SWq- (q is an integer between 1 and m) provided corresponding to a pixel column to which a video signal of gradation level k is written. Referring to FIG. 9, the switch elements SWq+ and SWq- are turned on at the rising edge of the start signal SW_Start, and then switched from on to off when the match signal Pq becomes active. Here, the switch elements SWq+ and SWq- sample reference ramp voltages Ref_R+ and Ref_R- (voltages P and Q in FIG. 9) at the timing of switching from on to off. These sampled voltages P and Q are supplied to data lines Dq+ and Dq-. In other words, analog voltages P and Q, which are the results of DA conversion of the video signal of gradation level k, are supplied to the data lines Dq+ and Dq-, respectively.

[0099] In the image display mode, an H-level mode switching signal MD is externally supplied. Therefore, n-row scanning pulses, sequentially output row by row from the vertical shift register & level shifter 15, are supplied to the row scanning lines G1 to Gn, respectively. This temporarily turns on the transistors Tr1 and Tr2 provided in each pixel 12 in, for example, the j-th row. As a result, the voltages of the corresponding positive and negative video signals are accumulated and held in the storage capacitors Cs1 and Cs2 provided in each pixel 12 in the j-th row. Meanwhile, the transistor Tr9 provided in each pixel 12 remains in the off state. The subsequent AC driving method for each pixel 12 is as described above.

[0100] As described above, the switch elements SW1+, SW1- to SWm+, and SWm- are simultaneously turned on at the start of each horizontal scanning period, but are each turned off at an arbitrary timing according to the gradation level of the image to be displayed in the corresponding pixel 12. That is, the switch elements SW1+, SW1- to SWm+, and SWm- may all be turned off at the same time, or may be turned off at different times. The order in which they are turned off is also not fixed.

[0101] In this way, the liquid crystal device 50 can improve the linearity of the image by using the ramp signal to perform DA conversion on the video signal and then writing it to the pixel 12.

[0102] (Operation of the liquid crystal device 50 in pixel inspection mode) Next, an operation of the liquid crystal device 50 in a pixel inspection mode (pixel readout mode) will be described. In the pixel inspection mode, an inspection device (not shown) is provided instead of the ramp signal generator 40. Alternatively, in the pixel inspection mode, the ramp signal generator 40 functions as the inspection device.

[0103] In the pixel inspection mode, first, a video signal for inspection is written to the m pixels 12 in the jth row to be inspected. The operation at this time is basically the same as the operation in the pixel display mode. Then, the video signal (pixel drive voltage VPE) written to the m pixels 12 in the jth row to be inspected is read out.

[0104] During pixel readout, the externally supplied mode switching signal MD switches from H level to L level. Therefore, the scan pulse for the jth row output from the vertical shift register & level shifter 15 is supplied to the readout switch selection line TGj. This temporarily turns on the transistor Tr9 provided in each pixel 12 in the jth row being inspected. Meanwhile, the transistors Tr1 and Tr2 provided in each pixel 12 remain off.

[0105] For example, in pixel 12 located on the jth row and the ith column, transistor Tr9 is turned on, thereby bringing the pixel drive electrode PE and data line Di+ into a conductive state. At this time, by activating transistors Tr7 and Tr8 and turning on either transistor Tr5 or Tr6, the pixel drive electrode PE is driven by a source follower buffer consisting of transistors Tr3 and Tr7 or transistors Tr4 and Tr8. As a result, the drive voltage VPE applied to the pixel drive electrode PE by the source follower buffer is read out to the data line Di+.

[0106] The m pixel drive voltages VPE read out from the m pixels 12 in the jth row to the data lines D1+ to Dm+, respectively, are sequentially supplied to the common wiring Dcom+ by sequentially turning on m sets of SW1+, SW1- to SWm+, and SWm- provided in the analog switch unit 17. An inspection device (not shown) provided in place of the ramp signal generator 40 detects whether or not there are any failures (pixel defects and characteristic degradation) in the m pixels 12 in the jth row, based on the m pixel drive voltages VPE sequentially supplied via the common wiring Dcom+.

[0107] Such an inspection is performed row by row from the m pixels 12 in the first row to the m pixels 12 in the nth row.

[0108] Here, in the pixel 12 to be inspected, the voltage VPE of the pixel drive electrode PE driven by the source follower buffer with low output impedance is read out as is, so that defects and characteristic degradation of the pixel 12 to be inspected can be accurately and easily detected.

[0109] Incidentally, vertical line defects may occur in the liquid crystal device 50 due to breakdown caused by aging. Possible breakdowns caused by aging of the liquid crystal device 50 include, for example, wiring breakage, wiring shorts due to cracks in the insulating film, transistor shorts, gate insulating film breakdown, increased transistor leakage current due to crystal defects in the silicon substrate, and PN junction breakdown due to crystal defects in the silicon substrate. The liquid crystal device 50 is required to accurately detect breakdowns such as vertical line defects.

[0110] In particular, when the liquid crystal device 50 is used as a reflective liquid crystal element 130 of the WSS array 100, the liquid crystal device 50 is used as a component inside the WSS array 100, and therefore there is a problem that the effects of a failure are less likely to be output to the outside, i.e., it is more difficult to discover the failure, compared to, for example, when the liquid crystal device 50 is installed in a projector and the effects of a failure appear on a monitor.

[0111] Therefore, a liquid crystal device 1 and a method for detecting a failure thereof have been found that are capable of detecting a failure with high accuracy even when the device is mounted on a WSS array 100, for example.

[0112] <First Embodiment> 10 is a diagram showing an example of the configuration of the liquid crystal device 1 according to the first embodiment. The liquid crystal device 1 is also used as a reflective liquid crystal element 130 of the WSS array 100.

[0113] Compared to the liquid crystal device 50, the liquid crystal device 1 further includes a fault detection circuit 18. The fault detection circuit 18 is provided between the horizontal driver 16 and the analog switch section 17. The other configurations of the liquid crystal device 1 are the same as those of the liquid crystal device 50, and therefore, description thereof will be omitted.

[0114] 11 is an enlarged view of the horizontal driver 16, the analog switch section 17, and the fault detection circuit 18 provided in the liquid crystal device 1. As shown in Fig. 11, the fault detection circuit 18 performs fault detection on the comparison results (match signals) P1 to Pm of the comparators 163_1 to 163_m, and outputs a fault detection result TO.

[0115] (Specific Configuration Example of Failure Detection Circuit 18) Fig. 12 is a diagram showing a specific configuration example of the failure detection circuit 18. As shown in Fig. 12, the failure detection circuit 18 is a so-called dynamic shift register, and includes m inverters INV1_1 to INV1_m, m inverters INV2_1 to INV2_m, m switch elements SW5_1 to SW5_m, m switch elements SW6_1 to SW6_m, m switch elements SW7_1 to SW7_m, and an inverter INVO.

[0116] Between the ground voltage terminal Vss and the output terminal TO, inverters INV1_1 to INV1_m, switch elements SW5_1 to SW5_m, inverters INV2_1 to INV2_m, and switch elements SW6_1 to SW6_m are alternately arranged. Specifically, from the ground voltage terminal Vss to the output terminal TO, first, inverter INV1_1, switch element SW5_1, inverter INV2_1, and switch element SW6_1 are arranged, followed by inverter INV1_2, switch element SW5_2, inverter INV2_2, and switch element SW6_2. This arrangement is repeated, and finally, inverter INV1_m, switch element SW5_m, inverter INV2_m, and switch element SW6_m are arranged. Furthermore, inverter INVO is arranged in the subsequent stage of switch element SW6_m. Switch elements SW5_1 to SW5_m are switched on and off based on a clock signal HCK. The switch elements SW6_1 to SW6_m are switched on and off based on a clock signal HCKb, which is an inverted signal of the clock signal HCK. However, the clock signals HCK and HCKb are generated so that the on periods of the switch elements SW5_1 to SW5_m and the on periods of the switch elements SW6_1 to SW6_m do not overlap.

[0117] Switching elements SW7_1 to SW7_m are provided between input nodes of the inverters INV2_1 to INV2_m and output nodes (signal supply terminals) of the comparators 163_1 to 163_m. The switching elements SW7_1 to SW7_m are switched on and off based on a trigger signal REG_S.

[0118] When the trigger signal REG_S becomes active and the switch elements SW7_1 to SW7_m turn on, the fault detection circuit 18 simultaneously takes in the match signals P1 to Pm, and shifts the match signals P1 to Pm in order by switching on and off the switch elements SW5_1 to SW5_m and the switch elements SW6_1 to SW6_m in a complementary manner in synchronization with the clock signals CLK and CLKb, and outputs the match signals P1 to Pm as the fault detection result TO.

[0119] Here, the fault detection circuit 18 performs fault detection for the match signals P1 to Pm (signals for switching the analog switches SW1+, SW1- to SWm+, SWm- from on to off) output from the comparators 163_1 to 163_m by controlling the on / off of each switch element in the fault detection circuit 18 using a clock signal HCK supplied to the shift register circuit 161 and a trigger signal REG_S supplied to the one-line latch circuit 162. In other words, the fault detection circuit 18 can perform fault detection using existing control signals without preparing any special control signals.

[0120] (Failure detection method by failure detection circuit 18) Next, a failure detection method by the failure detection circuit 18 in the pixel writing mode of the liquid crystal device 1 will be described with reference to FIG.

[0121] 9, when a pulse signal of the horizontal synchronization signal HST is supplied, the shift register circuit 161 sequentially captures m columns of video signals each having an N-bit width (N is an integer equal to or greater than 2) in synchronization with the clock signal HCK. The one-line latch circuit 162 simultaneously outputs the m columns of video signals captured by the shift register circuit 161 when the trigger signal REG_S temporarily becomes active.

[0122] The gradation counter 164 counts the number of rising edges of the clock signal CNT_CK and outputs a gradation signal Cout with a gradation level corresponding to the count value. Here, the gradation counter 164 outputs a gradation signal Cout with a minimum level at the start of one horizontal ramp period R (a transition period of the ramp signal within one horizontal scanning period) (at the rising edge of the horizontal synchronization signal HST), increases the gradation level of the gradation signal Cout as the count value increases, and outputs a gradation signal Cout with a maximum level at the end of one horizontal ramp period R (the time S before the next rising edge of the horizontal synchronization signal HST). The count value of the gradation counter 164 is initialized to "0" when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST, for example.

[0123] The m columns of comparators 163_1 to 163_m provided in the comparator section 163 operate in synchronization with the clock signal CMP_CK, and activate (for example, to L level) the match signals P1 to Pm at the timing when the gradation signal Cout output from the gradation counter 164 matches each of the m columns of video signals (line data) output simultaneously from the 1-line latch circuit 162.

[0124] Of the m sets of switch elements SW1+, SW1- to SWm+, and SWm- provided in the analog switch unit 17, the positive-side switch elements SW1+ to SWm+ are provided between the data lines D1+ to Dm+ and the common wiring Dcom+, respectively. Also, the negative-side switch elements SW1- to SWm- are provided between the data lines D1- to Dm- and the common wiring Dcom-, respectively. The m sets of switch elements SW1+, SW1- to SWm+, and SWm- are switched on and off by match signals P1 to Pm from the comparators 163_1 to 163_m, respectively.

[0125] The common wiring Dcom+ is supplied with a reference ramp voltage Ref_R+, which is a positive ramp signal output from the ramp signal generator 40. The common wiring Dcom- is supplied with a reference ramp voltage Ref_R-, which is a negative ramp signal output from the ramp signal generator 40.

[0126] The reference ramp voltage Ref_R+ is a sweep signal whose image level changes from black to white from the start to the end of each horizontal scanning period. The reference ramp voltage Ref_R- is a sweep signal whose image level changes from white to black from the start to the end of each horizontal scanning period. Therefore, the reference ramp voltage Ref_R+ relative to the common voltage Vcom and the reference ramp voltage Ref_R- relative to the common voltage Vcom are inversely related to each other.

[0127] The switch elements SW1+, SW1- to SWm+, and SWm- are simultaneously turned on when the start signal SW_Start becomes active (for example, H level) at the start of the horizontal ramp period R. Thereafter, the switch elements SW1+, SW1- to SWm+, and SWm- are switched from on to off when the match signals P1 to Pm output from the comparators 163_1 to 163_m become active (for example, L level). After the horizontal ramp period R ends, the start signal SW_Start becomes inactive (for example, L level).

[0128] Here, under normal circumstances, the m sets of analog switches SW1+, SW1- to SWm+, SWm- provided in the analog switch unit 17 are always turned off when the match signals P1 to Pm from the comparators 163_1 to 163_m provided in the comparator unit 163 become active (for example, L level) between the start and end of the horizontal ramp period R. In other words, under normal circumstances, the m sets of analog switches SW1+, SW1- to SWm+, SWm- are always turned off by the end time S of the horizontal ramp period R.

[0129] For example, when the liquid crystal device 1 (more specifically, the horizontal driver 16) is operating normally, the match signals P1 to Pm all indicate an L level after the horizontal ramp period R has elapsed, and therefore the fault detection circuit 18 receives L level signals at all input nodes of the inverters INV2_1 to INV2_m in synchronization with the rising edge of the trigger signal REG_S after the horizontal ramp period R has elapsed, and then shifts them to continue outputting an L level fault detection result (hereinafter referred to as the fault detection result TO) indicating that no fault has occurred.

[0130] At the rising edge of the trigger signal REG_S, all of the inverters INV1_1 to INV1_m are controlled to be off, and all of the inverters INV2_1 to INV2_m are controlled to be on. After the falling edge of the trigger signal REG_S, the inverters INV1_1 to INV1_m and the inverters INV2_1 to INV2_m are repeatedly turned on and off in a complementary manner for m columns, and the potentials of the trigger signals P1 to Pm supplied to the input nodes of the inverters INV2_1 to INV2_m are output as fault detection results TO from the output terminals TO in order from the inverter closest to the output terminal TO. The output terminal TO is connected to, for example, a fault diagnosis monitor (not shown) provided outside the liquid crystal device 1 for monitoring the fault detection results.

[0131] In contrast, consider the case where a vertical line defect occurs in the liquid crystal device 1 (more specifically, the horizontal driver 16) due to a failure caused by aging. Possible failures caused by aging of the liquid crystal device 1 include, for example, a broken wire, a short circuit in the wire due to a crack in the insulating film, a short circuit in the transistor, destruction of the gate insulating film, an increase in transistor leakage current due to a crystal defect in the silicon substrate, and destruction of a PN junction due to a crystal defect in the silicon substrate. When such a failure occurs, one of the comparators 163_1 to 163_m may be unable to detect a match between the grayscale signal Cout output from the grayscale counter 164 and the video signal output from the one-line latch circuit 162. In other words, when such a failure occurs, one of the comparators 163_1 to 163_m may be unable to transition the match signal, which has been at an H level when the start signal SW_Start becomes active, to an L level before the horizontal ramp period R has elapsed. In this case, the fault detection circuit 18 receives the above-mentioned H-level match signal at the input node of one of the inverters INV2_1 to INV2_m in synchronization with the rising edge of the trigger signal REG_S after the horizontal ramp period R has elapsed, and then shifts the signals to output a fault detection result TO including an H-level pulse waveform indicating the occurrence of a fault. A fault diagnosis monitor (not shown) provided outside the liquid crystal device 1 can identify the faulty pixel column from the output timing of the H-level pulse waveform included in the fault detection result TO. When the fault detection circuit 18 detects a fault in the liquid crystal device 1, repair measures such as replacing the faulty liquid crystal device with a good one become possible.

[0132] The fault detection result TO output from the fault detection circuit 18 corresponds to the match signals P1 to Pm (signals for switching the analog switches SW1+, SW1- to SWm+, SWm- from on to off) output from the comparators 163_1 to 163_m immediately after the horizontal ramp period R of one cycle ago has elapsed.

[0133] In this way, in the liquid crystal device 1 according to the present disclosure, the fault detection circuit 18 can detect faults such as vertical line defects caused by aging using existing control signals without using dedicated control signals. Furthermore, the liquid crystal device 1 according to the present disclosure is not limited to applications in projectors in which the effects of faults such as vertical line defects appear on the monitor, but even when used as the reflective liquid crystal element 130 of the WSS array 100, the fault detection result TO indicating whether or not a fault such as vertical line defects caused by aging has occurred can be output to the outside, allowing the user to be made aware of the fault in the liquid crystal device 1 using, for example, a fault diagnosis monitor.

[0134] <Embodiment 2> 13 is a diagram showing a configuration example of a portion of a liquid crystal device 2 according to embodiment 2. Compared to the liquid crystal device 1, the liquid crystal device 2 includes a horizontal driver 26, an analog switch section 27, and a failure detection circuit 28 instead of the horizontal driver 16, the analog switch section 17, and the failure detection circuit 18, and further includes an OR circuit 29. Compared to the horizontal driver 16, the horizontal driver 26 includes a shift register circuit 261, a one-line latch circuit 262, a comparator section 263, and a gradation counter 264 instead of the shift register circuit 161, the one-line latch circuit 162, the comparator section 163, and the gradation counter 164.

[0135] The shift register circuit 261 is configured with a plurality of shift register circuits corresponding to a plurality of video signals input in parallel. In the example of Fig. 13, the shift register circuit 261 is configured with four shift register circuits 261_1 to 261_4 corresponding to four video signals input in parallel.

[0136] The one-line latch circuit 262 simultaneously outputs the video signals corresponding to the number of pixel columns captured in the shift register circuits 261_1 to 261_4 at the timing when the trigger signal REG_S temporarily becomes active.

[0137] The comparators provided in the comparator unit 263, each equal to the number of pixel columns, operate in synchronization with the clock signal CMP_CK, and activate a match signal (for example, to L level) at the timing when the gradation signal Cout output from the gradation counter 264 matches each of the video signals (line data) for the number of pixel columns output simultaneously from the one line latch circuit 262.

[0138] A set of switch elements provided in the analog switch unit 27, the number of which corresponds to the number of pixel columns, is turned on all at once when the start signal SW_Start becomes active (e.g., H level) at the start of the horizontal ramp period R, and is switched from on to off when the match signals output from the comparators provided in the comparator unit 263, the number of which corresponds to the number of pixel columns, become active (e.g., L level). After the horizontal ramp period R ends, the start signal SW_Start becomes inactive (e.g., L level).

[0139] The failure detection circuit 28 is made up of 44 failure detection circuits (partial failure detection circuits) 28_1 to 28_4 corresponding to the four shift register circuits 261_1 to 261_4.

[0140] The failure detection circuit 28_1 performs failure detection on the match signal output from the comparator unit 263 when the video signal output from the shift register circuit 261_1 and passed through the one-line latch circuit 262 matches the gradation signal Cout output from the gradation counter 264, and outputs a failure detection result T1. The failure detection circuit 28_2 performs failure detection on the match signal output from the comparator unit 263 when the video signal output from the shift register circuit 261_2 and passed through the one-line latch circuit 262 matches the gradation signal Cout output from the gradation counter 264, and outputs a failure detection result T2. The failure detection circuit 28_3 performs failure detection on the match signal output from the comparator unit 263 when the video signal output from the shift register circuit 261_3 and passed through the one-line latch circuit 262 matches the gradation signal Cout output from the gradation counter 264, and outputs a failure detection result T3. The fault detection circuit 28_4 performs fault detection on the match signal output from the comparator section 263 when the video signal output from the shift register circuit 261_4 and passed through the one-line latch circuit 262 matches the gradation signal Cout output from the gradation counter 264, and outputs a fault detection result T4. Then, the OR circuit 29 outputs the logical sum of the fault detection results T1 to T4 to the outside of the liquid crystal device 2 as a fault detection result TO.

[0141] 14 is a timing chart showing an example of a fault detection method by the fault detection circuit 28 of the liquid crystal device 2. As shown in FIG. 14, for example, when the shift register circuit 261_3 is faulty, the fault detection circuit 28_3 outputs a fault detection result T3 including an H-level pulse waveform formed at a timing corresponding to the corresponding pixel column. In addition, the OR circuit 29 outputs a fault detection result TO similar to the fault detection result T3.

[0142] The other configurations and operations of the liquid crystal device 2 are the same as those of the liquid crystal device 1, and therefore the description thereof will be omitted. The liquid crystal device 2 can also achieve effects similar to those of the liquid crystal device 1.

[0143] The present disclosure is not limited to the above-described embodiment, and can be modified as appropriate within the scope of the present disclosure. [Explanation of symbols]

[0144] 1 Liquid crystal devices 11 Image display section 12 pixels 13 Timing Generator 14 Polarity switching control circuit 15 Vertical shift register & level shifter 16 Horizontal Driver 17 Analog switch section 18 Fault detection circuit 26 Horizontal driver 27 Analog switch section 28 Fault detection circuit 28_1~28_4 Fault detection circuit 29 OR Circuit 40 Ramp Signal Generator 50 Liquid Crystal Devices 100 WSS Array 100a WSS device 100b WSS device 110 Input section 120 Optical system 121 Lens 122 Lens 123 Lens 124 Dispersion element 130 Reflective liquid crystal element 161 Shift register circuit 162 1-line latch circuit 163 Comparator section 163_1~163_m Comparator 164 Gradation Counter 261 Shift Register Circuit 261_1~261_4 Shift register circuit 262 1-line latch circuit 263 Comparator section 264 Gradation Counter ADA1~ADAn AND circuit ADB1~ADBn AND circuit B Gate control signal line BF1 buffer CE common electrode Cs1,Cs2 retention capacity D1+,D1-~Dm+,Dm- data lines Dcom+, Dcom- common wiring FI1 Input Fiber (Input Port) FI2 Input Fiber (Input Port) FO1_1~FO1_n Output fibers (output ports) FO2_1~FO2_n Output fibers (output ports) G1~Gn row scanning line INV1_1~INV1_m inverters INV2_1~INV2_m inverters INV3 inverter LC liquid crystal display element LCM LCD LI1 Collimating Lens LI2 Collimating Lens LO1_1~LO1_n Collimating lenses LO2_1~LO2_n Collimating lenses N1,N2 nodes Na,Nb nodes Nd1_1~Nd1_m nodes Nd2_1~Nd2_m nodes PE Pixel driving electrode (reflective electrode) S+, S- Gate control signal lines SA_1~SA_m Sense amplifier SW1+, SW1- to SWm+, SWm- Switch elements SW2_1~SW2_m Switch elements SW3_1~SW3_m Switch elements SW4_1~SW4_m Switch elements SW5_1~SW5_m Switch elements SW6_1~SW6_m Switch elements SW7_1~SW7_m Switch elements SW8_1~SW8_m Switch elements TG1~TGn Readout switch selection lines Tr1 to Tr10 transistors Tr11~Tr17 transistors Tr21~Tr25 transistors

Claims

1. A plurality of pixels; a plurality of data lines provided corresponding to each column of the plurality of pixels; a shift register unit that sequentially captures video signals corresponding to the number of columns of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a grayscale signal whose potential changes monotonically, and activate a corresponding match signal when the signals match; an analog switch unit that supplies a plurality of analog voltages to the plurality of data lines in accordance with the timings at which the match signals of the plurality of comparators become active; a fault detection circuit that receives the coincidence signals from the plurality of comparators in synchronization with the trigger signal, and shifts the received coincidence signals in synchronization with the clock signal and outputs the shifted signals as fault detection results; A liquid crystal device comprising:

2. The fault detection circuit is a dynamic shift register.

10. The liquid crystal device according to claim 1.

3. The fault detection circuit a plurality of first inverters provided on the signal path, the number of which corresponds to the number of columns of pixels; a plurality of first switch elements provided on the signal path at a subsequent stage of each of the plurality of first inverters, the number of which corresponds to the number of columns of pixels whose on / off states are switched by the clock signal; a plurality of second inverters, the number of which corresponds to the number of columns of pixels, provided on the signal path at a subsequent stage of each of the plurality of first switch elements; a plurality of second switch elements, the number of which corresponds to the number of columns of pixels, that are provided on the signal path at a subsequent stage of each of the plurality of second inverters and that are switched on and off by an inverted signal of the clock signal; a plurality of third switch elements that are provided between input nodes of the plurality of second inverters and a plurality of signal supply terminals to which the respective coincidence signals of the plurality of comparators are supplied, and that are switched on and off by the trigger signal; At least outputting the fault detection result corresponding to the output signal of a second switch element at a final stage among the plurality of second switch elements; 10. The liquid crystal device according to claim 1.

4. The shift register unit a plurality of shift register circuits for sequentially capturing the plurality of video signals input in parallel in synchronization with the clock signal; The fault detection circuit a plurality of partial failure detection circuits that respectively receive a plurality of coincidence signals corresponding to the plurality of video signals received by the plurality of shift register circuits, and shift the received coincidence signals in synchronization with the clock signal and output the shifted signals as failure detection results; 10. The liquid crystal device according to claim 1.

5. An input port; one or more output ports; a reflective liquid crystal element, which is the liquid crystal device according to any one of claims 1 to 4, having a plurality of pixels that deflect an optical signal that is incident on the input port and outputs the deflected optical signal from any one of the one or more output ports; A wavelength selective switch device comprising:

6. A plurality of pixels; a plurality of data lines provided corresponding to each column of the plurality of pixels; a shift register unit that sequentially captures video signals corresponding to the number of columns of the plurality of pixels in synchronization with a clock signal; a latch unit that simultaneously outputs the plurality of video signals captured by the shift register unit in synchronization with a trigger signal; a plurality of comparators that compare each of the plurality of video signals output from the latch unit with a grayscale signal whose potential changes monotonically, and activate a corresponding match signal when the signals match; an analog switch unit that supplies a plurality of analog voltages to the plurality of data lines in accordance with the timings at which the match signals of the plurality of comparators become active; a fault detection circuit; A method for detecting a fault in a liquid crystal device, comprising: In the failure detection circuit, the coincidence signals of the plurality of comparators are acquired in synchronization with the trigger signal; the fault detection circuit shifts the acquired plurality of coincidence signals in synchronization with the clock signal and outputs the shifted signals as fault detection results; Fault detection methods.

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