Driving circuit

Abstract

To provide a novel semiconductor device.SOLUTION: A first terminal of a first transistor is connected to a first terminal of a second transistor and a first wire. A gate of the first transistor is connected to a first terminal of a fourth transistor and a first terminal of a fifth transistor. A second terminal of the fifth transistor is connected to a gate of the fifth transistor, a first terminal of a third transistor, and a first terminal of a first capacitor element. Each of a second terminal of the third transistor and a second terminal of the fourth transistor is connected to a second wire. A second terminal of the first transistor is connected to a third wire. A second terminal of the second transistor is connected to a fourth wire. Each of a gate of the third transistor and a gate of the fourth transistor is connected to a fifth wire. A second terminal of the first capacitor element is connected to a sixth wire.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a drive circuit.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, systems including these devices, driving methods thereof, or manufacturing methods thereof. [Background technology]

[0003] Display devices are used in a variety of applications. Examples of applications for large display devices include home televisions and public information displays (PIDs) for digital signage. Examples of applications for small display devices include mobile information terminals such as smartphones and tablet devices, and wearable devices such as devices for virtual reality (VR) and augmented reality (AR). Furthermore, by adding functions other than display to display devices, efforts are being made to improve the functionality and add value of display devices. For example, display devices with touch panel functions have been developed.

[0004] Furthermore, circuits for driving display devices have been developed. Patent Document 1 discloses an example of a drive circuit that can be used for a display device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-211088 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a highly reliable driver circuit or a semiconductor device including the driver circuit. Another object of one embodiment of the present invention is to provide a driver circuit with high operational stability or a semiconductor device including the driver circuit. Another object of one embodiment of the present invention is to provide a driver circuit with increased operating speed or a semiconductor device including the driver circuit. Another object of one embodiment of the present invention is to provide a driver circuit with a reduced occupation area or a semiconductor device including the driver circuit. Another object of one embodiment of the present invention is to provide a driver circuit with reduced power consumption or a semiconductor device including the driver circuit. Another object of one embodiment of the present invention is to provide a driver circuit that can improve the performance of a display device or a semiconductor device including the driver circuit. Another object of one embodiment of the present invention is to provide a novel driver circuit or a semiconductor device including the driver circuit.

[0007] The above-mentioned problem does not preclude the existence of other problems. A person skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and can extract other problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems). [Means for solving the problem]

[0008] (1) One embodiment of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor, in which a first terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first wiring, a gate of the first transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the fifth transistor, a second terminal of the fifth transistor is electrically connected to a gate of the fifth transistor, a first terminal of the third transistor, and a first terminal of the first capacitor, and a second terminal of the first transistor electrically connected to a third wiring; a second terminal of the second transistor electrically connected to a fourth wiring; a gate of the third transistor electrically connected to a fifth wiring; a second terminal of the first capacitance element electrically connected to a sixth wiring; the fifth wiring having a function of transmitting a first clock signal; and the sixth wiring having a function of transmitting a second clock signal having a phase different from that of the first clock signal.

[0009] (2) Furthermore, in the above (1), the semiconductor device may have a first circuit, the first circuit having a first terminal and a second terminal, the first terminal of the first circuit being electrically connected to the first terminal of the third transistor, the second terminal of the first circuit being electrically connected to the gate of the second transistor, the fourth wiring having a function of transmitting a first potential, the third wiring having a function of transmitting a second potential greater than the first potential, and the first circuit having a function of outputting the first potential to the first terminal of the first circuit in accordance with a first clock signal and a second clock signal, a function of making the first terminal of the first circuit high impedance, a function of outputting the first potential to the second terminal of the first circuit, and a function of outputting the second potential to the second terminal of the first circuit.

[0010] (3) In addition, in the above (1), the present invention includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein a gate of the sixth transistor is electrically connected to a first terminal of the ninth transistor, a first terminal of the tenth transistor, and a gate of the eleventh transistor, a first terminal of the sixth transistor is electrically connected to a first terminal of the seventh transistor, a second terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor and a gate of the second transistor, a first terminal of the eleventh transistor is electrically connected to a first terminal of the twelfth transistor, and a second terminal of the eleventh transistor is electrically connected to a third transistor. The gate of the eighth transistor and the gate of the tenth transistor may each be electrically connected to the first terminal of the fourth transistor, the second terminal of the sixth transistor may be electrically connected to the sixth wiring, the gate of the seventh transistor may be electrically connected to the sixth wiring, the second terminal of the eighth transistor may be electrically connected to the fourth wiring, the second terminal of the ninth transistor may be electrically connected to the third wiring, the gate of the ninth transistor may be electrically connected to the fifth wiring, the second terminal of the tenth transistor may be electrically connected to the fifth wiring, the second terminal of the twelfth transistor may be electrically connected to the fourth wiring, and the gate of the twelfth transistor may be electrically connected to the sixth wiring.

[0011] (4) In any one of the above (1) to (3), the channel width of the first transistor may be larger than the channel width of the fifth transistor. [Effects of the Invention]

[0012] According to one embodiment of the present invention, a highly reliable driver circuit or a semiconductor device including the driver circuit can be provided. According to another embodiment of the present invention, a driver circuit with high operational stability or a semiconductor device including the driver circuit can be provided. According to another embodiment of the present invention, a driver circuit with increased operating speed or a semiconductor device including the driver circuit can be provided. According to another embodiment of the present invention, a driver circuit with a reduced occupation area or a semiconductor device including the driver circuit can be provided. According to another embodiment of the present invention, a driver circuit with reduced power consumption or a semiconductor device including the driver circuit can be provided. According to another embodiment of the present invention, a driver circuit that can improve the performance of a display device or a semiconductor device including the driver circuit can be provided. According to another embodiment of the present invention, a novel driver circuit or a semiconductor device including the driver circuit can be provided.

[0013] It should be noted that the above-described effects do not preclude the existence of other effects. A person skilled in the art can naturally derive other effects from the description in this specification, drawings, claims, etc., and can extract other effects from the description in this specification, drawings, claims, etc. It should be noted that one embodiment of the present invention does not necessarily have all of these effects (the above-described effects and other effects). [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 2] FIG. 2 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 3] FIG. 3 is a timing chart illustrating an example of the operation of the drive circuit. [Figure 4] FIG. 4 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 5] FIG. 5 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 6] FIG. 6 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 7]FIG. 7 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 8] FIG. 8 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 9] FIG. 9 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 10] FIG. 10 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 11] FIG. 11 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 12] FIG. 12 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 13] FIG. 13 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 14] FIG. 14 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 15] FIG. 15 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 16] FIG. 16 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 17] FIG. 17 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 18] FIG. 18 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 19] FIG. 19 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 20] FIG. 20 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 21] FIG. 21 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 22] FIG. 22 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 23] FIG. 23 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 24] FIG. 24 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 25] FIG. 25 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 26] FIG. 26 is a timing chart illustrating an example of the operation of the drive circuit. [Figure 27] FIG. 27 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 28] FIG. 28 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 29] FIG. 29 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 30] FIG. 30 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 31] FIG. 31 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 32] FIG. 32 is a circuit diagram illustrating an example of the operation of the drive circuit. [Figure 33] FIG. 33 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 34] FIG. 34 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 35] FIG. 35 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 36] FIG. 36 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 37] FIG. 37 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 38] FIG. 38 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 39] FIG. 39 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 40] FIG. 40 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 41] FIG. 41 is a circuit diagram illustrating an example of the configuration of a drive circuit. [Figure 42] 42A and 42B are block diagrams illustrating configuration examples of a semiconductor device. [Figure 43] 43A to 43C are circuit diagrams illustrating configuration examples of semiconductor devices. [Figure 44] 44A is a top view illustrating a structural example of a transistor, and FIGS. 44B and 44C are cross-sectional views illustrating a structural example of a transistor. [Figure 45] 45A is a top view illustrating a structural example of a transistor, and FIGS. 45B and 45C are cross-sectional views illustrating a structural example of a transistor. [Figure 46] 46A is a top view illustrating a structural example of a transistor, and FIG. 46B is a cross-sectional view illustrating a structural example of a transistor. [Figure 47] 47A is a top view illustrating a structural example of a transistor, and FIGS. 47B and 47C are cross-sectional views illustrating a structural example of a transistor. [Figure 48] 48A is a top view illustrating a structural example of a transistor, and FIGS. 48B and 48C are cross-sectional views illustrating a structural example of a transistor. [Figure 49] 49(A) to 49(D) are cross-sectional views illustrating an example of a method for forming a metal oxide film. [Figure 50] 50(A) to 50(D) are cross-sectional views illustrating an example of a method for forming a metal oxide film. [Figure 51] FIG. 51 is a top view illustrating a configuration example of a semiconductor device. [Figure 52] FIG. 52 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 53] 53A to 53D are top views illustrating structural examples of semiconductor devices. [Figure 54] Fig. 54(A) is a perspective view illustrating a configuration example of a display device, and Fig. 54(B) to Fig. 54(F) are top views illustrating an example of a pixel arrangement. [Figure 55] FIG. 55 is a cross-sectional view illustrating an example of the configuration of a display device. [Figure 56] 56(A) and 56(B) are cross-sectional views illustrating a configuration example of a display device. [Figure 57] 57(A) and 57(B) are cross-sectional views illustrating a configuration example of a display device. [Figure 58] FIG. 58 is a perspective view illustrating an example of the configuration of a display device. [Figure 59]FIG. 59 is a cross-sectional view illustrating an example of the configuration of a display device. [Figure 60] 60(A) to 60(D) are diagrams showing examples of electronic devices. [Figure 61] 61(A) to 61(F) are diagrams showing examples of electronic devices. [Figure 62] 62(A) to 62(G) are diagrams showing examples of electronic devices. [Figure 63] 63(A1) to 63(A7) and 63(B1) to 63(B6) are diagrams for explaining electrical connections. DETAILED DESCRIPTION OF THE INVENTION

[0015] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. Examples of semiconductor devices include an electronic circuit including a semiconductor element, a chip equipped with an electronic circuit, an electronic component in which a chip is housed in a package, and an electronic device equipped with an electronic component. Furthermore, for example, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, and electronic devices may themselves be semiconductor devices and may also include semiconductor devices.

[0016] The following description of the embodiments will be given with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it will be readily understood by those skilled in the art that various changes can be made to the embodiments and their details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0017] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0018] In the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated explanations. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, for ease of understanding, the drawings may omit the illustration of some components, for example, in perspective views or top views (also called "plan views"). Furthermore, the drawings may omit the illustration of some hidden lines. Furthermore, the drawings may omit the illustration of, for example, hatching patterns.

[0019] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations to facilitate understanding of the present invention and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching. However, these may not be reflected in the drawings to facilitate understanding. Furthermore, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors. However, these may not be reflected in the drawings to facilitate understanding.

[0020] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0021] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m,n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0022] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cutoff state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cutoff state," or "off state."

[0023] In this specification and the like, the voltage between the gate and the source (gate-source) (based on the source potential unless otherwise specified) is sometimes referred to as the "gate voltage," the voltage between the drain and the source (drain-source) (based on the source potential unless otherwise specified) is sometimes referred to as the "drain voltage," and the voltage between the backgate and the source (backgate-source) (based on the source potential unless otherwise specified) is sometimes referred to as the "backgate voltage." Furthermore, the current flowing between the drain and the source (positive in the direction from the drain to the source unless otherwise specified) is sometimes referred to as the "drain current." Note that, in an n-channel transistor, terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" can be interchanged with terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" in a p-channel transistor, as appropriate. Furthermore, in an n-channel transistor, the terms "low gate voltage," "low drain voltage," and "low back gate voltage" can be interchanged with the terms "high gate voltage," "high drain voltage," and "high back gate voltage" in a p-channel transistor, as appropriate.

[0024] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source / drain (also referred to as gate leakage current) may be collectively referred to as leakage current.

[0025] In this specification and the like, one of the source or drain (also referred to as two input / output terminals) of a transistor may be referred to as a first terminal, and the other of the source or drain of the transistor may be referred to as a second terminal. That is, a transistor has at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. One terminal of a capacitor (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other terminal of the capacitor (also referred to as the other of the pair of terminals) may be referred to as a second terminal. One terminal of a display element may be referred to as a first terminal, and the other terminal of the display element may be referred to as a second terminal. One terminal of a liquid crystal element may be referred to as a first terminal, and the other terminal of the liquid crystal element may be referred to as a second terminal. One terminal of a light-emitting element may be referred to as a first terminal, and the other terminal of the light-emitting element may be referred to as a second terminal. One terminal of a light-receiving element may be referred to as a first terminal, and the other terminal of the light-receiving element may be referred to as a second terminal. In addition, one of the anode or cathode of the diode (also referred to as one of the pair of terminals) may be referred to as a first terminal, and the other of the anode or cathode of the diode (also referred to as the other of the pair of terminals) may be referred to as a second terminal.

[0026] (Embodiment 1) A driver circuit according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the driver circuit according to one embodiment of the present invention can be used in a semiconductor device such as a display device.

[0027] <Driver circuit configuration example> 1 and 2 are circuit diagrams illustrating a driver circuit of one embodiment of the present invention.

[0028] As shown in FIG. 1, the drive circuit 100 includes a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, and a capacitive element C11.

[0029] One of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M12 and the wiring OUTL. The gate of the transistor M11 is connected to one of the source or drain of the transistor M14 and one of the source or drain of the transistor M15. The other of the source or drain of the transistor M15 is connected to the gate of the transistor M15, one of the source or drain of the transistor M13, and one terminal of the capacitor C11. The other of the source or drain of the transistor M13 and the other of the source or drain of the transistor M14 are connected to the wiring SPL. The other of the source or drain of the transistor M11 is connected to the wiring VL1. The other of the source or drain of the transistor M12 is connected to the wiring VL2. The gate of the transistor M13 and the gate of the transistor M14 are connected to the wiring CKL1. The other terminal of the capacitor C11 is connected to the wiring CKL2.

[0030] A wiring connected to the other of the source or drain of the transistor M15 and one terminal of the capacitor C11 may be referred to as a node NDA. A wiring connected to the other of the source or drain of the transistor M15 and the gate of the transistor M11 may be referred to as a node NDB. A wiring connected to the gate of the transistor M12 may be referred to as a node NDC. Note that the terms "node" and "wiring" may be interchangeable.

[0031] In the driver circuit 100, each transistor (such as transistors M11 to M15) is an n-channel transistor or a p-channel transistor. Here, the description will be given assuming that each transistor is an n-channel transistor. An n-channel transistor has a larger on-state current than a p-channel transistor. Therefore, by using n-channel transistors, the operating speed of the driver circuit 100 can be improved. Furthermore, an n-channel transistor requires a smaller channel width to obtain the same level of on-state current than a p-channel transistor. Therefore, by using n-channel transistors, the area occupied by the driver circuit 100 can be reduced.

[0032] When a p-channel transistor is used for each transistor, the following description may appropriately interpret descriptions regarding the positive / negative relationship of voltage and the magnitude relationship of potential. For example, "high potential" may be appropriately interpreted as "low potential" and "low potential" may be appropriately interpreted as "high potential." Furthermore, for example, "increase potential" may be appropriately interpreted as "decrease potential" and "decrease potential" may be appropriately interpreted as "increase potential."

[0033] The wiring CKL1 has a function of transmitting, for example, a first clock signal. The wiring CKL2 has a function of transmitting, for example, a second clock signal whose phase is different from that of the first clock signal. Alternatively, the wiring CKL2 has a function of transmitting, for example, a second clock signal whose potential changes at a timing different from that of the first clock signal. Alternatively, the wiring CKL2 has a function of transmitting, for example, a second clock signal whose rising timing is different from that of the first clock signal. Alternatively, the wiring CKL2 has a function of transmitting, for example, a second clock signal whose falling timing is different from that of the first clock signal. The wiring VL1 has a function of transmitting, for example, a potential H. The wiring VL2 has a function of transmitting, for example, a potential L that is smaller than the potential H. In this case, the difference between the potential H and the potential L is preferably larger than the threshold voltage of a transistor included in the driver circuit 100. The wiring SPL has a function of transmitting, for example, a trigger signal. The wiring OUTL has a function of transmitting, for example, an output signal.

[0034] Here, the wiring CKL1 can be said to have a function of transmitting a first clock signal provided from a circuit provided outside the driver circuit 100 to the gate of the transistor M13 and the gate of the transistor M14, respectively. The wiring CKL2 can be said to have a function of transmitting a second clock signal provided from a circuit provided outside the driver circuit 100 to the other terminal of the capacitor C11, for example. The wiring VL1 can be said to have a function of transmitting a potential H provided from a circuit provided outside the driver circuit 100 to the other of the source and drain of the transistor M11, for example. The wiring VL2 can be said to have a function of transmitting a potential L provided from a circuit provided outside the driver circuit 100 to the other of the source and drain of the transistor M12, for example. The wiring SPL can also be said to have a function of transmitting, for example, a trigger signal (sometimes referred to as a start pulse signal) provided from a circuit provided outside the drive circuit 100 or an output signal provided to a wiring OUTL of another drive circuit 100 to the other of the source or the drain of the transistor M13 and the other of the source or the drain of the transistor M14. In addition, the wiring OUTL can also be said to have a function of transmitting, for example, an output signal provided from the drive circuit 100 to a pixel provided outside the drive circuit 100.

[0035] Note that, for example, either the potential H or the potential L is applied to the gate of the transistor M12 (corresponding to the node NDC).

[0036] In the driver circuit 100, the potential of the wiring VL1 is supplied to the wiring OUTL through the transistor M11 in accordance with signals supplied to the wirings CKL1, CKL2, and SPL and the potential of the node NDC. The potential of the wiring VL2 is supplied to the wiring OUTL through the transistor M12.

[0037] Here, for example, when the driver circuit 100 is used in a display device, a pixel is connected to the wiring OUTL. Therefore, the on-state current of each of the transistors M11 and M12 is preferably larger than the on-state current of each of the transistors M13 to M15. Increasing the on-state current of each of the transistors M11 and M12 can shorten the time required to change the potential of the wiring OUTL (i.e., the rise time and fall time), thereby improving the operation speed of the driver circuit and achieving a high-speed display device. To achieve this, for example, by making the channel widths of each of the transistors M11 and M12 larger than the channel widths of each of the transistors M13 to M15, the on-state current can be increased, thereby achieving a high-speed display device. Furthermore, for example, by making the channel lengths of each of the transistors M11 and M12 smaller than the channel lengths of each of the transistors M13 to M15, the on-state current can be increased, thereby achieving a high-speed display device.

[0038] As will be described in detail later, during operation of the driver circuit 100, when the potential of the wiring OUTL rises, the gate voltage (voltage between the gate and source) of the transistor M11 gradually decreases. Therefore, to increase the on-state current of the transistor M11, for example, the channel width of the transistor M11 may be made larger than the channel width of the transistor M12. Furthermore, the channel length of the transistor M11 may be made larger than the channel length of the transistor M12.

[0039] 2, the driving circuit 100 may further include a circuit 110. The circuit 110 includes a terminal OTA and a terminal OTB. The terminal OTA is connected to one of the source and drain of the transistor M13. The terminal OTB is connected to the gate of the transistor M12.

[0040] The circuit 110 has at least the functions of outputting a first potential to the terminal OTA, setting the terminal OTA to high impedance, outputting a second potential to the terminal OTB, and outputting a third potential to the terminal OTB. The circuit 110 may also have the function of setting the terminal OTB to high impedance. The first potential is, for example, the same as the potential (e.g., potential L) applied to the wiring VL2 or a potential that can turn off the transistor M15. The second potential is a potential higher than the first potential, for example, the same as the potential (e.g., potential H) applied to the wiring VL1 or a potential that can turn on the transistor M12. The third potential is, for example, the same as the first potential, a potential (e.g., potential L) applied to the wiring VL2, or a potential that can turn off the transistor M12. In this case, the circuit 110 can output any potential to each of the terminals OTA and OTB or can set each of the terminals OTA and OTB to high impedance, for example, in accordance with a signal applied to the wiring CKL1 and a signal applied to the wiring CKL2. Therefore, it can be said that the circuit 110 can operate in synchronization with, for example, a signal supplied to the wiring CKL1 and a signal supplied to the wiring CKL2.

[0041] An example of the operation of the driving circuit 100, as well as a specific configuration example and an example of the operation of the circuit 110 will be described later.

[0042] In one embodiment of the present invention, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used as a transistor included in the driver circuit 100. The semiconductor is not limited to a simple semiconductor whose main component is a single element (such as silicon or germanium), but can also be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0043] For example, as the transistors constituting the driver circuit 100, a transistor containing silicon in a channel formation region (Si transistor) may be used, a transistor containing an oxide semiconductor in a channel formation region (OS transistor) may be used, or both a Si transistor and an OS transistor may be used.

[0044] Furthermore, various types of transistors can be used as the transistors that make up the drive circuit 100. For example, MOS field effect transistors, junction field effect transistors, bipolar transistors, etc. can be used.

[0045] Transistors of various structures can be used as transistors constituting the driver circuit 100. For example, transistors of various structures can be used, such as top-gate type (e.g., planar type and staggered type), bottom-gate type (e.g., inverted planar type and inverted staggered type), dual-gate type (structure in which gates are arranged on both sides (e.g., top and bottom) of a channel formation region), FIN type (fin type), TRI-GATE type (tri-gate type), and GAA type (gate-all-around type). Also, for example, vertical transistors (transistors whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the surface on which they are formed)) can be used.

[0046] In one embodiment of the present invention, a transistor has a function of controlling conduction or non-conduction between a connection destination of its source and a connection destination of its drain. For example, the transistor M11 has a function of controlling conduction or non-conduction between the wiring VL1 and the wiring OUTL. For example, the transistor M12 has a function of controlling conduction or non-conduction between the wiring VL2 and the wiring OUTL. For example, the transistor M13 has a function of controlling conduction or non-conduction between the wiring SPL and the node NDA. For example, the transistor M14 has a function of controlling conduction or non-conduction between the wiring SPL and the node NDB. For example, the transistor M15 has a function of controlling conduction or non-conduction between the node NDA and the node NDB. However, one embodiment of the present invention is not limited thereto.

[0047] In one embodiment of the present invention, the on or off state of a transistor is controlled by the potential of a node to which the gate is connected. For example, the on or off state of the transistor M11 is controlled by the potential of the node NDB. For example, the on or off state of the transistor M12 is controlled by the potential of the node NDC. For example, the on or off state of the transistor M13 is controlled by the potential of the wiring CKL1 (for example, the first clock signal). For example, the on or off state of the transistor M14 is controlled by the potential of the wiring CKL1 (for example, the first clock signal). For example, the on or off state of the transistor M15 is controlled by the potential of the node NDA. However, one embodiment of the present invention is not limited to this.

[0048] In one embodiment of the present invention, a transistor supplies a potential of a destination connected to one of the source or drain to a destination connected to the other of the source or drain, or supplies a potential of the destination connected to the other of the source or drain to a destination connected to the other of the source or drain. In other words, a potential of a destination connected to one of the source or drain of a transistor is supplied to a destination connected to the other of the source or drain through a channel formation region of the transistor. Alternatively, a potential of a destination connected to the other of the source or drain of a transistor is supplied to a destination connected to the one of the source or drain of the transistor through a channel formation region of the transistor. For example, the transistor M11 supplies a potential of the wiring VL1 to the wiring OUTL. For example, the transistor M12 supplies a potential of the wiring VL2 to the wiring OUTL. For example, the transistor M13 supplies a potential of the wiring SPL to the node NDA. For example, the transistor M14 supplies a potential of the wiring SPL to the node NDB. For example, the transistor M15 supplies a potential of the node NDA to the node NDB. In this case, the potential supplied may differ by the threshold voltage of the transistor, but one embodiment of the present invention is not limited thereto.

[0049] Note that a structural example of a transistor that can be used in the driver circuit 100 will be described in Embodiment 2 to be described later.

[0050] [Example of operation] Next, an example of the operation of the driving circuit 100 will be described.

[0051] Fig. 3 is a timing chart illustrating an example of operation of the drive circuit 100. Figs. 4 to 9 are circuit diagrams illustrating an example of operation of the drive circuit 100. Note that, here, as an example, the operation of the drive circuit 100 shown in Fig. 2 will be described.

[0052] In the driver circuit 100, the wirings CKL1, CKL2, and SPL each function as a signal line. The potential of a signal applied to each of the wirings CKL1, CKL2, and SPL is either a potential L (sometimes simply referred to as "L") or a potential H (sometimes simply referred to as "H") that is higher than the potential L. In this case, the difference between the potential H and the potential L is higher than the threshold voltage of the transistor. Note that the potential L may be, for example, a ground potential.

[0053] The wiring VL1 and the wiring VL2 each function as a power supply line. Here, a potential H is applied to the wiring VL1, and a potential L is applied to the wiring VL2.

[0054] Note that a signal may be supplied to at least one of the wiring VL1 and the wiring VL2, that is, at least one of the wiring VL1 and the wiring VL2 can also function as a signal line.

[0055] For ease of understanding, the potential applied to each wiring is set to potential L or potential H, but different potentials may be applied to each wiring.

[0056] Furthermore, in the description of operations, when the potential changes, there may be rise and fall times due to loads (parasitic capacitance and parasitic resistance) such as wiring. Even if two different operations are shown to have the same timing, this does not necessarily mean that they are exactly the same timing. For example, even if there is a slight time difference due to signal delays in wiring, they may be considered to have the same timing.

[0057] Furthermore, in the timing chart, even if each period is shown to have the same length in the drawing for ease of explanation, the time length of each period may be different.

[0058] 3 shows potentials applied to the wirings CKL1, CKL2, and SPL in each period of operation. The timing chart in FIG. 3 also shows potentials H, L, or high impedance (denoted by "Hi-Z" in the drawing) for the terminals OTA and OTB of the circuit 110. The timing chart also shows changes in the potentials of the nodes NDA, NDB, and NDC. The timing chart also shows changes in the potential of the wiring OUTL.

[0059] 4 to 9 also show the state of the circuit at each point in time of operation (potentials of each wiring and each node, states of each transistor, currents flowing through each wiring and each node, etc.). For example, the potentials of wiring CKL1, wiring CKL2, wiring SPL, wiring VL1, wiring VL2, node NDA, node NDB, node NDC, and wiring OUTL are shown. A symbol indicating a potential such as "H" or "L" (also called a potential symbol) may be enclosed in a box next to each wiring. In particular, when a potential change occurs, the box may be thickened, and when a floating state occurs, the box may be dotted. An "x" symbol may be attached to a transistor in an off state. A dashed arrow indicating the direction of current flow (which may also be referred to as the direction of movement of positive charge) may be attached along each wiring.

[0060] The threshold voltage of transistor M11 may be denoted as Vt11, the threshold voltage of transistor M12 as Vt12, the threshold voltage of transistor M13 as Vt13, the threshold voltage of transistor M14 as Vt14, and the threshold voltage of transistor M15 as Vt15.

[0061] For ease of understanding, the description may be given without taking into consideration the influence of parasitic capacitance when the potential changes due to capacitive coupling of a capacitive element.

[0062] Immediately before the period T11, a potential L is applied to the wiring CKL1 and the wiring CKL2, and a potential H is applied to the wiring SPL. The terminal OTA is in a high-impedance state, and the terminal OTB is supplied with the potential L. Therefore, the transistors M13 and M14 are off, and the nodes NDA and NDB are floating. At this time, the potential of the node NDA is a potential H-Vt13, and the potential of the node NDB exceeds a potential H+Vt11. Therefore, the transistor M15 is off, and the transistor M11 is on. The potential of the node NDC is a potential L, and the transistor M12 is off. Therefore, the potential of the wiring VL1 is supplied to the wiring OUTL through the transistor M11, and the potential of the wiring OUTL is a potential H. The circuit configuration at this time is shown in FIG. 4. In the following description, unless otherwise specified, the previous state is maintained.

[0063] In the period T11, a potential H is applied to the wiring CKL1, and a potential L is applied to the wiring SPL. The potential L is output to the terminal OTA, or the terminal OTA becomes high impedance. In either case, the transistor M13 is turned on, and the potential of the node NDA becomes potential L. The transistor M14 is turned on, and the potential of the node NDB becomes potential L. Therefore, the transistor M11 is turned off. The potential L is output to the terminal OTB, or the terminal OTB becomes high impedance. In either case, the potential of the node NDC remains at potential L, and the transistor M12 remains off. Therefore, the wiring OUTL becomes floating, and the potential of the wiring OUTL remains at potential H. The circuit state at this time is shown in FIG. 5. Here, the case where the terminal OTA is high impedance and the potential L is output to the terminal OTB is shown.

[0064] In period T12, a potential L is applied to the wiring CKL1, a potential H is applied to the wiring CKL2, and a potential H is applied to the wiring SPL. The potential L is also output to the terminal OTA. This turns off the transistor M13. At this time, the potential H is applied to the wiring CKL2, but the potential L is output to the terminal OTA. Therefore, the potential of the node NDA remains at the potential L without increasing due to the capacitive coupling of the capacitor C11. This turns off the transistor M14, and the node NDB is floating. At this time, the potential of the node NDB remains at the potential L, and the transistor M11 remains off. The potential H is also output to the terminal OTB. This turns the potential of the node NDC to the potential H, and the transistor M12 is turned on. Therefore, the potential of the wiring VL2 is supplied to the wiring OUTL via the transistor M12, and the potential of the wiring OUTL becomes the potential L. The circuit configuration at this time is shown in FIG. 6.

[0065] During period T13, a potential H is applied to the wiring CKL1, and a potential L is applied to the wiring CKL2. The terminal OTA becomes high impedance. This turns on the transistor M13, and the potential of the node NDA increases to "potential H-Vt13." The transistor M14 turns on, and the potential of the node NDB increases to "potential H-Vt14." This turns on the transistor M11. This outputs a potential L to the terminal OTB. This turns the potential of the node NDC to potential L, and the transistor M12 turns off. This supplies the potential of the wiring VL1 to the wiring OUTL via the transistor M11. When the potential of the wiring OUTL increases to the potential of the node NDB minus Vt11, the transistor M11 turns off. This increases the potential of the wiring OUTL to "potential H-Vt14-Vt11." The circuit configuration at this time is shown in Figure 7.

[0066] For example, by making the potential of the wiring CKL1 higher than "potential H+Vt13", the potential of the node NDA can be increased to potential H. Also, by making the potential of the wiring CKL1 higher than "potential H+Vt14", the potential of the node NDB can be increased to potential H. Also, for example, if the potential of the node NDB can be increased to a value exceeding "potential H+Vt11" in response to an increase in the potential of the wiring OUTL, the potential of the wiring OUTL can be increased to potential H without turning off the transistor M11.

[0067] During period T14, a potential L is applied to the wiring CKL1, and a potential H is applied to the wiring CKL2. Furthermore, the terminal OTA remains at high impedance. Then, the transistor M13 is turned off, and the node NDA is floating. Furthermore, the transistor M14 is turned off, and the node NDB is floating. At this time, the potential H is applied to the wiring CKL2, and the potential of the node NDA increases due to the capacitive coupling of the capacitor C11. Here, if the increase in the potential of the node NDA is ΔV1, the potential of the node NDA becomes "potential H-Vt13+ΔV1." Furthermore, the transistor M15 is turned on, and the potential of the node NDB increases to a value obtained by subtracting Vt15 from the potential of the node NDA. That is, the potential of the node NDB becomes "potential H-Vt13+ΔV1-Vt15." At this time, if ΔV1, which is the increase in the potential of the node NDA, satisfies "ΔV1>Vt11+Vt13+Vt15," the potential of the node NDB exceeds "potential H+Vt11," and the transistor M11 is turned on. Also, potential L is output to the terminal OTB, or the terminal OTB becomes high impedance. In either case, the potential of the node NDC is potential L, and the transistor M12 remains off. Therefore, the potential of the wiring VL1 is supplied to the wiring OUTL via the transistor M11, and the potential of the wiring OUTL rises to potential H. The circuit state at this time is shown in Figure 8. Here, the case where potential L is output to the terminal OTB is shown.

[0068] In the period T15, a potential H is applied to the wiring CKL1, and a potential L is applied to the wiring CKL2. Furthermore, the terminal OTA remains at high impedance. Then, because the potential L is applied to the wiring CKL2, the potential of the node NDA drops due to the capacitive coupling of the capacitor C11. At this time, for example, the potential of the node NDA becomes "potential H-Vt13." Even if the potential of the node NDA drops to a value lower than "potential H-Vt13," the transistor M13 turns on, causing the potential to rise, and the potential of the node NDA becomes "potential H-Vt13." Furthermore, because the potential of the node NDB becomes higher than the potential of the node NDA, the transistor M15 is turned off. Furthermore, because the potential of the node NDB is higher than the potential of the wiring CKL1, the transistor M14 remains off. Therefore, the node NDB becomes floating. At this time, the potential of the node NDB remains at "potential H-Vt13+ΔV1-Vt15," and the transistor M11 remains on. Also, a potential L is output to the terminal OTB, or the terminal OTB becomes high impedance. In either case, the potential of the node NDC is potential L, and the transistor M12 remains off. Therefore, the potential of the wiring VL1 is supplied to the wiring OUTL via the transistor M11, and the potential of the wiring OUTL remains at potential H. The circuit state at this time is shown in Figure 9. Here, the case where a potential L is output to the terminal OTB is shown.

[0069] After the period T15, the operation of the period T14 and the operation of the period T15 are repeated.

[0070] 3, the periods between the periods T11 to T15 are illustrated. This is to clearly illustrate that, for example, when there is a time (rise time and fall time) during which the potential of each wiring changes, the potential of the wiring CKL1 falls from the potential H to the potential L, and then the potential of the wiring CKL2 starts to rise from the potential L to the potential H, and the potential of the wiring CKL2 falls from the potential H to the potential L, and then the potential of the wiring CKL1 starts to rise from the potential L to the potential H, when the potential of the wiring CKL2 falls from the potential H to the potential L. Therefore, it is preferable that the periods between the periods T11 to T15 are short. Alternatively, the periods T11 to T15 may be continuous without providing a period between them.

[0071] In the driver circuit of one embodiment of the present invention, for example, in the period T14, the potential of the node NDB can be increased to a value exceeding "potential H+Vt11" to increase the gate voltage of the transistor M11. This can increase the potential of the wiring OUTL to potential H. Furthermore, the rate at which the potential of the wiring OUTL increases can be increased. That is, the rise time of the potential of the wiring OUTL can be shortened. Therefore, the operation speed of the driver circuit can be improved, thereby enabling a higher-speed display device. Even if the load of the wiring OUTL is increased, for example, the gate voltage of the transistor M11 can be increased, thereby preventing a decrease in the operation speed of the driver circuit. Therefore, the resolution and the screen size of the display device can be increased. Furthermore, even if the power supply voltage for operating the driver circuit (e.g., corresponding to the potential difference between the potential H and the potential L) is reduced, for example, the gate voltage of the transistor M11 can be increased, thereby preventing a decrease in the operation speed of the driver circuit. Therefore, the power consumption of the display device can be reduced. Even if the channel width of the transistor M11 is reduced, for example, the gate voltage of the transistor M11 can be increased, thereby preventing a decrease in the operation speed of the driver circuit. Therefore, the area occupied by the driving circuit can be reduced, and the frame of the display device can be narrowed.

[0072] Furthermore, for example, in the period T15, the potential of the node NDB can be maintained at a value exceeding "potential H+Vt11." Therefore, the transistor M11 can be kept on, and the potential H can be continuously supplied to the wiring OUTL. That is, the wiring OUTL does not become floating, and the potential H can be continuously supplied to the wiring OUTL. Therefore, the influence of noise on the wiring OUTL can be reduced, and the operation of the display device can be stabilized.

[0073] For example, the potential of the node NDB can be prevented from changing or the change in the potential of the node NDB can be reduced between the periods T14 and T15. This prevents a change in the potential of the node NDB from being transmitted to the wiring OUTL through the gate capacitance (the electrostatic capacitance between the gate and one of the source and the drain) of the transistor M11, thereby preventing noise from being generated in the wiring OUTL. This stabilizes the operation of the display device. Even if the channel width of the transistor M11 is increased, for example, the potential of the node NDB can be prevented from changing or the change in the potential of the node NDB can be reduced, thereby preventing noise from being generated in the wiring OUTL. Therefore, the channel width of the transistor M11 can be increased to increase its on-state current. This increases the rate at which the potential of the wiring OUTL increases. That is, the rise time of the potential of the wiring OUTL can be shortened. This improves the operating speed of the driver circuit and increases the operating speed of the display device. Even if the load of the wiring OUTL is increased, for example, the channel width of the transistor M11 can be increased, thereby preventing a decrease in the operating speed of the driver circuit. This improves the resolution and size of the display device.

[0074] For example, in the period T14, the potential of the node NDB can be made lower than the potential of the node NDA. Therefore, the voltage applied between the terminals of the transistors M11 and M14 connected to the node NDB can be reduced. Therefore, damage and deterioration of the transistors can be suppressed, and the reliability of the display device can be improved.

[0075] Furthermore, in the configuration in which the other terminal of the capacitor C11 is connected to the wiring CKL2 without passing through the source and drain of the transistor (also referred to as the other terminal of the capacitor C11 being directly connected to the wiring CKL2), the rise time of the potential of the other terminal of the capacitor C11 can be shortened, for example, in the period T14, compared to the configuration in which the other terminal of the capacitor C11 is connected to the wiring CKL2 through the source and drain of the transistor (also referred to as the other terminal of the capacitor C11 being indirectly connected to the wiring CKL2). Here, if the rise time of the potential of the other terminal of the capacitor C11 is shortened, the rise time of the potential of the node NDA is shortened. If the rise time of the potential of the node NDA is shortened, the rise time of the potential of the node NDB is shortened. If the rise time of the potential of the node NDB is shortened, the timing at which the transistor M11 is turned on is advanced. If the timing at which the transistor M11 is turned on is advanced, the rise time of the potential of the wiring OUTL is shortened. Therefore, the operation speed of the driver circuit can be improved, and the display device can be made faster.

[0076] Furthermore, by connecting the other terminal of the capacitor C11 to the wiring CKL2 without passing through the source and drain of the transistor, the capacitance of the capacitor C11 can be reduced, for example, if the rise time of the potential of the other terminal of the capacitor C11 or the rise time of the potential of the node NDA is the same, compared to a configuration in which the other terminal of the capacitor C11 is connected to the wiring CKL2 via the source and drain of the transistor. Here, if the capacitance of the capacitor C11 is reduced, the area where a pair of electrodes (also referred to as a pair of terminals or a pair of conductive layers) of the capacitor C11 overlap each other can be reduced. This reduces the area occupied by the driver circuit, enabling a narrower frame of the display device.

[0077] Here, the other terminal of the capacitor C11 is connected to the wiring CKL2 without passing through the source and drain of the transistor, thereby reducing the capacitance of the capacitor C11. Therefore, the overlapping area of ​​the pair of electrodes of the capacitor C11 can be made smaller than the area of ​​the channel formation region of the transistor M11. The overlapping area of ​​the pair of electrodes of the capacitor C11 can be made smaller than the area of ​​the channel formation region of the transistor M12. However, if the capacitance of the capacitor C11 is made too small, the increase in potential of the node NDA, ΔV1, becomes smaller. Therefore, the overlapping area of ​​the pair of electrodes of the capacitor C11 can be made larger than the area of ​​the channel formation region of the transistor M13. The overlapping area of ​​the pair of electrodes of the capacitor C11 can be made larger than the area of ​​the channel formation region of the transistor M14. The overlapping area of ​​the pair of electrodes of the capacitor C11 can be made larger than the area of ​​the channel formation region of the transistor M15. Furthermore, the area where the pair of electrodes of the capacitance element C11 overlap can be made larger than the sum of the areas of the channel formation regions of the transistors M13, M14, and M15.

[0078] The driver circuit of one embodiment of the present invention can achieve at least one of the above-described various effects by adding the transistors M13, M15, and C11 to the driver circuit including the transistors M11, M12, and M14. Therefore, the driver circuit of one embodiment of the present invention has a reduced number of circuit elements such as transistors and capacitors, wirings, signals, and the like. Therefore, the area occupied by the driver circuit can be reduced, and the frame of the display device can be narrowed.

[0079] [Variation 1] The driver circuit of one embodiment of the present invention is not limited to the above structure, and various structures can be used as the driver circuit of one embodiment of the present invention.

[0080] 10 is a circuit diagram illustrating a modification of the driver circuit 100 shown in FIG. 2. The driver circuit 100 shown in FIG. 10 differs from the driver circuit 100 shown in FIG. 2 in that it further includes a transistor M16. In this case, the other of the source or the drain of the transistor M15 is connected to the gate of the transistor M15, one terminal of the capacitor C11, and one of the source or the drain of the transistor M16. The other of the source or the drain of the transistor M16 is connected to one of the source or the drain of the transistor M13. The gate of the transistor M16 is connected to the wiring VL1.

[0081] With this configuration, for example, during the period T14, application of a large voltage to the transistor M13, the transistors included in the circuit 110, and the like can be prevented, and breakdown and deterioration of these transistors can be suppressed. Therefore, reliability can be improved. Furthermore, for example, by increasing the amplitude of the signal applied to the wiring CKL2 and increasing ΔV1, which is the increase in the potentials of the nodes NDA and NDB, the gate voltage of the transistor M11 can be increased while preventing application of a large voltage to the transistor M13, the transistors included in the circuit 110, and the like. Therefore, the operating speed can be improved.

[0082] Note that since the potential of the node NDA is higher than the potential of the node NDB, it is particularly preferable to provide the transistor M16.

[0083] [Variation 2] 11 is a circuit diagram illustrating a modification of the driving circuit 100 shown in FIG. 10. The driving circuit 100 shown in FIG. 11 differs from the driving circuit 100 shown in FIG. 10 in that it further includes a transistor M17. In this case, the gate of the transistor M11 is connected to one of the source or drain of the transistor M15 and one of the source or drain of the transistor M17. The other of the source or drain of the transistor M17 is connected to one of the source or drain of the transistor M14. The gate of the transistor M17 is connected to the wiring VL1.

[0084] With this configuration, for example, during the periods T14 and T15, application of a large voltage to the transistor M14 can be prevented, and breakdown and degradation of the transistor can be suppressed. Therefore, reliability can be improved. Furthermore, for example, by increasing the amplitude of the signal applied to the wiring CKL2 and increasing ΔV1, which is the increase in the potentials of the nodes NDA and NDB, application of a large voltage to the transistor M14 can be prevented and the gate voltage of the transistor M11 can be increased. Therefore, the operating speed can be improved.

[0085] Here, as described above, if the capacitance of the capacitor C11 is made too small, ΔV1, which is the increase in the potential of the node NDA, becomes small. Therefore, the area where the pair of electrodes of the capacitor C11 overlap can be made larger than the area of ​​the channel formation region of the transistor M16. The area where the pair of electrodes of the capacitor C11 overlap can be made larger than the area of ​​the channel formation region of the transistor M17. Furthermore, the area where the pair of electrodes of the capacitor C11 overlap can be made larger than the sum of the areas of the channel formation regions of the transistors M13, M14, M15, M16, and M17.

[0086] Note that since the potential of the node NDB is lower than the potential of the node NDA, the number of transistors can be reduced and miniaturization can be achieved by using a structure in which the transistor M17 is not provided as in the structure shown in FIG.

[0087] [Variation 3] 12 is a circuit diagram illustrating a modification of the drive circuit 100 shown in FIG. 2. The drive circuit 100 shown in FIG. 12 differs from the drive circuit 100 shown in FIG. 2 in that it includes transistors M15a and M15b instead of the transistor M15. In this case, one of the source or drain of the transistor M15b is connected to the gate of the transistor M11. The other of the source or drain of the transistor M15b is connected to the gate of the transistor M15b and one of the source or drain of the transistor M15a. The other of the source or drain of the transistor M15a is connected to the gate of the transistor M15a and one terminal of the capacitance element C11.

[0088] With this configuration, for example, during the period T14, the potential of the node NDB can be made lower than the potential of the node NDA. This reduces the voltages applied to the transistors M11 and M14, thereby preventing breakdown and degradation of these transistors. This improves reliability. Furthermore, for example, during the period T15, charge is less likely to leak from the node NDB to the node NDA, making it easier to maintain the potential of the node NDB. This stabilizes operation.

[0089] [Variation 4] Fig. 13 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 12. The drive circuit 100 shown in Fig. 13 differs from the drive circuit 100 shown in Fig. 12 in terms of the connection of the transistor M15b. Here, the gate of the transistor M15b is connected to the gate of the transistor M15a.

[0090] With this configuration, for example, one conductive layer can have a region that functions as the gate of the transistor M15a and a region that functions as the gate of the transistor M15b. Therefore, compared to the configuration shown in FIG. 12, the number of vias can be reduced, and the layout area can be made smaller, resulting in a more compact device.

[0091] [Variation 5] Fig. 14 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 2. The drive circuit 100 shown in Fig. 14 differs from the drive circuit 100 shown in Fig. 2 in that it has a p-channel transistor M15p instead of the transistor M15. In this case, the gate of the transistor M15p is connected to one of the source or drain of the transistor M15p.

[0092] With this configuration, for example, a p-channel transistor may leak less charge in an off state (also referred to as having a smaller off-state current) than an n-channel transistor, which makes it easier to maintain the potential of the node NDB, thereby stabilizing the operation.

[0093] [Variation 6] Fig. 15 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 2. The drive circuit 100 shown in Fig. 15 differs from the drive circuit 100 shown in Fig. 2 in that it further includes a capacitive element C12. In this case, one terminal of the capacitive element C12 is connected to the gate of the transistor M11. The other terminal of the capacitive element C12 is connected to one of the source or drain of the transistor M11.

[0094] With this configuration, for example, in the period T13, the capacitor C12 functions as a bootstrap capacitor, and the potential of the node NDB can be increased as the potential of the wiring OUTL increases. At this time, by increasing the potential of the node NDB to a value exceeding "potential H+Vt11," the transistor M11 remains on, and the potential of the wiring OUTL can be increased to potential H. Therefore, the time required for the potential of the wiring OUTL to reach potential H can be shortened, and the operating speed can be improved.

[0095] Although not shown, one terminal of the capacitor C12 may be connected to the other of the source and drain of the transistor M15 (i.e., the node NDA). In this case, for example, in the period T13, as the potential of the wiring OUTL increases, the potential of the node NDA is increased to a value exceeding "potential H+Vt11+Vt15." This keeps the transistor M11 on, and the potential of the wiring OUTL can be increased to potential H. Therefore, the time required for the potential of the wiring OUTL to reach potential H can be shortened, and the operating speed can be improved.

[0096] [Variation 7] Fig. 16 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 2. The drive circuit 100 shown in Fig. 16 differs from the drive circuit 100 shown in Fig. 2 in that it includes a transistor M18 instead of the capacitive element C11. In this case, the gate of the transistor M18 is connected to the other of the source or the drain of the transistor M15. One of the source or the drain of the transistor M18 is connected to the wiring CKL2.

[0097] The other of the source or the drain of the transistor M18 may be connected to one of the source or the drain of the transistor M18, or to any wiring (for example, the wiring VL1 or the wiring VL2).

[0098] With this configuration, for example, during periods T13 to T15, a channel is formed in the channel formation region of the transistor M18, allowing the gate capacitance of the transistor M18 to function as a capacitive element instead of the capacitive element C11. Here, to increase ΔV1, the increase in potential at the node NDA, during period T14, it is preferable to increase the capacitance of the capacitive element C11. To increase the capacitance of the capacitive element C11, for example, the layout area of ​​the capacitive element C11 can be increased. Alternatively, to increase the capacitance while suppressing an increase in the layout area of ​​the capacitive element C11, for example, adding a conductive layer, reducing the thickness of the dielectric, or using a dielectric with a high dielectric constant can be used. However, these methods increase process costs. Therefore, by using the gate capacitance of the transistor M18 as a capacitive element instead of the capacitive element C11, the gate insulating film is used as the dielectric, making it easier to increase the capacitance per unit area. Therefore, compared to the configuration shown in FIG. 2, the layout area can be reduced, thereby enabling miniaturization.

[0099] Further, for example, during periods T11 and T12, a potential L is applied to the gate of the transistor M18. As a result, the transistor M18 is turned off, and no channel is formed in the channel formation region of the transistor M18. Since no channel is formed in the channel formation region of the transistor M18, the gate capacitance of the transistor M18 is reduced. By reducing the gate capacitance of the transistor M18 in this manner, the current required for charging and discharging the wiring CKL2 and the node NDA can be reduced, or the time required for charging and discharging can be shortened. This can reduce power consumption or improve operating speed. Furthermore, by reducing the gate capacitance of the transistor M18, it is possible to suppress changes in the potential of the node NDA that occur due to changes in the potential of the wiring CKL2. This can prevent malfunctions and stabilize operation.

[0100] [Variation 8] Fig. 17 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 16. The drive circuit 100 shown in Fig. 17 differs from the drive circuit 100 shown in Fig. 16 in terms of the connection of the transistor M18. Here, the gate of the transistor M18 is connected to a wiring CKL2. One of the source or drain of the transistor M18 is connected to one of the source or drain of the transistor M15.

[0101] The other of the source or the drain of the transistor M18 may be connected to one of the source or the drain of the transistor M18, or to any wiring (for example, the wiring VL1 or the wiring VL2).

[0102] With this configuration, the gate capacitance of the transistor M18 can function as a capacitive element instead of the capacitive element C11, similar to the configuration shown in Fig. 16. This makes it easier to increase the capacitance per unit area, thereby enabling miniaturization.

[0103] When the gate voltage of the transistor M18 exceeds the threshold voltage, a channel is formed in the channel formation region of the transistor M18, allowing the gate capacitance of the transistor M18 to function as a capacitive element. Therefore, the transistor M18 may be connected as shown in FIG. 16 or as shown in FIG. 17, depending on the operation of the driver circuit 100. Alternatively, a configuration may be used that includes both a transistor connected as shown in FIG. 16 and a transistor connected as shown in FIG. 17.

[0104] [Modification 9] FIG. 18 is a circuit diagram illustrating a modification of the drive circuit 100 shown in FIG. 2. The drive circuit 100 shown in FIG. 18 differs from the drive circuit 100 shown in FIG. 2 in that it further includes a transistor M18. In this case, the gate of the transistor M18 is connected to the other of the source or the drain of the transistor M15. One of the source or the drain of the transistor M18 is connected to a wiring CKL2. The drive circuit 100 shown in FIG. 18 can be said to have a configuration obtained by combining the drive circuit 100 shown in FIG. 2 and the drive circuit 100 shown in FIG. 16.

[0105] Although not shown, the transistor M18 may be connected as shown in Fig. 17. That is, a configuration may be used in which the drive circuit 100 shown in Fig. 2 and the drive circuit 100 shown in Fig. 17 are combined.

[0106] This configuration provides the advantages of both the capacitance element C11, which can easily stabilize the capacitance, and the transistor M18, which can easily increase the capacitance per unit area, thereby achieving stable operation and miniaturization.

[0107] [Modification 10] 19 is a circuit diagram illustrating a modification of the drive circuit 100 shown in FIG. 2. The drive circuit 100 shown in FIG. 19 differs from the drive circuit 100 shown in FIG. 2 in that it further includes a transistor M18 and in the connection of the capacitance element C11. In this case, the gate of the transistor M18 is connected to the other of the source or drain of the transistor M15. One of the source or drain of the transistor M18 is connected to a wiring CKL2. The other terminal of the capacitance element C11 is connected to the other of the source or drain of the transistor M18.

[0108] With this configuration, for example, during periods T13 to T15, the transistor M18 is turned on, which causes the potential of the node NDA to change due to capacitive coupling by the capacitor C11. At this time, the gate capacitance of the transistor M18 and the capacitance of the capacitor C11 are connected in parallel, increasing the capacitance. This increases the amount of change when the potential of the node NDA is changed due to capacitive coupling. This improves the operating speed.

[0109] Furthermore, for example, in the period T11 and the period T12, the transistor M18 is turned off, thereby preventing the capacitor C11 from functioning. This reduces the current required for charging and discharging the wiring CKL2 and the node NDA, or shortens the time required for charging and discharging. This reduces power consumption and improves operating speed. Furthermore, it is possible to suppress changes in the potential of the node NDA that occur due to changes in the potential of the wiring CKL2. This prevents malfunctions and stabilizes operation.

[0110] [Modification 11] Fig. 20 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 2. The drive circuit 100 shown in Fig. 20 differs from the drive circuit 100 shown in Fig. 2 in terms of the connection of the transistor M13. Here, the other of the source or drain of the transistor M13 is connected to one of the source or drain of the transistor M14.

[0111] By adopting such a configuration, the parasitic capacitance between the wiring CKL1 and the wiring SPL can be reduced. As will be described in detail later, for example, when a plurality of driving circuits 100 are used in the gate driver section of a display device, the wiring SPL of a driving circuit 100 in a certain row may be connected to the wiring OUTL of a driving circuit 100 in the row immediately preceding it. Therefore, by reducing the parasitic capacitance between the wiring CKL1 and the wiring SPL, it is possible to suppress the signal applied to the wiring CKL1 from being transmitted to the wiring SPL (i.e., the wiring OUTL in the row immediately preceding it) via the parasitic capacitance, thereby preventing noise from being generated. This can thereby stabilize operation.

[0112] For example, in the period T14, the potential difference between the source and drain of the transistor M13 (also referred to as the drain voltage) can be reduced. This can suppress deterioration of the transistor M13 and improve reliability. Furthermore, this can reduce charge leakage from the node NDA through the transistor M13, thereby maintaining the potential of the node NDA. This can stabilize operation.

[0113] 20, a configuration may be adopted in which a transistor M17 is provided as shown in Fig. 11. In this case, the other of the source or the drain of the transistor M13 is connected to one of the source or the drain of the transistor M14 and the other of the source or the drain of the transistor M17.

[0114] [Modification 12] Fig. 21 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 2. The drive circuit 100 shown in Fig. 21 differs from the drive circuit 100 shown in Fig. 2 in terms of the connection of the transistor M14. Here, the other of the source or drain of the transistor M14 is connected to one of the source or drain of the transistor M13.

[0115] By adopting such a configuration, the parasitic capacitance between the wiring CKL1 and the wiring SPL can be reduced. Therefore, similar to the configuration shown in FIG. 20, by reducing the parasitic capacitance between the wiring CKL1 and the wiring SPL, it is possible to suppress the signal applied to the wiring CKL1 from being transmitted to the wiring SPL (i.e., the wiring OUTL of the previous row) via the parasitic capacitance, thereby preventing noise from being generated. Therefore, it is possible to stabilize the operation.

[0116] Furthermore, for example, in the periods T14 and T15, the potential difference between the source and drain of the transistor M14 can be reduced. This can suppress deterioration of the transistor M14 and improve reliability. Furthermore, this can reduce charge leakage from the node NDB through the transistor M14, thereby maintaining the potential of the node NDB. This can stabilize operation.

[0117] 21, a configuration may be adopted in which a transistor M16 is provided as shown in Fig. 10 or 11. In this case, the other of the source or the drain of the transistor M14 is connected to one of the source or the drain of the transistor M13 and the other of the source or the drain of the transistor M16.

[0118] [Modification 13] 22 is a circuit diagram illustrating a modification of the drive circuit 100 shown in FIG. 2. The drive circuit 100 shown in FIG. 22 differs from the drive circuit 100 shown in FIG. 2 in that it further includes a transistor M10. In this case, the gate of the transistor M10 is connected to the other of the source or drain of the transistor M15. One of the source or drain of the transistor M10 is connected to the other of the source or drain of the transistor M11. The other of the source or drain of the transistor M10 is connected to the other of the source or drain of the transistor M11.

[0119] With this configuration, for example, in the periods T13 and T14, the potential of the wiring VL1 is supplied to the wiring OUTL through the transistor M11 and also through the transistor M10. Therefore, the rise time of the potential of the wiring OUTL can be shortened, and the operating speed can be improved.

[0120] [Modification 14] FIG. 23 is a circuit diagram illustrating a modification of the drive circuit 100 shown in FIG. 2. The drive circuit 100 shown in FIG. 23 differs from the drive circuit 100 shown in FIG. 2 in that it includes transistors M12a, M12b, and M12c instead of the transistor M12. In this case, one of the source or drain of the transistor M12a is connected to one of the source or drain of the transistor M11, the gate of the transistor M12c, and the wiring OUTL. The other of the source or drain of the transistor M12a is connected to one of the source or drain of the transistor M12b and one of the source or drain of the transistor M12c. The gates of the transistors M12a and M12b are each connected to a node NDC (i.e., the terminal OTB of the circuit 110). The other of the source or drain of the transistor M12b is connected to the wiring VL2. The other of the source or drain of the transistor M12c is connected to the wiring VL1.

[0121] With this configuration, when the potential of the wiring OUTL is potential H, the transistor M12c is turned on, and the potential of the wiring VL1 is supplied to the other of the source and drain of the transistor M12a and one of the source and drain of the transistor M12b via the transistor M12c. In this case, if the threshold voltage of the transistor M12c is denoted as Vt12c, the potential of the other of the source and drain of the transistor M12a and one of the source and drain of the transistor M12b becomes "potential H-Vt12c." Therefore, the potential difference between the source and drain of the transistor M12a can be made smaller than potential H, and the potential difference between the source and drain of the transistor M12b can be made smaller than potential H. This can suppress degradation of the transistors and improve reliability.

[0122] Furthermore, since the potential difference between the source and drain of the transistor M12a can be made smaller than the potential H and the potential difference between the source and drain of the transistor M12b can be made smaller than the potential H, it can be said that the value of the potential H can be increased while suppressing transistor degradation. As a result, by increasing the value of the potential H and increasing ΔV1, which is the increase in potential due to capacitive coupling of the capacitor C11, the potentials of the nodes NDA and NDB can be increased, thereby increasing the on-state current of the transistor M11. Therefore, the operating speed can be improved.

[0123] Furthermore, for example, when the transistors M12a and M12b are both off, leakage of charge from the wiring OUTL through the transistor M12a can be reduced, and the potential of the wiring OUTL can be maintained, thereby stabilizing operation.

[0124] [Modification 15] Figure 24 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Figure 11. The drive circuit 100 shown in Figure 24 differs from the drive circuit 100 shown in Figure 11 in that it has a switch S12 instead of the transistor M12, a switch S13 instead of the transistor M13, and a switch S14 instead of the transistor M14. Note that the circuit 110 is not shown in the illustration.

[0125] As described above, one embodiment of the present invention may have a structure in which at least some of the transistors included in the driver circuit 100 are replaced with other elements that function as switches.

[0126] Although not shown, a rectifying element such as a diode may be provided instead of the transistor M15. In this case, the rectifying element is connected so that a current can flow only from one terminal of the capacitance element C11 (i.e., node NDA) to the gate of the transistor M11 (i.e., node NDB).

[0127] The modifications of the driving circuit 100 described above, whether illustrated or not, can be applied to the driving circuit 100 shown in FIG.

[0128] Furthermore, two or more of the modifications of the driving circuit 100 described above with or without illustrations can be applied to the driving circuit 100 shown in FIGS.

[0129] Furthermore, the driving circuit 100 described above, whether illustrated or not, can at least solve the problem of providing a novel driving circuit by its circuit configuration alone.

[0130] <Example of a driving circuit> Next, the circuit 110 will be described.

[0131] The circuit 110 described below and its variations can be applied to the drive circuit 100 described above, whether illustrated or not.

[0132] FIG. 25 is a circuit diagram illustrating a specific example of the configuration of the circuit 110 included in the driver circuit 100 shown in FIG. 2 and other figures.

[0133] 25, the circuit 110 includes, for example, a transistor M21, a transistor M22, a transistor M23, a transistor M24, a transistor M25, a transistor M26, and a transistor M27, and may also include a capacitive element C22.

[0134] The gate of transistor M21 is connected to one of the source or drain of transistor M24, one of the source or drain of transistor M25, the gate of transistor M26, and one terminal of capacitor C22. The source or drain of transistor M21 is connected to one of the source or drain of transistor M22 and the other terminal of capacitor C22. The other of the source or drain of transistor M22 is connected to one of the source or drain of transistor M23 and to the gate of transistor M12 via terminal OTB. The source or drain of transistor M26 is connected to one of the source or drain of transistor M27. The other of the source or drain of transistor M26 is connected to one of the source or drain of transistor M13 via terminal OTA. The gates of transistor M23 and transistor M25 are each connected to one of the source or drain of transistor M14. The other of the source or drain of transistor M21 is connected to wiring CKL2. The gate of the transistor M22 is connected to the wiring CKL2. The other of the source and the drain of the transistor M23 is connected to the wiring VL2. The other of the source and the drain of the transistor M24 is connected to the wiring VL1. The gate of the transistor M24 is connected to the wiring CKL1. The other of the source and the drain of the transistor M25 is connected to the wiring CKL1. The other of the source and the drain of the transistor M27 is connected to the wiring VL2. The gate of the transistor M27 is connected to the wiring CKL2. Note that the capacitor C22 may be a parasitic capacitance between the gate and either the source or the drain of the transistor M21.

[0135] A wiring connected to the gate of the transistor M21, one terminal of the capacitor C22, and the like may be referred to as a node NDD.

[0136] [Example of operation] Fig. 26 is a timing chart illustrating an example of operation of the driving circuit 100 shown in Fig. 25. Figs. 27 to 32 are circuit diagrams illustrating an example of operation of the driving circuit 100. Note that the explanation of the example of operation shown in Fig. 3 and the like can be referred to as appropriate, and therefore, the operation of the circuit 110 will be mainly described here.

[0137] The timing chart shown in FIG. 26 shows the change in the potential of the node NDD in addition to the timing chart shown in FIG.

[0138] The threshold voltage of transistor M21 may be referred to as Vt21, the threshold voltage of transistor M22 as Vt22, the threshold voltage of transistor M23 as Vt23, the threshold voltage of transistor M24 as Vt24, the threshold voltage of transistor M25 as Vt25, the threshold voltage of transistor M26 as Vt26, and the threshold voltage of transistor M27 as Vt27.

[0139] Immediately before the period T11, the transistors M22, M24, and M27 are all off, and the transistors M23 and M25 are all on. Therefore, the potential of the node NDD is potential L, and the transistors M21 and M26 are all off. Therefore, the transistors M26 and M27 are all off, and the terminal OTA is at high impedance. In addition, the potential of the wiring VL2 is supplied to the terminal OTB via the transistor M23, and therefore the potential L is output to the terminal OTB. The circuit state at this time is shown in FIG. 27. In the following description, unless otherwise specified, the previous state is assumed to be maintained.

[0140] During period T11, transistor M24 is turned on, and transistors M23 and M25 are turned off. Then, the potential of node NDD becomes "potential H-Vt24," and transistors M21 and M26 are turned on. Therefore, terminal OTA remains at high impedance, and terminal OTB becomes high impedance. The circuit state at this time is shown in FIG. 28.

[0141] During period T12, transistor M24 is turned off, and transistors M22 and M27 are turned on. Then, the potential of the wiring CKL2 is supplied to terminal OTB via transistors M21 and M22. Also, node NDD is floating. At this time, capacitor C22 functions as a bootstrap capacitance, and the potential of node NDD increases due to capacitive coupling of capacitor C22. If the increase in the potential of node NDD is ΔV2, the potential of node NDD becomes "potential H-Vt24+ΔV2." Also, the potential of wiring VL2 is supplied to terminal OTA via transistors M27 and M26. Therefore, potential L is output to terminal OTA, and "potential H-Vt22" is output to terminal OTB. Because "potential H-Vt22" output to terminal OTB is greater than the threshold voltage of transistor M12, transistor M12 is turned on. The circuit configuration at this time is shown in FIG. 29.

[0142] During period T13, transistors M23, M24, and M25 are turned on, and transistors M22 and M27 are turned off. This causes the potential of node NDD to be at "potential H-Vt24." Because transistor M27 is turned off, the terminal OTA has high impedance. Furthermore, the potential of the wiring VL2 is supplied to terminal OTB via transistor M23, so that potential L is output to terminal OTB. The circuit configuration at this time is shown in FIG. 30.

[0143] During period T14, transistor M24 is turned off, and transistors M22 and M27 are turned on. Then, the potential of node NDD becomes potential L, and transistors M21 and M26 are turned off. Therefore, because transistor M26 is off, the terminal OTA remains at high impedance. Furthermore, because the potential of the wiring VL2 is supplied to the terminal OTB through transistor M23, the potential L continues to be output to the terminal OTB. The circuit state at this time is shown in FIG. 31.

[0144] During period T15, transistor M24 is turned on, and transistors M22 and M27 are turned off. At this time, the potential applied to the gate of transistor M25 (i.e., the potential of node NDB) exceeds "potential H+Vt25," causing the potential of node NDD to become potential H. Then, transistors M21 and M26 are turned on. Therefore, transistor M27 is turned off, and terminal OTA remains at high impedance. Furthermore, the potential of wiring VL2 is supplied to terminal OTB via transistor M23, so that potential L continues to be output to terminal OTB. The circuit state at this time is shown in FIG. 32.

[0145] [Variation 1] The driver circuit of one embodiment of the present invention is not limited to the above structure, and various structures can be used as the driver circuit of one embodiment of the present invention.

[0146] 33 is a circuit diagram illustrating a modification of the drive circuit 100 shown in FIG. 25. The drive circuit 100 shown in FIG. 33 differs from the drive circuit 100 shown in FIG. 25 in that it further includes a transistor M28. In this case, the gate of the transistor M21 is connected to one of the source or drain of the transistor M28 and one terminal of the capacitive element C22. The other of the source or drain of the transistor M28 is connected to one of the source or drain of the transistor M24, one of the source or drain of the transistor M25, and the gate of the transistor M26. The gate of the transistor M28 is connected to the wiring VL1.

[0147] With this configuration, for example, during the period T12, it is possible to prevent a large voltage from being applied to each of the transistors M24, M25, and M26, thereby suppressing breakdown and deterioration of these transistors, thereby improving reliability.

[0148] [Variation 2] FIG. 34 is a circuit diagram illustrating a modification of the driver circuit 100 shown in FIG. 33. The driver circuit 100 shown in FIG. 34 differs from the driver circuit 100 shown in FIG. 33 in that it further includes a transistor M16 and a transistor M17. The other of the source or drain of the transistor M15 is connected to the gate of the transistor M15, one terminal of the capacitor C11, and one of the source or drain of the transistor M16. The other of the source or drain of the transistor M16 is connected to one of the source or drain of the transistor M13 and to the other of the source or drain of the transistor M26 via the terminal OTA. The gate of the transistor M16 is connected to the wiring VL1. The gate of the transistor M11 is connected to one of the source or drain of the transistor M15 and one of the source or drain of the transistor M17. The other of the source or drain of the transistor M17 is connected to one of the source or drain of the transistor M14, the gate of the transistor M23, and the gate of the transistor M25. The gate of the transistor M17 is connected to the wiring VL1. The driving circuit 100 shown in Fig. 34 can be said to have a configuration obtained by combining the driving circuit 100 shown in Fig. 11 and the driving circuit 100 shown in Fig. 33.

[0149] With this configuration, for example, during period T12, application of a large voltage to each of transistors M24, M25, and M26 can be prevented, thereby suppressing breakdown and degradation of these transistors. Furthermore, during period T14, application of a large voltage to each of transistors M13 and M26 can be prevented, thereby suppressing breakdown and degradation of these transistors. Furthermore, during periods T14 and T15, application of a large voltage to each of transistors M14, M23, and M25 can be prevented, thereby suppressing breakdown and degradation of these transistors. This improves reliability.

[0150] [Variation 3] FIG. 35 is a circuit diagram illustrating a modification of the driver circuit 100 shown in FIG. 25. The driver circuit 100 shown in FIG. 35 differs from the driver circuit 100 shown in FIG. 25 in terms of the connections of the transistors M21 and M22. Here, one of the source or drain of the transistor M21 is connected to one of the source or drain of the transistor M23, the other terminal of the capacitor C22, and the gate of the transistor M12 via the terminal OTB. The other of the source or drain of the transistor M21 is connected to one of the source or drain of the transistor M22. The other of the source or drain of the transistor M22 is connected to a wiring CKL2.

[0151] This configuration can prevent a signal applied to the wiring CKL2 from being transmitted to the terminal OTB via the gate capacitance of the transistor M22, thereby preventing noise from occurring, thereby stabilizing operation.

[0152] [Variation 4] Fig. 36 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 25. The drive circuit 100 shown in Fig. 36 differs from the drive circuit 100 shown in Fig. 25 in terms of the connections of the transistors M23 and M25. Here, the gate of the transistor M23 and the gate of the transistor M25 are each connected to one of the source and drain of the transistor M13.

[0153] With this configuration, for example, during period T15, the voltages applied to the transistors M23 and M25 can be reduced, thereby preventing breakdown and degradation of these transistors. For example, the period during which the potentials applied to the gates of the transistors M23 and M25 are high can be shortened, thereby preventing degradation of the transistors. This improves reliability.

[0154] [Variation 5] Fig. 37 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 25. The drive circuit 100 shown in Fig. 37 differs from the drive circuit 100 shown in Fig. 25 in terms of the connection of the transistor M24. Here, the other of the source or the drain of the transistor M24 is connected to a wiring CKL1.

[0155] With this configuration, for example, during period T14, the voltage applied to transistor M24 can be reduced, thereby preventing breakdown and degradation of the transistor. For example, by changing the potential of the other of the source and drain of transistor M24, the period during which the potential difference between the source and drain is large can be shortened, thereby preventing degradation of the transistor. This improves reliability.

[0156] [Variation 6] 38 is a circuit diagram illustrating a modification of the drive circuit 100 shown in FIG. 25. The drive circuit 100 shown in FIG. 38 differs from the drive circuit 100 shown in FIG. 25 in terms of the connections of the transistors M26 and M27. Here, one of the source or drain of the transistor M26 is connected to the wiring VL2. The other of the source or drain of the transistor M26 is connected to one of the source or drain of the transistor M27. The other of the source or drain of the transistor M27 is connected to one of the source or drain of the transistor M13.

[0157] This configuration can prevent the change in the potential of the node NDA and the change in the potential of the node NDD from affecting each other via the gate capacitance of the transistor M26, thereby stabilizing operation.

[0158] [Variation 7] Fig. 39 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 25. The drive circuit 100 shown in Fig. 39 differs from the drive circuit 100 shown in Fig. 25 in terms of the connection of the transistor M12. Here, the other of the source or the drain of the transistor M12 is connected to the wiring VL3.

[0159] With this configuration, for example, by setting the potential applied to the wiring VL3 higher than the potential applied to the wiring VL2, the gate voltage of the transistor M12 can be lower than 0 V in the periods T13 to T15, and the transistor M12 can be reliably turned off. Therefore, the operation can be stabilized. Furthermore, for example, by setting the potential applied to the wiring VL3 lower than the potential applied to the wiring VL2, the gate voltage of the transistor M12 can be increased in the period T12, and the on-state current can be increased. Therefore, the fall time of the potential of the wiring OUTL can be shortened, and the operating speed can be improved.

[0160] [Variation 8] Fig. 40 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 34. The drive circuit 100 shown in Fig. 40 differs from the drive circuit 100 shown in Fig. 34 in that it has a switch S13 instead of the transistor M13, a switch S14 instead of the transistor M14, a switch S22 instead of the transistor M22, a switch S23 instead of the transistor M23, a switch S24 instead of the transistor M24, a switch S25 instead of the transistor M25, and a switch S27 instead of the transistor M27.

[0161] As described above, one embodiment of the present invention may have a structure in which at least some of the transistors included in the driver circuit 100 are replaced with other elements that function as switches.

[0162] [Modification 9] Fig. 41 is a circuit diagram illustrating a modification of the drive circuit 100 shown in Fig. 34. The drive circuit 100 shown in Fig. 41 differs from the drive circuit 100 shown in Fig. 34 in that it has p-channel transistors instead of n-channel transistors.

[0163] As described above, one embodiment of the present invention may have a structure in which the transistors included in the driver circuit 100 are replaced with p-channel transistors. In this case, the relationship in magnitude of potentials in the above description can be appropriately reinterpreted and referred to in the operation of the driver circuit 100.

[0164] It should be noted that two or more of the modifications described above, whether illustrated or not, can be applied to the driving circuit 100 shown in FIG.

[0165] The drive circuit 100 described above, whether illustrated or not, can at least solve the problem of providing a novel drive circuit by its circuit configuration alone.

[0166] One embodiment of the present invention also includes a structure in which at least one of a gate, a source, and a drain of one or more transistors is not connected to anything or is connected to any wiring. Another embodiment of the present invention also includes a structure in which nothing is input to one or more wirings or a signal or potential is input to one or more wirings.

[0167] <Configuration example of semiconductor device> Next, a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the driver circuit according to one embodiment of the present invention can be used for the semiconductor device. In addition, at least a part of the semiconductor device can be used for a display device or the like.

[0168] FIG. 42A is a block diagram illustrating a structural example of a semiconductor device of one embodiment of the present invention.

[0169] 42(A), a semiconductor device 160 includes a pixel section 162, a gate driver section 163, and a source driver section 164. The pixel section 162 includes a plurality of pixels 161 arranged in a matrix of m rows and n columns (m is an integer of 2 or more, and n is an integer of 2 or more), for example.

[0170] The pixel 161 may include a functional element. Here, for example, if the functional element is a display element such as a liquid crystal element or a light-emitting element, the semiconductor device 160 functions as a display device (sometimes referred to as an output device). Furthermore, for example, if the functional element is a light-receiving element, the semiconductor device 160 functions as an imaging device (sometimes referred to as an input device). Note that the pixel 161 may include both a display element and a light-receiving element. In this case, the semiconductor device 160 functions as both a display device and an imaging device (sometimes referred to as an input / output device).

[0171] 42(A), the pixel 161 arranged in the first row and first column is indicated as pixel 161[1,1], the pixel 161 arranged in the first row and nth column is indicated as pixel 161[1,n], the pixel 161 arranged in the mth row and first column is indicated as pixel 161[m,1], and the pixel 161 arranged in the mth row and nth column is indicated as pixel 161[m,n]. Note that the pixel 161 arranged in the uth row and vth column (u is an integer of 1 to m, and v is an integer of 1 to n) may be indicated as pixel 161[u,v]. Note that when describing matters common to each of multiple pixels 161, they may be described without the use of identifying symbols such as "[u,v]".

[0172] The semiconductor device 160 also has m gate lines 165 arranged in parallel, and the potentials of which are controlled by a circuit included in a gate driver unit 163. The potential of each gate line 165 is applied to n pixels 161 arranged in the row direction. Note that a configuration may be adopted in which each gate line 165 includes multiple wirings in accordance with the configuration of the pixels 161.

[0173] The semiconductor device 160 also has n source lines 166 that are arranged in parallel and whose potentials are controlled by a circuit included in a source driver unit 164. The potential of one source line 166 is applied to m pixels 161 arranged in the column direction. Note that a configuration may be adopted in which one source line 166 includes multiple wirings in accordance with the configuration of the pixels 161.

[0174] The circuit included in the gate driver unit 163 functions as, for example, a scanning line driving circuit (sometimes called a gate line driving circuit, gate driver, scan driver, or row driver).

[0175] The circuit included in the source driver unit 164 functions as, for example, a signal line driving circuit (sometimes called a source line driving circuit, a source driver, a data driver, or a column driver).

[0176] FIG. 42B is a block diagram illustrating a modified example of the semiconductor device 160. The semiconductor device 160 shown in FIG. 42B differs from the semiconductor device 160 shown in FIG. 42A in that it includes two gate driver units 163 arranged to face each other across a pixel unit 162. In the configuration shown in FIG. 42B, the potentials of m gate lines 165 are controlled by the two gate driver units 163. With this configuration, for example, the substantial wiring load (parasitic capacitance and parasitic resistance) can be reduced to one-fourth of the wiring load in the semiconductor device 160 shown in FIG. 42A. Therefore, a display device using the semiconductor device 160 can be made faster, more precise, and more highly resolved, with a narrower frame, a larger screen, and the like.

[0177] Note that in one embodiment of the present invention, various transistors can be used as transistors included in the semiconductor device 160. For example, Si transistors, OS transistors, or both Si transistors and OS transistors may be used.

[0178] OS transistors can be easily integrated because they can be freely arranged on, for example, a silicon substrate on which Si transistors are provided. Furthermore, OS transistors can be manufactured at low cost because they can be manufactured using the same manufacturing equipment as Si transistors.

[0179] Therefore, in the semiconductor device 160, for example, Si transistors including a part of a silicon substrate may be used as transistors constituting the source driver unit 164, and OS transistors provided on a silicon substrate may be used as transistors constituting each of the gate driver unit 163 and the pixel unit 162. Note that OS transistors may be used as at least some of the transistors constituting the source driver unit 164, and Si transistors may be used as at least some of the transistors constituting each of the gate driver unit 163 and the pixel unit 162.

[0180] Furthermore, various circuits (which may include an arithmetic circuit, a memory circuit, and the like) that control the operation of the semiconductor device 160 may be provided using Si transistors that include part of the silicon substrate. Thus, one embodiment of the present invention can have a structure in which, for example, an OS transistor is provided over a silicon substrate on which a Si transistor is provided, and a display element or a light-receiving element is provided over a layer on which the OS transistor is provided.

[0181] In one embodiment of the present invention, at least a part of the above-described driver circuit 100 can be used for the gate driver portion 163.

[0182] [Example of gate driver configuration] 43(A) is a circuit diagram illustrating an example in which a plurality of drive circuits 100 are connected to one another in the gate driver section 163. FIG. 43(B) is a circuit block corresponding to the drive circuit 100.

[0183] The gate driver unit 163 has at least m driver circuits 100 (driver circuits 100[1] to 100[m]) to drive the pixels 161 arranged in a matrix of m rows and n columns, row by row. In FIG. 43(A), the driver circuit 100[u-1] in the u-1th row, the driver circuit 100[u] in the u-th row, and the driver circuit 100[u+1] in the u+1th row are illustrated as circuit blocks. When describing matters common to each of the m driver circuits 100, they may be described without the use of identifying symbols such as "[u]."

[0184] The wiring SPL (wiring SPL[u]) of the drive circuit 100 in the u-th row (drive circuit 100[u]) is connected to the wiring OUTL (wiring OUTL[u-1]) of the drive circuit 100 in the u-1th row (drive circuit 100[u-1]). The wiring OUTL (wiring OUTL[u]) of the drive circuit 100 in the u-th row (drive circuit 100[u]) is connected to the wiring SPL (wiring SPL[u+1]) of the drive circuit 100 in the u+1th row (drive circuit 100[u+1]). The wiring CKL2 of the drive circuit 100 in the u-1th row (drive circuit 100[u-1]), the wiring CKL1 of the drive circuit 100 in the u-th row (drive circuit 100[u]), and the wiring CKL2 of the drive circuit 100 in the u+1th row (drive circuit 100[u+1]) are each connected to the wiring CKL_1. The wiring CKL1 of the driving circuit 100 in the u-1th row (driving circuit 100[u-1]), the wiring CKL2 of the driving circuit 100 in the uth row (driving circuit 100[u]), and the wiring CKL1 of the driving circuit 100 in the u+1th row (driving circuit 100[u+1]) are each connected to the wiring CKL_2.

[0185] With this configuration, the gate driver unit 163 can supply signals to the m wirings OUTL (wirings OUTL[1] to OUTL[m]) in order.

[0186] [Pixel section configuration example] FIG. 43C is a circuit diagram illustrating a pixel 161A that uses a light-emitting element LD as a functional element, as an example of the pixel 161 included in the semiconductor device 160.

[0187] FIG. 43(C) shows, as a representative example, the pixel 161A[u,v] in the u-th row and v-th column and the driving circuit 100[u] in the u-th row.

[0188] The pixel 161A[u,v] includes a transistor M31, a transistor M32, a transistor M33, and a light-emitting element LD. One of the source or drain of the transistor M33 is connected to one terminal of the light-emitting element LD. The other of the source or drain of the transistor M33 is connected to one of the source or drain of the transistor M32. The gate of the transistor M33 is connected to a wiring GLb[u] corresponding to the gate line 165. The other terminal of the light-emitting element LD is connected to a wiring CATH. The other of the source or drain of the transistor M32 is connected to a wiring ANO. The gate of the transistor M32 is connected to a wiring that applies a potential corresponding to the potential of one of the source or drain of the transistor M31. The other of the source or drain of the transistor M31 is connected to a wiring SL[v] corresponding to the source line 166. The gate of the transistor M31 is connected to a wiring GLa[u] corresponding to the gate line 165.

[0189] The wiring OUTL[u] is connected to, for example, the wiring GLb[u]. Although not shown, the wiring OUTL[u] may also be connected to, for example, the wiring GLa[u].

[0190] The light emitting element LD emits light with a light emitting intensity according to the amount of current flowing through the light emitting element LD. As the light emitting element LD, for example, an organic EL element can be used.

[0191] The transistor M32 can change its drain current depending on the potential applied to its gate. Therefore, in the pixel 161A[u,v], the transistor M32 has a function of controlling the amount of current flowing through the light-emitting element LD. That is, the transistor M32 has a function of controlling the light-emitting intensity of the light-emitting element LD. In this specification, a transistor having a function similar to that of the transistor M32 may be referred to as a driving transistor.

[0192] The transistor M31 functions as a switch that controls whether or not a data potential is written to the pixel 161A[u,v]. The transistor M33 functions as a switch that controls whether or not a current flows through the light-emitting element LD.

[0193] Although not shown, one of the source or drain of transistor M32 may be connected to one terminal of light-emitting element LD, the other of the source or drain of transistor M32 may be connected to one of the source or drain of transistor M33, and the other of the source or drain of transistor M33 may be connected to wiring ANO.

[0194] Although not shown, the pixel 161A[u,v] may further include a transistor, which can provide a configuration having a function of correcting variations in threshold voltage of the driving transistor, for example.

[0195] In one embodiment of the present invention, various transistors can be used as transistors included in the pixel 161A[u,v]. For example, OS transistors may be used.

[0196] An OS transistor has an extremely low off-state current. Therefore, for example, in the pixel 161A, it is preferable to use an OS transistor as a transistor that functions as a switch. This can reduce the frequency of data rewriting and power consumption, for example.

[0197] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0198] (Embodiment 2) In this embodiment, a transistor according to one embodiment of the present invention will be described. At least part of the transistor described in this embodiment can be applied to the driver circuit, the semiconductor device, or the like described in Embodiment 1.

[0199] <Transistor configuration example 1> FIG. 44(A) is a top view of a transistor 200A. FIG. 44(B) is a cross-sectional view taken along the line A1-A2 indicated by the dashed-dotted line in FIG. 44(A). FIG. 44(C) is a cross-sectional view taken along the line A3-A4 indicated by the dashed-dotted line in FIG. 44(A). Note that some elements are omitted from the top view of FIG. 44(A) for clarity. Some elements may also be omitted from other top views.

[0200] The transistor 200A has an insulating layer 202 over a substrate 201 and a semiconductor layer 203 over the insulating layer 202. The transistor 200A also has an insulating layer 204 over the insulating layer 202 and the semiconductor layer 203. The transistor 200A also has a conductive layer 205 over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have a region where they overlap with each other with the insulating layer 204 interposed therebetween.

[0201] The semiconductor layer 203 has a region 203a that functions as one of the source region and the drain region of the transistor 200A, a channel formation region 203b, and a region 203c that functions as the other of the source region and the drain region. In the semiconductor layer 203, a region that overlaps with the conductive layer 205 functions as the channel formation region 203b. Therefore, the conductive layer 205 functions as the gate electrode of the transistor 200A. The insulating layer 204 functions as a gate insulating film of the transistor 200A.

[0202] In the semiconductor layer 203, the length of the channel formation region 203b in the X direction (corresponding to the distance between the region 203a and the region 203c in the channel formation region 203b) is the channel length Lch of the transistor 200A (see FIGS. 44(A) and 44(B)). In the semiconductor layer 203, the length of the channel formation region 203b in the Y direction (corresponding to the length of the portion where the region 203a and the region 203c face each other in the channel formation region 203b) is the channel width Wch of the transistor 200A (see FIGS. 44(A) and 44(C)).

[0203] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203a of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with a region 203c of the semiconductor layer 203.

[0204] A conductive layer 208a is provided over the insulating layer 206 and in the opening 207a, and a conductive layer 208b is provided over the insulating layer 206 and in the opening 207b. The conductive layer 208a is in contact with the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is in contact with the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as one of a source electrode and a drain electrode of the transistor 200A, and the conductive layer 208b functions as the other of the source electrode and the drain electrode of the transistor 200A.

[0205] Furthermore, an insulating layer 209 is provided on the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0206] <Transistor configuration example 2> 45A is a top view of a transistor 200B. The transistor 200B is a variation of the transistor 200A. To reduce repetition, differences between the transistor 200B and the transistor 200A will be mainly described.

[0207] Fig. 45(B) is a cross-sectional view taken along the line A1-A2 indicated by the dashed line in Fig. 45(A), and Fig. 45(C) is a cross-sectional view taken along the line A3-A4 indicated by the dashed line in Fig. 45(A).

[0208] The transistor 200B differs from the transistor 200A in that a conductive layer 219 is provided between the substrate 201 and the insulating layer 202. The conductive layer 219 overlaps with the channel formation region 203b through the insulating layer 202. Thus, the insulating layer 202 functions as a back-gate insulating film of the transistor 200B, and the conductive layer 219 functions as a back-gate electrode of the transistor 200B. Note that the insulating layer 202 may have a uniform thickness or different thicknesses in a region overlapping with the conductive layer 219 and a region not overlapping with the conductive layer 219. The conductive layer 219 may extend beyond an end of the channel formation region 203b. Note that, although not shown, an insulating layer may be provided between the substrate 201 and the conductive layer 219.

[0209] In a transistor having a back gate, the gate and the back gate of the transistor are arranged to sandwich a channel formation region of the semiconductor layer. The back gate can function in the same manner as the gate. When the gate is used to control the on / off state of the transistor, the potential of the back gate can be the same as that of the gate. Alternatively, the back gate can be set to any potential.

[0210] For example, when a transistor is turned on, supplying a potential that turns the transistor on to both the gate and the back gate can increase the on-state current compared to supplying a potential to only one of them. For example, by connecting the gate and the back gate, the gate and the back gate can always be at the same potential. Furthermore, by controlling the back gate potential independently of the gate potential, the threshold voltage of the transistor can be adjusted.

[0211] A constant potential such as a ground potential may be supplied to the back gate. Since the gate and the back gate are formed of a conductive layer or the like, sandwiching the channel formation region of the semiconductor layer between the gate and the back gate makes it difficult for an electric field generated outside the transistor to act on the channel formation region (also referred to as an "electric field shielding effect"). Therefore, providing a back gate in a transistor stabilizes the operation of the transistor. Furthermore, providing a back gate in a transistor reduces variations in characteristics among multiple transistors. Providing a back gate in a transistor can improve the reliability of the transistor. Therefore, the reliability of a semiconductor device including the transistor can be improved. Note that the electric field shielding effect can be obtained even when one or both of the gate and the back gate are electrically floating (also referred to as a "floating state"), but the effect can be enhanced by supplying a potential to the gate and the back gate.

[0212] <Transistor configuration example 3> Fig. 46(A) is a top view of the transistor 200C. Fig. 46(B) is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 46(A).

[0213] The transistor 200C includes an insulating layer 202 over a substrate 201 and a conductive layer 255 over the insulating layer 202. The transistor 200C also includes an insulating layer 257 over the conductive layer 255, an insulating layer 258 over the insulating layer 257, and an insulating layer 259 over the insulating layer 258. Note that in this specification and the like, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as an insulating layer 256 or a spacer layer. The transistor 200C also includes a conductive layer 261 over the insulating layer 259.

[0214] An opening 262 is provided in the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 in a region overlapping with part of the conductive layer 255. A semiconductor layer 263 is provided in contact with an inner wall of the opening 262.

[0215] The semiconductor layer 263 has a region overlapping with the bottom of the opening 262 and a region overlapping with the inner wall of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 in the opening 262. The semiconductor layer 263 also has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 in the opening 262.

[0216] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 with the insulating layer 264 interposed therebetween.

[0217] Each of the insulating layer 264 and the conductive layer 265 has a region overlapping with the opening 262. In the opening 262, the semiconductor layer 263 has a region overlapping with the conductive layer 265 with the insulating layer 264 interposed therebetween and a region overlapping with the inner wall of the opening 262 (the side surface of the insulating layer 256).

[0218] Furthermore, an insulating layer 266 is provided on the insulating layer 264. The upper surface of the insulating layer 266 is preferably flat. Alternatively, the height (position in the Z direction) of the upper surfaces of the insulating layer 266 and the conductive layer 265 may be the same. For example, the flatness of the upper surface of the insulating layer 266 can be improved by performing a chemical mechanical polishing (CMP) process or the like. Furthermore, the height of the upper surfaces of the insulating layer 266 and the conductive layer 265 can be made the same by performing the CMP process. By performing the CMP process, unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0219] When an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0220] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable to use a material containing oxygen and having reduced hydrogen for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258, which has reduced hydrogen, makes it difficult for the semiconductor layer 263 to become n-type. Furthermore, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 containing oxygen reduces oxygen vacancies in the semiconductor layer 263, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0221] When an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 may contain excess oxygen. In this specification and the like, excess oxygen refers to oxygen that is released by heating. A material that releases oxygen by heating is a material that releases oxygen in terms of oxygen atoms in a thermal desorption spectroscopy (TDS) analysis of 1.0×10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more than 3.0 x 10 20 atoms / cm 3 The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0222] Furthermore, when a material containing excess oxygen is used for the insulating layer 258, it is preferable to use a material that is impermeable to oxygen for the insulating layers 257 and 259. Examples of the material that is impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, and a nitride of silicon. By using a material that is impermeable to oxygen for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is less likely to be released into a lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure may be used in which an insulating layer containing silicon and oxygen (the insulating layer 258) is provided between two insulating layers containing silicon and nitrogen (the insulating layer 257 and the insulating layer 259).

[0223] When an oxide semiconductor is used for the semiconductor layer 263, a material containing hydrogen may be used for the insulating layers 257 and 259. As a result, hydrogen is supplied to a region of the semiconductor layer 263 in contact with the insulating layer 257 and a region of the semiconductor layer 263 in contact with the insulating layer 259, and each region of the semiconductor layer 263 becomes n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of a source region and a drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0224] The conductive layer 261 functions as one of the source electrode or drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode or drain electrode of the transistor 200C. The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source electrode and the drain electrode of the transistor 200C are arranged at different heights. In other words, the source electrode and the drain electrode of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0225] In the above configuration, in the transistor 200C, which is a VFET, the length of the side surface of the insulating layer 258 as viewed in the X direction or the Y direction is the channel length Lch (here, the channel length L1) of the transistor 200C (see FIG. 46(B)). Therefore, the channel length Lch of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0226] Alternatively, the insulating layers 257 and 259 may be formed using a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride or silicon nitride oxide containing very little hydrogen may be used. In this case, the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259 are not made n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 functions as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 functions as the other of the source region and the drain region. The region of the semiconductor layer 263 in contact with the insulating layer 258 functions as a channel formation region.

[0227] In this case, the sum of the lengths of the side surfaces of insulating layer 257, insulating layer 258, and insulating layer 259 as viewed from the X direction or Y direction is the channel length Lch (here, channel length L2) of transistor 200C. Therefore, the channel length Lch of transistor 200C is determined according to the total thickness t2 of insulating layer 257, insulating layer 258, and insulating layer 259. In this way, transistor 200C has a region where the channel formation region is along the side surface of insulating layer 256.

[0228] Furthermore, since the semiconductor layer 263 is provided in the opening 262, the perimeter of the opening 262 when viewed from the Z direction is the channel width Wch of the transistor 200C (see FIG. 46A). The perimeter can be determined, for example, at a position halfway between the thickness t1 or the thickness t2 of the insulating layer 258. Note that the perimeter of any position of the opening 262 may be the channel width Wch as needed. For example, the perimeter of the bottom of the opening 262 may be the channel width Wch, or the perimeter of the top of the opening 262 may be the channel width Wch. Although the outline (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle in FIG. 46A, this is not limiting. For example, the outline of the opening 262 when viewed from the Z direction may be an ellipse or a rectangle.

[0229] Furthermore, it is preferable that the channel length Lch of the transistor 200C is at least smaller than the channel width Wch of the transistor 200C. For example, the channel length Lch can be set to 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width Wch.

[0230] In order to improve the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the inner wall of the opening 262, that is, the taper angle θ of each side surface of the insulating layer 257, the insulating layer 258, and the insulating layer 259, may be set to 45° or more and 90° or less, preferably 50° or more and 75° or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface and the side surface of the layer (see FIG. 46(B)).

[0231] A vertical transistor can occupy a smaller area than a transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane (also called a "horizontal transistor"). Therefore, by using a vertical transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0232] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. On the other hand, in a vertical transistor, the channel length can be set by the film thickness of the insulating layer 256 or 258. Therefore, the channel length of the transistor can be made into an extremely fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more) that is below the exposure limit of photolithography. This increases the on-current of the transistor 200C, thereby improving the frequency characteristics. By using a vertical transistor, a semiconductor device with high operating speed can be provided.

[0233] <Transistor configuration example 4> Fig. 47(A) is a top view of the transistor 200D. Fig. 47(B) is a cross-sectional view taken along the line A1-A2 indicated by the dashed-dotted line in Fig. 47(A). Fig. 47(C) is a cross-sectional view taken along the line A3-A4 indicated by the dashed-dotted line in Fig. 47(A). Note that Fig. 47(B) is a cross-sectional view of the transistor 200D in the channel length direction, and Fig. 47(C) is a cross-sectional view of the transistor 200D in the channel width direction.

[0234] 47(A) to 47(C), the transistor 200D includes a semiconductor layer 520a disposed on a substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed among the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed among the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, the insulating layer 580, and the insulating layer 550. 47(B) and 47(C), the height of the top surface of the conductive layer 560 is the same as the height of the top surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layers 520a, 520b, and 520c may be collectively referred to as semiconductor layers 520. The conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0235] 47A to 47C, an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, and the conductive layer 542b and the insulating layer 580. The insulating layer 554 is in contact with the top surface and side surfaces of the conductive layer 542a, the top surface and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0236] The conductive layer 542a functions as one of a source electrode and a drain electrode of the transistor 200D. The conductive layer 542b functions as the other of the source electrode and the drain electrode of the transistor 200D. In the semiconductor layer 520, a region overlapping with the conductive layer 560 functions as a channel formation region of the transistor 200D. Therefore, the conductive layer 560 functions as a gate electrode of the transistor 200D. The insulating layer 550 functions as a gate insulating film of the transistor 200D.

[0237] Here, the channel formation region of the transistor 200D is formed between a region that functions as one of the source region and the drain region and a region that functions as the other of the source region and the drain region in the semiconductor layer 520. Therefore, the distance between the conductive layer 542a and the conductive layer 542b can be defined as the channel length Lch of the transistor 200D (see FIGS. 47(A) and 47(B)). Also, the length of the portion where the conductive layer 542a and the conductive layer 542b face each other can be defined as the channel width Wch of the transistor 200D (see FIGS. 47(A) and 47(C)).

[0238] Although the transistor 200D has a three-layer structure including the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be provided. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may have a stacked structure of two or more layers.

[0239] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, if the semiconductor layer 520c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide may have a composition similar to that of the semiconductor layer 520b, and the second metal oxide may have a composition similar to that of the semiconductor layer 520a.

[0240] The conductive layer 560 is formed so as to fill the opening formed in the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. The conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening formed in the insulating layer 580. That is, in the transistor 200D, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200D. This reduces the area occupied by the semiconductor device. Furthermore, the integration density of the semiconductor device can be increased.

[0241] 47A to 47C, the conductive layer 560 includes a conductive layer 560a provided over the insulating layer 550 and a conductive layer 560b provided over the conductive layer 560a, both of which are located inside an opening formed in the insulating layer 580. The insulating layer 550 and the conductive layer 560 are embedded in the opening formed in the insulating layer 580. Note that although the conductive layer 560 in the transistor 200D has a two-layer stacked structure, the present invention is not limited thereto. For example, the conductive layer 560 may have a single-layer structure or a three- or more-layer stacked structure.

[0242] The transistor 200D has an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. Furthermore, a semiconductor layer 520a is disposed on the insulating layer 524.

[0243] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200D. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0244] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layers 522, 554, and 574 may be insulating layers having a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like). For example, the insulating layers 522, 554, and 574 may be insulating layers having a lower hydrogen permeability than the insulating layers 524, 550, and 580. Alternatively, the insulating layers 522 and 554 may be insulating layers having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulating layers 522 and 554 may be insulating layers having a lower oxygen permeability than the insulating layers 524, 550, and 580. For example, the insulating layers 522, 554, and 574 may be made of silicon nitride, silicon nitride oxide, or the like.

[0245] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated from the layers above the insulating layer 574 and below the insulating layer 522 by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in the layers above the insulating layer 574 and below the insulating layer 522 can be prevented from mixing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0246] 47B illustrates an example in which a conductive layer 545 (conductive layers 545a and 545b) connected to the transistor 200D and functioning as a plug is provided. Note that an example is shown in which an insulating layer 541 (insulating layers 541a and 541b) is provided in contact with a side surface of the conductive layer 545 functioning as a plug. That is, the insulating layers 541a and 541b are provided in contact with inner walls of two openings formed in the insulating layers 554, 580, 574, and 581. In addition, in FIG. 47B, a first conductive layer of the conductive layer 545 is provided in contact with a side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0247] Here, the height of the top surface of the conductive layer 545 can be approximately the same as the height of the top surface of the insulating layer 581. Note that although the transistor 200D has a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 may have a single layer structure or a stacked structure of three or more layers.

[0248] In addition, the thickness of a region of the semiconductor layer 520b that does not overlap with the conductive layer 542 may be thinner than the thickness of a region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this case, removing the low-resistance region located between the conductive layers 542a and 542b in the semiconductor layer 520b can prevent a channel from being formed in the region.

[0249] Next, the detailed configuration of the transistor 200D will be described.

[0250] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0251] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom and inner wall of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The height of the top surface of the conductive layer 505b is lower than the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0252] When an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c may be formed using a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms. Alternatively, the conductive layer 505a and the conductive layer 505c may be formed using a conductive material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like).

[0253] By using a conductive material that can reduce hydrogen diffusion for the conductive layers 505a and 505c, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, the conductive layer 505a can be formed as titanium nitride.

[0254] Alternatively, the conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0255] When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode. The insulating layers 522 and 524 function as back gate insulating films.

[0256] Note that the conductive layer 505 may be used as a gate electrode. In this case, the conductive layer 560 functions as a back gate electrode. The insulating layers 522 and 524 function as gate insulating films, and the insulating layer 550 functions as a back gate insulating film.

[0257] The conductive layer 505 may be larger than the channel formation region of the semiconductor layer 520. In particular, as shown in FIG. 47C, the conductive layer 505 may extend to a region outside an end portion intersecting with the channel width direction of the semiconductor layer 520. That is, the conductive layer 505 and the conductive layer 560 may overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0258] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0259] The conductive layer 505 may be used as wiring by extending it beyond the edge of the semiconductor layer 520. However, the present invention is not limited to this, and a conductive layer that functions as wiring may be provided under the conductive layer 505.

[0260] The insulating layer 514 may be made of an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200D from the substrate side. Therefore, the insulating layer 514 may be made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., impurity permeability). Alternatively, the insulating layer 514 may be made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen permeability).

[0261] For example, aluminum oxide, silicon nitride, or the like can be used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200D side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing from the insulating layer 514 to the substrate side.

[0262] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like.

[0263] Here, the insulating layer 524 in contact with the semiconductor layer 520 may contain excess oxygen. For example, silicon oxide, silicon oxynitride, or the like can be used for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200D is improved.

[0264] 47(C), the insulating layer 524 may have a thinner film thickness in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b than in other regions. The insulating layer 524 preferably has a film thickness in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b that allows the oxygen to diffuse sufficiently.

[0265] The insulating layer 522 may be formed using a material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200D from the substrate side, similar to the insulating layer 514. For example, the insulating layer 522 may be formed using a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be prevented from entering the transistor 200D from the outside.

[0266] Furthermore, the insulating layer 522 may be made of a material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., is less permeable to oxygen). For example, the insulating layer 522 may be made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen, which can reduce oxygen diffusing from the semiconductor layer 520 to the substrate side. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0267] The insulating layer 522 may be an insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Examples of insulating layers containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200D.

[0268] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Alternatively, a stacked structure of the above insulating layer and silicon oxide, silicon oxynitride, or silicon nitride may be used. For example, the insulating layer 522 may have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0269] The insulating layer 522 may be a single layer or a multilayer of insulating layers containing a high-dielectric-constant (high-k) material (such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST)). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as gate leakage current. By using a material with a high dielectric constant for the insulating layer that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0270] Note that each of the insulating layer 522 and the insulating layer 574 may have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 574 are not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0271] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0272] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 may have a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the semiconductor layer 520 includes at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a may be higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In may be higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c may use a metal oxide that can be used for the semiconductor layer 520a or the semiconductor layer 520b.

[0273] The energy levels of the conduction band minimums of the semiconductor layers 520a and 520c may be higher than the energy level of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layers 520a and 520c may be lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c may be higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In may be higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0274] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c may be reduced.

[0275] Specifically, if the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, contain a common element other than oxygen, a mixed layer with a low defect level density can be formed. For example, if the semiconductor layer 520b is indium gallium zinc oxide (In-Ga-Zn oxide), the semiconductor layers 520a and 520c may be made of In-Ga-Zn oxide, gallium zinc oxide (Ga-Zn oxide), gallium oxide, or the like. The semiconductor layer 520c may also have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide, can be used. In other words, a stacked structure of In-Ga-Zn oxide and an oxide not containing In can be used as the semiconductor layer 520c.

[0276] Specifically, semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. Semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. Semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a structure thereof near it and Ga:Zn=2:1 [atomic ratio] or a structure thereof near it, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a structure thereof near it and Ga:Zn=2:5 [atomic ratio] or a structure thereof near it, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a structure thereof near it and gallium oxide.

[0277] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect state density at the interface between the semiconductor layers 520a and 520b and at the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200D to achieve a large on-state current and high frequency characteristics. Note that when the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the semiconductor layers 520b and 520c, the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, the semiconductor layer 520c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, thereby suppressing In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating film, and diffusion of In can cause poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0278] A conductive layer 542 (conductive layer 542a and conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 may be formed using a conductive material that is not easily oxidized or a conductive material that maintains its conductivity even after absorbing oxygen.

[0279] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200D. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with an opening formed in the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0280] The insulating layer 550 functions as a gate insulating film. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. For example, the insulating layer 550 can be formed using silicon oxide or silicon oxynitride.

[0281] The insulating layer 550 may be formed using an insulating material with a reduced concentration of impurities such as water or hydrogen, similar to the insulating layer 524. The thickness of the insulating layer 550 may be greater than or equal to 1 nm and less than or equal to 20 nm.

[0282] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This suppresses oxidation of the conductive layer 560 by oxygen contained in the insulating layer 550.

[0283] Although the conductive layer 560 is shown as having a two-layer structure in FIGS. 47A to 47C, it may have a single-layer structure or a stacked structure of three or more layers.

[0284] The conductive layer 560a may be made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, the conductive layer 560a may be made of a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0285] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0286] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. Furthermore, the conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0287] 47(B) and 47(C), in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the conductive layer 560 is arranged to cover the side surface of the semiconductor layer 520. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200D, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200D and improves its frequency characteristics.

[0288] The insulating layer 554 may be formed using an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200D, similar to the insulating layer 514. For example, the insulating layer 554 may be formed using an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 47B and 47C, the insulating layer 554 is provided in contact with the side surface of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. With this structure, hydrogen contained in the insulating layer 580 can be prevented from entering the semiconductor layer 520.

[0289] Furthermore, an insulating material that has a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is less permeable) may be used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 may be used for the insulating layer 554.

[0290] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 may be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 in the vicinity of a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region to the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, and suppresses the transistor from becoming normally on.

[0291] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium may be formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0292] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0293] As for the insulating layer 574, similar to the insulating layer 514, an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulating layer 580 from above may be used. For example, the insulating layer 574 may be formed using an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like.

[0294] 47A to 47C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced may be used, similar to the insulating layer 524.

[0295] A conductive layer 545a and a conductive layer 545b are disposed in two openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layer 545a and the conductive layer 545b face each other with the conductive layer 560 interposed therebetween. Note that the height of the top surfaces of the conductive layer 545a and the conductive layer 545b may be the same as the height of the top surface of the insulating layer 581.

[0296] Note that insulating layer 541a is provided in contact with the inner wall of one of the two openings formed in insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554, and a first conductive layer of conductive layer 545a is formed in contact with the side surface of insulating layer 541a. Conductive layer 542a is located in at least a part of the bottom of the opening, and conductive layer 545a is in contact with conductive layer 542a. Similarly, insulating layer 541b is provided in contact with the inner wall of the other of the two openings formed in insulating layer 581, insulating layer 574, insulating layer 580, and insulating layer 554, and a first conductive layer of conductive layer 545b is formed in contact with the side surface of insulating layer 541b. Conductive layer 542b is located in at least a part of the bottom of the opening, and conductive layer 545b is in contact with conductive layer 542b.

[0297] The conductive layer 545a and the conductive layer 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layer 545a and the conductive layer 545b may have a stacked structure of two or more layers.

[0298] When the conductive layer 545 has a stacked-layer structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used in a conductive layer in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. The use of such a conductive material can suppress absorption of oxygen contained in the insulating layer 580 by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be suppressed from entering the semiconductor layer 520 through the conductive layers 545a and 545b.

[0299] The insulating layer 541a and the insulating layer 541b may be, for example, an insulating layer that can be used for the insulating layer 554. The insulating layer 541a and the insulating layer 541b are provided in contact with the insulating layer 554, and thus impurities such as water or hydrogen from the insulating layer 580 or the like can be prevented from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0300] <Transistor configuration example 5> FIG. 48 shows a modification of transistor 200D shown in FIG. 47. FIG. 48(A) is a top view of transistor 200E, which is a modification of transistor 200D. FIG. 48(B) is a cross-sectional view taken along line A1-A2 indicated by the dashed-dotted line in FIG. 48(A). FIG. 48(C) is a cross-sectional view taken along line A3-A4 indicated by the dashed-dotted line in FIG. 48(A). Since transistor 200E is a modification of transistor 200D, differences between transistor 200E and transistor 200D will be mainly described.

[0301] The transistor 200E has a configuration in which the semiconductor layer 520c and the conductive layer 505c are removed from the configuration of the transistor 200D. Reducing the number of transistor components reduces production costs. Furthermore, reducing the number of transistor components shortens the manufacturing process, improving manufacturing yield.

[0302] Furthermore, the transistor 200E has a region where the insulating layer 554 and the insulating layer 522 are in contact with each other outside the semiconductor layer 520, and has a structure in which the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used for the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing from the semiconductor layer 520 to the outside through the insulating layer 524 but also prevents excessive oxygen from being supplied to the semiconductor layer 520 from the insulating layer 524 side.

[0303] Note that an insulating layer may be provided between the insulating layer 550 and the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b. Aluminum oxide, hafnium oxide, or the like can be used as the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the semiconductor layer 520 to the insulating layer 550, excessive supply of oxygen from the insulating layer 550 to the semiconductor layer 520, oxidation of the conductive layer 542, and the like.

[0304] <Transistor constituent materials> Next, constituent materials that can be used for the transistor 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, and transistor 200E) will be described.

[0305] 〔substrate〕 When a transistor is provided on a substrate, the material used for the substrate is not particularly limited. The material used for the substrate can be determined depending on the purpose, taking into consideration the presence or absence of light transparency and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as the substrate. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like may also be used as the substrate.

[0306] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region within the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0307] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Other examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are also substrates in which a conductive layer or a semiconductor layer is provided on an insulator substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate.

[0308] Examples of materials that can be used for flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0309] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, a substrate having elements provided on it may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0310] [Insulating layer] An inorganic insulating film can be used for the insulating layers (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 257, insulating layer 258, insulating layer 259, insulating layer 264, insulating layer 266, insulating layer 516, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0311] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0312] For example, as transistors become more miniaturized and highly integrated, thinner gate insulating films can cause problems such as gate leakage current. Using a high-k (high-dielectric-constant) material for insulating layers that function as gate insulating films, such as insulating layer 204 and insulating layer 202, enables lower voltage operation of the transistor while maintaining the physical film thickness. This also enables a thinner equivalent oxide thickness (EOT) of the gate insulating film. Furthermore, using a material with a high dielectric constant for the insulating layer that functions as the dielectric of the capacitive element increases the capacitance per unit area. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as the interlayer film reduces the parasitic capacitance between wiring. Therefore, materials can be selected according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0313] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0314] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0315] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 255, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in the transistor 200, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. The alloy containing any of the above metal elements may be a nitride of the alloy or an oxide of the alloy. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Also, semiconductors with high conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0316] It is also preferable to use a conductive material that is resistant to oxidation, a conductive material that has the function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen. Examples of such materials include nitrogen-containing conductive materials such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride. Examples of oxygen-containing conductive materials include ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Examples of oxygen-containing conductive materials include materials containing tungsten oxide and indium oxide, materials containing titanium oxide and indium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0317] Furthermore, as a material with high conductivity, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

[0318] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0319] For example, in the transistor 200A or 200B, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, a conductive layer functioning as a gate electrode, such as the conductive layer 205 or the conductive layer 219, may have a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen may be provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, oxygen desorbed from the conductive material is easily supplied to a channel formation region of the semiconductor layer 203.

[0320] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, the semiconductor layer 263, or the semiconductor layer 520, the conductive layers 208a, 208b, 255, 261, 542a, and 542b in contact with the semiconductor layer 203, the semiconductor layer 263, or 520 may be formed using a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b.

[0321] By using a conductive material containing oxygen for the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductive layers 208a, 208b, 255, 261, 542a, and 542b, the conductive layers can maintain their conductivity even when they absorb oxygen. For example, even when insulating layers containing excess oxygen are used as insulating layers in contact with the conductive layers 208a, 208b, 255, 261, 542a, and 542b, this is preferable because the conductive layers 208a, 208b, 255, 261, 542a, and 542b can maintain their conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like can be used for each of the conductive layer 208a, the conductive layer 208b, the conductive layer 255, the conductive layer 261, the conductive layer 542a, and the conductive layer 542b.

[0322] [Semiconductor layer] As the semiconductor layer (semiconductor layer 203, semiconductor layer 263, semiconductor layer 520, etc.), a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.

[0323] The semiconductor layer may be a semiconductor made of a single element or a compound semiconductor. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide, silicon carbide, and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0324] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0325] For example, in transistor 200A or 200B, by using silicon for the semiconductor layer 203 and adding phosphorus or arsenic as an n-type dopant to regions 203a and 203c of the semiconductor layer 203, the transistor can function as an n-type transistor. Also, by adding boron as a p-type dopant to regions 203a and 203c of the semiconductor layer 203, the transistor can function as a p-type transistor. Note that when regions 203a and 203c of the semiconductor layer 203 contain both an n-type dopant and a p-type dopant, the conductivity type with the higher dopant concentration is more likely to be realized.

[0326] Alternatively, a two-dimensional material that functions as a semiconductor may be used as the semiconductor layer. Two-dimensional materials, also known as layered materials, are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high conductivity within each layer, i.e., high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity for the semiconductor layer, a transistor with a high on-state current can be provided.

[0327] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable to the semiconductor layer include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0328] Alternatively, an oxide semiconductor, which is a type of metal oxide, may be used for the semiconductor layer. In this case, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer, the off-state current of the transistor can be significantly reduced. Since the OS transistor has a small off-state current, the power consumption of the semiconductor device can be reduced.

[0329] In a transistor using an oxide semiconductor for a semiconductor layer, it is preferable that the channel formation region of the transistor has fewer oxygen vacancies or a lower impurity concentration (for example, the concentration of hydrogen, nitrogen, and metal elements) than the source and drain regions. O H (oxygen vacancy with hydrogen) is formed, and electrons that act as carriers may be generated. O It is also preferable that the amount of H is small. As described above, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0330] In addition, the source and drain regions of the transistor have more oxygen vacancies than the channel formation region. O It is preferable that the amount of H is large or the impurity concentration is high. In this way, the source region and drain region of the transistor are n-type regions with a higher carrier concentration and a lower resistance than the channel formation region.

[0331] Note that the oxide semiconductor will be described in detail in Embodiment 3 to be described later.

[0332] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0333] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0334] <Oxide semiconductor layer> The oxide semiconductor layer preferably contains a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (Polycrystalline) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0335] The oxide semiconductor layer preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) are c-axially oriented and connected without being oriented in the ab plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0336] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or a combination of these techniques may be used for analysis.

[0337] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0338] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In). The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, such as a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M is gallium, the metal oxide preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may include metalloid elements.

[0339] Examples of metal oxides include indium oxide. Examples of metal oxides include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum Examples of usable materials include aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon oxide (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0340] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide (also referred to as the indium (In) content), the transistor can have large on-state current and high frequency characteristics.

[0341] The metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements with higher period numbers in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0342] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0343] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0344] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0345] In the present embodiment, an In-Ga-Zn oxide may be used as an example of the metal oxide.

[0346] [Production method] The oxide semiconductor layer can be fabricated by forming a metal oxide using one type of film formation method, or by forming a metal oxide using at least two types of film formation methods. For example, the oxide semiconductor layer can be fabricated by forming a metal oxide using a first film formation method or a second film formation method, or by forming a metal oxide using the first film formation method and the second film formation method. Note that an oxide semiconductor layer formed using at least two types of film formation methods may be referred to as a hybrid OS.

[0347] The oxide semiconductor layer can be manufactured by forming a metal oxide as a first layer by a first deposition method, and then forming a metal oxide as a second layer on the first layer by a second deposition method. The first deposition method is preferably a deposition method that causes less damage to the surface on which the oxide semiconductor layer is to be formed than the second deposition method. By using the deposition method that causes less damage to the surface on which the oxide semiconductor layer is to be formed as the first deposition method, formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer, which can increase the crystallinity of the oxide semiconductor layer.

[0348] Examples of the first film formation method include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-CVD, and metal organic CVD (MOCVD). Examples of wet methods include spray coating. Compared to the sputtering method described below, the ALD and CVD methods are suitable as the first film formation method because they can reduce damage to the surface to be formed.

[0349] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0350] The ALD method allows for the deposition of atoms layer by layer, enabling the formation of ultrathin films, the formation of films on high-aspect-ratio structures or surfaces with large steps, the formation of films with fewer defects such as pinholes, the formation of films with excellent coverage, and the formation of films at low temperatures. Furthermore, the PEALD method, by utilizing plasma, may be preferable because it allows for film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Note that when the ALD method employs high substrate temperatures during film formation and / or impurity removal treatment, the amount of carbon and chlorine contained in the film may be lower than when the ALD method is used without these treatments.

[0351] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0352] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0353] Examples of the second film formation method include sputtering, pulsed laser deposition (PLD), etc. Metal oxides formed using the second film formation method tend to have a CAAC structure.

[0354] Here, the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure. Even in such a case, by forming a second layer (e.g., CAAC) having higher crystallinity on the first layer having lower crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased, with the second layer acting as a nucleus. This can increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0355] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0356] The oxide semiconductor layer can be fabricated by, for example, forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and forming a metal oxide as a third layer using the first deposition method. Specifically, the ALD method can be used as the first deposition method, and the sputtering method can be used as the second deposition method. The ALD method is a deposition method with superior coverage compared to the sputtering method, and using the ALD method as the deposition method for the first and third layers can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio.

[0357] An example of a method for manufacturing the semiconductor layer 230 will be described with reference to FIGS. 49A to 49D and 50A to 50D.

[0358] When a metal oxide film is formed by a sputtering method, alloying may occur between components contained in the metal oxide film and components contained in the layer on which the film is formed due to damage caused by sputtering particles on the surface on which the film is formed or by energy imparted to the substrate by the sputtering particles. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is formed.

[0359] Therefore, first, a semiconductor layer 230a is formed on the layer 229 by ALD (FIG. 49(A)). Subsequently, a semiconductor layer 230b is formed on the semiconductor layer 230a by sputtering (FIG. 49(B)).

[0360] In the method for manufacturing an oxide semiconductor layer described in this embodiment, the semiconductor layer 230a is formed between the semiconductor layer 230b and the layer 229 by a deposition method that causes little damage to a surface on which the semiconductor layer 230a is formed. This prevents alloying of components contained in the semiconductor layer 230 and components contained in the layer 229, thereby enabling the semiconductor layer 230 to have higher crystallinity.

[0361] By using the above configuration, the thickness of the alloyed region can be reduced, or made so thin that it is difficult to observe the alloyed region. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 49(A) and 49(B) show an example in which no alloyed region is formed between the layer 229 and the semiconductor layer 230a.

[0362] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0363] For example, EDX line analysis is performed on the above region and its periphery, with the direction perpendicular to the surface of the semiconductor layer 230a to be formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (In, if the semiconductor layer 230a contains In) that is the main component of the semiconductor layer 230a but is not the main component of the layer that will become the surface to be formed (here, layer 229) becomes half-value is defined as the depth (position) of the interface between the above region and the semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface to be formed but is not the main component of the semiconductor layer 230a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that will become the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0364] When the thickness of the alloyed region in the oxide semiconductor layer is observed by EDX analysis, the thickness is, for example, 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0365] For example, when a silicon oxide layer is used as the layer 229 and a SIMS analysis is performed on the semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0 × 10 20 atoms / cm 3 The distance between the depth at which the thickness decreases and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0366] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0367] By reducing the thickness of the alloyed region, it becomes possible to form the CAAC structure near the surface where the structure is to be formed. Here, "near the surface where the structure is to be formed" refers to, for example, a region of more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, perpendicularly from the surface where the semiconductor layer 230 is to be formed.

[0368] The CAAC structure near the surface to be formed can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of the semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed near the surface to be formed.

[0369] When the semiconductor layer 230a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 49(A), the semiconductor layer 230a may have a region having lower crystallinity than the semiconductor layer 230b.

[0370] The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure.

[0371] When the semiconductor layer 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the semiconductor layer 230a. Furthermore, when the semiconductor layer 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, and at least a portion of the semiconductor layer 230a may be crystallized.

[0372] It is preferable to heat the substrate when forming the semiconductor layer 230b by sputtering. In forming the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, it may be possible to form a metal oxide with high crystallinity.

[0373] Next, the semiconductor layer 230c is formed on the semiconductor layer 230b by the ALD method (FIG. 49(C)). For the formation of the semiconductor layer 230c by the ALD method, the method for forming the semiconductor layer 230a can be referred to.

[0374] When the semiconductor layer 230c is formed on the semiconductor layer 230b having the CAAC structure by the ALD method, the semiconductor layer 230c may grow epitaxially using the semiconductor layer 230b as a nucleus. Therefore, when the semiconductor layer 230c is formed, the semiconductor layer 230c may have a region having the CAAC structure. Furthermore, it is preferable that the region having the CAAC structure is formed over the entire semiconductor layer 230c.

[0375] Next, a heat treatment process may be performed. This heat treatment process may enhance the crystallinity of the region having the CAAC structure in the semiconductor layer 230c. Furthermore, if the region is formed only below the semiconductor layer 230c after film formation by the ALD method, this heat treatment process may cause the region to expand upward (FIG. 49(D)). That is, this heat treatment may cause the region having the CAAC structure to be formed throughout the entire semiconductor layer 230c.

[0376] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is converted into CAAC by this heat treatment process (FIG. 49(D)). The CAAC is more likely to occur because the mixed layer 231 formed in the semiconductor layer 230a during the deposition of the semiconductor layer 230b acts as a nucleus or seed. It is preferable that the region in the semiconductor layer 230a that is converted into CAAC is large, and it is preferable that the CAAC is converted up to the vicinity of the layer 229.

[0377] Furthermore, because the CAAC process is performed from the top to the bottom of the semiconductor layer 230a, the CAAC process can be performed up to the vicinity of the layer 229 without being limited by the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the semiconductor layer 230a can be formed with high crystallinity. Therefore, the method for manufacturing an oxide semiconductor layer described in this embodiment is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0378] 49(A) to 49(D) are cross-sectional views illustrating a metal oxide film formation method. Also, FIGS. 49(A) to 49(D) can be regarded as conceptual diagrams illustrating a metal oxide film formation model. As shown in FIGS. 49(A) to 49(D), the semiconductor layers 230a and 230c each have high crystallinity using the highly crystalline semiconductor layer 230b as a nucleus or seed. Specifically, the crystallinity of the semiconductor layer 230a may be increased by heat treatment during the formation of the semiconductor layer 230b or after the formation of the semiconductor layer 230c. The crystallinity of the semiconductor layer 230c may be increased by heat treatment during the formation of the semiconductor layer 230c or after the formation of the semiconductor layer 230c. The heat treatment has an assisting effect of increasing crystallinity.

[0379] As described above, in the metal oxide film formation method described in this embodiment, the semiconductor layer 230b (e.g., CAAC) with high crystallinity can be used as a nucleus or seed to increase the crystallinity of the upper and lower oxide semiconductors (here, the semiconductor layer 230a and the semiconductor layer 230c). This increases the crystallinity of the entire oxide semiconductor. In other words, the semiconductor layer 230b can be used as a nucleus or seed to perform solid-phase growth of the upper and lower oxide semiconductors, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed using such a film formation method, i.e., a CAAC film, can be referred to as an axial growth CAAC (AG CAAC). Note that although FIGS. 50A to 50D illustrate a structure including the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c, this is not limiting. For example, a structure including the semiconductor layer 230a and the semiconductor layer 230b can also be referred to as an AG CAAC.

[0380] In the semiconductor layer 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. FIG. 50(A) shows the state in which the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c are each crystallized. At this time, the boundary between the semiconductor layer 230a and the semiconductor layer 230b may not be observed. Also, the boundary between the semiconductor layer 230b and the semiconductor layer 230c may not be observed. The semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observed. The semiconductor layer 230 may be expressed as a single layer.

[0381] Furthermore, there are cases where a portion of the semiconductor layer 230a or the semiconductor layer 230c is not crystallized. The example shown in Figure 50(B) shows that the vicinity of the interface with the layer 229 in the semiconductor layer 230a is not crystallized. Figure 50(C) shows that the vicinity of the surface in the semiconductor layer 230c is not crystallized. Figure 50(D) shows that the vicinity of the interface with the layer 229 in the semiconductor layer 230a and the vicinity of the surface of the semiconductor layer 230c are not crystallized.

[0382] By increasing the crystallinity of the oxide semiconductor layer, the initial characteristics (particularly, on-state current) of a transistor including the oxide semiconductor layer can be improved, making the transistor suitable for high-speed operation.Furthermore, the reliability of the transistor can be improved, and the on-state current can be increased.

[0383] The oxide semiconductor layer described in this embodiment has high crystallinity throughout the entire layer. Therefore, in the semiconductor layer 230, it may be difficult to confirm the boundaries between the stacked films of the semiconductor layer 230a, the semiconductor layer 230b, and the semiconductor layer 230c. In particular, it may be difficult to confirm the boundaries between the stacked films after heat treatment. The presence or absence of boundaries between the stacked films can be confirmed using, for example, a TEM.

[0384] Here, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, oxide semiconductors with a high In content tend to become polycrystalline. Using a metal oxide with a polycrystalline structure in a transistor can adversely affect the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the semiconductor layers 230a and 230c, crystals that reflect the crystal orientation of the semiconductor layer 230b are formed, and polycrystallization can be suppressed.

[0385] At this time, it is preferable that the lattice mismatch between the crystals of semiconductor layer 230b and the crystals of semiconductor layer 230a or semiconductor layer 230c is small. This allows semiconductor layer 230a or semiconductor layer 230c to form crystals that reflect the orientation of the crystals of semiconductor layer 230b. At this time, for example, when a cross section of semiconductor layer 230 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in semiconductor layer 230a or semiconductor layer 230c.

[0386] Note that the crystal structure of the semiconductor layer 230a or 230c is not particularly limited as long as the lattice mismatch between the crystal of the semiconductor layer 230b and the crystal of the semiconductor layer 230a or 230c is small. The crystal structure of the semiconductor layer 230a or 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0387] 〔composition〕 The semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The semiconductor layer 230b can be formed by, for example, sputtering. The semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the metal oxide becomes highly crystalline. Furthermore, the semiconductor layer 230b preferably contains the element M in addition to zinc. By containing the element M in the semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor using an oxide semiconductor layer can be improved. Specifically, the semiconductor layer 230b may be made of a metal oxide having an In:M:Zn=1:1:1 atomic ratio or a similar composition, an In:M:Zn=1:1:1.2 atomic ratio or a similar composition, an In:M:Zn=1:1:0.5 atomic ratio or a similar composition, an In:M:Zn=1:1:2 atomic ratio or a similar composition, an In:M:Zn=4:2:3 atomic ratio or a similar composition, an In:M:Zn=1:3:2 atomic ratio or a similar composition, or an In:M:Zn=1:3:4 atomic ratio or a similar composition. Note that a similar composition includes a range of plus or minus 30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0388] The semiconductor layer 230b may also be configured to not contain the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, the semiconductor layer 230b may be configured to not contain the elements M or Zn. For example, indium oxide may be used. It may also be configured to contain a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. It may also have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0389] The semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a high proportion of In. The semiconductor layer 230a and the semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0390] The semiconductor layer 230a and the semiconductor layer 230c may be configured to not contain the element M. For example, they may be made of In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto, a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto. Alternatively, the semiconductor layer 230a and the semiconductor layer 230c may be configured to not contain the elements M and Zn. For example, indium oxide may be used. The semiconductor layer 230a and the semiconductor layer 230c may be configured to contain a trace amount of the element M. Specifically, the composition can be In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition close thereto, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition close thereto.

[0391] Increasing the atomic ratio of zinc contained in the oxide semiconductor can improve the crystallinity of the oxide semiconductor. It is particularly preferable that the semiconductor layer 230a contains zinc. For example, when the semiconductor layer 230a is formed by an ALD method and the semiconductor layer 230b is formed by a sputtering method, zinc contained in the semiconductor layer 230a may diffuse into the semiconductor layer 230b. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b can improve the crystallinity of the semiconductor layer 230b. Alternatively, the diffusion of zinc from the semiconductor layer 230a to the semiconductor layer 230b can promote the lateral growth of crystal parts having c-axis orientation in the semiconductor layer 230b, thereby promoting the formation of CAAC.

[0392] Furthermore, the semiconductor layer 230a and the semiconductor layer 230c can be made of a metal oxide having a higher proportion of In than the semiconductor layer 230b.

[0393] Alternatively, for example, the semiconductor layers 230a and 230c may be made of a metal oxide having a higher Ga content than the semiconductor layer 230b. For example, the semiconductor layers 230a and 230c may be made of a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition similar thereto, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition similar thereto, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition similar thereto. Increasing the Ga content may result in the band gaps of the semiconductor layers 230a and 230c being larger than those of the semiconductor layer 230b. This allows the semiconductor layer 230b to be sandwiched between the semiconductor layers 230a and 230c, which have larger band gaps, and the semiconductor layer 230b functions primarily as a current path. By sandwiching the semiconductor layer 230b between the semiconductor layers 230a and 230c, it is possible to reduce trap levels at the interface of the semiconductor layer 230b and in the vicinity thereof, thereby realizing a buried channel type transistor in which the channel is kept away from the insulating layer interface, and thus increasing the field effect mobility.

[0394] Furthermore, even when the semiconductor layers 230a and 230c are made of a composition that makes it difficult to form a CAAC structure when formed as a single layer, crystal growth occurs with the semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the semiconductor layers 230a and 230c can have a CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a portion of each of the semiconductor layers 230a and 230c and the semiconductor layer 230b.

[0395] In particular, even when the semiconductor layers 230a and 230c have a composition with a high In content, they can have suitable crystallinity for use as semiconductor layers of transistors. In the oxide semiconductor layer described in this embodiment, the increase in the In content can improve the on-state characteristics of the transistor, while the CAAC structure with high crystallinity can improve reliability.

[0396] The semiconductor layer 230a and the semiconductor layer 230c may have different compositions.

[0397] The semiconductor layer 230a and the semiconductor layer 230c may be made of a metal oxide having the same composition as the semiconductor layer 230b.

[0398] In this way, by using the oxide semiconductor layer having the CAAC structure formed by the above-described two types of film formation methods in the channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0399] The composition of the metal oxide used in the semiconductor layer 230 can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0400] [Crystalline] The degree of crystallinity of an oxide semiconductor layer can be evaluated using, for example, crystal orientation.

[0401] Crystal orientation can be determined from the Fast Fourier Transform (FFT) pattern obtained by processing a TEM image. Specifically, the direction of the crystal axis can be determined using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice spatial information similar to that of an electron diffraction pattern.

[0402] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystalline orientation of each region can be obtained. For example, by obtaining the crystalline orientation for each region within a certain area, a map showing the crystalline orientation can be created. Specifically, two spots with high intensity are observed in the FFT pattern of a region having layered crystalline parts. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0403] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing the crystal orientation.

[0404] The c-axis orientation rate of an oxide semiconductor layer can be calculated, for example, by performing TEM observation of a cross section or a plane of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. The region where FFT is performed is not limited to a circle.

[0405] In the oxide semiconductor layer, when the c-axis orientation rate is calculated as the percentage of regions whose difference from the c-axis is within 20°, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0406] The c-axis orientation rates of the region formed as semiconductor layer 230a, the region formed as semiconductor layer 230b, and the region formed as semiconductor layer 230c are defined as Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0407] After the semiconductor layer 230 is fabricated, the boundaries between the semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0408] The semiconductor layer 230 can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region is a layer-like region.

[0409] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rates of the second region and the third region are each 80% or higher, more preferably 90% or higher, and even more preferably 95% or higher.

[0410] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229, and the third region is located at a distance of 0 nm to 3 nm from the top surface of the semiconductor layer 230.

[0411] Alternatively, the layer thickness in each region may be the same, for example.

[0412] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0413] (Fourth embodiment) In this embodiment, an example of a layout in the case where the transistor described in Embodiment 2 is applied to the driver circuit described in Embodiment 1 will be described.

[0414] <Layout example> Fig. 51 is a top view showing an example of a layout when transistor 200A shown in Fig. 44 is used as a transistor constituting drive circuit 100 shown in Fig. 25. Fig. 52(A) is a cross-sectional view taken along line A1-A2 indicated by a dashed line in Fig. 51. Fig. 52(B) is a cross-sectional view taken along line A3-A4 indicated by a dashed line in Fig. 51.

[0415] 51 and the like illustrate semiconductor layers os01, os02, os04, os05, os06, os07, os08, and os09, which correspond to the semiconductor layer 203 on the insulating layer 202. Also illustrated are conductive layers ge01, ge02, ge03, ge04, ge05, ge06, ge07, ge08, ge09, ge10, ge11, and ge12, which correspond to the conductive layer 205 on the insulating layer 204. Also shown are conductive layers me01, me02, me03, me04, me05, me06, me09, me10, me11, me12, me13, me14, me15, me16, me17, me18, me19, me20, me21, and me22, which correspond to conductive layer 208 on insulating layer 206.

[0416] The semiconductor layer os01 and the semiconductor layer os02 each have a region that functions as a channel formation region for the transistor M11 and a region that functions as a channel formation region for the transistor M12. The semiconductor layer os04 has a region that functions as a channel formation region for the transistor M15. The semiconductor layer os05 has a region that functions as a channel formation region for the transistor M26 and a region that functions as a channel formation region for the transistor M27. The semiconductor layer os06 has a region that functions as a channel formation region for the transistor M13 and a region that functions as a channel formation region for the transistor M14. The semiconductor layer os07 has a region that functions as a channel formation region for the transistor M24 and a region that functions as a channel formation region for the transistor M25. The semiconductor layer os08 has a region that functions as a channel formation region for the transistor M21 and a region that functions as a channel formation region for the transistor M22. The semiconductor layer os09 has a region that functions as a channel formation region for the transistor M23.

[0417] The conductive layer ge01 has a region that functions as the gate of the transistor M11, a region that functions as the gate of the transistor M23, a region that functions as the gate of the transistor M25, and a region that functions as the node NDB. The conductive layer ge02 has a region that functions as the gate of the transistor M12 and a region that functions as the node NDC. The conductive layer ge03 has a region that functions as the wiring VL2a corresponding to the wiring VL2. The conductive layer ge04 has a region that functions as the wiring SPL. The conductive layer ge05 has a region that functions as the gate of the transistor M27, a region that functions as the other terminal of the capacitor C11, and a region that functions as the wiring CKL2. The conductive layer ge06 has a region that functions as the gate of the transistor M15 and a region that functions as the node NDA. The conductive layer ge07 has a region that functions as the gate of the transistor M21, a region that functions as the gate of the transistor M26, a region that functions as one terminal of the capacitor C22, and a region that functions as the node NDD. The conductive layer ge08 has a region that functions as the wiring VL2b corresponding to the wiring VL2. The conductive layer ge09 has a region that functions as the gate of the transistor M13, a region that functions as the gate of the transistor M14, a region that functions as the gate of the transistor M24, and a region that functions as the wiring CKL1. The conductive layer ge10 has a region that functions as the gate of the transistor M22 and a region that functions as the wiring CKL2. The conductive layer ge11 has a region that functions as the wiring CKL1. The conductive layer ge12 has a region that functions as the wiring VL2b corresponding to the wiring VL2.

[0418] The conductive layer me01 has a region that functions as either the source or the drain of the transistor M11, a region that functions as either the source or the drain of the transistor M12, and a region that functions as the wiring OUTL. The conductive layer me02 has a region that functions as the other of the source or the drain of the transistor M11 and a region that functions as the wiring VL1a corresponding to the wiring VL1. The conductive layer me03 has a region that functions as the wiring VL2a corresponding to the wiring VL2. The conductive layer me04 has a region that functions as the other of the source or the drain of the transistor M12 and a region that functions as the wiring VL2a corresponding to the wiring VL2. The conductive layer me05 has a region that functions as the wiring SPL. The conductive layer me06 has a region that functions as either the source or the drain of the transistor M13, a region that functions as the other of the source or the drain of the transistor M15, a region that functions as the other of the source or the drain of the transistor M26, a region that functions as one terminal of the capacitor C11, and a region that functions as the node NDA. The conductive layer me09 has a region that functions as the other of the source and drain of transistor M27 and a region that functions as wiring VL2b corresponding to wiring VL2. The conductive layer me10 has a region that functions as one of the source and drain of transistor M15 and a region that functions as node NDB. The conductive layer me11 has a region that functions as the other of the source and drain of transistor M13, a region that functions as the other of the source and drain of transistor M14, and a region that functions as wiring SPL. The conductive layer me12 has a region that functions as one of the source and drain of transistor M14 and a region that functions as node NDB. The conductive layer me13 has a region that functions as wiring CKL1. The conductive layer me14 has a region that functions as wiring CKL2. The conductive layer me15 has a region that functions as wiring VL2b corresponding to wiring VL2. The conductive layer me16 has a region that functions as the other of the source and drain of transistor M24 and a region that functions as wiring VL1b corresponding to wiring VL1.The conductive layer me17 has a region that functions as either the source or the drain of the transistor M21, a region that functions as either the source or the drain of the transistor M22, and a region that functions as the other terminal of the capacitor C22. The conductive layer me18 has a region that functions as the other of the source or the drain of the transistor M21 and a region that functions as the wiring CKL2. The conductive layer me19 has a region that functions as either the source or the drain of the transistor M24, a region that functions as either the source or the drain of the transistor M25, and a region that functions as the node NDD. The conductive layer me20 has a region that functions as the other of the source or the drain of the transistor M25 and a region that functions as the wiring CKL1. The conductive layer me21 has a region that functions as the other of the source or the drain of the transistor M23 and a region that functions as the wiring VL2b corresponding to the wiring VL2. The conductive layer me22 has a region that functions as the other of the source or the drain of the transistor M22, a region that functions as either the source or the drain of the transistor M23, and a region that functions as the node NDC.

[0419] The conductive layer me03 is connected to the conductive layer ge03 through an opening formed in the insulating layer 206. The conductive layer me04 is connected to the conductive layer ge03 through an opening formed in the insulating layer 206. The conductive layer me05 is connected to the conductive layer ge04 through an opening formed in the insulating layer 206. The conductive layer me06 is connected to the conductive layer ge06 through an opening formed in the insulating layer 206. The conductive layer me09 is connected to the conductive layer ge08 through an opening formed in the insulating layer 206. The conductive layer me10 is connected to the conductive layer ge01 through an opening formed in the insulating layer 206. The conductive layer me11 is connected to the conductive layer ge04 through an opening formed in the insulating layer 206. The conductive layer me12 is connected to the conductive layer ge01 through an opening formed in the insulating layer 206. The conductive layer me13 is connected to the conductive layer ge09 through an opening formed in the insulating layer 206. The conductive layer me13 is connected to the conductive layer ge11 through an opening formed in the insulating layer 206. The conductive layer me14 is connected to the conductive layer ge05 through an opening formed in the insulating layer 206. The conductive layer me14 is connected to the conductive layer ge10 through an opening formed in the insulating layer 206. The conductive layer me15 is connected to the conductive layer ge08 through an opening formed in the insulating layer 206. The conductive layer me15 is connected to the conductive layer ge12 through an opening formed in the insulating layer 206. The conductive layer me18 is connected to the conductive layer ge10 through an opening formed in the insulating layer 206. The conductive layer me19 is connected to the conductive layer ge07 through an opening formed in the insulating layer 206. The conductive layer me20 is connected to the conductive layer ge11 through an opening formed in the insulating layer 206. The conductive layer me21 is connected to the conductive layer ge12 through an opening formed in the insulating layer 206. The conductive layer me22 is connected to the conductive layer ge02 at an opening provided in the insulating layer 206. Figures 51 and 52(B) show a via that connects the conductive layer me04 and the conductive layer ge03 to each other at an opening provided in the insulating layer 206.

[0420] In the transistors 200A applied to each transistor constituting the driver circuit 100, a plurality of the transistors 200A may share a continuous semiconductor layer 203. Fig. 51 illustrates six transistors 200A sharing the semiconductor layer os01, six transistors 200A sharing the semiconductor layer os02, two transistors 200A sharing the semiconductor layer os05, two transistors 200A sharing the semiconductor layer os06, two transistors 200A sharing the semiconductor layer os07, and two transistors 200A sharing the semiconductor layer os08.

[0421] In FIG. 51 , for example, the transistors M11 and M12 share the semiconductor layers os01 and os02, respectively. For example, three of the six transistors 200A provided in the semiconductor layer os01 are transistors M11, and the remaining three are transistors M12. Furthermore, three of the six transistors 200A provided in the semiconductor layer os02 are transistors M11, and the remaining three are transistors M12. For example, the transistors M13 and M14 share the semiconductor layer os06. For example, one of the two transistors 200A provided in the semiconductor layer os06 is transistor M13, and the other is transistor M14. For example, the transistors M21 and M22 share the semiconductor layer os08. For example, one of the two transistors 200A provided in the semiconductor layer os08 is transistor M21, and the other is transistor M22. For example, the transistors M24 and M25 share the semiconductor layer os07. For example, one of the two transistors 200A provided in the semiconductor layer os07 is the transistor M24, and the other is the transistor M25. For example, the transistors M26 and M27 share the semiconductor layer os05. For example, one of the two transistors 200A provided in the semiconductor layer os05 is the transistor M26, and the other is the transistor M27. FIG. 52A illustrates the transistors M26 and M27 sharing the continuous semiconductor layer os05. In this way, the multiple transistors 200A share the continuous semiconductor layer 203, thereby reducing the area occupied by the transistors. This reduces the area occupied by the gate driver unit 163, thereby enabling miniaturization.

[0422] Furthermore, the transistor 200A used in each transistor included in the driver circuit 100 may have a configuration in which multiple transistors 200A are connected in parallel. In FIG. 51, for example, the transistor M11 has a configuration in which six transistors 200A are connected in parallel. For example, the transistor M12 has a configuration in which six transistors 200A are connected in parallel. In FIG. 52B, two transistors 200A are illustrated as part of the transistor M12. By connecting multiple transistors 200A in parallel in this manner, the effective channel width can be increased, and the on-state current can be increased. That is, the channel widths of the transistors M11 and M12 can be made larger than the channel widths of other transistors (such as the transistors M13 to M15 and the transistors M21 to M27), and the on-state current can be increased. This shortens the time required to change the potential of the wiring OUTL (i.e., the rise time and fall time), thereby improving the operating speed.

[0423] Although FIG. 51 illustrates an example in which the channel widths of the transistors M11 and M12 are the same, the channel widths of the transistors M11 and M12 may be different. For example, the channel width of the transistor M11 may be larger than the channel width of the transistor M12. In the operation of the driver circuit 100, the gate voltage of the transistor M11 gradually decreases when the potential of the wiring OUTL rises. Therefore, it is preferable to increase the channel width of the transistor M11 to increase its on-state current. For example, FIG. 53A illustrates a transistor M11 having a configuration in which eight transistors 200A are connected in parallel and a transistor M12 having a configuration in which four transistors 200A are connected in parallel, which are obtained by changing the layout of the conductive layers ge01, ge02, me01, me02, and me04. That is, four of the six transistors 200A provided in the semiconductor layer os01 are transistors M11, and the remaining two are transistors M12. Furthermore, four of the six transistors 200A provided in the semiconductor layer os02 are transistors M11, and the remaining two are transistors M12. Furthermore, for example, FIG. 53(B) illustrates, as an example, a transistor M11 having a configuration in which nine transistors 200A are connected in parallel and a transistor M12 having a configuration in which six transistors 200A are connected in parallel, which are obtained by further including a semiconductor layer os03 and changing the layout of the conductive layer ge01.

[0424] 51, the channel length (i.e., the width of the conductive layer 205) and the channel width (i.e., the width of the semiconductor layer 203) of each transistor 200A in each of the transistors M11 and M12 are configured to be equal to the channel lengths and channel widths of the transistors 200A in the other transistors (such as the transistors M13 to M15 and the transistors M21 to M27). In this way, when the on-state current of a transistor is increased, a configuration in which multiple transistors having the same channel length and channel width are connected in parallel can reduce variations in the characteristics of the transistors.

[0425] Although not shown, in order to increase the on-state current of a transistor, the channel length of each transistor may be reduced or the channel width of each transistor may be increased. This allows the number of transistors connected in parallel to be reduced to obtain the same on-state current, thereby reducing the area occupied by the transistors.

[0426] The capacitor C11 can be configured such that a portion of the insulating layer 206 serves as a dielectric in a region where the conductive layers ge05 and me06 overlap. The capacitor C22 can be configured such that a portion of the insulating layer 206 serves as a dielectric in a region where the conductive layers ge07 and me17 overlap. FIG. 52(A) shows, as an example, a capacitor C11 in which a portion of the insulating layer 206 serves as a dielectric and portions of the conductive layers ge05 and me06 serve as a pair of terminals (also referred to as a pair of electrodes or a pair of conductive layers).

[0427] FIG. 53(C) shows an excerpt of the capacitance element C11 and its periphery. The conductive layer ge05 may be laid out so as to encompass the conductive layer me06, as shown in FIG. 53(D). Alternatively, the conductive layer me06 may be laid out so as to encompass the conductive layer ge05, as shown in FIG. 53(C). For example, the configuration shown in FIG. 53(C) can suppress electric field concentration on the insulating layer 206 at the end of the conductive layer ge05. This reduces the likelihood of dielectric breakdown in the insulating layer 206, thereby improving reliability. Furthermore, for example, the configuration shown in FIG. 53(D) can also utilize the capacitance between the side of the conductive layer ge05 and the side of the conductive layer me06 covering it as capacitance. This facilitates increasing the capacitance per unit area, thereby enabling miniaturization.

[0428] Although not shown, the capacitor may have a structure in which, for example, a portion of each of the insulating layer 204 and the insulating layer 206 is a dielectric, and a portion of each of the semiconductor layer 203 and the conductive layer 208 is a pair of terminals. Alternatively, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, a portion of each of the insulating layer 202 and the insulating layer 204 is a dielectric, and a portion of each of the conductive layer (not shown) and the conductive layer 205 is a pair of terminals. Alternatively, for example, a conductive layer (not shown) may be provided between the substrate 201 and the insulating layer 202, a portion of the insulating layer 202 is a dielectric, and a portion of each of the conductive layer (not shown) and the semiconductor layer 203 is a pair of terminals.

[0429] 51, the area where the conductive layer 205 (conductive layers ge01 to ge12) and the conductive layer 208 (conductive layers me01 to me06, conductive layers me09 to me22) overlap with each other, other than the area where the capacitive element C11 and the capacitive element C22 are located, functions as a parasitic capacitance with a part of the insulating layer 206 as a dielectric. Therefore, the area of ​​the capacitive element C11 (i.e., the area of ​​the area where the conductive layer ge05 and the conductive layer me06 overlap with each other) is preferably larger than the area of ​​the area where the conductive layer ge05 and the conductive layer 208 other than the conductive layer me06 overlap with each other, and is preferably larger than the area where the conductive layer 205 other than the conductive layer ge05 and the conductive layer me06 overlap with each other. For example, the area of ​​the capacitive element C11 is preferably larger than the area where the conductive layer ge05 and the conductive layer me13 overlap with each other. Furthermore, the area of ​​the capacitive element C22 (i.e., the area of ​​the region where the conductive layer ge07 and the conductive layer me17 overlap) is preferably larger than the area of ​​the region where the conductive layer ge07 and the conductive layer 208 other than the conductive layer me17 overlap, and is preferably larger than the area of ​​the region where the conductive layer 205 other than the conductive layer ge07 and the conductive layer me17 overlap. For example, the area of ​​the capacitive element C22 is preferably larger than the area of ​​the region where the conductive layer ge07 and the conductive layer me13 overlap, preferably larger than the area of ​​the region where the conductive layer ge07 and the conductive layer me14 overlap, preferably larger than the area of ​​the region where the conductive layer ge07 and the conductive layer me15 overlap, and preferably larger than the area of ​​the region where the conductive layer ge07 and the conductive layer me16 overlap.

[0430] 51, the wiring VL1 is provided separately as a wiring VL1a connected to the other of the source or drain of the transistor M11, and a wiring VL1b connected to the other of the source or drain of the transistor M24. The wiring VL1a and the wiring VL1b are connected to each other, for example, outside the drive circuit 100. By using such a layout, the transistor M11, the transistor M24, and the wiring VL1 (the wiring VL1a and the wiring VL1b) can be laid out efficiently. The wiring VL2 is provided separately as a wiring VL2a connected to the other of the source or drain of the transistor M12, and a wiring VL2b connected to the other of the source or drain of the transistor M23 and the other of the source or drain of the transistor M27. The wiring VL2a and the wiring VL2b are connected to each other, for example, outside the drive circuit 100. By using such a layout, the transistor M12, the transistor M23, the transistor M27, and the wiring VL2 (the wiring VL2a and the wiring VL2b) can be laid out efficiently.

[0431] Here, the potential of the wiring VL1a is supplied to the wiring OUTL to which one row of pixels is connected. At this time, the current flowing through the wiring VL1a momentarily increases, causing a large voltage drop across the wiring VL1a. To mitigate the effects of this voltage drop across the wiring VL1a, it is preferable to increase the width of the wiring VL1a. The same applies to the wiring VL2a. However, because a large current also momentarily flows through the wirings VL1b, VL2b, CKL1, and CKL2, it is preferable to also increase the widths of the wirings VL1b, VL2b, CKL1, and CKL2. Increasing the widths of any of the wirings VL1a, VL2a, VL1b, VL2b, CKL1, and CKL2 results in a large layout area. Therefore, by prioritizing the width of the wirings through which a large current momentarily flows, it is possible to suppress the increase in layout area while also suppressing the effects of the voltage drop. Furthermore, by prioritizing the width of the wirings through which a large current momentarily flows, it is possible to reduce the current density within the wirings. This makes it difficult for breaks or short circuits in the wiring due to electromigration to occur, thereby improving reliability.

[0432] Specifically, the current instantaneously flowing through each of the wirings VL1a and VL2a is greater than the current instantaneously flowing through each of the wirings VL1b, VL2b, CKL1, and CKL2. Therefore, the width of the wiring VL1a may be greater than the widths of the wirings VL1b, VL2b, CKL1, and CKL2. Furthermore, the width of the wiring VL2a may be greater than the widths of the wirings VL1b, VL2b, CKL1, and CKL2. This makes it possible to suppress the influence of voltage drops in each of the wirings VL1a and VL2a while suppressing an increase in the layout area.

[0433] For example, if the width of the wiring VL1a is increased, the overlap between the conductive layer me02 having a region functioning as the wiring VL1a and the conductive layer ge01 having a region functioning as the node NDB, the conductive layer ge02 having a region functioning as the node NDC, and the conductive layer ge04 having a region functioning as the wiring SPL will increase. Therefore, there is a concern that the increase in parasitic capacitance due to the overlap of the two conductive layers may affect circuit operation. Therefore, although not shown, in such a case, to suppress the increase in parasitic capacitance, for example, the widths of the conductive layers ge01, ge02, and ge04 may be selectively reduced in the regions where the conductive layers ge01, ge02, and ge04 overlap with the conductive layer me02, or openings may be formed in the conductive layers ge01, ge02, and ge04. The same applies to the wiring VL2a. The same also applies to overlaps between other conductive layers where parasitic capacitance may be formed.

[0434] 51, the distance between conductive layer me13 having a region that functions as interconnect CKL1 and conductive layer me14 having a region that functions as interconnect CKL2 is larger than the distance between conductive layer me02 having a region that functions as interconnect VL1a and conductive layer me03 having a region that functions as interconnect VL2a, and is larger than the distance between conductive layer me16 having a region that functions as interconnect VL1b and conductive layer me15 having a region that functions as interconnect VL2b. The distance between conductive layer me14 having a region that functions as interconnect CKL2 and conductive layer me15 having a region that functions as interconnect VL2b is larger than the distance between conductive layer me02 having a region that functions as interconnect VL1a and conductive layer me03 having a region that functions as interconnect VL2a, and is larger than the distance between conductive layer me16 having a region that functions as interconnect VL1b and conductive layer me15 having a region that functions as interconnect VL2b. By using such a layout, the parasitic capacitance of the wiring CKL1 and the parasitic capacitance of the wiring CKL2 can be reduced. Since the wiring CKL1 and the wiring CKL2 each have the function of transmitting a clock signal, reducing the parasitic capacitance of the wiring CKL1 and the parasitic capacitance of the wiring CKL2 can reduce the load and improve the operating speed. Furthermore, the capacitance between the wiring VL1a and the wiring VL2a can be increased. Since the wiring VL1a and the wiring VL2a each have the function of transmitting a constant potential, increasing the capacitance between the wiring VL1a and the wiring VL2a can stabilize the potential and stabilize the operation.

[0435] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0436] (Embodiment 5) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0437] Note that at least part of the driver circuit, the semiconductor device, and the like described in Embodiment 1 can be applied to the display device described in this embodiment, a module including the display device, and the like.

[0438] Here, examples of modules having the display device include a module in which a connector such as a flexible printed circuit (FPC) or a tape carrier package (TCP) is attached to the display device, or a module in which an integrated circuit (IC) is implemented using a chip on glass (COG) method or a chip on film (COF) method.

[0439] <Example of display device configuration> FIG. 54A is a perspective view illustrating a structural example of a display device 400 of one embodiment of the present invention.

[0440] The display device 400 has a structure in which a substrate 411 and a substrate 451 are bonded together. In Fig. 54(A), the substrate 411 is indicated by a dashed line.

[0441] The display device 400 includes a display portion 452, a circuit portion 454a, a circuit portion 454b, a connection portion 457, and a wiring portion 458. Fig. 54A shows an example in which an IC chip 456 and an FPC 459 are mounted on the display device 400. Therefore, the configuration shown in Fig. 54A can also be said to be a display module including the display device 400, the IC chip, and the FPC.

[0442] Note that at least a part of the semiconductor device 160 described in Embodiment 1 can be applied to the display device 400. For example, at least a part of the driver circuit 100 described in Embodiment 1 can be applied to the circuit portion 454a and the circuit portion 454b. For example, at least a part of the pixel 161 described in Embodiment 1 can be applied to the display portion 452.

[0443] The circuit portion 454a includes, for example, a scan line driver circuit (also referred to as a gate driver or a scan driver), and the circuit portion 454b includes, for example, a signal line driver circuit (also referred to as a source driver or a data driver).

[0444] The wiring portion 458 has a function of supplying signals and power to the display portion 452, the circuit portion 454a, and the circuit portion 454b. The signals and power are input to the wiring portion 458 from the outside of the display device 400 via the FPC 459, or are input to the wiring portion 458 from the IC chip 456.

[0445] 54A shows an example in which an IC chip 456 is provided on a substrate 451 by a COG method, a COF method, or the like. The IC chip 456 can be, for example, an IC chip having one or both of a scan line driver circuit and a signal line driver circuit. Note that the display device 400 and the display module may not include an IC chip. Alternatively, the IC chip may be mounted on an FPC by a COF method or the like.

[0446] Note that a scanning line driver circuit may be configured by one or both of the IC chip 456 and the circuit portion 454a. In this case, the IC chip 456 may be referred to as a gate driver IC. Also, a signal line driver circuit may be configured by one or both of the IC chip 456 and the circuit portion 454b. In this case, the IC chip 456 may be referred to as a source driver IC.

[0447] The display section 452 is a region in the display device 400 that displays an image, and has a plurality of periodically arranged pixels 455. An enlarged view of one pixel 455 is shown in FIG.

[0448] The pixel 455 shown in FIG. 54A includes a pixel 453R that emits red (R) light, a pixel 453G that emits green (G) light, and a pixel 453B that emits blue (B) light. A full-color display can be achieved by configuring one pixel 455 with the pixels 453R, 453G, and 453B. The pixels 453R, 453G, and 453B each function as a sub-pixel. The display device 400 shown in FIG. 54A illustrates an example in which the pixels 453R, 453B, and 453G that function as sub-pixels are arranged in a stripe array. Note that the number of sub-pixels that configure one pixel 455 is not limited to three and may be four or more. For example, the pixel 455 may include four sub-pixels that emit R, G, B, and white (W) light, respectively. Alternatively, the pixel 455 may include four sub-pixels that emit R, G, B, and yellow (Y) light, respectively.

[0449] In this specification, elements relating to red light may be identified by the identification symbol "R," elements relating to green light by the identification symbol "G," and elements relating to blue light by the identification symbol "B," and these elements may be described separately. Furthermore, common elements may be described without identifying the elements. For example, when it is necessary to distinguish between multiple pixels 453, they may be referred to as pixel 453R, pixel 453G, or pixel 453B. Furthermore, when it is not necessary to distinguish between pixel 453R, pixel 453G, and pixel 453B, they may be simply referred to as pixel 453.

[0450] Each of the pixels 453R, 453G, and 453B includes a display element and a circuit (pixel circuit) that controls driving of the display element.

[0451] The connection portion 457 is provided outside the display portion 452. The connection portion 457 can be provided along one side or multiple sides of the display portion 452. The connection portion 457 may be single or multiple. FIG. 54A shows an example in which the connection portion 457 is provided so as to surround the four sides of the display portion. The connection portion 457 connects a common electrode of a display element and a wiring portion 458, and a potential can be supplied to the common electrode.

[0452] The substrate 451 and the substrate 411 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. The substrate (here, the substrate 411) on the side from which light from the display element is extracted is preferably made of a material that transmits the light. A polarizing plate may be used for at least one of the substrates 451 and 411. A flexible material can be used for the substrates 451 and 411. This increases the flexibility of the display device, making it possible to realize a flexible display (for example, a bendable display, a foldable display, a rollable display, a slidable display, a stretchable display, or the like).

[0453] Note that the display device of one embodiment of the present invention may function as a touch panel. For example, various sensing elements (also referred to as sensor elements) that can detect the proximity or contact of a sensed object such as a finger can be applied to the display device.

[0454] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0455] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferable because it enables simultaneous multi-point detection.

[0456] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that the in-cell type touch panel has a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.

[0457] [Pixel array] 54(B) to 54(F) are top views illustrating pixel arrays. In a display device of one embodiment of the present invention, the pixel array is not particularly limited, and various arrays can be applied. Examples of pixel arrays include a stripe array (see FIG. 54(B)), an S-stripe array (see FIG. 54(C)), a delta array (see FIG. 54(D)), a zigzag array (see FIG. 54(E)), and a Pentile array (see FIG. 54(F)). Other examples include a mosaic array, a diamond array, and a Bayer array.

[0458] 54(B) to 54(F), examples of the top surface shape of each subpixel (pixel 453R, pixel 453G, and pixel 453B) include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, shapes with rounded corners of these polygons, an ellipse, and a circle. Here, the top surface shape of each subpixel corresponds to the top surface shape of the display area of ​​the display element included in each subpixel. The top surface shape and size of each subpixel can be determined independently. Note that the arrangements of the pixel 453R, pixel 453G, and pixel 453B may be interchanged as appropriate. The display elements and pixel circuits may be arranged in the same or different arrangements.

[0459] [Display element] Various elements can be used as display elements, including liquid crystal elements and light-emitting elements. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, or display elements that employ microcapsule, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods. Also, quantum-dot LEDs (QLEDs) that utilize a light source and color conversion technology using quantum dot materials may be used.

[0460] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0461] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, fringe field switching (FFS) mode, in-plane switching (IPS) mode, twisted nematic (TN) mode, axially symmetric aligned micro-cell (ASM) mode, optically compensated birefringence (OCB) mode, ferroelectric liquid crystal (FLC) mode, antiferroelectric liquid crystal (AFLC) mode, electrically controlled birefringence (ECB) mode, and guest-host mode. Examples of VA modes include multi-domain vertical alignment (MVA) mode, patterned vertical alignment (PVA) mode, and advanced super view (ASV) mode.

[0462] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer-network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, or blue phase. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material.

[0463] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), organic EL (Electro Luminescence) elements (also called OLEDs (Organic LEDs)), and semiconductor lasers. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0464] Examples of light-emitting materials that light-emitting elements have include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (quantum dot materials, etc.).

[0465] The light-emitting element can emit light of red, green, blue, blue-green, magenta, yellow, or white. The light-emitting element can also emit ultraviolet or infrared light. The color purity can be improved by providing the light-emitting element with a micro-optical resonator (microcavity) structure.

[0466] One of a pair of electrodes included in the light-emitting element functions as an anode electrode, and the other electrode functions as a cathode electrode.

[0467] <Example of cross-sectional structure of display device> FIG. 55 is a cross-sectional view illustrating an example of a cross-sectional structure of a display device according to one embodiment of the present invention.

[0468] 55, the structures shown in the regions 490a, 490b, and 490c can be used in the display device 400. For example, the structure shown in the region 490a can be used in the region where the pixel 453 is provided. The structure shown in the region 490b can be used in the region where the circuit portion 454a, the circuit portion 454b, and the like are provided. The structure shown in the region 490c can be used in the region where the FPC 459 is provided.

[0469] The region 490a corresponds to a region where the pixel 161 described in the above-described embodiment 1 is provided. That is, the transistors provided in the region 490a correspond to the transistors included in the pixel 161 described in the above-described embodiment 1 (such as the transistors M31, M32, and M33 included in the pixel 161A). The region 490b corresponds to a region where the driver circuit 100 described in the above-described embodiment 1 is provided. That is, the transistors provided in the region 490b correspond to the transistors included in the driver circuit 100 described in the above-described embodiment 1 (such as the transistors M11, M12, M13, M14, and M15).

[0470] The display device 490 has a substrate 351 (corresponding to the substrate 451 described above) and a substrate 352 (corresponding to the substrate 411 described above). An adhesive layer 342 is provided between the substrates 351 and 352. The substrate 352 faces the substrate 351 with the adhesive layer 342 interposed therebetween. Note that the region 490c does not have the substrate 352 or the adhesive layer 342.

[0471] An insulating layer 382 is provided on the substrate 352 side of the substrate 351. On the insulating layer 382, ​​a transistor, a light emitting element, and the like are provided.

[0472] Here, as an example, a configuration is shown in which the transistor 200A described in the above-described Embodiment 2 is provided in each of the regions 490a and 490b, and the transistor 200B described in the above-described Embodiment 2 is provided in the region 490a.

[0473] Note that the transistors provided in the regions 490a and 490b are not limited to those having the same structures as the transistors 200A and 200B. Transistors having various structures, such as the transistors 200C, 200D, and 200E described in Embodiment 2, can be provided in the regions 490a and 490b. In this case, transistors having one type of structure may be provided, or two or more types of transistors having different structures may be provided.

[0474] Furthermore, the region 490c includes a conductive layer 384. The conductive layer 384 can be formed in the same process as the conductive layer 208 (the conductive layer 208a, the conductive layer 208b, etc.) in the transistor 200A and the transistor 200B.

[0475] An insulating layer 218 is provided to cover the transistor 200A and the transistor 200B.

[0476] In the region 490a, a pixel electrode 311 is provided on the insulating layer 218. The pixel electrode 311 is in contact with the conductive layer 208b in an opening provided in the insulating layer 218 and the insulating layer 209. In addition, an insulating layer 237 is provided on the insulating layer 218. The insulating layer 237 has a region that covers an edge of the pixel electrode 311.

[0477] An EL layer 313 is provided so as to cover the insulating layer 237 and the pixel electrode 311. A common electrode 315 is provided so as to cover the EL layer 313. A protective layer 331 is provided so as to cover the common electrode 315.

[0478] The pixel electrode 311 and the common electrode 315 overlap with the EL layer 313 interposed therebetween, and the region where the pixel electrode 311 and the EL layer 313 contact each other and the EL layer 313 and the common electrode 315 contact each other functions as a light-emitting element 330. The pixel electrode 311 functions as one electrode (or first terminal) of the light-emitting element 330, and the common electrode 315 functions as the other electrode (or second terminal). The EL layer 313 has a function of emitting light with a brightness according to the amount of current flowing between the pixel electrode 311 and the common electrode 315 via the EL layer 313.

[0479] The light emitting element 330 corresponds to the light emitting element LD included in the pixel 161A[u,v] shown in the first embodiment.

[0480] A light-shielding layer 317 is provided on the substrate 352 on the substrate 351 side.

[0481] In region 490a, an opening is provided in light-shielding layer 317 so as to have an area overlapping with light-emitting element 330. Therefore, light emitted by light-emitting element 330 passes through the opening provided in light-shielding layer 317 and is emitted to the outside of display device 490. In FIG. 55, this state is represented by a dashed arrow and the word "Light."

[0482] In the region 490c, the conductive layer 386 is provided over part of the insulating layer 218. The conductive layer 386 has a region that is in contact with the conductive layer 384 in an opening provided in the insulating layer 218 and the insulating layer 209.

[0483] The conductive layer 384 can be provided in the same layer as the conductive layers 208a and 208b. Therefore, the conductive layer 384 can have the same material as the conductive layers 208a and 208b and can be formed in the same process. For example, the conductive layers 208a, 208b, and 384 can be formed by processing the same conductive film. The conductive layer 386 can be provided in the same layer as the pixel electrode 311. Therefore, the conductive layer 386 can have the same material as the pixel electrode 311 and can be formed in the same process. For example, the pixel electrode 311 and the conductive layer 386 can be formed by processing the same conductive film. In the region 490c, the conductive layer 386 is exposed. This allows the conductive layer 386 and the FPC 459 to be connected via the connection layer 388.

[0484] The connection layer 388 may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0485] <Configuration example of light-emitting element> In one embodiment of the present invention, when a display device includes a light-emitting element, light-emitting elements with various structures can be used.

[0486] 56(A), 56(B), 57(A), and 57(B) are cross-sectional views illustrating light-emitting elements of various configurations.

[0487] [Configuration example 1] 56(A) has light-emitting elements 330R, 330G, and 330B between a substrate 351 and a substrate 352. The light-emitting element 330R is a display element included in a pixel that emits red light, the light-emitting element 330G is a display element included in a pixel that emits green light, and the light-emitting element 330B is a display element included in a pixel that emits blue light. When describing matters common to the light-emitting elements 330R, 330G, and 330B, they may be simply referred to as light-emitting elements 330.

[0488] 56A, some of the configuration between the substrate 351 and the light-emitting element 330 and the configuration between the substrate 352 and the light-emitting element 330 are omitted. The display device 490A includes, between the substrate 351 and the light-emitting element 330, for example, a transistor that constitutes a pixel circuit and an insulating layer 218 that is provided to cover the transistor.

[0489] The display device 490A employs an SBS (Side By Side) structure. The SBS structure is fabricated using a metal mask (or fine metal mask). This allows for greater freedom in selecting materials and configurations for each light-emitting element. This allows for optimizing materials and configurations for each light-emitting element, making it easier to improve light emission intensity and reliability.

[0490] The display device 490A is a top-emission type, which allows a transistor or the like to be arranged overlapping with a light-emitting region of a light-emitting element, thereby increasing the aperture ratio of a pixel compared to a bottom-emission type.

[0491] On the insulating layer 218, a light emitting element 330R, a light emitting element 330G, and a light emitting element 330B are provided.

[0492] The light-emitting element 330R has a pixel electrode 311R on the insulating layer 218, an EL layer 313R on the pixel electrode 311R, and a common electrode 315 on the EL layer 313R. The light-emitting element 330R shown in Fig. 56(A) emits red (R) light. The EL layer 313R has a light-emitting layer that emits red light.

[0493] The light-emitting element 330G has a pixel electrode 311G on the insulating layer 218, an EL layer 313G on the pixel electrode 311G, and a common electrode 315 on the EL layer 313G. The light-emitting element 330G shown in Fig. 56(A) emits green (G) light. The EL layer 313G has a light-emitting layer that emits green light.

[0494] The light-emitting element 330B has a pixel electrode 311B on the insulating layer 218, an EL layer 313B on the pixel electrode 311B, and a common electrode 315 on the EL layer 313B. The light-emitting element 330B shown in Figure 56(A) emits blue (B) light. The EL layer 313B has a light-emitting layer that emits blue light.

[0495] 56(A), the EL layer 313R, the EL layer 313G, and the EL layer 313B are all shown to have the same thickness, but this is not limited to this. The EL layer 313R, the EL layer 313G, and the EL layer 313B may have different thicknesses. For example, it is preferable to set the thickness of the EL layer 313R, the EL layer 313G, and the EL layer 313B so that the optical path length increases the intensity of the light emitted by each layer. This realizes a microcavity structure and improves the color purity of the light emitted from each light-emitting element.

[0496] The pixel electrode 311R is connected to a transistor (not shown) included in a pixel circuit corresponding to the light-emitting element 330R through an opening provided in the insulating layer 218 or the like. Similarly, the pixel electrode 311G is connected to a transistor (not shown) included in a pixel circuit corresponding to the light-emitting element 330G. Similarly, the pixel electrode 311B is connected to a transistor (not shown) included in a pixel circuit corresponding to the light-emitting element 330B.

[0497] The edges of the pixel electrode 311R, the pixel electrode 311G, and the pixel electrode 311B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a multilayer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the same material as that used for the insulating layer 218 can be used for the insulating layer 237. The insulating layer 237 can insulate the pixel electrodes from the common electrode. Furthermore, the insulating layer 237 can insulate adjacent light-emitting elements from each other.

[0498] The common electrode 315 is a continuous film provided in common to the light-emitting elements 330R, 330G, and 330B. Although not shown, the common electrode 315 shared by the plurality of light-emitting elements is connected to a conductive layer formed of the same material and in the same process as the pixel electrodes 311R, 311G, and 311B in areas where no light-emitting elements are provided.

[0499] Of the pixel electrode and the common electrode, the electrode from which light is extracted (here, the common electrode 315) is preferably made of a conductive film that transmits visible light, and the electrodes from which light is not extracted (here, the pixel electrode 311R, pixel electrode 311G, and pixel electrode 311B) are preferably made of a conductive film that reflects visible light.

[0500] A conductive film that transmits visible light may also be used on the electrode on the side from which light is not extracted. In this case, a reflective layer may be disposed opposite the EL layer via the conductive film. This allows light emitted from the EL layer to be reflected by the reflective layer and extracted to the outside of the display device.

[0501] Materials for forming the pair of electrodes (pixel electrode and common electrode) of a light-emitting element can include metals, alloys, conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Examples of such materials include indium tin oxide (In-Sn oxide, or ITO), In-Si-Sn oxide, indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Examples of such materials include aluminum alloys, such as aluminum-nickel-lanthanum (Al-Ni-La) alloys, and silver alloys, such as silver-magnesium alloys and silver-palladium-copper (Ag-Pd-Cu, or APC) alloys. Examples of such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these elements, and graphene.

[0502] It is preferable that a microcavity structure be applied to the light-emitting element. Therefore, for example, it is preferable that one electrode of the light-emitting element (here, the common electrode 315) is an electrode that is transparent and reflective to visible light (also called a semi-transmissive / semi-reflective electrode), and the other electrode of the light-emitting element (here, the pixel electrode 311R, the pixel electrode 311G, and the pixel electrode 311B) is an electrode that is reflective to visible light (also called a reflective electrode). When the light-emitting element has a microcavity structure, light emitted from the light-emitting layer can be resonated between the two electrodes, thereby intensifying the light emitted from the light-emitting element.

[0503] For example, the transmittance of the semi-transmitting / semi-reflective electrode to visible light (light with a wavelength of 400 nm or more and less than 750 nm) is 40% or more. The reflectance of the semi-transmitting / semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of the reflective electrode to visible light is 40% or more and less than 100%, preferably 70% or more and less than 100%. The resistivity of these electrodes is 1×10 -2 Ωcm or less is preferable.

[0504] The EL layer 313R, the EL layer 313G, and the EL layer 313B are each provided in an island shape. In FIG. 56(A), the ends of adjacent EL layers 313R and 313G overlap, and the ends of adjacent EL layers 313G and 313B overlap. Although not shown, the ends of adjacent EL layers 313R and 313B overlap. When forming island-shaped EL layers using a metal mask (or a fine metal mask), the ends of adjacent EL layers may overlap as shown in FIG. 56(A), but this is not limited thereto. That is, adjacent EL layers may not overlap but may be spaced apart. Furthermore, there may be both overlapping portions between adjacent EL layers and portions between adjacent EL layers that do not overlap but are spaced apart.

[0505] Each of the EL layers 313R, 313G, and 313B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red can be used as appropriate. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0506] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0507] The light-emitting layer may contain one or more organic compounds (such as a host material and an assist material) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transporting properties (hole-transporting material) and a substance with high electron-transporting properties (electron-transporting material) may be used. Alternatively, as the one or more organic compounds, a bipolar substance (a substance with high electron-transporting properties and high hole-transporting properties) or a TADF material may be used.

[0508] The light-emitting layer preferably contains, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows for efficient emission using Exciplex-Triplet Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth and light emission can be achieved efficiently. This configuration allows for high efficiency, low-voltage operation, and a long lifetime of the light-emitting element to be achieved simultaneously.

[0509] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0510] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. Each of the layers constituting the light-emitting element can be formed by a deposition method (such as a vacuum deposition method), a transfer method, a printing method (such as an inkjet method), or a coating method (such as a spin coating method).

[0511] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure makes it possible to obtain a light-emitting element that can emit light with high luminous intensity. Furthermore, the tandem structure can reduce the current required to obtain the same luminous intensity compared to a single structure, thereby improving reliability. The tandem structure can also be called a stacked structure.

[0512] In Figure 56(A), when a tandem structure is used as the light-emitting element, it is preferable that the EL layer 313R has a structure having multiple light-emitting units that emit red light, the EL layer 313G has a structure having multiple light-emitting units that emit green light, and the EL layer 313B has a structure having multiple light-emitting units that emit blue light.

[0513] A protective layer 331 is provided on the light-emitting elements 330R, 330G, and 330B. The protective layer 331 and the substrate 352 are bonded via an adhesive layer 362. A light-shielding layer 317 is provided on the substrate 352. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 56(A), the space between the substrates 352 and 351 is filled with the adhesive layer 362, thereby applying a solid sealing structure. Alternatively, a hollow sealing structure may be applied in which the space is filled with an inert gas (such as nitrogen or argon). In this case, the adhesive layer 362 may be provided so as not to overlap the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 362.

[0514] By providing the protective layer 331 on the light emitting elements 330R, 330G, and 330B, the reliability of the light emitting elements can be improved.

[0515] The protective layer 331 may have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 331 does not matter. The protective layer 331 can be made of at least one of an insulating film, a semiconductor film, and a conductive film.

[0516] The protective layer 331 having an inorganic film can prevent oxidation of the common electrode 315 and prevent impurities (such as moisture and oxygen) from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0517] The protective layer 331 can be made of an inorganic insulating film. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of inorganic insulating films are as described above. In particular, the protective layer 331 preferably contains a nitride or a nitride oxide, and more preferably contains a nitride.

[0518] The protective layer 331 may be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 315. The inorganic film may further contain nitrogen.

[0519] When light emitted from the light emitting element is extracted to the outside of the display device through the protective layer 331, it is preferable that the protective layer...

Claims

1. a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitance element; a first terminal of the first transistor is electrically connected to a first terminal of the second transistor and to a first wiring; a gate of the first transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the fifth transistor; a second terminal of the fifth transistor electrically connected to a gate of the fifth transistor, a first terminal of the third transistor, and a first terminal of the first capacitive element; a second terminal of the third transistor and a second terminal of the fourth transistor are electrically connected to a second wiring; a second terminal of the first transistor is electrically connected to a third wiring; a second terminal of the second transistor is electrically connected to a fourth wiring; a gate of the third transistor and a gate of the fourth transistor are electrically connected to a fifth wiring; a second terminal of the first capacitance element is electrically connected to a sixth wiring; the fifth wiring has a function of transmitting a first clock signal; the sixth wiring has a function of transmitting a second clock signal having a phase different from that of the first clock signal; Drive circuit.

2. In claim 1, a first circuit; the first circuit has a first terminal and a second terminal; a first terminal of the first circuit electrically connected to a first terminal of the third transistor; a second terminal of the first circuit electrically connected to a gate of the second transistor; the fourth wiring has a function of transmitting a first potential; the third wiring has a function of transmitting a second potential that is greater than the first potential; the first circuit has a function of outputting the first potential to a first terminal of the first circuit in accordance with the first clock signal and the second clock signal, a function of setting the first terminal of the first circuit to a high impedance state, a function of outputting the first potential to a second terminal of the first circuit, and a function of outputting the second potential to the second terminal of the first circuit; Drive circuit.

3. In claim 1, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; a gate of the sixth transistor is electrically connected to a first terminal of the ninth transistor, a first terminal of the tenth transistor, and a gate of the eleventh transistor; a first terminal of the sixth transistor electrically connected to a first terminal of the seventh transistor; a second terminal of the seventh transistor is electrically connected to a first terminal of the eighth transistor and to a gate of the second transistor; a first terminal of the eleventh transistor is electrically connected to a first terminal of the twelfth transistor; a second terminal of the eleventh transistor is electrically connected to a first terminal of the third transistor; a gate of the eighth transistor and a gate of the tenth transistor are each electrically connected to a first terminal of the fourth transistor; a second terminal of the sixth transistor is electrically connected to the sixth wiring; a gate of the seventh transistor is electrically connected to the sixth wiring; a second terminal of the eighth transistor is electrically connected to the fourth wiring; a second terminal of the ninth transistor is electrically connected to the third wiring; a gate of the ninth transistor is electrically connected to the fifth wiring; a second terminal of the tenth transistor is electrically connected to the fifth wiring; a second terminal of the twelfth transistor is electrically connected to the fourth wiring; a gate of the twelfth transistor is electrically connected to the sixth wiring; Drive circuit.

4. In any one of claims 1 to 3, The channel width of the first transistor is larger than the channel width of the fifth transistor. Drive circuit.

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