Manufacturing method of semiconductor device

Abstract

To suppress generation of poor connection of a first electrode while suppressing generation of electric field concentration at an opening end part of a trench.SOLUTION: Forming a trench 16 comprises: arranging a mask 30 on one surface 10a of a semiconductor substrate 10; patterning the mask 30 to expose a formation scheduled region where the trench 16 is formed, of the semiconductor substrate 10; forming the trench 16 in the semiconductor substrate 10 by etching using the mask 30; and forming a rounded part 160 in an opening end part 16a of the trench in a state in which the mask 30 is arranged. The forming the rounding part 160 in the opening end part 16a of the trench 16 comprises etching under a condition where a selection ratio of the mask 30 is higher than a selection ratio of the semiconductor substrate 10.SELECTED DRAWING: Figure 2F

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device having a trench gate structure. [Background technology]

[0002] Conventionally, semiconductor devices including semiconductor elements such as MOSFETs (short for metal oxide semiconductor field effect transistors) have been proposed. Specifically, these semiconductor devices include a semiconductor substrate having a drift layer, a base layer formed on one surface of the semiconductor substrate, and a source region formed in a surface layer of the base layer. Furthermore, the semiconductor substrate is formed with a plurality of trenches that penetrate the source region and the base layer and extend in one direction in the surface direction of the semiconductor substrate. A gate insulating film and a gate electrode are disposed in the trenches to form a trench gate structure.

[0003] A drain region is disposed on the other surface of the semiconductor substrate, a first electrode is disposed on one surface of the semiconductor substrate so as to be electrically connected to the source region and the base layer, and a second electrode is disposed on the other surface of the semiconductor substrate so as to be electrically connected to the drain region.

[0004] In the semiconductor device described above, electric field concentration is likely to occur at the opening edge of the trench. For this reason, for example, Patent Document 1 proposes forming a rounded portion at the opening edge of the trench.

[0005] Specifically, in this method, a mask is formed on one surface of a semiconductor substrate, and the mask is patterned to form an opening so that the portion of the semiconductor substrate where the trench will be formed is exposed. Subsequently, anisotropic etching or the like is performed using the mask to form the trench in the semiconductor substrate. Next, a process is performed to widen the opening of the mask, exposing the opening edge of the trench through the mask. After that, isotropic etching is performed to form a rounded portion at the opening edge of the trench. Note that the isotropic etching used to form the rounded portion is performed under conditions that result in a higher selectivity for the semiconductor substrate than for the mask. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-4360 Summary of the Invention [Problem to be solved by the invention]

[0007] In the semiconductor device described above, reducing the distance between adjacent trenches has been considered to reduce on-resistance. However, when a rounded portion is formed at the opening end of the trench as described above, the isotropic etching has a high selectivity for the semiconductor substrate, which means that the portion of the semiconductor substrate exposed through the mask is likely to be entirely removed. Furthermore, when a rounded portion is formed at the opening end of the trench as described above, the isotropic etching has a high selectivity for the semiconductor substrate, which means that the portion of the semiconductor substrate located near the opening of the mask may also be removed. In other words, the opening end of the trench may be widened overall. As a result, the portion of the surface of the semiconductor substrate located between adjacent trenches is reduced, which may reduce the connectivity between the first electrode and the source region, etc., resulting in poor connection.

[0008] In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the occurrence of electric field concentration at the opening end of a trench while suppressing the occurrence of poor connection of the first electrode. [Means for solving the problem]

[0009] To achieve the above object, claim 1 provides a method for manufacturing a semiconductor device having multiple trench gate structures, comprising: preparing a semiconductor substrate (10) having one surface (10a), forming trenches (16) from the one surface side, the trenches (16) having a longitudinal direction in one direction in the surface direction of the semiconductor substrate, and arranging a gate insulating film (17) and a gate electrode (18) in the trenches to form the multiple trench gate structures. The trench formation step includes placing a mask (30) on the one surface of the semiconductor substrate, patterning the mask to form openings (31) so as to expose regions of the semiconductor substrate where the trenches are to be formed, etching the semiconductor substrate using the mask, and forming rounded portions (160) at opening edges (16a) of the trenches by etching with the mask in place. The trench formation step includes etching under conditions where the mask has a higher selectivity than the semiconductor substrate, and the trench formation step includes anisotropic etching under conditions where the semiconductor substrate has a higher selectivity than the mask.

[0010] According to this method, the rounded portion is formed by etching under conditions where the mask has a higher selectivity than the semiconductor substrate. Therefore, the surface of the semiconductor substrate is less likely to be removed when forming the rounded portion, and the surface of the semiconductor substrate located between the trenches is less likely to be reduced. This prevents poor connection between the first electrode and the surface of the semiconductor substrate. Furthermore, because the rounded portion is formed at the opening edge of the trench, electric field concentration at the opening edge of the trench is prevented.

[0011] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment. [Figure 2A] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. [Figure 2B] 2B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 2A. [Figure 2C] 2C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 2B. [Figure 2D] 2D is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 2C. [Figure 2E] 2D. FIG. 2C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 2D. [Figure 2F] 2F is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 2E. [Figure 3] FIG. 1 is a plan view showing a wafer-shaped semiconductor substrate. [Figure 4] FIG. 10 is a diagram showing the depth of a trench. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0014] (First embodiment) A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle. This embodiment also describes a silicon carbide (hereinafter also referred to as SiC) semiconductor device in which an inversion-type MOSFET with a trench gate structure is formed. This embodiment describes the configuration of a cell region in which the MOSFET is formed, but an actual SiC semiconductor device is provided with an outer periphery region in which an FLR (abbreviation for Field Limiting Ring) structure or the like is formed so as to surround the cell region.

[0015] In the following description, one direction in the surface direction of a substrate 11 (described later) is defined as the X-axis direction, a direction intersecting with the one direction in the surface direction of the substrate is defined as the Y-axis direction, and a direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other.

[0016] As shown in Fig. 1, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device is configured using an n-type SiC semiconductor device. + In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and has an n-type impurity concentration of 1.0×10 19 / cm 3 The substrate 11 has a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes the drain region and corresponds to a high concentration layer.

[0017] On the surface of the substrate 11, a n-type SiC substrate is formed. - The n-type drift layer 12 and the p-type base layer 13 are epitaxially grown in this order. + type source region 14 and p + In this embodiment, the source regions 14 and the contact regions 15 are alternately formed along the longitudinal direction (i.e., the Y-axis direction) of the trench 16, which will be described later. In this embodiment, the source regions 14 correspond to impurity regions.

[0018] The drift layer 12 has an n-type impurity concentration of, for example, 0.5 to 2.0×10 16 / cm 3 The base layer 13 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, 3.0×10 17 / cm 3 The source region 14 has a higher impurity concentration than the drift layer 12, and the n-type impurity concentration in the surface layer is, for example, 2.5×10 18~1.0×10 19 / cm 3 The contact region 15 has a higher impurity concentration than the base layer 13, and the p-type impurity concentration is 1.0×10 18 ~1.0×10 20 / cm 3 The impurity concentrations and film thicknesses of the drift layer 12, the base layer 13, the source region 14, and the contact region 15 are arbitrary and are not limited to those described above.

[0019] As described above, in this embodiment, the semiconductor substrate 10 is configured to include the substrate 11, drift layer 12, base layer 13, source region 14, contact region 15, etc. In this embodiment, one surface 10a of the semiconductor substrate 10 is configured to include the source region 14 and the contact region 15, and the other surface 10b of the semiconductor substrate 10 is configured to include the substrate 11.

[0020] A plurality of trenches 16 are formed in the semiconductor substrate 10, penetrating the source region 14, the contact region 15, and the base layer 13 to reach the drift layer 12. Specifically, the plurality of trenches 16 extend along the Y-axis direction and are arranged at equal intervals in the X-axis direction to form a stripe pattern. Each trench 16 has a rounded portion 160 at its opening end 16a.

[0021] A gate insulating film 17 is formed on the inner wall surface of the trench 16, and a gate electrode 18 made of doped poly-Si or the like is formed on the gate insulating film 17. This forms a trench gate structure. Although not particularly limited, the gate insulating film 17 is formed by thermally oxidizing the inner wall surface of the trench 16 or by performing a CVD (short for chemical vapor deposition) method. The gate insulating film 17 has a thickness of about 100 nm on both the side and bottom surfaces of the trench 16.

[0022] In the SiC semiconductor device of this embodiment, the gate insulating film 17 and the gate electrode 18 are not disposed on the opening end 16a side of the trench 16. Specifically, the gate insulating film 17 and the gate electrode 18 are not disposed on the side of the trench 16 from the side of the first surface 10a of the semiconductor substrate 10 to a position partway along the Z-axis direction between the source region 14 and the contact region 15. That is, the opening end 16a on the side of the trench 16 is exposed from the gate insulating film 17 and the gate electrode 18. The gate insulating film 17 and the gate electrode 18 are also formed on the opening end 16a of the trench 16, for example, at the end of the trench 16 in the longitudinal direction, and extend onto the first surface 10a of the semiconductor substrate 10. The gate electrode 18 extended onto the first surface 10a of the semiconductor substrate 10 is electrically connected to a gate wiring or the like (not shown).

[0023] An interlayer insulating film 19 is formed on the opening end 16a of the trench 16 so as to cover the gate electrode 18, the gate insulating film 17, and the like. However, the interlayer insulating film 19 of this embodiment is disposed only in the trench 16 and is not formed on the first surface 10a of the semiconductor substrate 10. In this embodiment, by disposing the interlayer insulating film 19 in this manner, it is possible to more easily narrow the interval between adjacent trenches 16 than in the following SiC semiconductor device. That is, in the SiC semiconductor device of this embodiment, it is possible to more easily narrow the interval between adjacent trenches 16 than in a case where the interlayer insulating film 19 is disposed on the first surface 10a of the semiconductor substrate 10 and contact holes are formed to expose the source region 14 and the contact region 15. The interlayer insulating film 19 is made of BPSG (abbreviation for borophosphosilicate glass) or the like.

[0024] An upper electrode 20 is formed on one surface 10a of the semiconductor substrate 10 and is electrically connected to the source region 14 and the contact region 15. In this embodiment, the upper electrode 20 corresponds to a first electrode.

[0025] The upper electrode 20 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 14) is made of a metal that can make ohmic contact with the n-type SiC. At least the portion of the plurality of metals that contacts the p-type SiC (i.e., the contact region 15) is made of a metal that can make ohmic contact with the p-type SiC.

[0026] A lower electrode 21 electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 21 corresponds to the second electrode.

[0027] In the SiC semiconductor device of this embodiment, an n-channel inversion trench gate MOSFET is configured with this structure. + The first conductivity type corresponds to p-type, p + The type corresponds to the second conductivity type.

[0028] When the gate voltage applied to the gate electrode 18 is equal to or greater than the threshold voltage of the insulated gate structure, the SiC semiconductor device is in an ON state, where a current flows between the upper electrode 20 and the lower electrode 21. When the gate voltage applied to the gate electrode 18 is less than the threshold voltage, the SiC semiconductor device is in an OFF state, where no current flows between the upper electrode 20 and the lower electrode 21.

[0029] Next, a method for manufacturing the SiC semiconductor device will be described with reference to Figures 2A to 2F, which are cross-sectional views in which the Y-axis direction in Figure 1 is the normal direction.

[0030] First, as shown in Fig. 2A, a semiconductor substrate 10 is prepared, which includes a substrate 11, a drift layer 12, a base layer 13, a source region 14, and a contact region 15. In this embodiment, as shown in Fig. 3, a wafer-like semiconductor substrate 10 is prepared as the semiconductor substrate 10, with each chip formation region R defined by a dicing line DL. Figs. 2A to 2F show a cross section of the semiconductor substrate 10 in one chip formation region R. The contact region 15 is formed in a cross section different from that shown in Fig. 2A.

[0031] 2B, a mask 30 and a resist 40 are sequentially disposed on one surface 10a of the semiconductor substrate 10. The mask 30 in this embodiment is made of, for example, SiO (i.e., an oxide film) formed by a CVD (short for Chemical Vapor Deposition) method or the like.

[0032] Subsequently, as shown in FIG. 2C, photolithography, etching, and the like are performed to pattern the mask 30 to form an opening 31 so as to expose the region of the semiconductor substrate 10 where the trench 16 is to be formed.

[0033] 2D, after removing the resist 40 by ashing or the like, anisotropic etching or the like is performed using the mask 30 to form the trench 16 in the semiconductor substrate 10. The anisotropic etching here is performed under conditions that provide a higher selectivity for the semiconductor substrate 10 than for the mask 30. After this step is completed, the opening end 16a of the trench 16 is not exposed by the mask 30.

[0034] 2E, wet etching is performed to widen the opening 31 of the mask 30 and expose the opening end 16a of the trench 16. In other words, the opening 31 of the mask 30 is retracted to expose the opening end 16a of the trench 16. At this time, in this embodiment, wet etching is performed under conditions where the selectivity of the mask 30 is higher than that of the semiconductor substrate 10 so that the semiconductor substrate 10 is less likely to be etched.

[0035] Then, as shown in FIG. 2F , etching is performed using a mask 30 to form rounded portions 160 at the opening edges 16a of the trenches 16. In this embodiment, the rounded portions 160 are formed at the opening edges 16a of the trenches 16 by performing anisotropic etching under conditions that provide a higher selectivity for the mask 30 than for the semiconductor substrate 10. That is, the rounded portions 160 are formed at the opening edges 16a of the trenches 16 by performing anisotropic etching under conditions that make it difficult to remove the semiconductor substrate 10. As a result, the rounded portions 160 are formed by slightly removing only the opening edges 16a. Furthermore, since this process is performed under conditions that make it difficult to remove the semiconductor substrate 10, exposing only the vicinity of the opening edges 16a makes it difficult for the surface 10a of the semiconductor substrate 10 to be removed, thereby preventing the surface 10a of the semiconductor substrate 10 located between the trenches 16 from being reduced. However, as will be described later, this process also removes a small amount of the bottom surface of the trenches 16.

[0036] When anisotropic etching is performed, for example, a mixed gas containing a CF-based gas and an SF-based gas is used as the etching gas, and the selectivity can be adjusted by adjusting the flow rates of the CF-based gas and the SF-based gas. Specifically, the selectivity of SiO2 (i.e., the mask 30) can be increased by increasing the flow rate of the CF-based gas, and the selectivity of SiC (i.e., the semiconductor substrate 10) can be increased by increasing the flow rate of the SF-based gas. Therefore, in this embodiment, the selectivity of SiO2 is made higher than that of SiC by increasing the flow rate of the CF-based gas.

[0037] In this embodiment, a wafer-shaped semiconductor substrate 10 is used, and the inventors obtained the results shown in Fig. 4. Fig. 4 shows the depth of the trench 16 along the line IV-IV in Fig. 3.

[0038] Specifically, as shown in FIG. 4, when trench 16 is formed in the process of FIG. 2D, etching gas flows more easily toward the outer edge of the wafer, and it has been confirmed that trench 16 becomes deeper toward the outer edge of the wafer. In other words, it has been confirmed that when trench 16 is formed, semiconductor substrate 10 is more easily scraped toward the outer edge of the wafer. On the other hand, when rounded portion 160 is formed at opening end 16a of trench 16 in the process of FIG. 2F, it has been confirmed that the bottom surface of trench 16 is more easily scraped toward the center of the wafer (i.e., trench 16 is more likely to become deeper), although the exact reason is not clear. In other words, it has been confirmed that the parts of semiconductor substrate 10 that are more easily scraped are reversed between forming trench 16 and forming rounded portion 160 at opening end 16a of trench 16. Therefore, in this embodiment, by forming the trench 16 as described above and forming a rounded portion 160 at the opening end 16a of the trench 16, the variation in the final depth of the trench 16 within the surface of the wafer can be reduced.

[0039] Thereafter, although not shown, the mask 30 is removed by etching or the like, and a general semiconductor manufacturing process is carried out to form the gate insulating film 17, the gate electrode 18, the interlayer insulating film 19, the upper electrode 20, the lower electrode 21, etc., thereby manufacturing the SiC semiconductor device.

[0040] According to the present embodiment described above, the rounded portions 160 are formed by etching under conditions in which the mask 30 has a higher selectivity than the semiconductor substrate 10. This makes it difficult for the surface 10a of the semiconductor substrate 10 to be removed, thereby preventing the surface 10a of the semiconductor substrate 10 located between the trenches 16 from being reduced. This means that the source regions 14 and contact regions 15 exposed from the surface 10a of the semiconductor substrate 10 are prevented from being reduced. This prevents poor connection between the upper electrode 20 and the source regions 14 and contact regions 15. Furthermore, since the source regions 14 and contact regions 15 exposed from the surface 10a of the semiconductor substrate 10 are prevented from being reduced, the distance between adjacent trenches 16 can be shortened, thereby reducing the on-resistance. Furthermore, since the rounded portions 160 are formed at the opening ends 16a of the trenches 16, electric field concentration at the opening ends 16a of the trenches 16 is prevented.

[0041] (1) In this embodiment, anisotropic etching is performed by forming the rounded portion 160 at the opening end 16a of the trench 16. This prevents damage to the side surface of the trench 16. In addition, the portion below the mask 30 is less likely to be removed, and the source region 14 and the contact region 15 exposed from the surface 10a of the semiconductor substrate 10 are prevented from being reduced.

[0042] (2) In this embodiment, a wafer-like semiconductor substrate 10 is used. Then, when forming the trench 16, anisotropic etching is performed under conditions where the selectivity of the semiconductor substrate 10 is higher than that of the mask 30. Furthermore, when forming the rounded portion 160 at the opening end 16a of the trench 16, anisotropic etching is performed under conditions where the selectivity of the mask 30 is higher than that of the semiconductor substrate 10. Therefore, when forming the trench 16 and when forming the rounded portion 160 at the opening end 16a of the trench 16, the portions of the semiconductor substrate 10 that are easily etched are reversed. This reduces variation in the final depth of the trench 16 within the wafer surface.

[0043] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the etching used to form the rounded portion 160 at the opening end 16a of the trench 16 is changed. As the rest of the structure is the same as the first embodiment, a description thereof will be omitted here.

[0044] In this embodiment, after forming the trench 16 by performing the step of FIG. 2D , the step of FIG. 2E is not performed, and the step of FIG. 2F is performed directly to form the rounded portion 160 at the opening end 16 a of the trench 16. Specifically, in this embodiment, isotropic etching such as CDE (short for Chemical Dry Etching) is performed to form the rounded portion 160 at the opening end 16 a of the trench 16. Note that, in this step, the isotropic etching is also performed under conditions in which the mask 30 has a higher selectivity than the semiconductor substrate 10. During this process, the mask 30 is more likely to be removed from the opening 31 side, so as shown in FIG. 2F , the mask 30 is removed from the opening side to form the rounded portion 160 at the opening end 16 a of the trench 16. In this case, because the mask 30 has a higher selectivity than the semiconductor substrate 10, the rounded portion 160 can be formed by slightly removing only the corners of the opening end 16 a. Furthermore, since the conditions are such that the mask 30 has a higher selectivity than the semiconductor substrate 10, it is possible to prevent the portion of the semiconductor substrate 10 located below the mask 30 from being removed by isotropic etching. Note that even in CDE, the conditions can be easily adjusted so that the mask 30 has a higher selectivity than the semiconductor substrate 10 by appropriately adjusting the flow rate of the etching gas.

[0045] Thereafter, in the same manner as in the first embodiment, the mask 30 is removed, and the gate insulating film 17 and the like are formed, thereby completing the manufacture of the SiC semiconductor device.

[0046] According to the present embodiment described above, the rounded portions 160 are formed by etching under conditions where the mask 30 has a higher selectivity than the semiconductor substrate 10, and therefore the same effects as those of the first embodiment can be obtained.

[0047] (1) In this embodiment, by forming the rounded portion 160 at the opening end 16a of the trench 16, isotropic etching is performed using the mask 30 used when forming the trench 16. Therefore, there is no need to perform a process to widen the opening end 16a of the trench 16, and the manufacturing process can be simplified.

[0048] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0049] For example, in the first embodiment described above, an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type is taken as an example. However, this is merely an example, and for example, a p-channel type trench gate structure MOSFET in which the conductivity types of each component are reversed from the n-channel type may also be used. Furthermore, the SiC semiconductor device may be configured such that, in addition to the MOSFET, an IGBT with a similar structure is formed. In the case of an IGBT, the n-channel type MOSFET in each of the above embodiments is + The substrate 11 is + Other than the change to the collector layer of the type, the vertical MOSFET is the same as that described in each of the above embodiments.

[0050] In the first embodiment, the semiconductor substrate 10 is made of SiC. However, the semiconductor substrate 10 may be made of a silicon substrate, another compound semiconductor substrate, or the like. [Explanation of symbols]

[0051] 10. Semiconductor substrate 10a one side 16 Trench 16a Open end 17 Gate insulating film 18 gate electrode 160 Rounding section

Claims

1. A method for manufacturing a semiconductor device having a plurality of trench gate structures, comprising: Providing a semiconductor substrate (10) having one surface (10a); forming a trench (16) from the one surface side, the trench having a longitudinal direction in one direction in the surface direction of the semiconductor substrate; and disposing a gate insulating film (17) and a gate electrode (18) in the trenches to form the plurality of trench gate structures; In forming the trench, placing a mask (30) on one side of the semiconductor substrate; patterning the mask to form an opening (31) so as to expose a region of the semiconductor substrate where the trench is to be formed; forming the trench in the semiconductor substrate by etching using the mask; and forming a rounded portion (160) at the open end (16a) of the trench by etching with the mask in place; forming a rounded portion at the opening end of the trench, the etching is performed under conditions in which the selectivity of the mask is higher than that of the semiconductor substrate; A method for manufacturing a semiconductor device, wherein anisotropic etching is performed under conditions in which the selection ratio of the semiconductor substrate is higher than that of the mask when the trench is formed.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein forming the rounded portion at the opening end of the trench comprises widening the opening of the mask to expose the opening end of the trench.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the rounded portion is formed at the opening end of the trench by performing anisotropic etching under conditions in which the mask has a higher selectivity than the semiconductor substrate.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of preparing the semiconductor substrate comprises preparing the semiconductor substrate in a wafer form in which a plurality of chip formation regions (R) are partitioned by dicing lines (DL).

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