Electronic control type mechanical timepiece

Abstract

To provide an electronic control type mechanical timepiece that can extend duration and restraining upsizing a movement.SOLUTION: An electronic control type mechanical timepiece comprises: a spiral spring; a gear train for transmitting mechanical energy of the spiral spring; a pointer that is driven by the gear train and displays time; a speed regulator for controlling a rotation period of the gear train; control means for controlling the speed regulator; a generator for transducing mechanical energy to electric energy; a first energy storage device for storing electric energy and supplying the electric energy to the control means; a second energy storage device capable of storing electric energy; and a connection circuit capable of connecting the first energy storage device and the second energy storage device in parallel. The connection circuit can be switched to at least three states, namely a first state in which the first energy storage device and the second energy storage device are connected, a second state in which the first energy storage device and the second energy storage device are connected in a state in which the amount of travel of an electric charge per unit time is smaller than in the first state, and a third state in which the first energy storage device is disconnected from the second energy storage device.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an electronically controlled mechanical timepiece. [Background technology]

[0002] An electronically controlled mechanical timepiece is known that uses the mechanical energy generated when a mainspring is released to drive a generator, generating electrical energy that is stored in a first storage device, and then uses the electrical energy supplied from the first storage device to drive a rotation control device, controlling the rotation period of the generator, thereby accurately driving the hands moved by a train wheel and displaying the time accurately (see Patent Document 1).

[0003] The electronically controlled mechanical watch of Patent Document 1 discloses that an additional power supply device is provided, which includes an additional generator such as a solar power generation device and a second power storage device, and that when the voltage of the first power storage device drops, electrical energy is supplied from the additional power supply device to extend the running time. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-214271 Summary of the Invention [Problem to be solved by the invention]

[0005] The electronically controlled mechanical timepiece of Patent Document 1 has a problem in that the movement of the timepiece becomes large because an additional power supply device including an additional generator is provided in addition to the generator that generates electricity using mechanical energy. [Means for solving the problem]

[0006] The electronically controlled mechanical timepiece disclosed herein comprises a mainspring, a train wheel that transmits the mechanical energy of the mainspring, hands driven by the train wheel to display the time, a regulator that controls the rotation period of the train wheel, a control means that controls the regulator, a generator that converts the mechanical energy into electrical energy, a first storage device that stores the electrical energy of the generator and supplies the electrical energy to the control means, a second storage device that can store electrical energy, and a connection circuit that can connect the first storage device and the second storage device in parallel, wherein the connection circuit is switchable between at least three states: a first state that connects the first storage device and the second storage device; a second state that connects the first storage device and the second storage device in a state where the amount of charge transferred per unit time is less than in the first state; and a third state that disconnects the first storage device and the second storage device. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a front view showing an electronically controlled mechanical timepiece according to a first embodiment. [Figure 2] 1 is a block diagram showing the configuration of an electronically controlled mechanical timepiece according to a first embodiment. FIG. [Figure 3] 2 is a circuit diagram showing a connection circuit and a power storage device according to the first embodiment. FIG. [Figure 4A] FIG. 2 is a diagram illustrating a PMOS transistor of the switch according to the first embodiment. [Figure 4B] FIG. 2 is a diagram illustrating an NMOS transistor of the switch according to the first embodiment. [Figure 5A] 4 is a graph showing the relationship between the gate voltage and the drain current of the MOSFET of the first embodiment. [Figure 5B] 4 is a semi-logarithmic graph showing the relationship between the gate voltage and the drain current of the MOSFET of the first embodiment. [Figure 6] FIG. 2 is a circuit diagram showing a gate input signal generation circuit of the connection circuit according to the first embodiment. [Figure 7] 5A and 5B are diagrams illustrating detection signals for switch control and switch states in the first embodiment. [Figure 8] 4 is a graph showing voltage changes of a first power storage device and a second power storage device in the first embodiment. [Figure 9] FIG. 10 is a block diagram showing the configuration of an electronically controlled mechanical timepiece according to a second embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a connection circuit and a power storage device according to a second embodiment. [Figure 11] 10A and 10B are diagrams illustrating detection signals for switch control and switch states in the second embodiment. [Figure 12] 10 is a timing chart showing an oscillation-stop detection signal and a switch control signal according to the second embodiment. [Figure 13] 10 is a graph showing voltage changes of a first power storage device, a second power storage device, and a third power storage device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] [First embodiment] An electronically controlled mechanical timepiece 1 according to a first embodiment of the present disclosure will now be described with reference to the drawings. Fig. 1 is a front view of an electronically controlled mechanical timepiece 1. As shown in Fig. 1, the electronically controlled mechanical timepiece 1 is a wristwatch worn on the user's wrist, and is equipped with a cylindrical exterior case 2, with a dial 3 located on the inner periphery of the exterior case 2. Of the two openings in the exterior case 2, the opening on the front side is closed with a cover crystal, and the opening on the back side is closed with a back cover.

[0009] The electronically controlled mechanical timepiece 1 is equipped with a movement (not shown) housed in an exterior case 2 and hands 4 that display time information. The hands 4 are made up of an hour hand 4A, a minute hand 4B, and a second hand 4C. The dial 3 is provided with a small calendar window 3A, through which a date wheel 6 can be seen. The dial 3 also has hour marks 3B for indicating the time and a fan-shaped subdial 3C that indicates the duration with a power reserve hand 5.

[0010] A crown 7 is provided on the side of the exterior case 2. The crown 7 can be moved from a 0 position where it is pushed toward the center of the electronically controlled mechanical timepiece 1 to a 1 position or a 2 position by being pulled out. When the crown 7 is pulled out to the first position and rotated, the date wheel 6 moves and the date can be set. When the crown 7 is pulled out to the second position, the second hand 4C stops, and when the crown 7 is rotated in the second position, the hour hand 4A and minute hand 4B move and the time can be set. The method of adjusting the date wheel 6, hour hand 4A and minute hand 4B using the crown 7 is the same as that of conventional watches, so a description will be omitted.

[0011] [Outline of the clock] FIG. 2 is a block diagram showing the configuration of the electronically controlled mechanical timepiece 1. As shown in FIG. 2, the electronically controlled mechanical timepiece 1 comprises a control IC 10 as control means, a mainspring 40 as a mechanical energy source, a speed-increasing train wheel 50 as an energy transmission device that transmits the torque of the mainspring 40, a display unit 60 that is connected to the speed-increasing train wheel 50 and displays the time, a generator 70 that is driven by the torque transmitted via the speed-increasing train wheel 50 and also serves as a regulator for the speed-increasing train wheel 50, a quartz oscillator 80, a rectifier circuit 90, and a power supply circuit 30.

[0012] The mainspring 40 is wound via a winding train wheel by manual winding using the crown 7 or automatic winding using an oscillating weight. The speed-increasing train wheel 50 is configured with multiple gears that rotate using the mechanical energy stored in the mainspring 40, and moves the hour hand 4A, minute hand 4B, and second hand 4C that are attached to the shafts of these gears. The speed-increasing train wheel 50 also meshes with the pinion of the rotor of the generator 70, rotating the rotor. Although not shown, a winding train wheel that winds the mainspring 40 and a power reserve train wheel that is linked to the speed-increasing train wheel 50 are provided, and this power reserve train wheel is equipped with a power reserve hand 5. The electronically controlled mechanical timepiece 1 of this embodiment can ensure a running time of approximately 72 hours when the mainspring 40 is fully wound. The display unit 60 is configured with the hands 4 and date wheel 6 shown in FIG. 1, and displays the time.

[0013] The generator 70 is an electromagnetic induction generator equipped with a coil and a rotor magnetized to two poles, and generates electricity by generating an induced voltage due to changes in magnetic flux passing through the coil as the rotor rotates. The rotor is rotated by the speed-up train wheel 50, and the speed of the rotor's rotation is regulated by a short brake using chopping control that intermittently shorts both ends of the coil, thereby regulating the speed of the hands 4 provided on the speed-up train wheel 50 and improving the accuracy of the time indication by the hands 4. For this reason, the generator 70 also serves as a regulator that regulates the speed of the speed-up train wheel 50, i.e., the speed of the hands 4. The output terminal of the coil of the generator 70 is connected to a brake circuit controlled by the control IC 10 and a rectifier circuit 90. Therefore, the electrical energy supplied from the generator 70 is charged into the power supply circuit 30 via the rectifier circuit 90. The brake circuit is equipped with a transistor that shorts both ends of the coil to allow the generator 70 to function as a speed governor, and by performing chopping control that shorts the transistor intermittently, both ends of the coil are shorted to create a closed loop state, thereby applying a short brake to the generator 70. The rectifier circuit 90 is made up of a step-up rectifier, a full-wave rectifier, a half-wave rectifier, a transistor rectifier, or the like, and it steps up and rectifies the AC output from the generator 70 and supplies it to the power supply circuit 30 for charging.

[0014] [Control IC] 2, the control IC 10 includes an oscillation circuit 11, a frequency divider circuit 12, a rotation detection circuit 13, a braking control circuit 14, a power supply voltage detection circuit 15, and an oscillation stop detection circuit 16. Note that IC is an abbreviation for Integrated Circuit. The oscillator circuit 11 and the crystal resonator 80 constitute the crystal oscillator circuit 100. The crystal oscillator circuit 100 stops oscillating when the IC-applied voltage VDD of the power supply circuit 30 falls below the oscillation stop voltage, and starts oscillating when the IC-applied voltage VDD exceeds the oscillation start voltage. The oscillation start voltage may be the same as the oscillation stop voltage, but is preferably set to a voltage higher than the oscillation stop voltage so that the oscillation can continue stably after it starts. Furthermore, for the crystal oscillator circuit 100 to start oscillating, the oscillator circuit 11 must be operating, i.e., the control IC 10 must be operating. Therefore, the oscillation start voltage need only be equal to or higher than the operation start voltage of the control IC 10. In this embodiment, the oscillation start voltage and the operation start voltage of the control IC 10 are set to the same voltage. The oscillation stop voltage is set to a voltage higher than the operation stop voltage of the control IC 10 so that the oscillation circuit 11 stops oscillation before the control IC 10 stops. The oscillator circuit 11 outputs an oscillation signal of a predetermined frequency generated by the oscillation of the crystal oscillator 80 to the frequency divider circuit 12. In this embodiment, the oscillator circuit 11 generates an oscillation signal of 32768 Hz. Therefore, the crystal oscillator circuit 100 including the crystal oscillator 80 and the oscillator circuit 11 is an oscillation means that outputs a clock signal of 32768 Hz.

[0015] The frequency divider circuit 12 divides the output of the oscillator circuit 11 to generate clock signals of multiple frequencies, and outputs the clock signals required by the brake control circuit 14. The clock signal output from the frequency divider circuit 12 to the brake control circuit 14 is a reference signal that serves as a basis for controlling the rotation of the rotor of the generator 70. In this embodiment, since the reference speed of the rotor of the generator 70 is 8 Hz, the frequency divider circuit 12 generates an 8 Hz reference signal and outputs it to the brake control circuit 14.

[0016] The rotation detection circuit 13 is composed of a waveform shaping circuit (not shown) and a mono multivibrator connected to the generator 70, and outputs a rotation detection signal representing the rotor rotation frequency, i.e., rotation speed, from the induced voltage waveform generated in the generator 70 to the braking control circuit 14.

[0017] The braking control circuit 14 compares the rotation detection signal output from the rotation detection circuit 13 with the reference signal output from the frequency divider circuit 12, and outputs a braking control signal to the brake circuit of the generator 70 to regulate the speed of the generator 70. In this embodiment, the reference signal is a signal that is synchronized with the reference rotation speed of the rotor during normal hand movement. Therefore, the brake control circuit 14 adjusts the braking force of the brake circuit and controls the rotation of the rotor by outputting a brake control signal according to the difference between the rotation detection signal corresponding to the rotor rotation speed and the reference signal.

[0018] The power supply voltage detection circuit 15 is a voltage detection means that detects the voltages of the first power storage device 31 and the second power storage device 32 of the power supply circuit 30 at predetermined intervals. Power supply voltage detection circuit 15 compares the first storage device voltage, which is the detected voltage of first power storage device 31, with a predetermined first threshold Vdet1 and outputs a first voltage detection signal based on the comparison result. When the first storage device voltage is less than first threshold Vdet1, power supply voltage detection circuit 15 outputs a low-level signal as the first voltage detection signal, and when the first storage device voltage is equal to or greater than first threshold Vdet1, it outputs a high-level signal as the first voltage detection signal. Power supply voltage detection circuit 15 compares the second storage device voltage, which is the detected voltage of second storage device 32, with a predetermined second threshold Vdet2 and outputs a second voltage detection signal based on the comparison result. When the second storage device voltage is less than second threshold Vdet2, power supply voltage detection circuit 15 outputs a low-level signal as the second voltage detection signal, and when the second storage device voltage is equal to or greater than second threshold Vdet2, it outputs a high-level signal as the second voltage detection signal. Note that second threshold Vdet2 is set to a voltage equal to or greater than first threshold Vdet1. The specific voltage values ​​of first threshold Vdet1 and second threshold Vdet2 may be set appropriately depending on the capacities of first storage device 31 and second storage device 32, the operation start voltage of control IC 10, etc.

[0019] The oscillation stop detection circuit 16 is an oscillation stop detection means that detects the stop of oscillation of the crystal oscillation circuit 100 by monitoring the clock signal output from the oscillation circuit 11. When the oscillation stop detection circuit 16 detects the stop of oscillation of the crystal oscillation circuit 100, it outputs a low-level control signal that switches the switch 36 to the off state regardless of the amount of mechanical energy of the mainspring 40. In addition, when the first power storage device 31 of the power supply circuit 30 is charged, the control IC 10 starts operating, and the crystal oscillator circuit 100 starts oscillating from a state in which the control IC 10 is stopped, the oscillation stop detection circuit 16 outputs a high-level control signal that enables switching of the switch 36 according to the amount of mechanical energy of the mainspring 40.

[0020] [Power circuit] The power supply circuit 30 includes a first power storage device 31, a second power storage device 32, and a connection circuit . 3, the first power storage device 31 is configured with a capacitor, stores the electric charge generated by the generator 70, smooths the voltage, and supplies it to the control IC 10. Since the first power storage device 31 needs to quickly increase the voltage, the capacity of the capacitor is set according to the power generation capacity of the generator 70. Since the second power storage device 32 needs to store a large amount of charge, a power storage device with a larger capacity than the first power storage device 31 is selected. For this reason, a rechargeable secondary battery such as a lithium-ion battery or an all-solid-state battery, or a large-capacity capacitor is used for the second power storage device 32. In particular, by using a secondary battery with a flat voltage-capacity characteristic for the second power storage device 32, it becomes possible to efficiently charge the generated energy without the voltage of the second power storage device 32 becoming too high. Furthermore, even if an all-solid-state battery with low internal resistance is used as the second power storage device 32, improved charging efficiency can be expected.

[0021] The first power storage device 31 is directly connected to the rectifier circuit 90, and the second power storage device 32 is connected in parallel to the first power storage device 31 via the connection circuit 35. Therefore, when the connection circuit 35 is controlled to a connected state, the first power storage device 31 and the second power storage device 32 are connected in parallel to the first power supply line 21 that is connected to the VDD terminal of the control IC 10 and the second power supply line 22 that is connected to the VSS terminal of the control IC 10. When the connection circuit 35 is controlled to an off state, the second power storage device 32 is disconnected from the first power supply line 21, and only the first power storage device 31 is connected to the first power supply line 21 and the second power supply line 22. Therefore, the connection circuit 35 functions as a switch that connects the second power storage device 32 to the first power storage device 31 in parallel. In this embodiment, the second power supply line 22 is set to the ground potential VSS, and the control IC 10 is applied with the voltage VDD. In addition, in this embodiment, the connection circuit 35 is described between the first power supply line 21 and the second power storage device 32, but it may also be located between the second power supply line 22 and the second power storage device 32.

[0022] As shown in FIG. 3, the connection circuit 35 includes a switch 36 and a gate input signal generation circuit 37 that controls the switch 36, and is controlled by a first voltage detection signal and a second voltage detection signal input from the power supply voltage detection circuit 15 and an oscillation stop detection signal input from the oscillation stop detection circuit 16. The switch 36 is an analog switch in which a PMOS transistor 361 and an NMOS transistor 362 of a MOSFET are connected in parallel. MOSFET is an abbreviation for metal-oxide-semiconductor field-effect transistor. By using both the PMOS transistor 361 and the NMOS transistor 362 in the switch 36, the switch 36 can efficiently pass current even if the voltage of the first power storage device 31 and the second power storage device 32 changes and the direction of current flow changes. As shown in FIG. 4A, when a low-level signal is input to the gate G of the PMOS transistor 361, the voltage of the gate G is lowered compared to the voltage of the source S, and the gate voltage Vgs, which is the voltage between the gate and source when the source S is used as the reference, becomes equal to or higher than the threshold voltage, a drain current Id flows from the source S to the drain D. As shown in FIG. 4B, when a high-level signal is input to the gate G of the NMOS transistor 362, the voltage of the gate G is made higher than the voltage of the source S, and the gate voltage Vgs, which is the voltage between the gate and source when the source S is used as the reference, becomes equal to or higher than the threshold voltage, a drain current Id flows from the drain D to the source S. In the following description, the control signal input to the gate of the PMOS transistor 361 is referred to as a gate input signal PMOS, and the control signal input to the gate of the NMOS transistor 362 is referred to as a gate input signal NMOS.

[0023] FIG. 5A is a graph showing an example of the relationship between the gate voltage Vgs and the drain current Id in the PMOS transistor 361 and the NMOS transistor 362, and FIG. 5B is a semi-logarithmic graph in which the vertical axis of the drain current Id in FIG. 5A is logarithmic. 5A and 5B, the threshold voltage Vth of the PMOS transistor 361 and the NMOS transistor 362 is 0.6 V. As shown in Fig. 5A, the region where the voltage Vgs is equal to or less than the threshold voltage Vth is a weak inversion region where almost no drain current Id flows, and the region where the voltage Vgs is greater than the threshold voltage Vth is a strong inversion region where the drain current Id flows and increases in proportion to the voltage Vgs. As shown in Figure 5B, in the weak inversion region, the drain current Id increases exponentially with the voltage Vgs. Therefore, in the strong inversion region, where the gate voltage Vgs is near 1.0 V and the transistors 361 and 362 are turned on in this embodiment, the drain current Id is approximately 100 µA. In contrast, in the weak inversion region, where the gate voltage Vgs is near 0.45 V and the transistors 361 and 362 are turned on weakly in this embodiment, the drain current Id is approximately 100 nA, which is approximately 1 / 1000 of the current amount when the gate voltage Vgs is 1.0 V. Furthermore, in this embodiment, when the gate voltage Vgs is near 0 V, which turns off the transistors 361 and 362, the drain current Id is strictly about 1.0×10 -13 Although a leakage current of about A flows, it is so small that it can be ignored, and therefore the current flowing through the switch 36, that is, the amount of charge movement per unit time, can be considered to be zero. Note that the values ​​in the graphs of FIGS. 5A and 5B are examples and will vary depending on the size and process of the transistor.

[0024] Therefore, when the switch 36 is turned off to disconnect the first power storage device 31 and the second power storage device 32, a high-level signal is input as the gate input signal PMOS and a low-level signal is input as the gate input signal NMOS. In this state, a leakage current flows through the switch 36, but it is negligibly small, so the switch 36 is in a switch-off state in which the first power storage device 31 and the second power storage device 32 are disconnected from each other, and this disconnected state is defined as the third state.

[0025] When the switch 36 is turned on to connect the first power storage device 31 and the second power storage device 32, a low-level signal is input as the gate input signal PMOS and a high-level signal is input as the gate input signal NMOS. This state is a switch-on state in which the transistors 361 and 362 are turned on in the strong inversion region and a predetermined current flows through the switch 36, and this state is defined as the first state. 5B and the gate voltage Vgs in the first state is approximately 1.0 V, a current of approximately 100 μA flows through the switch 36. Therefore, the amount of charge transferred per unit time through the switch 36 in the first state is approximately 100 μC (microcoulombs) when the unit time is one second.

[0026] When adjusting the on-resistance of the switch 36 to adjust the current, a signal Vsub_p with a voltage value at the weak inversion region level of the PMOS transistor 361 is input as the gate input signal PMOS, and a signal Vsub_n with a voltage value at the weak inversion region level of the NMOS transistor 362 is input as the gate input signal NMOS. Inputting a signal at the weak inversion region level allows a smaller current to flow compared to the switch-on state. This state is defined as the weak on state, or second state. If each transistor 361, 362 has the characteristics shown in FIG. 5B and the gate voltage Vgs in the second state is approximately 0.45 V, a current of approximately 100 nA, 1 / 1000 of that in the first state, flows through the switch 36. Therefore, the amount of charge transferred per unit time through the switch 36 in the second state is approximately 100 nC (nanocoulombs) when the unit time is one second. By setting switch 36 to the second state, i.e., the weak on state, it is possible to prevent a sudden voltage drop in first power storage device 31 when the charge stored in first power storage device 31 is transferred to second power storage device 32. Therefore, it is possible to charge second power storage device 32 while ensuring the voltage of first power storage device 31. When switch 36 is in the first state or the second state, a current flows from the power storage device with the higher voltage to the power storage device with the lower voltage, either first power storage device 31 or second power storage device 32.

[0027] 3, the gate input signal generation circuit 37 includes a terminal VL1 to which the first voltage detection signal is input, a terminal VL2 to which the second voltage detection signal is input, a terminal to which the oscillation stop detection signal is input, a terminal to which a gate input signal PMOS is output, and a terminal to which a gate input signal NMOS is output. That is, the gate input signal generation circuit 37 is a circuit that generates gate input signals PMOS and NMOS to be input to the gates of the PMOS transistor 361 and the NMOS transistor 362 based on the first voltage detection signal, the second voltage detection signal, and the oscillation stop detection signal. In the following description, the first voltage detection signal may be referred to as the first voltage detection signal VL1, and the second voltage detection signal may be referred to as the second voltage detection signal VL2.

[0028] FIG. 6 is a circuit diagram showing the gate input signal generating circuit 37 in detail. The gate input signal generation circuit 37 includes control signal generation circuits 371, 372, and 373, a first generation circuit 38 that generates a gate input signal PMOS, and a second generation circuit 39 that generates a gate input signal NMOS.

[0029] The control signal generating circuit 371 is configured as a NOR circuit that receives the inverted signal of the first voltage detection signal VL1 and the oscillation stop detection signal, and outputs the control signal netA. The control signal generating circuit 372 is composed of an AND circuit 375 to which the first voltage detection signal VL1 and the second voltage detection signal VL2 are input, and an AND circuit 376 to which the inverted signal of the oscillation stop detection signal and the output of the AND circuit 375 are input, and which outputs a control signal netB. The control signal generating circuit 373 is composed of a NAND circuit 377 to which an inverted signal of the second voltage detection signal VL2 and the first voltage detection signal VL1 are input, and an OR circuit 378 to which the output of the NAND circuit 377 and the oscillation stop detection signal are input and which outputs a control signal netC.

[0030] 7 shows the relationship between the oscillation stop detection signal, the first voltage detection signal VL1, the second voltage detection signal VL2, and the control signals netA, netB, and netc. The "x" in FIG. 7 for the first voltage detection signal VL1 and the second voltage detection signal VL2 means that the signal applies whether it is high or low. 7, the control signal netA is at a low level when the oscillation stop detection signal is at a high level. The control signal netA is also at a low level when the oscillation stop detection signal is at a low level and the first voltage detection signal VL1 is at a low level. The control signal netA is also at a high level when the oscillation stop detection signal is at a low level and the first voltage detection signal VL1 is at a high level. The control signal netB is at a low level when the oscillation stop detection signal is at a high level. The control signal netB is also at a low level when the oscillation stop detection signal is at a low level and the first voltage detection signal VL1 or the second voltage detection signal VL2 is at a low level. The control signal netB is also at a high level when the oscillation stop detection signal is at a low level and both the first voltage detection signal VL1 and the second voltage detection signal VL2 are at a high level. The control signal netC is at a high level when the oscillation stop detection signal is at a high level. The control signal netC is also at a high level when the oscillation stop detection signal is at a low level and the first voltage detection signal VL1 is at a low level or the second voltage detection signal VL2 is at a high level. The control signal netC is also at a low level when the oscillation stop detection signal and the second voltage detection signal VL2 are at a low level and the first voltage detection signal VL1 is at a high level.

[0031] As shown in FIG. 6, the first generation circuit 38 includes a first constant current circuit 381, a PMOS transistor 382, ​​a PMOS transistor 383, an NMOS transistor 384, a NOT circuit 385, a PMOS transistor 386, an NMOS transistor 388, and an output line 380 connected to a terminal that outputs a gate input signal PMOS. A PMOS transistor 382 and a PMOS transistor 383 are connected in series between the first power supply line 21 and the first constant current circuit 381. An NMOS transistor 384 is connected between the second power supply line 22 and the first constant current circuit 381. The PMOS transistor 383 has both its gate and drain connected to the output line 380, and is a saturated-connected transistor. A control signal netC output from the control signal generation circuit 373 is input to the gate of the PMOS transistor 382, ​​and a signal obtained by inverting the control signal netC by a NOT circuit 385 is input to the gate of the NMOS transistor 384. Therefore, the PMOS transistor 382 and the NMOS transistor 384 are turned off when the control signal netC is a high-level signal, and are turned on when the control signal netC is a low-level signal. A control signal netA output from the control signal generating circuit 371 is input to the gate of the PMOS transistor 386. Therefore, the PMOS transistor 386 is turned on when the control signal netA is a low-level signal, and is turned off when the control signal netA is a high-level signal. The control signal netB output from the control signal generating circuit 372 is input to the gate of the NMOS transistor 388. Therefore, the NMOS transistor 388 is turned on when the control signal netB is a high-level signal, and is turned off when the control signal netB is a low-level signal.

[0032] The second generation circuit 39 includes a second constant current circuit 391, a PMOS transistor 392, an NMOS transistor 393, an NMOS transistor 394, a NOT circuit 395, a PMOS transistor 396, a NOT circuit 397, an NMOS transistor 398, a NOT circuit 399, and an output line 390 connected to a terminal that outputs a gate input signal NMOS. A PMOS transistor 392 is connected between the first power supply line 21 and the second constant current circuit 391. An NMOS transistor 393 and an NMOS transistor 394 are connected in series between the second power supply line 22 and the second constant current circuit 391. The NMOS transistor 393 has both its gate and drain connected to the output line 390, and is a saturated-connected transistor. A control signal netC output from the control signal generation circuit 373 is input to the gate of the PMOS transistor 392, and a signal obtained by inverting the control signal netC by a NOT circuit 395 is input to the gate of the NMOS transistor 394. Therefore, the PMOS transistor 392 and the NMOS transistor 394 are turned off when the control signal netC is a high-level signal, and are turned on when the control signal netC is a low-level signal. A signal obtained by inverting the control signal netB output from the control signal generating circuit 372 by a NOT circuit 397 is input to the gate of the PMOS transistor 396. Therefore, the PMOS transistor 396 is turned off when the control signal netB is a low-level signal, and is turned on when the control signal netB is a high-level signal. A signal obtained by inverting the control signal netA output from the control signal generating circuit 371 by a NOT circuit 399 is input to the gate of the NMOS transistor 398. Therefore, the NMOS transistor 398 is turned on when the control signal netA is a low-level signal, and is turned off when the control signal netA is a high-level signal.

[0033] Therefore, as shown in FIG. 7, when the oscillation of the oscillator circuit 11 has stopped and the oscillation stop detection signal output from the oscillation stop detection circuit 16 is a high-level signal, in the first generation circuit 38, the PMOS transistor 386 is turned on and the PMOS transistor 382, ​​the NMOS transistor 384, and the NMOS transistor 388 are turned off, so that the output line 380 is connected to the first power supply line 21 and the gate input signal PMOS becomes a high-level signal. In the second generation circuit 39, the NMOS transistor 398 is turned on, and the PMOS transistor 392, the NMOS transistor 394, and the PMOS transistor 396 are turned off, so that the output line 390 is connected to the second power supply line 22, and the gate input signal NMOS becomes a low-level signal. Therefore, when oscillation is stopped, the PMOS transistor 361 and the NMOS transistor 362, that is, the switch 36, are in the OFF state (third state), and the second power storage device 32 is disconnected from the first power storage device 31. When oscillation is stopped, there is no control clock for each circuit, so the state of each circuit cannot be determined and switch 36 may be in the on state, but by determining the switch state using the oscillation stop detection signal, switch 36 can be reliably controlled to the off state. Because switch 36 is in the off state when oscillation is stopped, when power generation by generator 70 begins, electrical energy is charged only to first power storage device 31, and as shown in Figure 8, the rate at which the voltage rises is faster than when second power storage device 32 is connected to first power storage device 31.

[0034] When the voltage of the first power storage device 31 rises and exceeds an oscillation start voltage, which is equal to or greater than the operation start voltage of the control IC 10, the control IC 10 operates and oscillation starts in the crystal oscillation circuit 100. After oscillation starts in the crystal oscillation circuit 100, if the voltage of the first power storage device 31 is lower than the first threshold value Vdet1, the oscillation stop detection signal becomes low level, the first voltage detection signal VL1 becomes low level, and as shown in FIG. 7, the gate input signal PMOS is a high level signal and the gate input signal NMOS is a low level signal, so the switch 36 remains off.

[0035] When the voltage of the first power storage device 31 increases and becomes equal to or greater than the first threshold Vdet1 at time t1 in FIG. 8 , the switch 36 enters a weakly on state (second state). That is, when the oscillation-stop detection signal output from the oscillation-stop detection circuit 16 becomes a low-level signal, the voltage of the first power storage device 31 is equal to or greater than the first threshold Vdet1 and the first voltage detection signal VL1 is a high-level signal, and the voltage of the second power storage device 32 is less than the second threshold Vdet2 and the second voltage detection signal VL2 is a low-level signal, in the first generation circuit 38, the PMOS transistor 382 and the NMOS transistor 384 are in an on state, and the PMOS transistor 386 and the NMOS transistor 388 are in an off state. Therefore, by causing a constant current from the first constant current circuit 381 to flow through the saturated-connected PMOS transistor 383, a signal Vsub_p having a voltage level between the voltages VDD and VSS is output from the output line 380 as the gate input signal PMOS. In the second generation circuit 39, the PMOS transistor 392 and NMOS transistor 394 are turned on, and the PMOS transistor 396 and NMOS transistor 398 are turned off. Therefore, by causing the constant current of the second constant current circuit 391 to flow through the saturated-connected NMOS transistor 393, a signal Vsub_n at a voltage level between the voltage VDD and the voltage VSS is output from the output line 390 as the gate input signal NMOS. The voltage levels of the signals Vsub_p and Vsub_n are, for example, VDD-0.45V and 0.45V, respectively, relative to the voltage VSS. Because these voltages are in the weak inversion regions of the PMOS transistor 361 and the NMOS transistor 362, the switch 36 is in a weak on state (second state), and the current flowing through the switch 36 is limited. Therefore, even when the capacity of the first power storage device 31 is small and the capacity of the second power storage device 32 is large, as shown in FIG. 8 , the voltage drop of the first power storage device 31 is suppressed to ensure the voltage, while the voltage of the second power storage device 32 increases. The capacity of the first power storage device 31 is, for example, 5 μF, and the capacity of the second power storage device 32 is, for example, 2 mAh. However, the capacities of the first power storage device 31 and the second power storage device 32 are not limited to these values; the capacity of the second power storage device 32 may be larger than the capacity of the first power storage device 31.

[0036] However, there are cases where the power generation efficiency decreases due to external factors or variations in the gear train load, causing a larger outflow of charge from the first storage device 31 and a drop in the voltage of the first storage device 31. However, by setting the first threshold Vdet1 at a voltage that is sufficient to offset the oscillation stop voltage, even if the voltage of the first storage device 31 drops due to the above-mentioned variations, the oscillation circuit 11 will not stop and switch control can continue. When the voltage of the second storage device 32 gradually increases and reaches or exceeds the second threshold Vdet2 at time t2, it is determined that a sufficient charge has been stored in the second storage device 32, and the switch 36 is turned on (first state) as shown in FIG. 7. The time elapsed from time t1, at which the second power storage device 32 is charged via the switch 36 in the weak-on state and the voltage thereof reaches or exceeds the second threshold value Vdet2, to time t2 depends on the capacity of the second power storage device 32 and the current value that can be passed through the switch 36 in the weak-on state, but is, for example, approximately 5 to 10 days. The current value of the switch 36 in the weak-on state, i.e., the amount of charge transferred per unit time, is set by the voltage values ​​of Vsub_p and Vsub_n input to the gates of the PMOS transistor 361 and the NMOS transistor 362. That is, to increase the amount of charge transferred per unit time through the switch 36, i.e., the current, the voltage level of Vsub_p and the voltage level of Vsub_n input to the gates of the PMOS transistor 361 and the NMOS transistor 362 are reduced and the voltage level of Vsub_n input to the gates of the transistors 361 and 362 are increased. Conversely, to decrease the current, the voltage level of Vsub_p and the voltage level of Vsub_n input to the gates are increased and the voltage level of Vsub_n are decreased, respectively. Furthermore, the voltage levels of Vsub_p and Vsub_n can be changed by changing the magnitude of the constant currents from the first constant current circuit 381 and the second constant current circuit 391, or by changing the capabilities of the PMOS transistor 383 and the NMOS transistor 393 that pass the constant current.

[0037] After this, when the spring torque is large, the electrical energy generated by the generator 70 is large, and therefore the voltage of the first power storage device 31 is maintained at a high level, and charging from the first power storage device 31 to the second power storage device 32 continues. When the mainspring torque decreases, the electrical energy generated by the generator 70 decreases and the voltage of the first power storage device 31 becomes equal to or lower than that of the second power storage device 32, so that charge moves from the second power storage device 32 to the first power storage device 31, thereby preventing a drop in the voltage of the first power storage device 31. In other words, even if the mainspring torque decreases and the mechanical energy required for power generation decreases, the voltage required to drive the control IC 10 can be secured, so the duration can be extended.

[0038] [Effects of the first embodiment] According to the electronically controlled mechanical watch 1 of the first embodiment, the switch 36 of the connection circuit 35 is controlled in accordance with the first voltage detection signal VL1 and the second voltage detection signal VL2 that detect the voltages of the first storage device 31 and the second storage device 32, and the oscillation stop detection signal that indicates the oscillation stop state. Therefore, even if the second storage device 32 is completely discharged, the voltage of the first storage device 31 can be quickly increased by controlling the switch 36 to the off state (third state) until the voltage of the first storage device 31 exceeds the first threshold Vdet1, thereby shortening the time until a voltage sufficient to oscillate the crystal oscillation circuit 100 and drive the control IC 10 can be secured. Furthermore, when the voltage of the first storage device 31 exceeds the first threshold Vdet1, the switch 36 is controlled to a weak on state (second state) to control the amount of charge to the second storage device 32, thereby preventing or suppressing a voltage drop in the first storage device 31 and allowing the second storage device 32 to be charged while maintaining a voltage capable of driving the control IC 10. Furthermore, when the second storage device 32 is sufficiently charged, the voltage of the first storage device 31 is equal to or greater than the first threshold Vdet1, and the voltage of the second storage device 32 is equal to or greater than the second threshold Vdet2, by controlling the switch 36 to the on state (first state), the control IC 10 can be driven by the electrical energy stored in the second storage device 32 even in the final stages when the mainspring 40 is unwound, and the running time of the electronically controlled mechanical timepiece 1 can be extended.

[0039] The electronically controlled mechanical timepiece 1 is equipped with a generator 70 that generates electricity using the mechanical energy of the mainspring 40, and the generator 70 also serves as a regulator that regulates the speed of the speed-increasing train wheel 50, thereby improving the volumetric efficiency of the movement and enabling the movement to be made more compact. Furthermore, there is no need to provide other power generating means such as an additional generator to extend the duration, which also contributes to the miniaturization of the movement.

[0040] [Second embodiment] Next, an electronically controlled mechanical timepiece 1B according to a second embodiment will be described with reference to FIGS. As shown in FIG. 9, the electronically controlled mechanical timepiece 1B has the same configuration as the first embodiment except for the switch control circuit 17 of the control IC 10B and the connection circuit 35B of the power supply circuit 30B, so the same reference numerals are used and the description will be omitted.

[0041] The connection circuit 35B of the power supply circuit 30B is provided in the control IC 10B, and includes a first switch 410, a second switch 420, a first logic circuit 430, a second logic circuit 440, and a third power storage device 33, as shown in FIG. Similar to the switch 36, the first switch 410 includes an analog switch configured of a PMOS transistor 411 and an NMOS transistor 412 connected in parallel, and a NOT circuit 413. The NOT circuit 413 is connected to the gate of the PMOS transistor 411 and inverts the signal input to the gate of the PMOS transistor 411. Similar to the first switch 410, the second switch 420 includes an analog switch configured of a PMOS transistor 421 and an NMOS transistor 422 connected in parallel, and a NOT circuit 423. The NOT circuit 423 is connected to the gate of the PMOS transistor 421, and inverts the signal input to the gate of the PMOS transistor 421. As in the first embodiment, each of the analog switches, the first switch 410 and the second switch 420, has PMOS transistors 411, 421 and NMOS transistors 412, 422 connected in parallel, and is therefore designed to have low loss even if the direction of current flow changes.

[0042] The third power storage device 33 is a small-capacity capacitor built into the connection circuit 35B, i.e., the control IC 10B. Although the third power storage device 33 can be provided outside the control IC 10B, arranging it inside the control IC 10B can improve wiring efficiency. The third power storage device 33 is connected in parallel to the first power storage device 31 via the first switch 410, and is connected in parallel to the second power storage device 32 via the second switch 420. The first power storage device 31 is configured by a capacitor as in the first embodiment, and the second power storage device 32 is configured by a secondary battery as in the first embodiment. The capacities of the first storage device 31, the second storage device 32, and the third storage device 33 can be set as appropriate for implementation. For example, an example of the capacitance ratio when it is assumed that a constant current can flow even when the voltage changes is as follows: That is, if the capacitance of the third storage device 33 is 5 pF and this capacitance is set to 1, the capacitance of the first storage device 31 is 10 times the capacitance of the third storage device 33. 6 The capacitance of the second power storage device 32 is approximately 1.5×10 times that of the third power storage device 33, that is, approximately 5 μF. 12 It is about twice as much, or about 2mAh.

[0043] The first logic circuit 430 is a circuit that controls the first switch 410, and includes an OR circuit 431, a NAND circuit 432, and a NOR circuit 433. The OR circuit 431 receives the first switch control signal output from the switch control circuit 17 and the second voltage detection signal VL2. The NAND circuit 432 receives the output of the OR circuit 431 and the first voltage detection signal VL1. The NOR circuit 433 receives the output of the NAND circuit 432 and the oscillation stop detection signal. The output of the NOR circuit 433 is input to the first switch 410. That is, the output of the NOR circuit 433 is input to the gate of the NMOS transistor 412, and is inverted by the NOT circuit 413 and input to the gate of the PMOS transistor 411.

[0044] The second logic circuit 440 is a circuit that controls the second switch 420, and similar to the first logic circuit 430, includes an OR circuit 441, a NAND circuit 442, and a NOR circuit 443. The OR circuit 441 receives the second switch control signal output from the switch control circuit 17 and the second voltage detection signal VL2. The NAND circuit 442 receives the output of the OR circuit 441 and the first voltage detection signal VL1. The NOR circuit 443 receives the output of the NAND circuit 442 and the oscillation stop detection signal. The output of the NOR circuit 443 is input to the second switch 420. That is, the output of the NOR circuit 443 is input to the gate of the NMOS transistor 422, and is inverted by the NOT circuit 423 and input to the gate of the PMOS transistor 421.

[0045] FIG. 11 is a diagram showing the relationship between the oscillation stop detection signal, the first voltage detection signal VL1, the second voltage detection signal VL2, the first switch control signal, the second switch control signal, and the states of the first switch 410 and the second switch 420. When the oscillation stop detection circuit 16 detects that the crystal oscillation circuit 100 has stopped oscillating and the oscillation stop detection signal is at a high level, the first switch 410 and the second switch 420 are both turned off and controlled to a third state that disconnects the first power storage device 31 from the third power storage device 33. Therefore, in the oscillation stop state, the charge supplied from the generator 70 via the rectifier circuit 90 is stored only in the first power storage device 31, ensuring a sufficient voltage rise rate. When the voltage of the first power storage device 31 rises and reaches the oscillation start voltage of the crystal oscillator circuit 100, which is equal to or higher than the operation start voltage of the control IC 10B, the crystal oscillator circuit 100 starts oscillating, and the control IC 10B starts operating, the voltage of the first power storage device 31 is lower than the first threshold Vdet1, so the first switch 410 and the second switch 420 remain in the off state (third state).

[0046] Furthermore, when the voltage of the first storage device 31 rises to or exceeds the first threshold Vdet1 and the voltage of the second storage device 32 is less than the second threshold Vdet2, the first switch 410 and the second switch 420 are controlled by a first switch control signal and a second switch control signal input from the switch control circuit 17. The first switch 410 is turned on when the first switch control signal is at a high level and turned off when the second switch control signal is at a low level. Similarly, the second switch 420 is turned on when the second switch control signal is at a high level and turned off when the second switch control signal is at a low level. As shown in FIG. 12 , when the crystal oscillation circuit 100 starts oscillating, that is, when the oscillation stop detection signal becomes low, the switch control circuit 17 outputs the first switch control signal and the second switch control signal. At this time, the switch control circuit 17 outputs each control signal so that there is no period in which both the first switch control signal and the second switch control signal are at a high level. Therefore, a first open / close control period in which the first switch 410 is controlled to a first open / close state in which the second switch 420 is controlled to an off state and a second open / close control period in which the first switch 410 is controlled to an off state and the second switch 420 is controlled to an on state alternates, sandwiched between switch-off periods in which both the first switch 410 and the second switch 420 are disconnected and turned off. The frequency at which first switch 410 and second switch 420 are turned on and off can be set as appropriate, for example, to 4 kHz. The amount of charge that moves per unit time from first power storage device 31 to second power storage device 32 via third power storage device 33 and the amount of charge that moves from second power storage device 32 to first power storage device 31 via third power storage device 33, i.e., the average current value that flows per unit time, is changed by the frequency at which each switch 410, 420 is turned on and off.

[0047] During the first opening / closing control period, the first switch 410 is in the ON state and the second switch 420 is in the OFF state, so the charge stored in the first power storage device 31 is transferred to the third power storage device 33. At this time, because the capacity of the third power storage device 33 is smaller than the capacity of the first power storage device 31, the amount of charge transferred to the third power storage device 33 is small, and the voltage drop of the first power storage device 31 is small. Next, the switch-off period begins, and the first switch 410 and the second switch 420 are turned off, so that the connection between the first power storage device 31 and the third power storage device 33 is released and the charge stored in the third power storage device 33 is preserved. Next, during the second open / close control period, the second switch 420 is in the ON state and the first switch 410 is in the OFF state, so that part of the charge stored in the third storage device 33 is transferred to the second storage device 32. At this time, the capacity of the third storage device 33 is significantly smaller than the capacity of the second storage device 32, so the voltage of the third storage device 33 drops significantly depending on the voltage of the second storage device 32. However, because the first switch 410 is in the OFF state and the connection between the first storage device 31 and the third storage device 33 is released, this does not affect the voltage of the first storage device 31.

[0048] Thereafter, the first switching control period and the second switching control period are alternately and repeatedly executed with a switch-off period sandwiched therebetween. As described above, by alternately executing the first opening / closing control and the second opening / closing control, the charge stored in the first power storage device 31 can be transferred little by little to the high-capacity second power storage device 32 via the third power storage device 33. Therefore, the amount of charge transferred per unit time between the first power storage device 31 and the second power storage device 32 is smaller than in the first state in which the first switch 410 and the second switch 420 are both in the on state. Therefore, the period in which the first opening / closing control period and the second opening / closing control period are alternately executed is the second state similar to the weak on state of the first embodiment, and the second power storage device 32 can be charged while maintaining the voltage of the first power storage device 31.

[0049] Here, as with the first embodiment, the first threshold value Vdet1 is set to a voltage that is relatively high relative to the oscillation stop voltage, i.e., a voltage with a margin, depending on factors such as a decrease in power generation efficiency due to external factors and the capacity ratio between the first storage device 31 and the third storage device 33. In the second embodiment, a switch-off period is provided between the first opening / closing control period and the second opening / closing control period, in which the first storage device 31 and the second storage device 32 are disconnected from each other, and the third storage device 33 and the second storage device 32 are also disconnected from each other. Therefore, even if a delay occurs in the signal controlling the connection between the second storage device 32 and the third storage device 33 due to wiring routing within the control IC 10B, it is possible to prevent the first storage device 31 and the second storage device 32 from being electrically connected, i.e., the first switch 410 and the second switch 420 from being turned on simultaneously.

[0050] When the voltage further increases and the voltage of the second storage device 32 becomes equal to or greater than the second threshold Vdet2, as shown in FIG. 11, regardless of the switch control signal, the first switch 410 and the second switch 420 are both in the on state, i.e., the first state in which the first storage device 31, the second storage device 32, and the third storage device 33 are connected is entered. Thereafter, when the mainspring torque is large, charging from the first power storage device 31 to the second power storage device 32 via the third power storage device 33 continues. When the mainspring torque decreases, charge moves from the second power storage device 32 to the first power storage device 31 via the third power storage device 33, thereby preventing a voltage drop in the first power storage device 31. In other words, even if the mainspring torque decreases and the mechanical energy required for power generation decreases, the voltage required to drive the control IC 10B can be secured, and the duration can be extended.

[0051] With the above configuration, even if the second storage device 32 is completely discharged, the amount of charge to the second storage device 32 via the third storage device 33 can be controlled, and the time required to secure a voltage capable of driving the control IC 10B can be shortened. Furthermore, by winding the mainspring 40 and generating electricity with the generator 70, it is possible to recharge not only the first storage device 31 but also the second storage device 32. Therefore, even at the end of the period when the mainspring 40 is unwound, the charge stored in the second storage device 32 can be transferred to the first storage device 31 to drive the control IC 10B, thereby once again achieving the effect of extending the duration.

[0052] Next, changes in voltage of the first power storage device 31, the second power storage device 32, and the third power storage device 33 in the second embodiment will be described with reference to FIG. When the generator 70 starts generating electricity while the first power storage device 31, the second power storage device 32, and the third power storage device 33 are in a discharged state, the voltage Vc1 of the first power storage device 31 rises. When the voltage Vc1 exceeds the oscillation start voltage Vsta of the control IC 10B and further becomes equal to or greater than the first threshold value Vdet1, the on / off control of the first switch 410 and the second switch 420 starts. At time t1 when the voltage Vc1 of the first power storage device 31 becomes equal to or greater than the first threshold Vdet1, the first switch 410 is turned on, and the first power storage device 31 and the third power storage device 33 are connected. The voltage V2 of the first power storage device 31 and the third power storage device 33 at this time is given by the following equation (1). In equation (1), the voltage of the first power storage device 31 immediately before the first switch 410 is turned on is given by V1, the capacity of the first power storage device 31 is given by C1, and the capacity of the third power storage device 33 is given by C3.

[0053]

number

[0054] From time t1 to time t2, the voltages of the first power storage device 31 and the third power storage device 33 rise simultaneously. At time t2, the first switch 410 turns off, disconnecting the first power storage device 31 from the third power storage device 33. Thereafter, the voltage of the first power storage device 31 rises until time t5, when the first power storage device 31 is next connected to the third power storage device 33. At time t3, the second switch 420 is turned on, connecting the third power storage device 33 and the second power storage device 32. At this time, the voltage V4 of the third power storage device 33 and the second power storage device 32 is expressed by the following equation (2). In equation (2), the voltage of the third power storage device 33 immediately before the second switch 420 is turned on is V3, and the capacity of the second power storage device 32 is C2. Because the capacity C2 of the second power storage device 32 is much larger than the capacity C3 of the third power storage device 33, the voltage of the third power storage device 33 immediately drops significantly, and the second power storage device 32 and the third power storage device 33 have the same voltage V4.

[0055]

number

[0056] At time t4, the second switch 420 is turned off, and the connection between the third power storage device 33 and the second power storage device 32 is released. At time t5, the first switch 410 is turned on, and the first power storage device 31 and the third power storage device 33 are connected again. At this time, the voltage V2' of the first power storage device 31 and the third power storage device 33 is given by the following equation (3). In equation (3), the voltage of the first power storage device 31 immediately before the first switch 410 is turned on is V1', and the voltage of the third power storage device 33 is V4.

[0057]

number

[0058] Until time t6, the voltages of first power storage device 31 and third power storage device 33 increase simultaneously. At time t6, first switch 410 is turned off, disconnecting first power storage device 31 from third power storage device 33. Thereafter, the voltage of first power storage device 31 rises until the next time it is connected to third power storage device 33. At time t7, the second switch 420 is turned on, connecting the third power storage device 33 and the second power storage device 32. At this time, the voltage V4' of the third power storage device 33 and the second power storage device 32 is expressed by the following equation (4). In equation (4), the voltage of the third power storage device 33 immediately before the second switch 420 is turned on is V3', and the voltage of the second power storage device 32 is V4.

[0059]

number

[0060] Thereafter, the same switch control as that performed at times t4 to t7 is repeated, so that the voltage of second power storage device 32 gradually increases. At time t8, when the voltage of the second power storage device 32 rises to V4″ and exceeds the second threshold value Vdet2, the first switch 410 and the second switch 420 are simultaneously turned on, all of the power storage devices 31 to 33 are connected, and the voltages of all of the power storage devices 31 to 33 rise simultaneously. Thereafter, when the mainspring 40 unwinds and reaches the end of its life, the voltage of the first power storage device 31 drops, but the charge stored in the second power storage device 32 moves to the first power storage device 31, compensating for the drop in voltage of the first power storage device 31. This makes it possible to delay the stopping of the speed regulation of the control IC 10B, and the running time of the electronically controlled mechanical timepiece 1B can be extended.

[0061] [Effects of the second embodiment] The electronically controlled mechanical timepiece 1B of the second embodiment can also achieve the same effects as the electronically controlled mechanical timepiece 1 of the first embodiment. Furthermore, the second state, which is a weakly on state, can be achieved simply by controlling the on / off cycles of the first switch 410 and the second switch 420, so that control circuits for the first switch 410 and the second switch 420 can be easily configured.

[0062] [Variations] The present disclosure is not limited to the above-described embodiments, and includes modifications, improvements, etc. within the scope of achieving the object of the present disclosure. For example, the amount of charge transfer per unit time during the weak on state, which is the second state, may be controlled so as to be changeable in accordance with the electrical energy generated by generator 70. For example, when the electrical energy of generator 70 is large, that is, when the mechanical energy stored in mainspring 40 is large, the rate of increase in the voltage of first power storage device 31 increases, but the power generation efficiency decreases as the difference with the induced voltage during power generation decreases. Therefore, when the electrical energy of generator 70 is large, the amount of charge transferred per unit time during the weak on state is increased to suppress the rate of increase in the voltage of first power storage device 31, thereby increasing the amount of charge to second power storage device 32 and improving the power generation efficiency of generator 70.

[0063] In the first embodiment, the amount of charge transferred per unit time can be changed by adjusting the voltage level input to the gates of the PMOS transistor 361 and NMOS transistor 362 of the switch 36. To increase the amount of charge transferred per unit time, the gate voltage Vgs, which is the gate-source voltage with the source as the reference, is increased; conversely, to decrease the amount of charge transferred per unit time, the gate voltage Vgs is decreased. The voltage level input to the gates of the transistors 361 and 362 can be changed by varying the constant currents of the first constant current circuit 381 and the second constant current circuit 391, or by changing the capabilities of the PMOS transistor 383 and the NMOS transistor 393 that pass the constant current. In the second embodiment, the amount of charge transferred per unit time can be changed by adjusting the frequencies of the first switch control signal and the second switch control signal. To increase the amount of charge transferred per unit time, the frequency of each switch control signal can be increased, and conversely, to decrease the amount of charge transferred per unit time, the frequency of each switch control signal can be decreased. To change the frequency of each switch control signal, the frequency of the clock that generates the switch control signal can be changed.

[0064] Because the electrical energy of generator 70 is proportional to the mechanical energy of spring 40 that rotates the rotor of generator 70, the electrical energy of generator 70 can also be detected by detecting the amount of braking of the rotor by braking control circuit 14. In other words, when the amount of braking is large, the mechanical energy transmitted to generator 70 is also large, so it can be detected that the electrical energy of generator 70 is large, and when the amount of braking is small, it can be detected that the electrical energy of generator 70 is small.

[0065] Not only when oscillation stops, but also when it is detected that the mainspring 40 has unwound and the wheel train has stopped, the connection circuits 35, 35B may be set to the third state to disconnect the first power storage device 31 and the second power storage device 32. This makes it possible to prevent the second power storage device 32 from discharging when the hands of the electronically controlled mechanical timepieces 1, 1B stop moving. The connection state between first power storage device 31 and second power storage device 32 by connection circuit 35 is not limited to being switchable among three states: a first state which is an on state, a second state which is a weak on state, and a third state which is a disconnected state, and may be configured to be switchable among four or more states. For example, the gate voltage Vgs of a MOSFET having the characteristics of Figures 5A and 5B may be input at multiple levels such as 0.7 V, 0.8 V, and 1.0 V, which are in a strong inversion region, so that the drain current in the strong inversion region can be changed in multiple steps. Alternatively, the gate voltage Vgs of the MOSFET may be input at multiple levels such as 0.2 V, 0.4 V, and 0.5 V, which are in a weak inversion region, so that the drain current in the weak inversion region can be changed in multiple steps. In the connection circuit 35B of the second embodiment, a switch-off period is provided between the first opening / closing control period and the second opening / closing control period, but the switch-off period may be eliminated.

[0066] In the above embodiment, the invention is applied to an electronically controlled mechanical timepiece 1 in which the rotor of the generator 70, which also serves as a speed regulator, is rotated by mechanical energy from the mainspring 40, and the rotational speed of the rotor is regulated and controlled to control the speed of movement of each hand 4, but is not limited to this. For example, the invention may be applied to an electronically controlled mechanical timepiece in which, when the train wheel that transmits mechanical energy from the mainspring 40 is regulated using an escape wheel, anchor, and balance, the vibration of the balance is detected to regulate the operation of the balance.

[0067] [summary] The electronically controlled mechanical timepiece disclosed herein comprises a mainspring, a train wheel that transmits the mechanical energy of the mainspring, hands driven by the train wheel to display the time, a regulator that controls the rotation period of the train wheel, a control means that controls the regulator, a generator that converts the mechanical energy into electrical energy, a first storage device that stores the electrical energy of the generator and supplies the electrical energy to the control means, a second storage device that can store electrical energy, and a connection circuit that can connect the first storage device and the second storage device in parallel, wherein the connection circuit is switchable between at least three states: a first state that connects the first storage device and the second storage device; a second state that connects the first storage device and the second storage device in a state where the amount of charge transferred per unit time is less than in the first state; and a third state that disconnects the first storage device and the second storage device. According to the electronically controlled mechanical timepiece of the present disclosure, the connection circuit, which can connect the first and second power storage devices in parallel, can be switched between three states: state 1, state 2, and state 3, allowing the state of the connection circuit to be selected depending on the winding state of the mainspring and the charge state of each power storage device. Therefore, when each power storage device is discharging, the connection circuit can be set to state 3, connecting only the first power storage device to the generator side for charging, thereby quickly increasing the voltage of the first power storage device and shortening the time until a control means such as an IC begins speed regulation control. Furthermore, even when the second power storage device is discharging and its voltage is low, the connection circuit can be set to state 2 to adjust the amount of charge transferred from the first power storage device to the second power storage device, allowing the second power storage device, which has a larger capacity, to be charged while suppressing a voltage drop of the first power storage device. When the mainspring unwinds and the mechanical energy transmitted to the generator decreases, causing a decrease in the electrical energy generated by the generator, electrical energy can be supplied from the second power storage device to the first power storage device, so the voltage level of the first power storage device can be maintained at a voltage that allows the control means to operate for a long period of time, thereby extending the duration. Furthermore, by adding the second power storage device and connection circuit, there is no need to provide an additional generator, which also helps prevent the movement from becoming larger.

[0068] In the electronically controlled mechanical timepiece disclosed herein, it is preferable that the connection circuit is in the first state when the voltage of the first storage device is equal to or greater than a first threshold and the voltage of the second storage device is equal to or greater than a second threshold, is in the second state when the voltage of the first storage device is equal to or greater than the first threshold and the voltage of the second storage device is less than the second threshold, and is in the third state when the voltage of the first storage device is less than the first threshold. According to the electronically controlled mechanical timepiece of the present disclosure, when the voltage of the first power storage device is low and below the first threshold, the connection circuit is set to the third state and only the first power storage device is connected to the generator, so the voltage of the first power storage device can be increased in a short time. Therefore, even when the mainspring is unwound, the wheel train is stopped, and the control means is also stopped, once the mainspring is wound up, the wheel train starts moving, and the generator begins to generate electricity, the control means can start operating in a short time and perform speed regulation control. When the voltage of the first power storage device is equal to or greater than the first threshold and the voltage of the second power storage device is less than the second threshold, the connection circuit transitions to the second state. In the second state, the amount of charge transfer per unit time, i.e., the value of the current flowing through the switch, is limited. Therefore, even if the capacity of the first power storage device is significantly smaller than that of the second power storage device, the second power storage device can be charged while suppressing a voltage drop of the first power storage device, and it is also possible to prevent the voltage of the first power storage device from dropping below the stop voltage of the control means. When the voltage of the first power storage device is equal to or greater than a first threshold and the voltage of the second power storage device is equal to or greater than a second threshold, the connection circuit transitions to a first state. In the first state, the connection circuit is maintained in a constantly connected state, so that even when the mainspring is unwound and the amount of generated energy is reduced, the energy stored in the second power storage device can be used to continue to operate the control means, thereby extending the running time of the electronically controlled mechanical timepiece.

[0069] In the electronically controlled mechanical timepiece of the present disclosure, the connection circuit includes a switch that connects the first power storage device and the second power storage device, the switch being composed of a metal oxide semiconductor field effect transistor, and the amount of charge transfer can be adjusted by the voltage level of a control signal input to the gate of the metal oxide semiconductor field effect transistor, and it is preferable that the second state is such that the voltage level of the control signal input to the gate is the voltage level in the weak inversion region of the metal oxide semiconductor field effect transistor. According to the electronically controlled mechanical timepiece of the present disclosure, the amount of charge transfer can be adjusted by adjusting the input voltage to the gate of the metal oxide semiconductor field effect transistor that constitutes the switch. In this case, by applying a voltage in the weak inversion region, the amount of charge transfer can be reduced compared to when applying a voltage in the strong inversion region, and the voltage of the first power storage device can be maintained while charging the second power storage device.

[0070] In the electronically controlled mechanical timepiece of the present disclosure, the connection circuit may include a third storage device having a smaller capacity than the first storage device, a first switch connecting the first storage device and the third storage device, and a second switch connecting the third storage device and the second storage device, and the second state may be a state in which a first open / close state in which the first switch is connected and the second switch is disconnected, and a second open / close state in which the first switch is disconnected and the second switch is connected, are alternately repeated. According to the electronically controlled mechanical timepiece of the present disclosure, charge can be transferred little by little between the first and second power storage devices via the third power storage device. Also, by transferring charge via the third power storage device, which has a smaller capacity than the first power storage device, the voltage drop of the first power storage device when the first switch is connected can be reduced, and the second power storage device can be charged while maintaining the voltage of the first power storage device.

[0071] In the electronically controlled mechanical timepiece of the present disclosure, it is preferable that the second state has a period between the first opening / closing state and the second opening / closing state in which both the first switch and the second switch are disconnected. According to the electronically controlled mechanical timepiece of the present disclosure, a period is provided in which both of the switches are simultaneously disconnected, so that delays in the signals controlling the connection of the power storage devices due to wiring routing within the control IC, etc., can be prevented, preventing malfunctions such as the first power storage device, the second power storage device, and the third power storage device being electrically connected simultaneously.

[0072] In the electronically controlled mechanical timepiece of the present disclosure, it is preferable to have an oscillation means that outputs a clock signal and an oscillation stop detection means that detects the stop of the oscillation means, and when the oscillation stop detection means detects the stop of the oscillation means, to switch the connection circuit to the third state. According to the electronically controlled mechanical timepiece of the present disclosure, when the oscillator stops and the voltage is so low that a control clock signal cannot be generated, it is possible to prevent the first and second storage devices from being connected due to a malfunction, and to prevent a decrease in the rate of voltage rise of the first storage device when the generator generates electricity.

[0073] In the electronically controlled mechanical timepiece of the present disclosure, it is preferable that a detection means is provided for detecting the electrical energy generated by the generator, and the connection circuit changes the amount of charge movement per unit time in the second state according to the electrical energy detected by the detection means. According to the electronically controlled mechanical timepiece of the present disclosure, when the electrical energy generated by the generator is large, the rate of voltage rise of the first storage device can be suppressed by increasing the amount of charge transferred per unit time in the second state, and the difference between the induced voltage of the generator and the voltage of the first storage device can be prevented from becoming too small, thereby improving power generation efficiency and increasing the amount of charge to the second storage device. [Explanation of symbols]

[0074] 1...electronically controlled mechanical clock, 1B...electronically controlled mechanical clock, 4...hand, 10...control IC, 10B...control IC, 11...oscillation circuit, 12...frequency divider circuit, 13...rotation detection circuit, 14...brake control circuit, 15...power supply voltage detection circuit, 16...oscillation stop detection circuit, 17...switch control circuit, 21...first power supply line, 22...second power supply line, 30...power supply circuit, 30B...power supply circuit, 31...first power storage device, 32...second power storage device, 33...third power storage device, 35...connection circuit, 35B...connection circuit, 36...switch, 37...gate input signal generating circuit, 40...spring, 50...speed increasing gear train, 60...display unit, 70...generator, 80...quartz crystal oscillator, 90...rectifier circuit, 100...quartz crystal oscillator circuit, 361...PMOS transistor, 362...NMOS transistor, 410...first switch, 411...PMOS transistor, 412...NMOS transistor, 420...second switch, 421...PMOS transistor, 422...NMOS transistor.

Claims

1. Spring and a gear train that transmits mechanical energy of the mainspring; A hand driven by the train wheel to display the time; a governor that controls the rotation period of the wheel train; a control means for controlling the speed governor; a generator that converts the mechanical energy into electrical energy; a first power storage device that stores the electric energy of the generator and supplies the electric energy to the control means; a second power storage device capable of storing electrical energy; a connection circuit capable of connecting the first power storage device and the second power storage device in parallel, The connection circuit includes: a first state in which the first power storage device and the second power storage device are connected; a second state in which the first power storage device and the second power storage device are connected in a state in which an amount of charge transfer per unit time is smaller than in the first state; a third state in which the first power storage device and the second power storage device are disconnected from each other; It can be switched to at least three states: An electronically controlled mechanical watch characterized by:

2. 2. The electronically controlled mechanical timepiece according to claim 1, The connection circuit includes: The first state is established when the voltage of the first power storage device is equal to or greater than a first threshold and the voltage of the second power storage device is equal to or greater than a second threshold, the second state is established when the voltage of the first power storage device is equal to or greater than the first threshold value and the voltage of the second power storage device is less than the second threshold value; When the voltage of the first power storage device is less than the first threshold, the third state is established. An electronically controlled mechanical watch characterized by:

3. 2. The electronically controlled mechanical timepiece according to claim 1, The connection circuit includes: a switch that connects the first power storage device and the second power storage device; the switch is composed of a metal oxide semiconductor field effect transistor, and the amount of charge transfer can be adjusted by the voltage level of a control signal input to a gate of the metal oxide semiconductor field effect transistor; In the second state, the voltage level of the control signal input to the gate is a voltage level in a weak inversion region of the metal oxide semiconductor field effect transistor. An electronically controlled mechanical watch characterized by:

4. 2. The electronically controlled mechanical timepiece according to claim 1, The connection circuit includes: a third power storage device having a capacity smaller than that of the first power storage device; a first switch connecting the first power storage device and the third power storage device; a second switch connecting the third power storage device and the second power storage device, The second state is a first open / close state in which the first switch is connected and the second switch is disconnected; a second open / close state in which the first switch is disconnected and the second switch is connected, and An electronically controlled mechanical watch characterized by:

5. 5. The electronically controlled mechanical timepiece according to claim 4, In the second state, a period in which both the first switch and the second switch are turned off is provided between the first open / close state and the second open / close state. An electronically controlled mechanical watch characterized by:

6. 2. The electronically controlled mechanical timepiece according to claim 1, an oscillator for outputting a clock signal; an oscillation stop detection means for detecting a stop of the oscillation means, When the oscillation stop detection means detects the stop of the oscillation means, the connection circuit is switched to the third state. An electronically controlled mechanical watch characterized by:

7. 2. The electronically controlled mechanical timepiece according to claim 1, a detection means for detecting the electric energy generated by the generator; The connection circuit includes: The amount of charge movement per unit time in the second state is changed according to the electric energy detected by the detection means. An electronically controlled mechanical watch characterized by:

Images