Configuration change mechanism, processing system, processing method, and program

Abstract

To provide a configuration change mechanism for suppressing declines in a propagation speed of information between a CPU (Central Processing Unit) and a common memory and in a propagation speed of information between a device and the common memory in the case of adding the device and the common memory cooperating with arithmetic processing in order to execute processing that cannot be processed by a single arithmetic processing part unit including the CPU and an internal memory.SOLUTION: In a processing system 1, a configuration change mechanism is provided with a connection control part for specifying a device and a common memory which cooperate with an arithmetic processing part on the basis of a first connection distance between a CPU (Central Processing Unit) and the common memory and a second connection distance between the device and the common memory in the case of executing processing that cannot be executed by a single arithmetic processing part unit including the CPU and an internal memory.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a configuration change mechanism, a processing system, a processing method, and a program. [Background technology]

[0002] Various processes are performed using a shared memory that is accessed by multiple devices. Patent Document 1 discloses a related technology relating to a memory system that can improve the utilization efficiency of memory resources that make up a memory hierarchy. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-135760 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology using a shared memory related to Patent Document 1, in order to execute processing that cannot be processed by a central processing unit (CPU) and an internal memory alone, a shared memory may be added in addition to a device that cooperates with the processing unit. In such cases, there is a need for a technology that can suppress a decrease in the speed of information propagation between the CPU and the shared memory, and between the device and the shared memory.

[0005] The objective of each aspect of the present disclosure is to provide a configuration change mechanism, a processing system, a processing method, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a configuration change mechanism includes a connection control unit that, when executing processing that cannot be processed by a processing unit alone that has a CPU (Central Processing Unit) and internal memory, identifies a device and shared memory that cooperate with the processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory.

[0007] According to another aspect of the present disclosure, a processing system includes the above-mentioned configuration change mechanism, and a connection control mechanism provided between a main processing mechanism and the device and the shared memory so that the device and the shared memory are connected to a desired main processing mechanism having a connection control unit including a CPU (Central Processing Unit) and an internal memory, and which connects the main processing mechanism to the device and the shared memory in response to instructions from the configuration change mechanism.

[0008] According to another aspect of the present disclosure, a processing method includes, when executing processing that cannot be processed by a processing unit having a CPU (Central Processing Unit) and internal memory alone, identifying a device and a shared memory that cooperate with the processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory.

[0009] According to another aspect of the present disclosure, the program causes a computer to, when executing processing that cannot be processed by a processing unit having a CPU (Central Processing Unit) and internal memory alone, identify a device and shared memory that cooperate with the processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory. [Effects of the Invention]

[0010] According to each aspect of the present disclosure, when a device and shared memory that cooperate with a processing unit having a CPU (Central Processing Unit) and internal memory are added to perform processing that cannot be processed by the processing unit alone, it is possible to suppress a decrease in the speed of information propagation between the CPU and the shared memory, and between the device and the shared memory. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 illustrates an example of a configuration of a processing system according to some embodiments of the present disclosure. [Figure 2] 10A and 10B are diagrams illustrating an example of a configuration of a connection portion according to some embodiments of the present disclosure. [Figure 3] FIG. 1 illustrates an example of connection distances according to some embodiments of the present disclosure. [Figure 4] FIG. 10 is a diagram illustrating an example of utilization efficiency stored in a configuration storage unit according to some embodiments of the present disclosure. [Figure 5] FIG. 10 is a diagram illustrating an example of configuration information according to some embodiments of the present disclosure. [Figure 6] FIG. 10 is a diagram illustrating an example of memory efficiency information according to some embodiments of the present disclosure. [Figure 7] FIG. 2 is a diagram illustrating a first example of a processing flow of a processing system according to some embodiments of the present disclosure. [Figure 8] FIG. 10 is a diagram illustrating a second example of a processing flow of a processing system according to some embodiments of the present disclosure. [Figure 9] FIG. 10 is a diagram illustrating an example of a configuration of a configuration change mechanism according to another embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating an example of a processing flow of a configuration change mechanism according to another embodiment of the present disclosure. [Figure 11] FIG. 1 is a schematic block diagram illustrating the configuration of a computer according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings. <Embodiment> (Processing system configuration) A processing system 1 according to an embodiment of the present disclosure will be described with reference to the drawings. The processing system 1 is a system that can suppress a decrease in the speed of information propagation between a CPU (Central Processing Unit) and the shared memory, and between the device and the shared memory, when a device and a shared memory that cooperate with a processing unit including a CPU and an internal memory are added to execute processing that cannot be processed by the processing unit alone.

[0013] FIG. 1 is a diagram illustrating an example of the configuration of a processing system 1 according to some embodiments of the present disclosure. As shown in FIG. 1, the processing system 1 includes main processing units 10a1, 10a2,..., shared memories 20a1, 20a2,..., devices 30a1, 30a2,..., a connection control unit 40, and a configuration change unit 50. The main processing units 10a1, 10a2,... may be collectively referred to as main processing unit 10. The shared memories 20a1, 20a2,... may be collectively referred to as shared memory 20. The devices 30a1, 30a2,... may be collectively referred to as device 30. Note that, as will be described later, processes A1 and A2 in FIG. 1 require the device 30 and the shared memory 20 in addition to the processing unit 102. Processes A1 and A2 may be collectively referred to as process A.

[0014] Each of the main processing units 10 includes an execution control unit 101 and a processing unit 102. When executing process A, the execution control unit 101 requests the shared memory 20 and the device 30 from the configuration change unit 50. The execution control unit 101 then instructs the processing unit 102 to execute the process using the allocated shared memory 20 and device 30.

[0015] The arithmetic processing unit 102 includes a CPU 102a and an internal memory 102b. Each main processing unit 10 is connected to a shared memory 20 and a device 30 via a connection control unit 40. The processes that each main processing unit 10 can execute independently are the processes executed by the arithmetic processing unit 102 (i.e., the CPU 102a and the internal memory 102b). Because there are limits to the processes that the CPU 102a and the internal memory 102b can execute, the main processing unit 10 executes process A using, in addition to the arithmetic processing unit 102, the shared memory 20 and the device 30 allocated in response to a request from the execution control unit 101, i.e., the shared memory 20 and the device 30 connected via the connection control unit 40. In other words, the arithmetic processing unit 102 executes process A in cooperation with the shared memory 20 and the device 30 connected via the connection control unit 40 in response to a request from the execution control unit 101.

[0016] Each of the shared memories 20 is memory that is also used by devices other than the main processing unit 10. Each of the devices 30 is a device of various types.

[0017] As shown in FIG. 1, the connection control mechanism 40 includes a configuration change unit 401, a monitoring unit 402, and a connection unit 403. The configuration change unit 401 changes the connection relationships of the connection unit 403 in response to a request from the configuration change mechanism 50. This change allows the main processing unit 10, the shared memory 20, and the device 30 to be connected as desired. The monitoring unit 402 monitors the current utilization efficiency of the shared memory 20. For example, the monitoring unit 402 determines the current utilization efficiency of the shared memory 20 based on the size of the memory access bandwidth (access speed). The monitoring unit 402 measures and stores the amount of data transferred by the connection control mechanism.

[0018] 2 is a diagram illustrating an example of the configuration of connection unit 403 according to some embodiments of the present disclosure. As shown in FIG. 2, connection unit 403 includes connection devices 403a1, 403a2, and so on. Connection devices 403a1, 403a2, and so on may be collectively referred to as connection device 403a.

[0019] For example, as shown in FIG. 2, two main processing units 10, one shared memory 20, and one device 30 are connected to each of the connection devices 403a. Each of the connection devices 403a is also connected to at least one other connection device 403a. This configuration allows the main processing units 10, the shared memory 20, and the device 30 to be arbitrarily connected under changes made by the configuration change unit 401. This arbitrarily connected configuration is realized, for example, by a device such as a PCIe (Peripheral Component Interconnect express) switch. Connections made by such devices logically establish connection relationships, as opposed to actual hard-wired connections. For example, a mechanism connecting the main processing units 10, the shared memory, and the device 30 maintains the correspondence between the connection devices 403a and ports in the connection control mechanism 40, and logically changes the connection based on this correspondence.

[0020] When the main processing unit 10, the shared memory 20, and the device 30 are connected, a connection distance occurs between the main processing unit 10 and the shared memory 20, and between the device 30 and the shared memory 20. The connection distance here is not limited to the actual connection distance (meters) and may be expressed, for example, by latency (communication time / second). However, the connection distance here is assumed to depend on the actual connection and remains fixed unless a physical connection change occurs. FIG. 3 is a diagram showing an example of a connection distance according to some embodiments of the present disclosure. As shown in FIG. 3, the connection distance can take on various values ​​depending on the combination of the main processing unit 10, the shared memory 20, and the device 30. The utilization efficiency of the shared memory 20 varies depending on this connection distance. Generally, the shorter the connection distance from the main processing unit 10 to the shared memory 20 or the distance from the device 30 to the shared memory 20, the shorter the information propagation delay, and therefore the higher the utilization efficiency of the shared memory 20. When the main processing unit 10 uses a device 30 to execute a process, it connects to a device 30 appropriate for the process being executed. However, the device 30 is not necessarily located near the main processing unit 10 that executes the processing. In addition, the shared memory 20 through which the CPU 102a of the processing unit 102 of the main processing unit 10 and the device 30 mutually handle information also needs to be located in an appropriate location depending on the processing content.

[0021] The configuration change mechanism 50 instructs the connection control mechanism 40 to change the connection so as to select an appropriate shared memory depending on the process to be executed and the device to be used. As shown in FIG. 1, the configuration change mechanism 50 includes a connection control unit 501 and a configuration storage unit 502.

[0022] The connection control unit 501 selects the shared memory 20 and device 30 in response to the request from the execution control unit 101, based on the information stored in the configuration storage unit 502. The connection control unit 501 then connects the selected shared memory 20 to the main processing unit 10 that includes the execution control unit 101 that output the request, and outputs a connection request to the configuration change unit 401 of the connection control mechanism 40 to connect the selected shared memory 20 to the selected device 30.

[0023] The connection control unit 501 also acquires the current utilization efficiency of each shared memory 20 via the monitoring unit 402 of the connection control mechanism 40. The monitoring unit 402 can measure the utilization efficiency of the shared memory 20 separately as the utilization efficiency in the processing unit 102 of the main processing unit 10 and the utilization efficiency in the device 30, depending on the memory access bandwidth (access speed). FIG. 4 is a diagram illustrating an example of utilization efficiencies stored in the configuration storage unit 502 according to some embodiments of the present disclosure. For example, the utilization efficiency is calculated for each shared memory 20, as shown in FIG. 4. In the example shown in FIG. 4, the utilization efficiency of the main processing unit 10 using the shared memory 20a1 (referred to as "main processing unit-side utilization efficiency" in FIG. 4) is 20, and the utilization efficiency of the device 30 (referred to as "device-side utilization efficiency" in FIG. 4) is 30. Furthermore, the utilization efficiency of the main processing unit 10 using the shared memory 20a2 is 15, and the utilization efficiency of the device 30 is 25. Furthermore, the utilization efficiency of the main processing unit 10 that uses the shared memory 20a3 is 10, and the utilization efficiency of the device 30 is 20. Note that the memory efficiency of the shared memory 20 is also shown in FIG.

[0024] The configuration storage unit 502 associates the specific processing performed in the past by the main processing unit 10 with the combination of the processing unit 102, device 30, and shared memory 20 used in that processing, and the utilization efficiency at that time, and stores these as configuration information. Figure 5 is a diagram showing an example of configuration information according to some embodiments of the present disclosure. As shown in Figure 5, even if the specific processing is the same, the combination of the processing unit 102, device 30, and shared memory 20 may be different, and the utilization efficiency may also be different.

[0025] Furthermore, the configuration storage unit 502 stores information associating the expected memory efficiency for each process as memory efficiency information. This memory efficiency information may be specified (i.e., created) by a user of the processing system 1. FIG. 6 is a diagram illustrating an example of memory efficiency information according to some embodiments of the present disclosure. In the example shown in FIG. 6, the memory efficiency expected for process A1 (denoted as "expected memory efficiency" in FIG. 6) is 50, the memory efficiency expected for process A2 is 60, and the memory efficiency expected for process A3 is 40. Note that the expected memory efficiency may be defined by the user.

[0026] (Processing performed by the processing system) The above-described processing performed by the processing system 1 is merely an example, and the processing performed by the processing system 1 according to an embodiment of the present disclosure is not limited to the above-described processing. For example, the processing system 1 may perform the processing described below.

[0027] Next, a description will be given of the processing performed by the processing system 1. Fig. 7 is a diagram showing a first example of a processing flow of the processing system 1 according to some embodiments of the present disclosure. Fig. 8 is a diagram showing a second example of a processing flow of the processing system 1 according to some embodiments of the present disclosure.

[0028] (Behavior when process A is executed) First, the operation of the processing system 1 when executing process A1 shown in FIG. 7 will be described. Here, it is assumed that the main processing unit 10a1 executes process A1. When the main processing unit 10a1 executes process A1, the execution control unit 101 of the main processing unit 10a1 requests the connection control unit 501 of the configuration change unit 50 to add the device 30 required for the execution of process A1 (step S1). In response to the request to add the device 30 required for the execution of process A1 by the main processing unit 10a1, the connection control unit 501 of the configuration change unit 50 determines the required device 30 (step S2). It is assumed that the device 30 required for the execution of process A1 (i.e., the device 30 to be added) is device 30a2. Since the type of device 30 selected depends on the process to be executed and is expected to be used in other main processing units 10, it is not necessarily the case that the device 30 selected is located close to the main processing unit 10a1. (Generally, a nearby device is selected from among the available devices 30, but the selection method is not limited thereto.)

[0029] At this time, the connection control unit 501 of the configuration change mechanism 50 refers to the combination of the process, the processing unit 102, the device 30, and the shared memory 20 as shown in FIG. 5, stored in the configuration storage unit 502, according to the process A1 to be executed and the device 30a2 to be used, and information indicating the utilization efficiency of the shared memory 20 in that combination (step S3). The connection control unit 501 determines whether or not there is a combination that uses the device 30a2 to execute the process A1 among the combinations (step S4). The connection control unit 501 can know the process A1 by obtaining information (such as program information) related to the process to be executed presented by the execution control unit 101.

[0030] If the connection control unit 501 determines that the combinations include a combination that uses the device 30a2 to execute the process A1 (YES in step S4), it selects an allocatable shared memory 20 in descending order of utilization efficiency (step S5). If the connection control unit 501 determines that the combinations include no combination that uses the device 30a2 to execute the process A1 (NO in step S4), it selects an available shared memory 20 in descending order of distance from the main processing unit 10a1 (step S6). Here, it is assumed that the shared memory 20 selected by the connection control unit 501 is the shared memory 20a1. The connection control unit 501 obtains information about the distance from the main processing unit 10a1 from distance information stored in the configuration storage unit 502.

[0031] The connection control unit 501 of the configuration change mechanism 50 outputs a connection request to the configuration change unit 401 of the connection control mechanism 40 to connect the shared memory 20a1 selected by the connection control unit 501 to the main processing mechanism 10a1 (step S7). When the shared memory 20a1 is connected to the main processing mechanism 10a1, the execution control unit 101 of the main processing mechanism 10a1 instructs the processing unit 102 of the main processing mechanism 10a1 to use the connected device 30a2 and shared memory 20a1 when executing process A1 (step S8). In response to the instruction from the execution control unit 101, the processing unit 102 of the main processing mechanism 10a1 executes process A1 using the device 30a2 selected based on process A1 and the shared memory 20a1 selected in the processing of step S5 or step S6 (in cooperation with the selected device 30a2 and shared memory 20a1) (step S9).

[0032] (Behavior after execution of process A) Next, a description will be given of the operation of the processing system 1 after executing the process A1 shown in Fig. 8. Note that the operation described here is performed at regular intervals after the processing system 1 executes the process A1.

[0033] After executing process A1, the connection control unit 501 of the configuration change mechanism 50 refers to information on the memory efficiency expected for the process, such as that shown in Fig. 6, from the configuration storage unit 502. Then, the connection control unit 501 acquires the expected memory efficiency associated with process A1 from the configuration storage unit 502 (step S21).

[0034] Next, the connection control unit 501 acquires the memory efficiency of the actual process from the monitoring unit 402 of the connection control mechanism 40 (step S22). The connection control unit 501 determines whether the acquired memory efficiency of the actual process is equal to or greater than the memory efficiency value assumed for the executed process A (step S23).

[0035] If the connection control unit 501 determines that the memory efficiency of the actual process acquired for the executed process A1 is equal to or greater than the assumed memory efficiency value of 50, for example, as shown in FIG. 6 (YES in step S23), the process is terminated.

[0036] If the connection control unit 501 determines that the acquired memory efficiency of the actual processing is less than the memory efficiency value assumed for the executed processing A (NO in step S23), it updates (or adds if no record exists) information indicating the memory efficiency of the actual processing in the combination of processing A, the processing unit 102, the device 30, and the shared memory 20 shown in Figure 5, for example (step S24).

[0037] The connection control unit 501, via the monitoring unit 402 of the connection control mechanism 40, refers to Figure 6 for the shared memory 20a1 used in processing process A1, and determines whether the utilization efficiency value on the main processing unit 10a1 side is greater than the utilization efficiency value on the device 30a2 side (step S25).

[0038] If the connection control unit 501 determines that the utilization efficiency value on the main processing unit 10a1 side is greater than the utilization efficiency value on the device 30a2 side (YES in step S25), the connection control unit 501 checks the distance between the main processing unit 10a1 or each shared memory 20 determined to have the greater utilization efficiency value, based on the connection distances shown in FIG. 3 stored in the configuration storage unit 502. Then, the connection control unit 501 selects, from the checked shared memories 20, the shared memory 20 that is closest to and has a shorter connection distance than the current connection distance from the main processing unit 10a1 (step S26). For example, if the current connection distance of the shared memory 20 is 30 and there are candidate shared memories 20 with connection distances of 20, 25, and 35, the connection control unit 501 selects the shared memory 20 with a connection distance of 25, which is less than the current connection distance of 30 and closest to 30. This selection by the connection control unit 501 is based on the idea that it is better to use a nearby device, taking into account the migration cost incurred when using another device, which varies depending on the distance. In addition, when the distance between the main processing unit 10a1 and the device 30a2 changes significantly, one side may become more efficient while the other side may become less efficient. Note that the connection control unit 501 ends the process if there is no corresponding shared memory 20.

[0039] Furthermore, if the connection control unit 501 determines that the utilization efficiency value on the main processing unit 10a1 side is equal to or less than the utilization efficiency value on the device 30a2 side (NO in step S25), it checks the distance between the device 30a2 whose utilization efficiency value is determined to be greater than or equal to that of each shared memory 20, based on the connection distance as shown in Fig. 3. Then, the connection control unit 501 selects, from the checked shared memories 20, the shared memory 20 that is shorter than the current connection distance to the device 30a2 and is closest to the current connection distance (step S27).

[0040] The connection control unit 501 of the configuration change mechanism 50 instructs the configuration change unit 401 of the connection control mechanism 40 to connect the selected shared memory 20 to the main processing unit 10 (step S28). The connection control unit 501 also instructs the execution control unit 101 of the main processing unit 10 to change the shared memory 20 so that the shared memory 20 used in process A1 becomes the selected shared memory 20. The execution control unit 101 re-specifies the shared memory 20 to be used in process A1 to the processing unit 102 (step S29). The shared memory 20 used in process A1 is switched to the re-specified shared memory 20 (step S30). Thereafter, the connection control unit 501 of the configuration change mechanism 50 instructs the configuration change unit 401 of the connection control mechanism 40 to disconnect the shared memory 20 before re-specification (step S31). Then, the connection control unit 501 ends the process.

[0041] (advantage) The processing system 1 according to an embodiment of the present disclosure has been described above. In the processing system 1, the configuration change mechanism 50 includes a connection control unit 501 that, when executing processing that cannot be processed by a processing unit 102 having a CPU (Central Processing Unit) 102a and an internal memory 102b alone, identifies a device 30 and a shared memory 20 that cooperate with the processing unit 102 based on a first connection distance between the CPU 102a and the shared memory 20 and a second connection distance between the device 30 and the shared memory 20. This configuration change mechanism can suppress a decrease in the speed of information propagation between the CPU and the shared memory and between the device and the shared memory when adding a device and a shared memory that cooperate with the processing unit to execute processing that cannot be processed by a processing unit having a CPU (Central Processing Unit) and an internal memory alone.

[0042] In the processing system 1 according to one embodiment of the present disclosure, information indicating memory efficiency based on previous execution results (e.g., the information shown in FIG. 5 ) is used when performing process A. However, in the processing system 1 according to another embodiment of the present disclosure, information indicating memory efficiency (e.g., the information shown in FIG. 5 ) may not be used. In the processing system 1 according to another embodiment of the present disclosure, even if there is no information indicating memory efficiency, the shared memory 20 may be selected using any method as long as it achieves the expected memory efficiency. For example, the shared memory 20 may be selected to be located midway between the main processing unit 10 and the device. Alternatively, the shared memory 20 may be selected randomly.

[0043] In addition, in the processing system 1 according to another embodiment of the present disclosure, a method may be used in which the expected memory efficiency is determined and set based on previous execution results. In addition, in the processing system 1 according to another embodiment of the present disclosure, a method may be used in which the memory efficiency is estimated from information indicating the memory efficiency of a similar process A by machine learning or the like. In addition, in the processing system 1 according to another embodiment of the present disclosure, a method may be used in which the shared memory 20 is reset from the current value while repeating the process shown in FIG. 8. Specifically, information indicating the type may be added to the process A, and in the process of step S22, the memory efficiency may be calculated by taking an average based on information of the same type as the type of the process A.

[0044] In the processing system 1 according to one embodiment of the present disclosure, the shared memory 20 is selected based on the utilization efficiency information shown in Fig. 4. However, in the processing system 1 according to another embodiment of the present disclosure, the mechanism itself that selects another shared memory 20 to change the utilization efficiency of the shared memory 20 and reflects this in the main processing unit 10 is the main feature, and other methods may be used for the selection method. For example, in the processing system 1 according to another embodiment of the present disclosure, the shared memory 20 may be selected randomly in the processing of steps S25 to S27, and a process (step S32) for measuring memory efficiency may be added after the processing of step S31 is completed, and once the processing of step S32 is performed, the process may return to the processing of step S23.

[0045] 9 is a diagram illustrating an example of the configuration of a configuration change mechanism 50 according to another embodiment of the present disclosure. As shown in FIG.

[0046] When executing processing that cannot be processed by a single arithmetic processing unit having a CPU (Central Processing Unit) and internal memory, the connection control unit 301 identifies the device and shared memory that cooperate with the arithmetic processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory.

[0047] The connection control unit 301 can be realized, for example, by using the functions of the connection control unit 501 illustrated in FIG.

[0048] 10 is a diagram showing an example of a processing flow of the configuration change mechanism 50 according to another embodiment of the present disclosure. Next, processing of the configuration change mechanism 50 according to another embodiment of the present disclosure will be described with reference to FIG.

[0049] When executing processing that cannot be processed by a single arithmetic processing unit having a CPU (Central Processing Unit) and internal memory, the connection control unit 301 identifies the device and shared memory that cooperate with the arithmetic processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory (step S101).

[0050] The above has described a configuration change mechanism 50 according to another embodiment of the present disclosure. When a device and shared memory that cooperate with a processing unit including a CPU (Central Processing Unit) and internal memory are added to execute processing that cannot be processed by the processing unit alone, this configuration change mechanism 50 can suppress a decrease in the speed of information propagation between the CPU and the shared memory, and between the device and the shared memory.

[0051] The order of the processes in the embodiments of the present disclosure may be changed as long as the processes are performed appropriately.

[0052] Although the embodiments of the present disclosure have been described, the processing system 1, main processing unit 10, device 30, connection control unit 40, configuration change unit 50, and other control devices may have computer systems built therein. The above-described processing steps are stored in the form of a program on a computer-readable recording medium, and the computer reads and executes this program to perform the above processing. Specific examples of computers are shown below.

[0053] 11 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in FIG. 11, the computer 5 includes a CPU (Central Processing Unit) 6, a main memory 7, a storage 8, and an interface 9.

[0054] For example, the above-described processing system 1, main arithmetic unit 10, device 30, connection control unit 40, configuration change unit 50, and other control devices are each implemented in a computer 5. The operations of each of the above-described processing units are stored in the form of a program in storage 8. CPU 6 reads the program from storage 8, loads it into main memory 7, and executes the above-described processing in accordance with the program. Furthermore, CPU 6 allocates storage areas in main memory 7 corresponding to each of the above-described storage units in accordance with the program. Note that the CPU 6 of the present disclosure may be a controller.

[0055] Examples of storage 8 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read-only memory (CD-ROM), a digital versatile disc read-only memory (DVD-ROM), and a semiconductor memory. Storage 8 may be an internal medium directly connected to the bus of computer 5, or an external medium connected to computer 5 via interface 9 or a communication line. In addition, when this program is distributed to computer 5 via a communication line, computer 5 that receives the program may load the program into main memory 7 and execute the above-mentioned processing. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

[0056] The program may also implement some of the functions described above. Furthermore, the program may be a file that can implement the functions described above in combination with a program already recorded in the computer system, a so-called differential file (differential program).

[0057] Although several embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

[0058] Note that part or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0059] (Appendix 1) a connection control unit that, when executing a process that cannot be processed by a processing unit alone, includes a CPU (Central Processing Unit) and an internal memory, identifies a device and a shared memory that cooperate with the processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory; A configuration change mechanism comprising:

[0060] (Appendix 2) a configuration storage unit that stores information indicating the first connection distance and the second connection distance; Equipped with The connection control unit identifying the device and the shared memory based on the first connection distance and the second connection distance stored in the configuration storage unit; The configuration change mechanism described in Appendix 1.

[0061] (Appendix 3) The connection control unit When changing the current shared memory, a shared memory that is smaller than the current first connection distance and closest to the current first connection distance is selected from among the multiple shared memories. The configuration change mechanism described in Appendix 2.

[0062] (Appendix 4) The connection control unit When changing the current shared memory, a shared memory that is smaller than the current second connection distance and closest to the current second connection distance is selected from among the multiple shared memories. 2. The configuration change mechanism according to claim 2 or 3.

[0063] (Appendix 5) The connection control unit instructing a connection in a connection control mechanism that is provided between the main processing unit and the device and the shared memory, and that connects the main processing unit with the device and the shared memory, so that the identified device and the shared memory are connected to a desired main processing unit having the connection control unit; 5. The configuration change mechanism according to any one of appendices 1 to 4.

[0064] (Appendix 6) A configuration change mechanism according to any one of Supplementary Note 1 to Supplementary Note 5; a connection control mechanism provided between a main processing unit and the device and the shared memory so that the device and the shared memory are connected to a desired main processing unit having a connection control unit including a CPU (Central Processing Unit) and an internal memory, and which connects the main processing unit with the device and the shared memory in response to an instruction from the configuration change mechanism; A processing system comprising:

[0065] (Appendix 7) When executing a process that cannot be processed by a single arithmetic processing unit including a CPU (Central Processing Unit) and an internal memory, identifying a device and a shared memory that cooperate with the arithmetic processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory; A processing method comprising:

[0066] (Appendix 8) storing information indicating the first connection distance and the second connection distance; identifying the device and the shared memory based on the stored first connection distance and the stored second connection distance; Attachment 7, a processing method comprising:

[0067] (Appendix 9) When changing the current shared memory, selecting, from among a plurality of shared memories, a shared memory that is smaller than the current first connection distance and that is closest to the current first connection distance; Attachment 8, a processing method comprising:

[0068] (Appendix 10) When changing the current shared memory, selecting, from among a plurality of shared memories, a shared memory that is smaller than the current second connection distance and that is closest to the current second connection distance; 10. The method of claim 8 or 9,

[0069] (Appendix 11) instructing a connection in a connection control mechanism that is provided between the main processing unit and the device and the shared memory, and that connects the main processing unit with the device and the shared memory, so that the specified device and the shared memory are connected to a desired main processing unit; 11. The method of any one of claims 7 to 10,

[0070] (Appendix 12) When executing a process that cannot be processed by a single arithmetic processing unit including a CPU (Central Processing Unit) and an internal memory, identifying a device and a shared memory that cooperate with the arithmetic processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory; A program that causes a computer to execute the following.

[0071] (Appendix 13) storing information indicating the first connection distance and the second connection distance; identifying the device and the shared memory based on the stored first connection distance and the stored second connection distance; 13. The program according to claim 12, which causes the computer to execute the above steps.

[0072] (Appendix 14) When changing the current shared memory, selecting, from among a plurality of shared memories, a shared memory that is smaller than the current first connection distance and that is closest to the current first connection distance; 14. The program according to claim 13, which causes the computer to execute the above steps.

[0073] (Appendix 15) When changing the current shared memory, selecting, from among a plurality of shared memories, a shared memory that is smaller than the current second connection distance and that is closest to the current second connection distance; 15. The program according to claim 13 or 14, which causes the computer to execute the above.

[0074] (Appendix 16) instructing a connection in a connection control mechanism that is provided between the main processing unit and the device and the shared memory, and that connects the main processing unit with the device and the shared memory, so that the specified device and the shared memory are connected to a desired main processing unit; 16. The program according to any one of appendices 12 to 15, which causes the computer to execute the above. [Explanation of symbols]

[0075] 1. Processing System 5. Computer 6 CPU 7. Main memory 8. Storage 9. Interface 10, 10a1, 10a2...Main operation mechanism 20, 20a1, 20a2... Shared memory 30, 30a1, 30a2... devices 40 Connection control mechanism 50. Configuration change mechanism 101 Execution control unit 102 Processing unit 102a···CPU 102b Internal memory 401···Configuration Change Section 402...Monitoring Department 403···Connection 403a1, 403a2, 403a3... Connection device 501 Connection control unit 502...Configuration storage unit

Claims

1. a connection control unit that, when executing a process that cannot be processed by a processing unit alone that includes a CPU (Central Processing Unit) and an internal memory, identifies a device and a shared memory that cooperate with the processing unit based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory; A configuration change mechanism comprising:

2. a configuration storage unit that stores information indicating the first connection distance and the second connection distance; Equipped with The connection control unit identifying the device and the shared memory based on the first connection distance and the second connection distance stored in the configuration storage unit; The configuration change mechanism according to claim 1 .

3. The connection control unit When changing the current shared memory, a shared memory that is smaller than the current first connection distance and closest to the current first connection distance is selected from among a plurality of shared memories. The configuration change mechanism according to claim 2 .

4. The connection control unit When changing the current shared memory, a shared memory that is smaller than the current second connection distance and closest to the current second connection distance is selected from among a plurality of shared memories. The configuration change mechanism according to claim 2 .

5. The connection control unit instructing a connection in a connection control mechanism that is provided between the main processing unit and the device and the shared memory, and that connects the main processing unit with the device and the shared memory, so that the identified device and the shared memory are connected to a desired main processing unit having the connection control unit; The configuration change mechanism according to any one of claims 1 to 4.

6. The configuration change mechanism according to claim 1; a connection control mechanism provided between a main processing unit and the device and the shared memory so that the device and the shared memory are connected to a desired main processing unit having a connection control unit including a CPU (Central Processing Unit) and an internal memory, and which connects the main processing unit with the device and the shared memory in response to an instruction from the configuration change mechanism; A processing system comprising:

7. When executing a process that cannot be processed by a single arithmetic processing unit including a CPU (Central Processing Unit) and an internal memory, a device and a shared memory that cooperate with the arithmetic processing unit are identified based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory; A processing method comprising:

8. When executing a process that cannot be processed by a single arithmetic processing unit including a CPU (Central Processing Unit) and an internal memory, a device and a shared memory that cooperate with the arithmetic processing unit are identified based on a first connection distance between the CPU and the shared memory and a second connection distance between the device and the shared memory; A program that causes a computer to execute the following.

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