Inverter device and motor driving apparatus

Abstract

To provide an inverter device capable of suppressing a noise voltage which is generated by switching in two phases.SOLUTION: An inverter device comprises: an inverter body 300 including switching elements corresponding to phases of a three-phase voltage; and a gate drive circuit 400 which outputs a signal for controlling an open / closed state of each switching element. Further, the inverter device comprises a control unit 200 including: a carrier signal output section 210; comparators 221, 231 and 241 each for comparing a carrier signal with a modulation wave of each phase and outputting a comparison voltage for each phase; and a dead time correction section 250 by which, before and after a time point in which a voltage of the carrier signal matches voltages of modulation waves of any two phases in the modulation waves of the respective phases, and on the basis of the comparison voltages outputted from the comparators corresponding to the two phases in the comparators, a correction dead time is added to any one of ON times, which are set to the two phases, and outputted to the gate drive circuit 400.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an inverter device and a motor drive device including the inverter device. [Background technology]

[0002] Patent Document 1 discloses an inverter device and a motor drive device equipped with the inverter device. The inverter device discloses a switching method that prevents malfunction even when noise is present in the AC power supply. Specifically, the polarity of the voltage of the AC power supply is detected, and the dead time between the upper and lower arms of the inverter device is made variable according to the polarity of the detected voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 66033 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the inverter device described in Patent Document 1, when switching the voltages of the multiple phases performed in the inverter device, the dead time is made variable regardless of the switching status of each of the multiple phases.

[0005] Therefore, if voltage noise generated by the switching of one phase continues while the switching of another phase also occurs in time, the noise generated by the switching of both phases becomes synergistic, resulting in the problem of large noise voltages.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide an inverter device and a motor drive device that, when switching of multiple phase voltages in an inverter device is performed and it is predicted that switching will occur in at least two of the multiple phases in a time-overlapping manner, make the dead time of at least one of the two phases in which switching occurs variable, thereby suppressing synergistic noise voltages caused by switching in two phases in a time-overlapping manner. [Means for solving the problem]

[0007] The inverter device according to the present disclosure includes an inverter main body having switching elements provided corresponding to upper and lower arms of each phase of a three-phase voltage, a gate drive circuit that outputs gate signals to control the open / close states of each switching element provided in the inverter main body, and a control unit including a carrier signal output unit that outputs a carrier signal, a modulated wave output unit that outputs modulated waves for each phase of the three-phase voltage, comparators that compare the carrier signal with the modulated waves for each phase and output a comparison voltage for each phase, and a dead time correction unit that adds a correction dead time to one of the ON times set for two phases based on the comparison voltages output from the comparators corresponding to the two phases around the time when the voltage of the carrier signal matches the voltage of the modulated waves for any two of the phases, and outputs the result to the gate drive circuit. [Effects of the Invention]

[0008] The inverter device and the motor drive device including this inverter device according to the present disclosure have the advantage that when switching the three-phase voltage performed in the inverter device, at least any two of the three phases of the three-phase voltage are not switched in a time-overlapping manner, thereby suppressing synergistic noise caused by the overlapping of noises generated by the switching of each phase. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a functional configuration of an inverter device according to a first embodiment. [Figure 2] FIG. 3 is an explanatory diagram for explaining the operation of the inverter device according to the first embodiment. [Figure 3] FIG. 2 is a block diagram showing the functional configuration of an inverter main body. [Figure 4] 10 is an explanatory diagram for explaining the relationship between the open / closed states of the upper arm and the lower arm in each phase of the inverter main body and the space vector. FIG. [Figure 5] 10 is an explanatory diagram for explaining the relationship between the open / closed states of the upper arm and the lower arm in each phase of the inverter main body and the space vector. FIG. [Figure 6] FIG. 2 is an explanatory diagram for explaining the relationship between the operation of the inverter device and space vectors. [Figure 7] FIG. 2 is an explanatory diagram for explaining setting of an ON time of each phase and correction of the ON time. [Figure 8] FIG. 10 is a block diagram showing a functional configuration of an inverter device according to a second embodiment. [Figure 9] FIG. 10 is an explanatory diagram for explaining the duration of noise generated by switching in an inverter. [Figure 10] 1 is an explanatory diagram for explaining an equivalent circuit of a printed circuit board and generated noise; [Figure 11] FIG. 2 is a schematic diagram illustrating an example of an inverter noise detection unit. [Figure 12] FIG. 2 is a block diagram showing the functional configuration of the motor drive device. [Figure 13] FIG. 2 is an explanatory diagram illustrating an example of a hardware configuration of a control unit included in the inverter device. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the accompanying drawings. In each drawing, the same or corresponding parts are designated by the same reference numerals. Duplicate descriptions of such parts will be appropriately simplified or omitted. In addition, the size relationships between the components in each drawing may differ from the actual size relationships. Furthermore, the present invention is not limited to the embodiments for carrying out the present disclosure.

[0011] Embodiment 1 1 is a block diagram showing a functional configuration of an inverter device according to embodiment 1. In the following description of embodiment 1, an inverter device 100 will be described as an example of an inverter device. A specific example of the inverter device 100 can be a PWM inverter device. PWM stands for pulse width modulation.

[0012] The inverter device 100 includes, for example, an inverter main body 300 that drives a motor 500, a control unit 200 for driving the inverter main body 300, and a gate drive circuit 400 that outputs a drive signal to be given to the inverter main body 300.

[0013] In the following, a case will be described in which the motor 500 is a so-called three-phase drive motor driven by a three-phase AC voltage of U phase, V phase, and W phase, and the inverter device 100 is an inverter device for driving the three-phase drive motor 500.

[0014] The control unit 200 includes a carrier signal output unit 210 that outputs a triangular wave as a carrier signal, a U-phase modulated wave output unit 220 that outputs a U-phase voltage of the three-phase voltage, a V-phase modulated wave output unit 230 that outputs a V-phase voltage of the three-phase voltage, and a W-phase modulated wave output unit 240 that outputs a W-phase voltage of the three-phase voltage. Specifically, the control unit 200 can be exemplified as a PWM control unit that outputs a control signal based on PWM.

[0015] Furthermore, control unit 200 includes comparators 221, 231, and 241. Comparator 221 compares a triangular wave serving as a carrier signal output from carrier signal output unit 210 with a U-phase modulated wave output from U-phase modulated wave output unit 220, and outputs a comparison voltage (hereinafter, sometimes referred to as a U-phase pulse train) whose pulse width changes according to the amplitude of the U-phase modulated wave.

[0016] Comparator 231 compares the triangular wave as the carrier signal output from carrier signal output unit 210 with the V-phase modulated wave output from V-phase modulated wave output unit 230, and outputs a comparison voltage (hereinafter sometimes referred to as a V-phase pulse train) whose pulse width changes according to the amplitude of the V-phase modulated wave. Furthermore, comparator 241 compares the triangular wave as the carrier signal output from carrier signal output unit 210 with the W-phase modulated wave output from W-phase modulated wave output unit 240, and outputs a comparison voltage (hereinafter sometimes referred to as a W-phase pulse train) whose pulse width changes according to the amplitude of the W-phase modulated wave.

[0017] The U-phase pulse train output from comparator 221, the V-phase pulse train output from comparator 231, and the W-phase pulse train output from comparator 241 are each input to dead time correction section 250.

[0018] The dead time correction unit 250 and the inverter main body 300 will now be described. In the dead time correction unit 250, first, the ON time (hereinafter referred to as ON time) of the switch elements of the upper and lower arms corresponding to each of the U, V, and W phases is set. Here, the switch elements of the upper and lower arms for each of the U, V, and W phases and their operation will be described with reference to FIG.

[0019] Fig. 3 is a block diagram showing the functional configuration of inverter main body 300. As shown in Fig. 3, inverter main body 300 includes switch element 301 corresponding to the upper arm of the U phase and switch element 311 corresponding to the lower arm of the U phase. In addition, inverter main body 300 includes switch element 302 corresponding to the upper arm of the V phase and switch element 312 corresponding to the lower arm of the V phase. In addition, inverter main body 300 includes switch element 303 corresponding to the upper arm of the W phase and switch element 313 corresponding to the lower arm of the W phase.

[0020] Specifically, power semiconductor elements are used for the switch elements (i.e., switch elements 301, 311, 302, 312, 303, and 313) of the upper and lower arms of each of the U, V, and W phases shown in Fig. 3. More specifically, MOSFETs (metal-oxide-semiconductor field-effect transistors, an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (insulated gate bipolar transistors, an abbreviation for Insulated Gate Bipolar Transistors) can be exemplified.

[0021] In the following description, an example will be described in which MOSFETs are used for the switch elements 301, 311, 302, 312, 303, and 313. The opening and closing operation of each of the switch elements 301, 311, 302, 312, 303, and 313 is also referred to as switching.

[0022] In each of the switch elements 301, 311, 302, 312, 303, and 313 shown in FIG. 3, the symbol G indicates the gate of the MOSFET (hereinafter referred to as gate G), the symbol D indicates the drain of the MOSFET (hereinafter referred to as drain D), and the symbol S indicates the source of the MOSFET (hereinafter referred to as source S).

[0023] 3 outputs a gate signal GS to the gate G of each of the switch elements 301, 311, 302, 312, 303, and 313. The gate signal GS is a binary signal that specifies either ON (i.e., the switch element is closed) or OFF (i.e., the switch element is open) for the gate G.

[0024] That is, when a gate signal GS that turns ON each of the switch elements 301, 311, 302, 312, 303, and 313 is applied, each of the switch elements 301, 311, 302, 312, 303, and 313 turns ON (the switch element is closed). Also, when a gate signal GS that turns OFF each of the switch elements 301, 311, 302, 312, 303, and 313 is applied, each of the switch elements 301, 311, 302, 312, 303, and 313 turns OFF (the switch element is open).

[0025] In this way, the ON or OFF state of each of the switch elements 301, 311, 302, 312, 303, and 313 is controlled by the gate signal GS input to the gate G of each switch element.

[0026] The drains D of the switch elements 301, 302, and 303 constituting the upper arms of the U, V, and W phases are connected to the anodes of the DC power supplies. The sources S of the switch elements 311, 312, and 313 constituting the lower arms of the U, V, and W phases are connected to the cathodes of the DC power supplies.

[0027] The sources S of the switch elements 301, 302 and 303 constituting the upper arms of the U, V and W phases are connected to the drains D of the switch elements 311, 312 and 313 constituting the lower arms of the U, V and W phases, respectively.

[0028] The sources S of the switch elements 301, 302 and 303 constituting the upper arms of the U, V and W phases (i.e., the voltage is the same as that of the drains D of the switch elements 311, 312 and 313 constituting the lower arms of the U, V and W phases, respectively) are connected to the U-phase coil, V-phase coil and W-phase coil of the motor 500, which is driven by a three-phase voltage.

[0029] Therefore, voltages VU, VV, and VW are applied to the U-phase coil, V-phase coil, and W-phase coil of motor 500 from sources S of switch elements 301, 302, and 303 constituting the upper arms of the U-phase, V-phase, and W-phase, respectively (i.e., the same voltage as drains D of switch elements 311, 312, and 313 constituting the lower arms of the U-phase, V-phase, and W-phase, respectively). That is, power for driving motor 500 is supplied to motor 500 based on the ON or OFF state of each switch element.

[0030] When the motor 500 is a three-phase drive motor, the inverter main body 300 uses upper and lower arm switch elements corresponding to the U, V, and W phases. Therefore, the inverter main body 300 that drives the three-phase drive motor 500 uses two switch elements corresponding to each of the three phases, and is provided with a total of six switch elements.

[0031] A voltage for driving the motor 500 is supplied to the inverter main body 300 from a DC power supply 310. That is, the inverter main body 300 chops the DC voltage supplied from the DC power supply 310 by opening and closing six switch elements, converts it into a three-phase AC voltage, and outputs this three-phase AC voltage (hereinafter, sometimes referred to as a motor voltage) to the motor 500.

[0032] Here, when setting the ON time for each of the upper and lower arms of each phase, a comparison output is used, which is the output from a comparator that inputs the voltage of the carrier signal (shown as a triangular wave in Figure 2) and the voltage of the modulated wave of each phase (shown as modulated wave U for the U phase and modulated wave V for the V phase in Figure 2).

[0033] That is, the dead time correction unit 250 outputs the ON time corrected by the dead time of each phase (the dead time of each phase includes single-phase dead time, inter-phase dead time, and correction dead time having at least the time length obtained by adding the time length of the inter-phase dead time to the time length of the single-phase dead time, as will be described later) which is set based on the U-phase pulse train, V-phase pulse train, and W-phase pulse train.

[0034] Therefore, the dead time correction unit 250 inputs to the gate drive circuit 400 either an output corresponding to the ON time set based on the U-phase pulse train, V-phase pulse train, and W-phase pulse train, or an output corresponding to the ON time after correcting the ON time set based on the U-phase pulse train, V-phase pulse train, and W-phase pulse train.

[0035] The gate drive circuit 400 outputs a gate signal GS that controls the opening and closing of each of the multiple switch elements provided in the inverter main body 300 corresponding to each of the U, V, and W phases, and the inverter main body 300 operates as described with reference to Fig. 3. When the inverter main body 300 operates, a motor voltage is output to the motor 500.

[0036] Next, the operation of the inverter device 100 according to the first embodiment will be specifically described. First, the operation of the dead time correction unit 250 of the control unit 200 provided in the inverter device 100 to set the ON times of the switch elements of the upper and lower arms corresponding to each of the U, V, and W phases will be described in detail with reference to FIG. 2.

[0037] The timing for setting the ON time is as follows: Control unit 200 starts calculating the ON time for each of the U, V, and W phases, starting from timing ta, the peak of the carrier signal (i.e., a triangular wave in this case) output from carrier signal output unit 210. This calculation is performed by a calculation unit (not shown) included in control unit 200. The period covered by the calculation starting from timing ta is the period from timing ta onwards until timing tb, the next peak of the triangular wave.

[0038] Similarly, the control unit 200 calculates the ON time for each of the U, V, and W phases, starting from the timing tb of the peak of the carrier signal (ie, triangular wave) output from the carrier signal output unit 210.

[0039] This calculation is performed in a calculation unit (not shown) included in the control unit 200, similar to the calculation starting from the timing ta of the peak of the carrier signal. The period covered by the calculation starting from timing tb is the period from timing tb to the timing of the next peak of the triangular wave. Similar calculations are performed sequentially for the timing of the next peak of the triangular wave and thereafter. The ON time set starting from timing ta will be described below.

[0040] Fig. 2 is an explanatory diagram for explaining the operation of the inverter device according to embodiment 1. A in Fig. 2 shows temporal changes in the voltage of the carrier signal (a triangular wave is shown in Fig. 2) and the voltage of the modulated wave of each phase (a modulated wave U of the U phase and a modulated wave V of the V phase are shown in Fig. 2).

[0041] B1 in Figure 2 shows the ON times set for the U-phase upper arm and the U-phase lower arm. B2 in Figure 2 shows the ON times after the ON times set for the U-phase upper arm and the U-phase lower arm have been corrected. C in Figure 2 shows the ON times set for the V-phase upper arm and the V-phase lower arm. Note that while the ON time settings for the U-phase and V-phase are shown here, the same applies to the ON time settings for the U-phase and W-phase and the ON time settings for the V-phase and W-phase.

[0042] First, with reference to A in FIG. 2, the relationship between the voltage of the carrier signal (shown as a triangular wave in FIG. 2) and the voltage of the modulated wave of each phase (shown as a modulated wave U of the U phase and a modulated wave V of the V phase in FIG. 2) will be described. The carrier signal shown in A in FIG. 2 is output from carrier signal output unit 210. The modulated wave U shown in A in FIG. 2 is output from U-phase modulated wave output unit 220. The carrier signal and modulated wave U are input to comparator 221, and a comparison is made between the two voltages. Similarly, the modulated wave V shown in A in FIG. 2 is output from V-phase modulated wave output unit 230. The carrier signal and modulated wave V are input to comparator 231, and a comparison is made between the two voltages.

[0043] Modulated wave W, which is not shown in A of Fig. 2, is output from W-phase modulated wave output unit 240. The carrier signal and modulated wave W are input to comparator 241, and the two voltages are compared. Hereinafter, the setting of the ON time for each of the U and V phases will be described with reference to A of Fig. 2. Note that the setting of the ON time for each of the U and W phases and the ON time for each of the V and W phases is similar to the setting of the ON time for each of the U and V phases, and therefore a detailed description thereof will be omitted.

[0044] It is assumed that the voltage of the W-phase modulated wave W during the target period described with reference to A in Figure 2 is very low compared to the voltages of the U-phase or V-phase, and is close to the voltage of the cathode of the DC power supply 310, and that the switch element 313 of the lower arm is ON during the target period.

[0045] If the comparison result in comparator 221 shows that the voltage of the U-phase modulated wave is equal to or greater than the voltage of the triangular wave carrier signal, then switch element 301 of the U-phase upper arm is set to ON, and switch element 311 of the U-phase lower arm is set to OFF. Also, if the comparison result in comparator 221 shows that the voltage of the U-phase modulated wave is less than the voltage of the triangular wave carrier signal, then switch element 301 of the U-phase upper arm is set to OFF, and switch element 311 of the U-phase lower arm is set to ON. In this way, the U-phase pulse train output from comparator 221 is a binary pulse signal.

[0046] In terms of the correspondence between H (high) and L (low) of the U-phase pulse train, which is a binary pulse signal, when the voltage of the U-phase modulated wave is equal to or higher than the voltage of the triangular wave that is the carrier signal, H of the U-phase pulse train corresponds to ON of switch element 301 of the upper arm of the U-phase, and L of the U-phase pulse train corresponds to ON of switch element 311 of the lower arm of the U-phase.

[0047] However, when setting the ON time of switching element 301 of the U-phase upper arm and the ON time of switching element 311 of the U-phase lower arm, it is necessary to take into account the rise time from OFF to ON or the fall time from ON to OFF, respectively, and the single-phase dead time as described above. Note that in FIG. 2, the time length TdU0 corresponds to twice the time length of the single-phase dead time between the U-phase upper arm and lower arm. Also, in FIG. 2, the time length TdV corresponds to twice the time length of the single-phase dead time between the V-phase upper arm and lower arm. TdV is also referred to as the V-phase dead time.

[0048] In the first embodiment, the time length TdU0 is the same as the time length TdV. Also, in FIG. 2, the time length of the dead time between the phases is indicated by TdU1 for the dead time between the lower arms of the U phase and the V phase, and by TdU2 for the dead time between the upper arms of the U phase and the V phase. In the first embodiment, the time length TdU2 is the same as the time length TdU1. Furthermore, in FIG. 2, the time length TdU is indicated as the sum of the time lengths TdU0, TdU1, and TdU2. TdU is also referred to as the dead time of the U phase.

[0049] Therefore, as shown in B1 of Fig. 2, a single-phase dead time is set for setting the ON time of switching element 301 of the upper arm of U-phase and the ON time of switching element 311 of the lower arm of U-phase. Specifically, as shown in B1 of Fig. 2, the ON time of switching element 301 of the upper arm of U-phase is set so that, with the point in time at which the voltages of the carrier signal and modulated wave U match as the boundary, the ON time ends earlier than the point in time at which the voltages of the carrier signal and modulated wave U match by the length of the single-phase dead time.

[0050] Furthermore, as shown in B1 of FIG. 2, the ON time of the switch element 311 of the lower arm of the U phase is set so that the ON time starts later than the point at which the voltages of the carrier signal and the modulating wave U match by the length of the single-phase dead time, with the point at which the voltages of the carrier signal and the modulating wave U match as the boundary.

[0051] Such a setting operation is referred to as “ON time setting.” Here, the setting of the ON time in the U-phase upper arm and the setting of the ON time in the U-phase lower arm are described, but when referring collectively to the settings of the ON times of switch element 301 in the U-phase upper arm and switch element 311 in the U-phase lower arm, they are also referred to as “U-phase ON time setting.”

[0052] Similarly, for the V-phase, when the comparison result in comparator 231 shows that the voltage of the V-phase modulated wave is equal to or greater than the voltage of the triangular wave that is the carrier signal, switch element 302 of the upper arm of the V-phase is set to ON, and switch element 312 of the lower arm of the V-phase is set to OFF. Furthermore, when the comparison result in comparator 231 shows that the voltage of the V-phase modulated wave is less than the voltage of the triangular wave that is the carrier signal, switch element 302 of the upper arm of the V-phase is set to OFF, and switch element 312 of the lower arm of the V-phase is set to ON. In this way, the V-phase pulse train that is output from comparator 231 is a binary pulse signal.

[0053] In terms of the correspondence between H (high) and L (low) of the V-phase pulse train, which is a binary pulse signal, when the voltage of the V-phase modulated wave is equal to or greater than the voltage of the triangular wave that is the carrier signal, H of the V-phase pulse train corresponds to ON of the switch element 302 of the upper arm of the V-phase, and L of the V-phase pulse train corresponds to ON of the switch element 312 of the lower arm of the V-phase.

[0054] However, when setting the ON time of switching element 301 of the V-phase upper arm and the ON time of switching element 311 of the V-phase lower arm, it is necessary to take into account the rise time from OFF to ON or the fall time from ON to OFF, respectively, and to consider the single-phase dead time as described above.

[0055] Therefore, as shown in C of Fig. 2, a single-phase dead time is set for setting the ON time of V-phase upper arm switching element 302 and the ON time of V-phase lower arm switching element 312. Specifically, as shown in C of Fig. 2, the ON time of V-phase upper arm switching element 302 is set so that, with the point in time at which the voltages of the carrier signal and modulated wave V match as the boundary, the ON time ends earlier than the point in time at which the voltages of the carrier signal and modulated wave V match by the length of the single-phase dead time.

[0056] Furthermore, as shown in FIG. 2C, the ON time of the V-phase lower arm switch element 312 is set so that the ON time starts later than the point at which the voltages of the carrier signal and modulating wave V match by the length of the single-phase dead time.

[0057] Here, the setting of the ON time in the V-phase upper arm and the setting of the ON time in the V-phase lower arm are described, but when referring collectively to the settings of the ON times of switch element 302 in the V-phase upper arm and switch element 312 in the V-phase lower arm, they are also referred to as the V-phase ON time setting.

[0058] Although not described here, the ON time of the upper arm of the W phase and the ON time of the lower arm of the W phase are set in the same way for the W phase, taking into account the length of the dead time of the single phase. The W-phase pulse train output from comparator 241 is a binary pulse signal.

[0059] In terms of the correspondence between H (high) and L (low) of the W-phase pulse train, which is a binary pulse signal, when the voltage of the W-phase modulating wave is equal to or higher than the voltage of the triangular wave that is the carrier signal, H of the W-phase pulse train corresponds to ON of switch element 303 of the upper arm of the W-phase, and L of the W-phase pulse train corresponds to ON of switch element 313 of the lower arm of the W-phase.

[0060] The ON time settings of the W-phase upper arm switch element 303 and the W-phase lower arm switch element 313 are also referred to as W-phase ON time settings when referring collectively. Note that the ON time settings of the upper arm and lower arm switch elements in the U, V, and W phases are also referred to as phase ON time settings when referring collectively.

[0061] The single-phase dead time is set so that, for example, the switching element 301 of the upper arm of the U phase and the switching element 311 of the lower arm do not overlap in time and are turned on. This point will be described in detail below.

[0062] When the state of the switch element 301 and the switch element 311 changes from ON to OFF or from OFF to ON, the voltage changes suddenly. Therefore, in reality, there is a finite time (also referred to as a transition period) for the voltage to transition. As shown in FIG. 3, the switch element 301 and the switch element 311 are connected in series. Therefore, during the transition period, both the switch element 301 and the switch element 311 are ON or close to ON. Therefore, to prevent the voltage of the DC power supply 310 from being short-circuited due to both the switch element 301 and the switch element 311 being ON or close to ON, when setting the ON time, both the switch element 301 and the switch element 311 are treated as being ON.

[0063] That is, at least during such a transition period, both switch element 301 and switch element 311 are forcibly turned off so that no voltage is applied to either. In this way, switching can be controlled so that both switch element 301 and switch element 311 are turned off for a period longer than at least the transition time. The time during which switch element 301 and switch element 311 are forcibly set to OFF corresponding to such a transition period is called single-phase dead time. The single-phase dead time can be set in the same way for each of the V phase and W phase.

[0064] The length of the single-phase dead time is set to at least a length corresponding to the length of time from time t1 to time t3, which will be described later with reference to D in Fig. 9. However, the single-phase dead time in the first embodiment will be described as having a predetermined length.

[0065] Furthermore, the length of the dead time between phases in the following description is set to at least a length corresponding to the length of time from time t3 to time t5, which will be described later with reference to D in Fig. 9. However, the dead time between phases in the first embodiment will be described as having a predetermined length.

[0066] As described above, a method for correcting the ON time of the U phase set at timing ta using the dead time between phases will be described with reference to FIG. At timing ta, the U-phase pulse train after timing ta is input to dead time correction unit 250. In addition, the difference between the voltage of the carrier signal (i.e., the triangular wave) and the voltage of modulated wave U is detected by a detection unit (not shown) of control unit 200. Similarly, the difference between the voltage of the carrier signal and the voltage of modulated wave V is also detected by a detection unit (not shown) of control unit 200.

[0067] If the difference value (voltage difference) between the voltage of the carrier signal and the voltage of the modulated wave U detected by the control unit 200 and the difference value (voltage difference) between the voltage of the carrier signal and the voltage of the modulated wave V detected by the control unit 200 become smaller than a predetermined voltage range (for example, 1 / 10 of the voltage amplitude of the modulated wave U and the modulated wave V), it is determined that the voltage of the carrier signal, the voltage of the modulated wave U, and the voltage of the modulated wave V are expected to match after the voltage difference between the modulated wave U and the modulated wave V becomes smaller than the predetermined voltage range.

[0068] Therefore, based on the voltage value of the carrier signal and the voltage difference value at the time when the voltage difference between each phase becomes smaller than a predetermined voltage range, the time at which the crossover timing occurs, at which the voltage of the carrier signal matches the voltage of the modulated wave U, is calculated. In A of Figure 2, the calculated crossover timing is represented as time tx.

[0069] The ON time set for the U phase includes the dead time of each phase. The ON time set for the V phase also includes the dead time of each phase.

[0070] The ON and OFF states of the U phase before and after the crossover time tx are as follows: Before the crossover time tx, the upper arm of the U phase is OFF, and the lower arm of the U phase is ON. Therefore, after the single-phase dead time has elapsed from the crossover time tx, the upper arm of the U phase changes from OFF to ON. Also, the lower arm of the U phase changes from ON to OFF earlier than the crossover time tx by the length of the single-phase dead time.

[0071] The ON and OFF states of the V-phase before and after the crossover time tx are as follows: Before the crossover time tx, the upper arm of the V-phase is OFF, and the lower arm of the V-phase is ON. Therefore, after the single-phase dead time has elapsed from the crossover time tx, the upper arm of the V-phase changes from OFF to ON. Furthermore, the lower arm of the V-phase changes from ON to OFF earlier than the crossover time tx by the length of the single-phase dead time.

[0072] That is, in both the U phase and the V phase, the upper arms change from OFF to ON and the lower arms change from ON to OFF at similar timings. However, as will be described later, when the switching of each switch element of the inverter main body 300 in each phase changes from OFF to ON and from ON to OFF, switching noise occurs.

[0073] Therefore, before the crossover timing tx, switching noise is generated from the switch elements 311 and 312 of the lower arms of the U and V phases. Furthermore, even after the crossover timing tx, switching noise is generated from the switch elements 301 and 302 of the upper arms of the U and V phases.

[0074] Switching noise generated at similar timing from two phases in this way is synergistically larger than single-phase switching noise generated from only the U phase or only the V phase. This type of noise will also occur between the U and W phases and between the V and W phases if the switching timing is similar to that described above in accordance with the triangular wave voltage and modulating wave voltage.

[0075] Therefore, in the first embodiment, the ON times set for the upper arm and the lower arm of the U phase are corrected before and after the crossover timing tx using the dead time between the phases, thereby preventing the switching noises of the U phase and the V phase from occurring at similar times.

[0076] Specifically, the correction is made as follows, with reference to B2 in FIG. Since the upper arm of the U phase is ON at a point after the crossover timing tx, the switch element 301 of the upper arm of the U phase is corrected to change from OFF to ON after the time from the crossover timing tx that is the sum of the time length of the single-phase dead time and the time length of the dead time between the phases has elapsed.

[0077] Similarly, because the U-phase lower arm is ON prior to crossover time tx, the switch element 311 of the U-phase lower arm is corrected to change from ON to OFF earlier than crossover time tx by the sum of the single-phase dead time and the inter-phase dead time. In this way, in relation to the correction of the ON time of the U-phase upper arm and the correction of the ON time of the U-phase lower arm, the dead time having a length equal to the sum of the single-phase dead time and the inter-phase dead time before and after crossover time tx is the correction dead time. In other words, the set ON time can be corrected by adding the correction dead time to it.

[0078] By correcting the ON time in this manner, switching element 301 of the U-phase upper arm changes from OFF to ON after the length of time TdU2 of the dead time between the phases has elapsed from the timing at which switching element 302 of the V-phase upper arm changes from OFF to ON. Therefore, noise generated by switching element 301 of the U-phase upper arm does not overlap in time with noise generated by switching element 302 of the V-phase upper arm.

[0079] Similarly, by correcting the ON time in this manner, switching element 311 of the U-phase lower arm changes from ON to OFF before the timing at which switching element 312 of the V-phase upper arm changes from ON to OFF, which is the duration of the dead time between the phases, TdU1. Therefore, noise generated by switching element 311 of the U-phase lower arm does not overlap in time with noise generated by switching element 312 of the V-phase lower arm.

[0080] In this way, when an intersection timing tx occurs, by taking into account the dead time between the phases before and after the intersection timing tx and correcting the ON time of at least one phase (here, the U phase is used as an example), it is possible to prevent the switching noises of the U phase and V phase from occurring at a time when they overlap in time.

[0081] In the above explanation, the ON time is corrected so that it is earlier than the crossover time tx by the sum of the single-phase dead time and the inter-phase dead time, or so that it is later than the crossover time tx by the sum of the single-phase dead time and the inter-phase dead time. However, the sum of the single-phase dead time and the inter-phase dead time (sometimes referred to as the correction dead time) is the minimum dead time length and is merely an example. Therefore, to increase design tolerance, it is also possible to correct the ON time by a correction dead time that is longer than the correction dead time described here.

[0082] In the above explanation, the ON time correction due to the dead time between the U and V phases is performed only on the U phase. Next, we will explain which of the U and V phases the ON time is corrected for by the correction dead time.

[0083] First, a description will be given of the ON or OFF state and space vectors of the upper and lower arms in each of the U, V, and W phases of the inverter main body 300. Figures 4 and 5 are explanatory diagrams for describing the relationship between the ON or OFF state and space vectors of the upper and lower arms in each of the U, V, and W phases of the inverter main body 300.

[0084] In FIGS. 4 and 5, among the switch elements 301, 311, 302, 312, 303, and 313 provided in the inverter main body 300, the switch elements enclosed by circles indicate that they are switched ON.

[0085] Space vector (111) shown in Fig. 4 indicates that upper arm switch elements 301, 302, and 303 in the U, V, and W phases are all switched ON. Space vector (100) shown in Fig. 4 indicates that upper arm switch element 301 in the U phase is switched ON, and upper arm switch element 302 in the V phase and upper arm switch element 303 in the W phase are switched OFF.

[0086] 4 indicates that switch element 301 of the upper arm in the U phase is switched OFF, and switch element 302 of the upper arm in the V phase and switch element 303 of the upper arm in the W phase are switched ON. Furthermore, space vector (001) shown in FIG. 4 indicates that switch element 301 of the upper arm in the U phase and switch element 302 of the upper arm in the V phase are switched OFF, and switch element 303 of the upper arm in the W phase is switched ON.

[0087] Space vector (110) shown in Fig. 5 indicates that upper arm switch element 301 in the U phase and upper arm switch element 302 in the V phase are switched ON, and upper arm switch element 303 in the W phase is switched OFF. Also, space vector (010) shown in Fig. 5 indicates that upper arm switch element 301 in the U phase and upper arm switch element 303 in the W phase are switched OFF, and upper arm switch element 302 in the V phase is switched ON.

[0088] 5 indicates that upper arm switch element 301 in the U phase and upper arm switch element 303 in the W phase are switched ON, and that upper arm switch element 302 in the V phase is switched OFF. Furthermore, space vector (000) shown in FIG. 5 indicates that upper arm switch elements 301, 302, and 303 in the U, V, and W phases are all switched OFF.

[0089] 4 and 5, the switching states of each of the switch elements 301, 311, 302, 312, 303, and 313 provided in the inverter main body 300 can be expressed by a space vector (111), a space vector (100), a space vector (011), a space vector (001), a space vector (110), a space vector (010), a space vector (101), and a space vector (000), respectively. That is, the space vectors represent ON and OFF in the switching of each switch element provided in the inverter main body 300 by associating them with 1 and 0, respectively. Note that the ON and OFF of the upper arm switching element and the lower arm switching element in each phase are in a mutually opposing relationship.

[0090] In actual electrical control, since time is required for the voltage to rise or fall during switching, the time that elapses from the time a control input related to turning the switch element on or off for the voltage to rise or fall during switching is regarded as dead time (particularly when describing the dead time in one phase, this is referred to as single-phase dead time), and the switch is controlled to be OFF during the time that elapses for the voltage to rise or fall.

[0091] FIG. 6 is an explanatory diagram for explaining the relationship between the operation of the inverter device and space vectors. FIG. 6 schematically shows the relationship between the switching of the upper and lower arms of the U phase and the space vectors indicating the open / closed states of the upper and lower arms of each phase of the inverter. Before and after the crossing timing, the switching of the lower arms of the U phase and the V phase overlaps on the time axis. In this case, if either the U phase or the V phase changes the direction of current, the ON time of the phase that changes the direction of current is corrected.

[0092] This will be explained in detail with reference to the change in the space vector. First, the space vector before correction will be explained. Before the crossing timing tx, the space vector is (000), and after the crossing timing tx, the space vector is (110) (here, it is assumed that the space vector of the W phase remains 0 before and after the crossing timing).

[0093] The transition of the direction of current in the U phase and V phase when the space vector is changed will be described below. In the following description, for convenience, the direction of current from switch element 301 or switch element 302 to motor 500 will be expressed as "rightward" (shown by a rightward arrow in FIG. 5), and the direction of current from motor 500 to switch element 301 or switch element 302 will be expressed as "leftward" (shown by a leftward arrow in FIG. 5).

[0094] Before the correction with the corrected dead time, the space vector after the crossing timing tx is (110). Therefore, since the space vector of the W phase remains 0 before and after the crossing timing tx, there are two options: (a) When changing the space vector of the U phase, the space vector (110) is changed to the space vector (010). (b) When changing the space vector of the V phase, the space vector (110) is changed to the space vector (100).

[0095] When changing the space vector of the U phase (a) above, the space vector changes in the order (000), (110), and (010), so the transition of the direction of the U phase current is "leftward," "rightward," and "leftward." Therefore, every time the space vector changes, the direction of the U phase current also changes.

[0096] When the space vector of the V phase (b) above is changed, the space vector changes in the order (000), (110), and (100), so the transition of the direction of the V phase current becomes "rightward," "rightward," and "leftward." Therefore, although the direction of the V phase current changes due to the change in the space vector, the change is smaller than the change in the direction of the U phase current.

[0097] That is, (a) changing the space vector of the U phase causes a greater change in the direction of the current than (b) changing the space vector of the V phase. In such a case, the correction dead time is set in the phase where the change in the direction of the current is greater due to the change in the space vector. This is because, even if the absolute value of the current is close to 0, changing the dead time in the phase where the change in the direction of the current is greater is less susceptible to the effects of distortion.

[0098] If the direction of the current in the U and V phases does not change when the space vector is changed, the correction dead time may be set in either phase. The same setting can also be used between the U and W phases, and between the V and W phases.

[0099] Next, a description will be given of a flow for setting or changing the ON time in the control unit 200. Fig. 7 is a flowchart for explaining the setting of the ON time of each phase and the correction of the ON time.

[0100] In the first embodiment, as explained with reference to FIG. 2, at timing ta, the ON time of each phase in the period from timing ta to timing tb is calculated, and if it is expected that crossing timing tx will occur, the ON time of each phase is corrected by the correction dead time.

[0101] First, it is determined whether or not the timing is the peak of a triangular wave (step S01). If it is determined that the timing is the peak of a triangular wave, an ON time is set (step S02). Furthermore, a single-phase dead time is set to the set ON time (step S03). Next, it is determined whether or not the triangular wave intersects with modulated waves of two or more phases (step S04).

[0102] After determining whether the triangular wave intersects with modulated waves of two or more phases, if it is determined that the U phase and V phase intersect with the triangular wave, a correction dead time for the ON time of the U phase is set (step S05). In this case, the ON time of the U phase is corrected by adding the correction dead time to the ON time after the single-phase dead time was set in step S03 around the intersection timing tx (step S06). The switch element is turned OFF during the dead time set after the correction (step S07).

[0103] In step S04, in which it is determined whether the triangular wave intersects with the modulated waves of two or more phases, if it is determined that the triangular wave does not intersect with the modulated waves of two or more phases, the ON time set for each phase is not corrected and the switch element is turned OFF during the dead time set in step S03 (step S07).The same applies to the U-phase and W-phase and the V-phase and W-phase.

[0104] By doing so, it is possible to suppress the overlap in time of the switching noises occurring in the two phases.

[0105] The correction of the ON time of each phase explained above will now be explained using specific numerical examples. Assume that the duration of the noise voltage generated by switching is 0.3 microseconds. In this case, for example, if the V-phase upper arm is switched within 0.3 microseconds after the U-phase upper arm is switched, a synergistic noise will be generated due to the noise generated by the switching of the U-phase upper arm and the noise generated by the switching of the V-phase upper arm.

[0106] Here, if the calculation results show that the ON time of the U-phase upper arm is 30.0 microseconds and the ON time of the V-phase upper arm is 30.1 microseconds under the condition that the maximum ON time is 60 microseconds, then the ON time of the U-phase upper arm is changed to 29.7 microseconds, a decrease of 0.3 microseconds. The 0.3 microsecond decrease here corresponds to the correction dead time. By changing the ON time of the U-phase upper arm in this way, the difference between the ON times of the U-phase and V-phase changes from 0.1 microseconds before the change to 0.4 microseconds after the change.

[0107] In this case, the difference in ON times between the U and V phases (0.4 microseconds) exceeds the 0.3 microsecond duration of the noise voltage generated by switching, making it possible to suppress the synergistic noise generation described above. Note that the duration of the noise voltage and the correction dead time can be set to values ​​required for the system.

[0108] Note that, depending on how the ON time of the U phase is changed using the methods described above, a discrepancy in the voltages applied to motor 500 between the U phase, V phase, and W phase may occur, causing an imbalance in the currents flowing through the wires of each phase, which may distort the driving force of motor 500 over time and increase vibration or noise.

[0109] However, such a time distortion of the driving force of the motor 500 can be suppressed by the method described below. That is, in an example where the ON time of the U phase is shortened by the corrected dead time, causing a drop in the voltage equivalent to voltage α(V), the line voltage between each phase is as follows: The line voltage between the U phase and the V phase decreases by the voltage α(V). The line voltage between the V and W phases remains unchanged. The line voltage between the W phase and the U phase increases by a voltage α (V).

[0110] Therefore, the difference in line voltage across the three phases is 2α(V), which is the difference between the line voltage between the U phase and the V phase and the line voltage between the W phase and the U phase. As a result, the current flowing through the wires of each phase becomes unbalanced, which may distort the driving force of the motor 500 over time, increasing the possibility of increased vibration or noise.

[0111] In an example where the voltage equivalent to the voltage α(V) described above drops, for example, by shortening the ON time of the W phase by a correction dead time (such dead time is also referred to as a voltage correction dead time) that is different from the correction dead time set between the U phase and the V phase, the voltage is lowered to a value that always corresponds to the voltage of the W phase minus the voltage α ÷ 2(V), and the difference in line voltage between each phase can be reduced as follows: The line voltage between the U phase and the V phase decreases by the voltage α(V). The line voltage between the V phase and the W phase increases by the voltage α÷2 (V). The line voltage between the W phase and the U phase increases by the voltage α÷2 (V).

[0112] Therefore, the difference in line voltage across the three phases, between the line voltage between the U and V phases and the line voltage between the W and U phases, becomes one-third (i.e., 2α÷3(V)) of the difference when the W phase voltage is not changed, so the difference in line voltage across the three phases does not become small. This reduces the imbalance in current flowing through the electric wires of each phase, thereby reducing the temporal distortion of the driving force of motor 500 and suppressing the degree of increase in vibration, noise, etc.

[0113] In this way, the ON time of the W phase, which is not related to the change in ON time due to the correction dead time, can also be changed by a correction dead time that is different from the correction dead time set between the U phase and the V phase, thereby reducing the imbalance in the current flowing through the wires of each phase.

[0114] Since the dead time TdU is set as described above, it is possible to avoid a time overlap between the timing at which the U-phase lower arm MOSFET (i.e., switch element 311) turns ON and the timing at which the V-phase lower arm MOSFET (i.e., switch element 312) turns ON, which are set at timing ta. It is also possible to avoid a time overlap between the timing at which the U-phase upper arm MOSFET (i.e., switch element 301) turns ON and the V-phase upper arm MOSFET (i.e., switch element 302) turns ON.

[0115] That is, the control unit 200 has a dead time correction unit 250 that adds a correction dead time to one (i.e., the U phase) of the ON times set for each of the two phases (i.e., the U phase and the V phase) and outputs the result to the gate drive circuit 400, thereby preventing the MOSFETs of the U phase and V phase (i.e., the switch element 311 of the lower arm of the U phase and the switch element 312 of the lower arm of the V phase, or the switch element 301 of the upper arm of the U phase and the switch element 302 of the upper arm of the V phase) from being turned ON at the same time.

[0116] This makes it possible to suppress the generation of synergistic voltage noise that occurs when the MOSFETs (i.e., switch element 311 of the lower arm of the U phase and switch element 312 of the lower arm of the V phase, or switch element 301 of the upper arm of the U phase and switch element 302 of the upper arm of the V phase) are switched in a time-overlapping manner. In other words, it is possible to suppress the synergistic noise that occurs when noises generated by the switching of each of the multiple phases are overlapped.

[0117] Furthermore, by suppressing the generation of synergistic voltage noise, it is possible to reduce the maximum value of the common mode current flowing through the DC power supply unit of the inverter, for example.

[0118] Furthermore, by suppressing the generation of synergistic voltage noise, for example, the instantaneous common mode current is reduced, which prevents saturation of the common mode choke coil, allowing the use of less expensive noise suppression components.Furthermore, it also leads to a reduction in the number of ferrite cores wound around electric cables, which is environmentally friendly.

[0119] Furthermore, in addition to two phases such as U and V, even for one other phase such as W, the amount of ON time correction can be corrected using the corrected dead time to reduce the difference in line voltage and thereby reduce imbalances in the currents flowing through the electric wires of each phase. This reduces the temporal distortion of the driving force of motor 500 and can suppress increases in vibration, noise, and the like.

[0120] Embodiment 2 8 is a block diagram showing the functional configuration of an inverter device according to embodiment 2. Here, control unit 700 according to embodiment 2 differs from control unit 200 according to embodiment 1 in that control unit 700 further includes inverter noise detection unit 260, but other configurations are the same as or equivalent to those of embodiment 1. For this reason, parts that are the same as or equivalent to those of embodiment 1 are given the same reference numerals, and description of these parts will be omitted.

[0121] In the inverter device 100 according to the first embodiment, the noise duration is set to a constant value. However, in an actual product, it may be desirable to take into consideration variations between products, changes in the noise duration caused by changes in the usage environment, and the like.

[0122] In inverter device 101 according to the second embodiment, the noise duration is measured in an actual product, and the corrected dead time is corrected based on the noise duration obtained by the measurement. The noise duration is output to dead time correction unit 250. Note that the noise duration may be measured multiple times, and the average of the measured noise durations may be used as the noise duration.

[0123] The inverter noise detection unit 260 included in the control unit 700 detects noise generated in the inverter main body 300. The noise duration is mainly determined by the parasitic resistance R, parasitic inductance L, and capacitance C resulting from stray capacitance, which are generated by the wiring pattern on the board and the substrate of the board. Therefore, within a single product, the wiring pattern on the board and the substrate of the board are kept in the same state, so there is little variation in the noise duration generated by the wiring pattern on the board and the substrate of the board.

[0124] Fig. 9 is an explanatory diagram for explaining the duration of noise generated by switching in an inverter. A in Fig. 9 is a signal input to gate drive circuit 400. B in Fig. 9 is a signal output from gate drive circuit 400 and input to the gate of any MOSFET included in inverter main body 300 (specifically, the gate of the MOSFET used in any of the switch elements used in each of switch elements 301, 311, 302, 312, 303, and 313).

[0125] 9C shows the drain current flowing through the drain of the MOSFET to which the output from the gate drive circuit 400 is input (specifically, the drain of the MOSFET used in any of the switch elements 301, 311, 302, 312, 303, and 313). D in Fig. 9D shows the noise generated from the MOSFET to which the output from the gate drive circuit 400 is input (i.e., any of the switch elements 301, 311, 302, 312, 303, and 313).

[0126] Time t1 is the time when the signal output from the control unit 200 and input to the gate drive circuit 400 changes from OFF to ON. In the gate drive circuit 400, a time delay occurs within the gate drive circuit 400 because the part where the signal is input and the part where the signal is output are insulated. Furthermore, a further time delay occurs within the gate drive circuit 400 because it is also affected by gate resistance and the like that adjusts the switching of the power semiconductor used in the output stage of the gate drive circuit 400.

[0127] Because the gate drive circuit 400 experiences the time delay described above, the output signal output from the gate drive circuit 400 transitions in voltage from OFF to ON with a slope starting from time t2, which is after time t1, as shown in FIG. 9B, and turns ON at time t3.

[0128] In this case, the length of time from time t1 to time t3 corresponds to the length of the single-phase dead time.

[0129] The output signal output from the gate drive circuit 400 is input to the inverter main body 300 as a gate signal for the MOSFET provided in the subsequent inverter main body 300 (specifically, a gate signal provided to the gate of the MOSFET used in any of the switch elements used in each of the switch elements 301, 311, 302, 312, 303, and 313).

[0130] When the voltage of the gate signal exceeds the threshold voltage, the gate of the MOSFET (specifically, the gate of the MOSFET used in any of the switch elements 301, 311, 302, 312, 303, and 313) included in the inverter main body 300 turns ON, and as shown in FIG. 9C, from time t3, the drain current ID flows with the amount of current increasing, and the drain current ID stabilizes from time t4 onwards.

[0131] The time change in the current between time t3 and time t4 contains high-frequency components, so a noise voltage is generated at the point where the current flows that follows a damped oscillation with a resonant frequency and damping time determined mainly by the parasitic resistance R, parasitic inductance L, and capacitance C resulting from stray capacitance.

[0132] The generated noise voltage is shown in D of Figure 9. Here, time t5 is the point in time when the noise voltage following damped oscillation has become one-tenth of its maximum amplitude and the influence of the noise voltage at points other than the point where the current has flowed has become sufficiently small. In each embodiment, the noise duration will be described as the period between time t3 and time t5.

[0133] In this case, the length of time from time t3 to time t5 corresponds to the length of the dead time between the phases.

[0134] Fig. 10 is an explanatory diagram for explaining an inverter noise detection unit. A in Fig. 10 schematically shows an inverter noise detection unit 260 according to the second embodiment. The inverter noise detection unit 260 can be thought of as a copper foil 11 provided on a substrate 12. That is, when a current flows from point A to point B of the copper foil 11 provided on the substrate 12, the current is affected by parasitic resistance R, parasitic inductance L, and capacitance C due to stray capacitance.

[0135] 10B shows an equivalent circuit of the parasitic resistance R, parasitic inductance L, and capacitance C resulting from stray capacitance, which affect the current flowing between points A and B of the copper foil 11. FIG. 10C shows the change over time in the amplitude voltage of the noise generated when a current flows between points A and B of the copper foil 11.

[0136] The change in amplitude voltage over time in the generated noise shown here is similar to the generated noise shown in D of Figure 9, and the mechanism by which the generated noise occurs from time t1 to time t5 is the same as that explained with reference to D of Figure 9.

[0137] 10, the inverter noise detection unit 260 is schematically illustrated as having copper foil 11 provided on a substrate 12, but it may also be, for example, an ordinary electric cable. The copper foil 11 does not necessarily have to be copper, and may be any other good electrical conductor such as a conductive metal or a transparent electrode.

[0138] Fig. 11 is a schematic diagram showing an example of the inverter noise detection unit 260. As shown in Fig. 11, the voltage generated between point A and point B is amplified using a non-inverting amplifier configured with an operational amplifier 20 and resistors R1 and R2 to a voltage that can be detected by, for example, a microcomputer (not shown) external to the inverter noise detection unit 260.

[0139] When determining the noise duration in a microcomputer, the noise duration can be the time from when the absolute value of the voltage of the generated noise becomes equal to or greater than a predetermined first voltage value until it becomes less than a predetermined second voltage value. Note that the predetermined first voltage value and the predetermined second voltage value here may be the same value or different values ​​(however, the predetermined first voltage value is a voltage value greater than the predetermined second voltage value).

[0140] 11 shows an example of inverter noise detection unit 260 that uses a non-inverting amplifier configured with operational amplifier 20 and resistors R1 and R2, but an inverting amplifier may also be used. Also, a capacitor may be added between point B and resistor R1 to form a high-pass filter, and a noise detection circuit may be used that detects noise generated according to the pass frequency of the high-pass filter.

[0141] As described above, in the inverter device 101 of the second embodiment, noise generated in the inverter main body 300 is detected by the inverter noise detection unit 260 and a microcomputer (not shown), and the noise duration is measured. Then, a correction dead time is set based on the measured noise duration, and the ON time of each phase is changed using the correction dead time.

[0142] Note that points A and B shown in inverter noise detection unit 260 are selected from locations other than parasitic resistance R, parasitic inductance L, and capacitance C resulting from stray capacitance, for example, locations that do not include resistive elements of electronic components. Furthermore, for example, while measuring the noise duration of the U phase, any location can be selected as long as it is not affected by switching of phases other than the U phase (i.e., the V phase or the W phase).

[0143] More specifically, regarding points A and B, for example, two points can be selected and measured in the pattern of the portion where the DC power supply 310 and the inverter main body 300 are connected as shown in Fig. 8. Alternatively, two points can be selected and measured in the pattern of the lower arms of each phase provided in the inverter main body 300 as shown in Fig. 3. However, in either case, the measurement must be performed at a timing when current is flowing only in the U phase while, for example, the noise duration of the U phase is being measured.

[0144] As described above, in the inverter device according to the second embodiment, it is possible to set a correction dead time that is measured based on the noise duration time in accordance with the actual device. Furthermore, it is possible to set an optimal correction dead time in response to, for example, variations between products and changes in the installation environment.

[0145] Embodiment 3 12 is a block diagram showing the functional configuration of a motor drive device according to embodiment 3. The motor drive device according to embodiment 3 is configured to include the inverter device according to embodiment 1 or embodiment 2. Therefore, the other configuration is the same as or equivalent to embodiment 1 or embodiment 2. For this reason, parts that are the same as or equivalent to parts of embodiment 1 or embodiment 2 are assigned the same reference numerals, and description of these parts will be omitted.

[0146] Motor drive device 1 is configured to include a power conversion device 3 in addition to the inverter device according to embodiment 1 or 2, and to drive motor 500. Power is supplied to power conversion device 3 included in motor drive device 1 from an external AC power supply 2.

[0147] 12, an AC power supply 2 is connected to a power conversion device 3 provided in a motor drive device 1, and AC power is first converted to DC power. That is, the power conversion device 3 functions as a DC power supply for the motor drive device 1. A general bridge circuit and smoothing circuit can be used to convert AC power to DC power in the power conversion device 3, and therefore a description thereof will be omitted.

[0148] In FIG. 12, the inverter noise detection unit 260 described in the second embodiment is not shown, but when the inverter device 101 is used in the motor drive device 1 of the third embodiment, it includes the inverter noise detection unit 260 and operates in the same manner as that described in the second embodiment.

[0149] With this configuration, inverter device 100 or inverter device 101 used in motor drive device 1 of embodiment 3 can suppress the effects of switching noise generated from inverter main body 300, stabilizing the rotation operation of motor 500. Furthermore, since the effects of switching noise generated from inverter main body 300 can be suppressed, heat generation and noise generation in motor 500 can be suppressed.

[0150] Fig. 13 is an explanatory diagram illustrating an example of the hardware configuration of a control unit provided in an inverter device. Fig. 13 illustrates the hardware configuration when the functions of control unit 200 are realized using hardware that executes a program. Control unit 200 includes processor 201 and memory 202.

[0151] The processor 201 is a CPU (Central Processing Unit). The processor 201 may be a processing device, an arithmetic unit, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor). Each function of the control unit 200 is realized by the processor 201, software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 202, which is an internal memory. The memory 202 is a non-volatile or volatile semiconductor memory, such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), or an EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory).

[0152] The configurations described in the above embodiments are merely examples, and may be combined with other known technologies. Furthermore, parts of the configurations may be omitted or modified without departing from the spirit of the invention.

[0153] Various aspects of the present disclosure are summarized below as appendices.

[0154] (Appendix 1) an inverter main body having switching elements provided corresponding to upper and lower arms of each phase of a three-phase voltage; a gate drive circuit that outputs a gate signal that controls the open / closed state of each of the switching elements provided in the inverter main body; an inverter device comprising: a control unit having a carrier signal output unit that outputs a carrier signal; a modulated wave output unit that outputs a modulated wave of each phase of the three-phase voltage; a plurality of comparators that compare the voltage of the carrier signal with the voltage of the modulated wave of each phase and output a comparison voltage for each of the phases; and a dead time correction unit that adds a correction dead time to one of the ON times set for each of the two phases based on the comparison voltages output from the comparators corresponding to the two phases around a time point when the voltage of the carrier signal matches the voltage of the modulated wave of any two of the modulated waves of the phases, and outputs the result to the gate drive circuit. (Appendix 2) 2. The inverter device according to claim 1, wherein the length of the corrected dead time is at least equal to the sum of the length of the single-phase dead time and the length of the inter-phase dead time. (Appendix 3) 2. The inverter device according to claim 1, wherein the three-phase voltage is composed of voltages of three phases, namely, a U phase, a V phase, and a W phase, and the two phases are two phases included in any one of combinations of the U phase and the V phase, the V phase and the W phase, and the W phase and the U phase. (Appendix 4) 4. The inverter device according to claim 3, wherein a voltage correction dead time is added to an ON time set for a phase other than the phases included in any one of the combinations. (Appendix 5) The inverter device according to appendix 1, wherein the timing for adding the correction dead time is before and after switching at a timing when the voltages of two modulated waves corresponding to any two of the three phases and the carrier voltage match, and the correction dead time is added to the ON time of the phase whose current direction changes more frequently among the current directions corresponding to any two of the three phases. (Appendix 6) 2. The inverter device according to claim 1, further comprising an inverter noise detector, wherein the control unit measures a noise duration based on a noise signal detected by the inverter noise detector and outputs the measured noise duration to the dead time correction unit. (Appendix 7) 7. The inverter device according to claim 6, wherein the noise duration is measured multiple times and an average of the measured noise durations is output to the dead time correction unit. (Appendix 8) 2. The inverter device according to claim 1, wherein the carrier signal is a triangular wave, and the ON time of each phase is set at the timing of the peak of the triangular wave. (Appendix 9) A motor drive device comprising the inverter device according to any one of Supplementary Note 1 to Supplementary Note 8. [Explanation of symbols]

[0155] 100 inverter device, 300 inverter main body, 200 control unit, 500 motor, 400 gate drive circuit, 210 carrier signal output unit, 220 U-phase modulated wave output unit, 230 V-phase modulated wave output unit, 240 W-phase modulated wave output unit, 221 comparator, 231 comparator, 241 comparator, 250 dead time correction unit, 310 DC power supply, ta timing, tb timing, TdU interphase dead time, TdV V-phase dead time, 700 control unit, 260 inverter noise detection unit.

Claims

1. an inverter main body having switching elements provided corresponding to upper and lower arms of each phase of a three-phase voltage; a gate drive circuit that outputs a gate signal that controls the open / closed state of each of the switching elements provided in the inverter main body; a control unit including a carrier signal output unit that outputs a carrier signal; a modulated wave output unit that outputs a modulated wave for each phase of the three-phase voltage; a plurality of comparators that compare the voltage of the carrier signal with the voltage of the modulated wave for each phase and output a comparison voltage for each of the phases; and a dead time correction unit that adds a correction dead time to one of the ON times set for each of the two phases based on the comparison voltages output from the comparators corresponding to the two phases around a time point when the voltage of the carrier signal matches the voltage of the modulated wave for any two of the modulated waves for each phase, and outputs the correction dead time to the gate drive circuit.

2. 2. The inverter device according to claim 1, wherein the length of the corrected dead time is at least equal to the sum of the length of the single-phase dead time and the length of the inter-phase dead time.

3. 2. The inverter device according to claim 1, wherein the three-phase voltage is constituted by voltages of three phases, namely, a U phase, a V phase, and a W phase, and the two phases are two phases included in any one of combinations of the U phase and the V phase, the V phase and the W phase, and the W phase and the U phase.

4. 4. The inverter device according to claim 3, wherein a voltage correction dead time is added to an ON time set for a phase other than the phases included in any one of the combinations.

5. 2. The inverter control device according to claim 1, wherein the timing for adding the correction dead time is before and after switching at a timing when the voltages of two modulated waves corresponding to any two of the three phases and the carrier voltage match, and the correction dead time is added to the ON time of a phase that changes current direction more frequently among the current directions corresponding to any two of the three phases.

6. 2. The inverter device according to claim 1, further comprising an inverter noise detector, wherein the control unit measures a noise duration based on a noise signal detected by the inverter noise detector and outputs the measured noise duration to the dead time correction unit.

7. 7. The inverter device according to claim 6, wherein the noise duration is measured a plurality of times, and an average of the measured noise durations is output to the dead time correction unit.

8. 2. The inverter device according to claim 1, wherein the carrier signal is a triangular wave, and the ON time of each phase is set at the timing of the peak of the triangular wave.

9. A motor drive device comprising the inverter device according to any one of claims 1 to 8.

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