Light receiving element

Abstract

To provide a light receiving element in which crosstalk between adjacent pixels can be reduced.SOLUTION: A light receiving element is provided, comprising: a substrate including a main surface; a light receiving layer provided on the main surface; a groove provided between a plurality of pixels; and a contact layer provided on the light receiving layer and provided on each of the plurality of pixels. The light receiving layer includes a first semiconductor layer provided on the main surface and a second semiconductor layer provided on the first semiconductor layer. The first semiconductor layer includes a type II quantum well layer including an InGaAs layer and a GaAsSb layer. The second semiconductor layer includes an InGaAs layer. The groove includes a bottom surface located in the second semiconductor layer. The light receiving layer includes a high-resistance region located on the bottom surface.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a light receiving element. [Background technology]

[0002] Patent Documents 1 to 3 disclose a photodetector for detecting infrared light, which includes a photodetector layer having a type II quantum well layer. In the photodetector, grooves are formed between multiple pixels, and a mesa is provided for each pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-144278 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-175686 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-149422 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above light receiving element, it is difficult to reduce crosstalk between adjacent pixels.

[0005] An object of the present disclosure is to provide a light-receiving element that can reduce crosstalk between adjacent pixels. [Means for solving the problem]

[0006] A light-receiving element according to one aspect of the present disclosure is a light-receiving element including a plurality of pixels, comprising: a substrate including a main surface; a light-receiving layer provided on the main surface; grooves provided between the plurality of pixels; and a contact layer provided on the light-receiving layer and provided in each of the plurality of pixels, wherein the light-receiving layer includes a first semiconductor layer provided on the main surface and a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer including a type-II quantum well layer including an InGaAs layer and a GaAsSb layer, the second semiconductor layer including an InGaAs layer, the grooves having a bottom surface located in the second semiconductor layer, and the light-receiving layer including a high-resistance region located at the bottom surface. [Effects of the Invention]

[0007] According to the present disclosure, a light receiving element capable of reducing crosstalk between adjacent pixels is provided. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view schematically showing a light-receiving element according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view showing a structure in which the light receiving element shown in FIG. 1 and a readout circuit board are connected. [Figure 4] FIG. 4 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 5] FIG. 5 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 9]FIG. 9 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 11] FIG. 11 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a step in a method for manufacturing the light-receiving element of FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a light-receiving element according to a modified example of this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] (1) A light-receiving element is a light-receiving element including a plurality of pixels, comprising: a substrate including a main surface; a light-receiving layer provided on the main surface; grooves provided between the plurality of pixels; and a contact layer provided on the light-receiving layer and provided in each of the plurality of pixels, wherein the light-receiving layer includes a first semiconductor layer provided on the main surface and a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer includes a type-II quantum well layer including an InGaAs layer and a GaAsSb layer, the second semiconductor layer includes an InGaAs layer, the grooves have a bottom surface located in the second semiconductor layer, and the light-receiving layer includes a high-resistance region located at the bottom surface.

[0011] According to the light receiving element of this embodiment, the grooves and the high resistance regions can reduce crosstalk between adjacent pixels.

[0012] (2) In the above (1), the groove may have a width greater than the width of the high resistance region.

[0013] (3) In the above (1) or (2), the high resistance region may include a lower surface that is located at the same level as or lower than the lower surface of the second semiconductor layer.

[0014] (4) In any one of (1) to (3) above, the absorption layer may further include a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer may include beryllium, and the high resistance region may include a lower surface located within the third semiconductor layer.

[0015] (5) In any one of the above (1) to (4), the high resistance region may contain at least one of zinc and iron.

[0016] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same or equivalent elements are designated by the same reference numerals, and redundant description will be omitted.

[0017] FIG. 1 is a plan view schematically illustrating a light-receiving element according to this embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. As shown in FIGS. 1 and 2, the light-receiving element 1 includes a plurality of pixels P. The light-receiving element 1 may include a substrate 10, a contact layer 20, a light-receiving layer 30, a contact layer 40, grooves TR1 and TR2, a passivation film 50, an anti-reflection film 60, a p-electrode 70, an n-electrode 80, and bumps 90. The light-receiving element 1 may not include at least one of the contact layer 20, groove TR2, passivation film 50, anti-reflection film 60, p-electrode 70, n-electrode 80, and bumps 90.

[0018] A plurality of pixels P are arranged on the substrate 10. The plurality of pixels P may be arranged two-dimensionally on the substrate 10. In this embodiment, the plurality of pixels P are arranged two-dimensionally on a main surface 10a of the substrate 10, which will be described later. The pitch between adjacent pixels P may be 20 μm or more and 100 μm or less. The pitch between adjacent pixels P may be 30 μm, 50 μm, or 90 μm. The light receiving element 1 may include 256×320 pixels P, 512×640 pixels P, or 32×128 pixels P.

[0019] The substrate 10 may be an n-type indium phosphide substrate. The substrate 10 may contain sulfur. In this case, the concentration of sulfur contained in the substrate 10 is about 5×10 18 cm -3 The substrate 10 may have a thickness of approximately 300 μm. The substrate 10 includes a main surface 10a and a main surface 10b located opposite the main surface 10a. In the following description, the direction from the main surface 10b toward the main surface 10a is referred to as the first direction D1. The direction that runs along the main surfaces 10a and 10b and intersects the first direction D1 is referred to as the second direction D2. The direction that intersects both the first direction D1 and the second direction D2 is referred to as the third direction D3. The first direction D1 may be perpendicular to the main surfaces 10a and 10b. In this embodiment, the first direction D1, the second direction D2, and the third direction D3 are perpendicular to one another.

[0020] A buffer layer may be provided on the primary surface 10a. That is, the light-receiving element 1 may include a buffer layer provided on the primary surface 10a. The buffer layer may be an n-type buffer layer. The buffer layer may be an InP layer having a thickness of about 0.5 μm. The buffer layer may contain silicon. In this case, the concentration of silicon contained in the buffer layer is about 1×10 18 cm -3 may be.

[0021] The contact layer 20 is provided on the substrate 10. For example, the contact layer 20 is provided on the major surface 10a of the substrate 10. In this embodiment, the contact layer 20 includes an upper surface 20a and a lower surface 20b located on the opposite side to the upper surface 20a and in contact with the major surface 10a. That is, in this embodiment, the contact layer 20 is in contact with the substrate 10. The contact layer 20 may be an n-type contact layer. In this embodiment, the contact layer 20 is an n-type InGaAs layer. The concentration of the n-type dopant in the contact layer 20 is 1×10 18 cm -3 More than 1×10 19 cm -3 The contact layer 20 may have a thickness of 0.1 μm or more and 0.2 μm or less.

[0022] The absorption layer 30 includes a first semiconductor layer 31, a second semiconductor layer 32, and a third semiconductor layer 33. The first semiconductor layer 31 is provided on the substrate 10. For example, the first semiconductor layer 31 is provided on the upper surface 20a of the contact layer 20. In this embodiment, the first semiconductor layer 31 includes an upper surface 31a and a lower surface 31b located on the opposite side to the upper surface 31a and in contact with the upper surface 20a. That is, in this embodiment, the first semiconductor layer 31 is in contact with the contact layer 20.

[0023] The first semiconductor layer 31 includes a type II quantum well layer including an indium gallium arsenide (InGaAs) layer and a gallium arsenide antimonide (GaAsSb) layer. In this embodiment, the first semiconductor layer 31 may include a type II quantum well layer in which InGaAs layers and GaAsSb layers are alternately stacked. In this case, the InGaAs layer may have a thickness of 2 nm or more and 6 nm or less. The GaAsSb layer may have a thickness of 2 nm or more and 6 nm or less.

[0024] The number of pairs of InGaAs layers and GaAsSb layers may be 100 or more and 350 or less. The composition of the InGaAs layers included in the first semiconductor layer 31 is In 0.53 Ga 0.47 The composition of the GaAsSb layer may be GaAs.0.51 Sb 0.49 It may be. 0.53 Ga 0.47 As and GaAs 0.51 Sb 0.49 is lattice matched to indium phosphide.

[0025] The second semiconductor layer 32 is provided on the first semiconductor layer 31. For example, the second semiconductor layer 32 is provided on the upper surface 31a of the first semiconductor layer 31. In this embodiment, the second semiconductor layer 32 includes an upper surface 32a and a lower surface 32b located on the opposite side to the upper surface 32a.

[0026] The second semiconductor layer 32 may have a thickness of 0.5 μm or more and 1.5 μm or less. x Ga y In 1-x-y The second semiconductor layer 32 includes an n-type InGaAs layer. x is equal to or greater than 0 and less than 1. y is equal to or greater than 0 and less than 1. x+y is greater than 0 and less than 1. In this embodiment, the second semiconductor layer 32 includes an n-type InGaAs layer. The concentration of the n-type dopant in the second semiconductor layer 32 is 1×10 15 cm -3 More than 1×10 16 cm -3 The second semiconductor layer 32 may include an i-type InGaAs layer. In this embodiment, the composition of the InGaAs layer included in the second semiconductor layer 32 is In 0.53 Ga 0.47 In other words, in this embodiment, x is 0 and y is 0.53. The composition of the InGaAs layer included in the second semiconductor layer 32 is In 1-y Ga y It may be As, and y may be 0.454 or more and 0.499 or less. In this case, lattice distortion between the second semiconductor layer 32 and the indium phosphide substrate can be suppressed.

[0027] The third semiconductor layer 33 is provided between the first semiconductor layer 31 and the second semiconductor layer 32. For example, the third semiconductor layer 33 is provided on the upper surface 31a of the first semiconductor layer 31. In this embodiment, the third semiconductor layer 33 includes an upper surface 33a in contact with the lower surface 32b of the second semiconductor layer 32, and a lower surface 33b located opposite the upper surface 33a and in contact with the upper surface 31a of the first semiconductor layer 31. That is, in this embodiment, the third semiconductor layer 33 is in contact with both the first semiconductor layer 31 and the second semiconductor layer 32.

[0028] The third semiconductor layer 33 may have a thickness of 0.05 μm or more and 0.15 μm or less. The third semiconductor layer 33 contains beryllium. In this embodiment, the third semiconductor layer 33 includes an InGaAs layer containing beryllium. The composition of the InGaAs layer included in the third semiconductor layer 33 is In 0.53 Ga 0.47 It may be As.

[0029] The contact layer 40 is provided on the second semiconductor layer 32. For example, the contact layer 40 is provided on the upper surface 32a of the second semiconductor layer 32. In this embodiment, the contact layer 40 is in contact with the upper surface 32a. The contact layer 40 may include a p-type InGaAs layer. The contact layer 40 may include zinc. When the contact layer 40 includes zinc, the concentration of zinc contained in the contact layer 40 is 1×10 18 cm -3 More than 1×10 19 cm -3 The contact layer 40 may have a thickness of 0.1 μm or more and 0.3 μm or less. Although no intentional impurities are implanted into the second semiconductor layer 32 during the manufacturing process of the light-receiving element 1, the second semiconductor layer 32 may have a weak n-type conductivity due to unavoidable impurity contamination or the like. Therefore, a pn junction may exist between the second semiconductor layer 32 and the contact layer 40.

[0030] The grooves TR1 are provided between multiple pixels P. Each pixel P includes a contact layer 40 and a second semiconductor layer 32. In this embodiment, the grooves TR1 separate the contact layers 40 of adjacent pixels P from each other. The grooves TR1 separate the second semiconductor layers 32 of adjacent pixels P from each other. In other words, the grooves TR1 in this embodiment can also be said to be grooves for separating adjacent pixels P from each other.

[0031] The groove TR1 includes a bottom surface TR1a. The bottom surface TR1a is located within the second semiconductor layer 32. That is, the bottom surface TR1a is located between the upper surface 32a and the lower surface 32b of the second semiconductor layer 32. The groove TR1 may have a depth of 0.4 μm or more. The groove TR1 may have a width of 3 μm or more and 5 μm or less. In this embodiment, the groove TR1 has a depth of 0.5 μm and a width of 4 μm. For example, the width of the groove TR1 is determined by the length of the groove TR1 in the third direction D3. The third direction D3 is, for example, perpendicular to the second direction D2 in which the groove TR1 extends. A mesa M is formed for each pixel P by the groove TR1. The mesa M includes a contact layer 40 and the second semiconductor layer 32. The planar shape of the mesa M may be a square with a side length of 20 μm.

[0032] The groove TR2 is formed in the absorption layer 30. The groove TR2 may be formed along the outer periphery of the substrate 10. The upper surface 20a of the contact layer 20 is located at the bottom of the groove TR2.

[0033] The passivation film 50 covers the contact layer 40, the absorption layer 30, and the contact layer 20. The passivation film 50 may be a silicon oxide film. The passivation film 50 may have a thickness of 0.2 μm or more and 0.3 μm or less. The passivation film 50 has an opening 50a that exposes the contact layer 40 at the mesa M and an opening 50b that exposes the upper surface 20a of the contact layer 20 at the bottom surface of the groove TR2.

[0034] The p-electrode 70 is formed on the contact layer 40 in each mesa M. The p-electrode 70 is in contact with the contact layer 40 through the opening 50a. The p-electrode 70 may be a metal laminate film in which a titanium layer, a platinum layer, and a gold layer are laminated in this order.

[0035] The n-electrode 80 is formed on the top surface 20a of the contact layer 20, at the bottom of the groove TR2. The n-electrode 80 is in contact with the top surface 20a through the opening 50b. The n-electrode 80 may be a metal stacked film in which a titanium layer, a platinum layer, and a gold layer are stacked in this order.

[0036] The bump 90 is provided on the p-electrode 70. The bump 90 may be an indium bump. In each of the multiple pixels P, the p-electrode 70 is formed on the upper surface of the mesa M, and the bump 90 is formed on the p-electrode 70. The planar shapes of the p-electrode 70 and the bump 90 may be circular. The bump 90 may have a height of approximately 10 μm. Each of the multiple p-electrodes 70 is connected to an electrode provided on the readout circuit board 200 (see FIG. 3) via the corresponding bump 90.

[0037] The light-receiving layer 30 further includes a high-resistivity region 34. For example, the high-resistivity region 34 has a resistance of 1×10 5 Ω or more 1×10 6 The high resistance region 34 is a region having an electrical resistance of Ω or less. The electrical resistance of the high resistance region 34 can be measured by scanning spreading resistance microscopy (SSRM). In measurements using SSRM, a conductive probe is scanned along the surface of the high resistance region 34 to which a bias voltage is applied, thereby measuring the electrical resistance of the high resistance region 34. The high resistance region 34 may be formed in a ring shape surrounding the mesa M in a plan view. The high resistance region 34 may also be separated from the mesa M in a plan view.

[0038] The high-resistance region 34 may contain the same semiconductor material as the second semiconductor layer 32. When the second semiconductor layer 32 contains n-type InGaAs, the high-resistance region 34 may contain p-type InGaAs. In this case, the concentration of the p-type dopant in the high-resistance region 34 may be approximately the same as the concentration of the n-type dopant in the second semiconductor layer 32. The concentration of the p-type dopant in the high-resistance region 34 may be 0.9 to 1.1 times the concentration of the n-type dopant in the second semiconductor layer 32. The concentration of the p-type dopant in the high-resistance region 34 may be 1×10 15 cm -3 More than 1×10 16 cm -3 Examples of p-type dopants include zinc and iron. For example, the high resistance region 34 includes at least one of zinc or iron.

[0039] The high-resistance region 34 is located on the bottom surface TR1a of the trench TR1. The high-resistance region 34 includes an upper surface 34a that forms at least a part of the bottom surface TR1a of the trench TR1, and a lower surface 34b that is located on the opposite side to the upper surface 34a. The lower surface 34b is located, for example, at the same level as or lower than the lower surface 32b of the second semiconductor layer 32. In this embodiment, the lower surface 34b is located at the same level as the lower surface 32b. That is, in this embodiment, the lower surface 34b is in contact with the upper surface 33a of the third semiconductor layer 33. Alternatively, the lower surface 34b may be located within the second semiconductor layer 32.

[0040] The high resistance region 34 may have a thickness of 0.3 μm or more. The high resistance region 34 may have a width of 1 μm or more and 3 μm or less. In this embodiment, the high resistance region 34 has a thickness of 0.4 μm and a width of 2 μm. In the light receiving element 1, the width of the high resistance region 34 and the width of the groove TR1 may be different from each other or may be the same. In this embodiment, the groove TR1 has a width larger than that of the high resistance region 34. The width of the groove TR1 may be larger than that of the high resistance region 34 throughout the entire groove TR1, or may be larger than that of the high resistance region 34 only in a portion of the groove TR1. For example, the width of the high resistance region 34 is determined by the length of the high resistance region 34 in the third direction D3.

[0041] The high-resistance region 34 can be formed by diffusion or ion implantation into the second semiconductor layer 32. No intentional introduction of impurities is performed in regions of the absorption layer 30 other than the high-resistance region 34. However, impurities may be inevitably mixed into the surface layer of the absorption layer 30 during the formation of the passivation film 50, etc. The depth of the inevitably mixed impurities may be 0.1 μm or less. The concentration of n-type dopants in regions of the absorption layer 30 other than the high-resistance region 34 is 1×10 15 cm -3 It may be less than.

[0042] The anti-reflective coating 60 is provided on the major surface 10b of the substrate 10. The anti-reflective coating 60 may be a silicon oxynitride film. The anti-reflective coating 60 may have a refractive index of approximately 1.8. The anti-reflective coating 60 may have a thickness of approximately 148 nm.

[0043] The above-described light receiving element 1 may be connected to a readout circuit board to form a photodetector together with the readout circuit board. Below, with reference to Fig. 3, a structure in which the light receiving element 1 is connected to the readout circuit board, i.e., the structure of a photodetector including the light receiving element 1, will be described. Fig. 3 is a cross-sectional view showing a structure in which the light receiving element shown in Fig. 1 is connected to a readout circuit board.

[0044] The photodetector 100 shown in FIG. 3 includes a light receiving element 1 and a readout integrated circuit (ROIC) 200. The readout circuit 200 includes a wiring substrate 210 and pixel electrodes 220. The pixel electrodes 220 are arranged on one surface of the wiring substrate 210. The readout circuit 200 may include a circuit that reads out signals output from the light receiving element 1. The circuit that reads out signals output from the light receiving element 1 may include a multiplexer. The readout circuit 200 is an example of a circuit substrate.

[0045] The photodetector 100 further includes a connection member 230 that connects the p-electrode 70 and the pixel electrode 220. The connection member 230 is formed by the bump 90 and a bump that was provided on the pixel electrode 220 of the readout circuit substrate 200 before bonding. The bump that was provided on the pixel electrode 220 of the readout circuit substrate 200 may be an indium bump.

[0046] The light receiving element 1 according to this embodiment can reduce crosstalk between adjacent pixels P by the grooves TR1 and the high resistance regions 34. Since the adjacent pixels P are separated from each other by both the grooves TR1 and the high resistance regions 34, crosstalk between the adjacent pixels P can be further reduced compared to a light receiving element that does not have the high resistance regions 34.

[0047] In the light receiving element 1, the absorption edge wavelength of the first semiconductor layer 31 may be longer than the absorption edge wavelength of the second semiconductor layer 32. The first semiconductor layer 31 has high sensitivity in a wavelength range of, for example, 1.0 μm or more and 2.5 μm or less. The second semiconductor layer 32 has high sensitivity in a wavelength range of, for example, 1.0 μm or more and 1.6 μm or less.

[0048] Next, a method for manufacturing the light-receiving element 1 according to this embodiment will be described with reference to Fig. 4 to Fig. 12. Fig. 4 to Fig. 12 are cross-sectional views showing steps in a method for manufacturing the light-receiving element of Fig. 1.

[0049] First, as shown in FIG. 4 , the contact layer 20, the first semiconductor layer 31, the third semiconductor layer 33, the fourth semiconductor layer 32A, and the fifth semiconductor layer 40A are formed in this order by epitaxial growth on the primary surface 10a of the substrate 10. The fourth semiconductor layer 32A includes the same semiconductor material as the second semiconductor layer 32. The fourth semiconductor layer 32A may include n-type InGaAs. The fifth semiconductor layer 40A includes the same semiconductor material as the contact layer 40. The fifth semiconductor layer 40A may include p-type InGaAs. Metal organic vapor phase epitaxy (MOVPE) may be used for the epitaxial growth of the compound semiconductor layers. If the photodiode 1 includes a buffer layer, the buffer layer may be formed on the primary surface 10a of the substrate 10 before the formation of the contact layer 20.

[0050] 5, an insulating film F is formed on the fifth semiconductor layer 40A so as to cover the fifth semiconductor layer 40A. The insulating film F may be a silicon nitride film. The insulating film F includes an opening Fa in a region for forming the high-resistance region 34.

[0051] Next, as shown in FIG. 6 , a high-resistance region 34A is formed. The high-resistance region 34A has electrical resistance comparable to that of the high-resistance region 34. In one example, the high-resistance region 34A is formed by implanting zinc into the fifth semiconductor layer 40A and the fourth semiconductor layer 32A by diffusion. In this example, the high-resistance region 34A may be formed as follows: First, the substrate 10 with the insulating film F formed on the fifth semiconductor layer 40A is sealed in an ampoule together with a zinc member. The ampoule is then heated, causing zinc elements from the zinc member to diffuse through the opening Fa into the fifth semiconductor layer 40A and the fourth semiconductor layer 32A, thereby forming the high-resistance region 34A containing zinc. The depth to which zinc is implanted into the fifth semiconductor layer 40A and the fourth semiconductor layer 32A can be adjusted by adjusting the heating temperature and heating time of the ampoule. The insulating film F is then removed using buffered hydrofluoric acid.

[0052] In another example, the high-resistance region 34A containing iron may be formed by implanting iron ions into the fifth semiconductor layer 40A and the fourth semiconductor layer 32A. The depth to which the iron ions are implanted into the fifth semiconductor layer 40A and the fourth semiconductor layer 32A can be adjusted by the dose and acceleration voltage of the iron ions.

[0053] Next, as shown in FIG. 7, a groove TR1 is formed in the fifth semiconductor layer 40A, the fourth semiconductor layer 32A, and a portion of the high-resistance region 34A. In one example, the groove TR1 may be formed as follows: First, a silicon nitride film is formed on the fifth semiconductor layer 40A and the high-resistance region 34A. The silicon nitride film may be formed by a plasma-enhanced chemical vapor deposition (CVD) method. The silicon nitride film may have a thickness of 0.5 μm. Then, a resist pattern is formed on the silicon nitride film. The resist pattern may be formed by applying a photoresist to the silicon nitride film, exposing it using an exposure device, and developing it. The resist pattern has an opening in a region where the groove TR1 will be formed. The silicon nitride film in the opening is removed by wet etching using buffered hydrofluoric acid, thereby forming a mask from the silicon nitride film.

[0054] The resist pattern is then removed using an organic solvent or the like. Then, using a mask, the fifth semiconductor layer 40A, the fourth semiconductor layer 32A, and a portion of the high-resistance region 34A are removed by dry etching. Reactive ion etching (RIE) or the like may be used as the dry etching. When RIE is used as the dry etching, a mixed gas of silicon tetrachloride gas and argon gas may be used. In this manner, the groove TR1 is formed. The mesa M is formed with the formation of the groove TR1, and adjacent pixels P are separated from each other. The fifth semiconductor layer 40A is separated by the groove TR1, and the contact layer 40 is formed from the fifth semiconductor layer 40A. The fourth semiconductor layer 32A is separated by the groove TR1, and the second semiconductor layer 32 is formed from the fourth semiconductor layer 32A. The remaining region of the high-resistance region 34A when the groove TR1 is formed becomes the high-resistance region 34. In this process, the compound semiconductor layer in the region where the groove TR2 (described later) is formed is also removed. The silicon nitride film is then removed with buffered hydrofluoric acid.

[0055] Next, as shown in FIG. 8, a groove TR2 is formed. The groove TR2 may be formed along the outer periphery of the substrate 10. In one example, the groove TR2 may be formed as follows: First, a silicon nitride film is formed on the contact layer 40 and the high-resistance region 34. The silicon nitride film may be formed by a plasma CVD method. The silicon nitride film may have a thickness of 0.5 μm. Then, a resist pattern is formed on the silicon nitride film. The resist pattern may be formed by applying a photoresist to the silicon nitride film, exposing it using an exposure device, and developing it. The resist pattern has an opening in an area where the groove TR2 will be formed. The silicon nitride film in the opening is removed by wet etching using buffered hydrofluoric acid, thereby forming a mask from the silicon nitride film.

[0056] The resist pattern is then removed using an organic solvent or the like. The second semiconductor layer 32, the third semiconductor layer 33, and the first semiconductor layer 31 are then removed by dry etching using a mask, thereby exposing the upper surface 20a of the contact layer 20. RIE or the like may be used as the dry etching. The silicon nitride film is then removed using buffered hydrofluoric acid. In this manner, the groove TR2 is formed.

[0057] The above-described dry etching may damage the compound semiconductor layer, so after the formation of the groove TR2, wet etching may be performed to remove the damaged portion.

[0058] Next, as shown in FIG. 9 , a passivation film 50 is formed. In one example, the passivation film 50 may be formed as follows: First, a silicon oxide film is formed on the surfaces of the contact layer 40, the second semiconductor layer 32, and the high-resistance region 34 by plasma CVD. The silicon oxide film may be formed at a substrate temperature of 150° C. Then, a photoresist is applied to the formed silicon oxide film, and a resist pattern is formed by exposing and developing the photoresist using an exposure device. The resist pattern includes openings in regions for forming the p-electrode 70 and the n-electrode 80. The silicon oxide film in the openings of the resist pattern is then removed by dry etching. RIE or the like may be used as the dry etching. This results in the formation of the passivation film 50, including an opening 50a exposing the top surface of the contact layer 40 of the mesa M and an opening 50b exposing the contact layer 20.

[0059] Next, as shown in FIG. 10 , a p-electrode 70 is formed on the contact layer 40, and an n-electrode 80 is formed on the contact layer 20. The p-electrode 70 and the n-electrode 80 may be formed by a lift-off method. In one example, the p-electrode 70 and the n-electrode 80 may be formed as follows. First, a resist pattern is formed, including openings in an area for forming the p-electrode 70 and an area for forming the n-electrode 80. Then, a metal laminate film, in which a titanium layer, a platinum layer, and a gold layer are laminated in this order, is formed on the resist pattern by electron beam (EB) evaporation. Then, the metal laminate film on the resist pattern is removed together with the resist pattern using an organic solvent or the like. The p-electrode 70 and the n-electrode 80 are formed from the remaining metal laminate film.

[0060] 11, an anti-reflection coating 60 is formed on the main surface 10b of the substrate 10. In one example, the main surface 10b may be polished to a mirror finish, and then the anti-reflection coating 60 may be formed on the main surface 10b by plasma CVD. In this example, the anti-reflection coating 60 may be formed at a substrate temperature of 200°C. The time required to form the anti-reflection coating 60 may be approximately 40 minutes.

[0061] 12, bumps 90 are formed on the p-electrodes 70. The bumps 90 may be formed by a lift-off method. Thereafter, the substrate 10 is divided into a plurality of chips, thereby forming the light-receiving elements 1.

[0062] In this manner, the light receiving element 1 according to this embodiment can be manufactured.

[0063] Although the preferred embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments.

[0064] In the above-described embodiment, the lower surface 34b of the high-resistance region 34 is located at the same position as the lower surface 32b, but the position of the lower surface 34b is not limited to the above-described position. FIG. 13 is a cross-sectional view showing a light-receiving element according to a modified example of this embodiment. FIG. 13 is a cross-sectional view corresponding to, for example, FIG. 2. In the example shown in FIG. 13, the lower surface 34b is located within the third semiconductor layer 33. In this example, the lower surface 34b is located higher than the lower surface 33b of the third semiconductor layer 33. The lower surface 34b may be located at the same position as the lower surface 33b.

[0065] In the above-described embodiment, the absorption layer 30 includes the third semiconductor layer 33. However, the absorption layer 30 does not necessarily include the third semiconductor layer 33. In this case, the lower surface 32b may be in contact with the upper surface 31a. That is, the second semiconductor layer 32 may be in contact with the first semiconductor layer 31.

[0066] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above meaning, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0067] 1...Photodetector 10...Substrate 10a…main surface 10b…main surface 20...Contact layer 20a…Top surface 20b…Bottom surface 30...Light-receiving layer 31...First semiconductor layer 31a…Top surface 31b…Bottom surface 32...Second semiconductor layer 32a…Top surface 32b…Bottom surface 32A...Fourth semiconductor layer 33...Third semiconductor layer 33a…Top surface 33b…Bottom surface 34…High resistance region 34a…Top surface 34b…Bottom surface 34A…High resistance area 40...Contact layer 40A...5th semiconductor layer 50...Passivation film 50a...Opening 50b…Opening 60…Anti-reflection film 70…p electrode 80…n electrode 90...Bump 100...Photodetector 200...Readout circuit board 210...Wiring board 220...pixel electrode 230...Connecting member D1…first direction D2…Second direction D3…Third direction F...insulating film Fa...Opening M...Mesa P...pixel TR1…groove TR1a…Bottom TR2…Groove

Claims

1. A light receiving element including a plurality of pixels, a substrate including a major surface; a light-receiving layer provided on the principal surface; a groove provided between the plurality of pixels; a contact layer provided on the light receiving layer and provided in each of the plurality of pixels; The light-receiving layer is a first semiconductor layer provided on the major surface; a second semiconductor layer provided on the first semiconductor layer, the first semiconductor layer includes a type II quantum well layer including an InGaAs layer and a GaAsSb layer; the second semiconductor layer includes an InGaAs layer; the groove includes a bottom surface located within the second semiconductor layer; The light-receiving layer includes a high-resistance region located on the bottom surface.

2. The light-receiving element according to claim 1 , wherein the groove has a width greater than a width of the high-resistance region.

3. 3. The light-receiving element according to claim 1, wherein the high-resistance region includes a lower surface that is located at the same level as or lower than a lower surface of the second semiconductor layer.

4. the absorption layer further includes a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer contains beryllium; 3. The light-receiving element according to claim 1, wherein the high-resistance region includes a lower surface located within the third semiconductor layer.

5. 3. The light-receiving element according to claim 1, wherein the high-resistance region contains at least one of zinc and iron.

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