Detection device

Abstract

This detection device comprises: a plurality of lower electrodes (210) adjacent to each other; an organic material layer (220) including a lower carrier transport layer (221) having a plurality of first electrode coating portions (241) each coating at least the upper surface of a corresponding one of the plurality of lower electrodes (210); and a carrier transport suppression unit (250) which is provided at least in a portion between the first electrode coating portions (241) adjacent to each other, and which suppresses carrier transport between the adjacent first electrode coating portions (241).

Description

Detection Device

[0001] The present invention relates to a detection device.

[0002] BACKGROUND ART In recent years, detection devices have become known in which organic photodiodes (OPDs) are arranged on a substrate. Such detection devices are used as biosensors for detecting biometric information such as fingerprints and veins.

[0003] In a detection device using an OPD, a thin film transistor, an organic photoelectric conversion layer, and the like are formed on a substrate. The organic photoelectric conversion layer is formed by disposing an organic material layer having multiple layers, including an organic light-receiving layer, between an upper electrode and a lower electrode. Here, as disclosed in Patent Documents 1 and 2 below, for example, the organic material layer may be commonly provided on multiple lower electrodes.

[0004] JP 2021-125691 A JP 2021-57422 A

[0005] In a detection device using an OPD, if a highly conductive carrier transport layer (e.g., a hole transport layer) among organic material layers is provided in common on multiple lower electrodes, leakage current is likely to occur between adjacent lower electrodes. Such leakage current can occur more significantly as the density of the lower electrodes increases with increasing resolution and the resistance of the carrier transport layer decreases.

[0006] In view of the above, an object of the present invention is to provide a detection device in which leakage current occurring between adjacent lower electrodes via a carrier transport layer is suppressed.

[0007] One aspect of the detection device according to the present invention comprises an organic material layer including a lower carrier transport layer having a plurality of adjacent lower electrodes and a plurality of first electrode covering portions each covering at least an upper surface of a corresponding one of the plurality of lower electrodes, and a carrier movement suppression portion provided at least partially between the adjacent first electrode covering portions and suppressing carrier movement between the adjacent first electrode covering portions.

[0008] According to the present invention, it is possible to suppress leakage current that occurs between adjacent lower electrodes via the carrier transport layer.

[0009] 8 is a plan view showing an outline of a detection device according to an embodiment of the present invention. FIG. 9 is a block diagram showing an example of the configuration of a detection device according to an embodiment of the present invention. FIG. 1 is an enlarged plan view of a region A surrounded by a dashed line in FIG. 1. FIG. 1 is a partial cross-sectional view showing a cross section along line IV-IV in FIG. 1 in the first embodiment. FIG. 4 is a partial cross-sectional view showing an enlarged schematic view of the periphery of the OPL in FIG. 4. FIG. 10 is a cross-sectional schematic view illustrating a process of forming the carrier mobility suppression portion 250 according to the first embodiment. FIG. 11 is a table showing an example of laser conditions used when forming the carrier mobility suppression portion 250 according to the first embodiment. FIG. 12 is an enlarged plan view of another example of region A surrounded by a dashed line in FIG. 1. FIG. 13 is a schematic view showing an example of a film formation mask used in the process of forming the carrier mobility suppression portion 250. FIG. 14 is a partial cross-sectional view showing a cross section along line IV-IV in FIG. 1 in the second embodiment. FIG. 8 is a partial cross-sectional view showing an enlarged schematic view of the periphery of the OPL in FIG. 8. FIG. 15 is a cross-sectional schematic view illustrating a process of forming the carrier mobility suppression portion 250 according to the second embodiment. FIG. 16 is a table showing an example of laser conditions used when forming the carrier mobility suppression portion 250 according to the second embodiment.

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and the present invention should not be construed as being limited to the description of the embodiments exemplified below.

[0011] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those explained in the previous drawings may be assigned the same reference numerals, and duplicate explanations may be omitted.

[0012] Furthermore, in the detailed description of the present invention, when defining the positional relationship between a certain component and another component, "above" and "below" do not only mean being located directly above or directly below a certain component, but also include cases where there are other components interposed between them, unless otherwise specified.

[0013] 1 is a plan view showing an outline of a detection device according to an embodiment of the present invention, which includes a resin substrate 100, a sensor unit 10, a gate line driving circuit 20, a signal line selection circuit 21, a detection circuit 24, a control circuit 26, and a power supply circuit 28.

[0014] A control board 400 is electrically connected to the resin substrate 100 via a flexible printed circuit board 300. A detection circuit 24 is provided on the flexible printed circuit board 300. A control circuit 26 and a power supply circuit 28 are provided on the control board 400. The control circuit 26 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 26 supplies control signals to the sensor unit 10, the gate line driving circuit 20, and the signal line selection circuit 21 to control the detection operation of the sensor unit 10. The power supply circuit 28 supplies a power supply voltage to the sensor unit 10, the gate line driving circuit 20, and the signal line selection circuit 21.

[0015] The resin substrate 100 has a detection area DA and a frame area PA. The detection area DA is an area where the sensor unit 10 is provided. The frame area PA is an area outside the detection area DA, and is an area where the sensor unit 10 is not provided. In other words, the frame area PA is an area between an end of the detection area DA and an end of the resin substrate 100.

[0016] The frame area PA has a bending area BA and a terminal area TA. The bending area BA and the terminal area TA are provided at one end of the frame area. Wiring connected to the detection area DA is arranged in the bending area BA and the terminal area TA. The resin substrate 100 and the flexible printed circuit board 300 are connected in the terminal area TA.

[0017] The sensor unit 10 has a plurality of pixels PX. The pixels PX are arranged in a matrix in the detection area DA. Each of the pixels PX is a photodiode, and outputs an electrical signal corresponding to the light incident thereon. Each pixel PX outputs an electrical signal corresponding to the light incident thereon as a detection signal Vdet to the signal line selection circuit 21. In this embodiment, the detection device 2 detects information related to the living body, such as blood vessel images of a finger or palm, pulse wave, pulse rate, and blood oxygen saturation, based on the detection signal Vdet from each pixel PX. Furthermore, each pixel PX performs detection in accordance with a gate drive signal Vgcl supplied from the gate line drive circuit 20.

[0018] The gate line driving circuit 20 and the signal line selection circuit 21 are provided in the frame region PA. Specifically, the gate line driving circuit 20 is provided in a region of the frame region PA extending in the extension direction of the signal lines SGL (second direction Dy). The signal line selection circuit 21 is provided in a region of the frame region PA extending in the extension direction of the gate lines GCL (first direction Dx), and is provided between the sensor unit 10 and the bending region BA.

[0019] 2 is a block diagram showing an example of the configuration of a detection device according to an embodiment of the present invention. As shown in FIG. 2, the detection device 2 further includes a detection control unit 30 and a detection unit 40. Some or all of the functions of the detection control unit 30 are included in a control circuit 26. In addition, some or all of the functions of the detection unit 40 other than the detection circuit 24 are included in the control circuit 26.

[0020] The detection control unit 30 is a circuit that supplies control signals to the gate line driving circuit 20, the signal line selection circuit 21, and the detection unit 40, respectively, and controls their operations. The detection control unit 30 supplies various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST, to the gate line driving circuit 20. The detection control unit 30 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 21.

[0021] The gate line driving circuit 20 is a circuit that drives the gate lines GCL based on various control signals. The gate line driving circuit 20 sequentially or simultaneously selects multiple gate lines GCL and supplies a gate driving signal Vgcl to the selected gate lines GCL. In this way, the gate line driving circuit 20 selects the pixels PX connected to the gate lines GCL.

[0022] The signal line selection circuit 21 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SGL. The signal line selection circuit 21 is, for example, a multiplexer. The signal line selection circuit 21 connects the selected signal line SGL to the detection circuit 24 based on a selection signal ASW supplied from the detection control unit 30. As a result, the signal line selection circuit 21 outputs the detection signal Vdet of the pixel PX to the detection unit 40.

[0023] The detection unit 40 includes a detection circuit 24, a signal processing unit 44, a storage unit 45, a coordinate extraction unit 46, and a detection timing control unit 47. Based on a control signal supplied from the detection control unit 30, the detection timing control unit 47 controls the detection circuit 24, the signal processing unit 44, and the coordinate extraction unit 46 so that they operate in synchronization.

[0024] The detection circuit 24 is, for example, an analog front end (AFE) circuit. The detection circuit 24 is a signal processing circuit having at least the functions of a detection signal amplifier 42 and an A / D converter 43. The detection signal amplifier 42 amplifies the detection signal Vdet. The A / D converter 43 converts the analog signal output from the detection signal amplifier 42 into a digital signal.

[0025] The signal processing unit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 24. When a detection target such as a finger or palm comes into contact with or close to the detection surface, the signal processing unit 44 can detect unevenness on the surface of the finger, palm, etc. based on the signal from the detection circuit 24. Furthermore, the signal processing unit 44 can detect information related to the living body, such as a blood vessel image of the finger, palm, etc., a pulse wave, a pulse rate, and blood oxygen saturation, based on the signal from the detection circuit 24.

[0026] The storage unit 45 temporarily stores the signals calculated by the signal processing unit 44. The storage unit 45 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0027] The coordinate extraction unit 46 is a logic circuit that calculates the detected coordinates of the unevenness of the surface of the finger, palm, etc. when the signal processing unit 44 detects contact or proximity of a finger, palm, etc. The coordinate extraction unit 46 is also a logic circuit that calculates the detected coordinates of the blood vessels of the finger, palm, etc. The coordinate extraction unit 46 combines the detection signals Vdet output from each pixel PX of the sensor unit 10 to generate two-dimensional information that indicates the shape of the unevenness of the surface of the finger, palm, etc. Note that the coordinate extraction unit 46 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0028] 3 is an enlarged plan view of region A surrounded by a dashed line in FIG. 1. The pixels PX are arranged in a matrix so as to be adjacent to one another. A carrier movement suppression portion 250 is provided between adjacent pixels PX. As will be explained later, in more detail, the carrier movement suppression portion 250 is provided between adjacent electrode covering portions 240. The carrier movement suppression portion 250 suppresses leakage current that occurs between adjacent pixels PX.

[0029] 3 , in a plan view, the carrier migration suppression unit 250 includes a first carrier migration suppression unit 251 extending in the row direction of the plurality of pixels PX (here, the first direction Dx) and a second carrier migration suppression unit 252 extending in the column direction of the plurality of pixels PX (here, the second direction Dy). In a plan view, the first carrier migration suppression unit 251 and the second carrier migration suppression unit 252 intersect so as to surround each pixel PX. That is, in a plan view, the carrier migration suppression unit 250 has a lattice shape that surrounds each of the plurality of pixels PX.

[0030] 4 is a partial cross-sectional view showing a section taken along line IV-IV in FIG. 1 according to the first embodiment. In FIG. 4, a portion of the display area DA and a portion of the frame area PA are shown in cross section. As described above, the display area DA has a plurality of pixels PX, and the frame area PA has a bending area BA and a terminal area TA. Each pixel PX has a corresponding lower electrode 210 and a corresponding thin-film transistor TFT.

[0031] 4 also shows a cross-sectional view of a laminate of the resin substrate 100, the circuit layer CL, the organic photoelectric conversion layer OPL, and the sealing film 260. Here, the circuit layer CL has a barrier inorganic film 110 to an inorganic insulating film 180, and the organic photoelectric conversion layer OPL has a lower electrode 210 to an upper electrode 230.

[0032] 4 shows a cross section in the second direction Dy, but when the display area DA is cut in the first direction Dy, the same cross-sectional structure as in FIG. 4 is observed. In addition, in FIG. 4, hatching of some layers is omitted to make the cross-sectional structure easier to see (the same applies to FIGS. 5-6A and 8-10A).

[0033] From here on, the laminated structure from the resin substrate 100 to the sealing film 260 will be described in order from the bottom up. First, the circuit layer CL provided on the resin substrate 100 will be described.

[0034] A barrier inorganic film 110 is laminated on a resin substrate 100. The resin substrate 100 is formed of polyimide. However, other resin materials may be used as long as the substrate is sufficiently flexible for use in a sheet-type optical detection device. Meanwhile, the barrier inorganic film 110 has a three-layer laminate structure consisting of a first inorganic film (e.g., a silicon oxide film) 111, a second inorganic film (e.g., a silicon nitride film) 112, and a third inorganic film (e.g., a silicon oxide film) 113. The first inorganic film 111 is provided to improve adhesion to the substrate, the second inorganic film 112 serves as a blocking film against external moisture and impurities, and the third inorganic film 113 serves as a blocking film to prevent hydrogen atoms contained in the second inorganic film 112 from diffusing toward the semiconductor layer 131. However, the structure is not particularly limited to this. Further laminates may be provided, or a single layer or two-layer laminate may be used.

[0035] The additional film 120 may be formed in accordance with the location where the thin film transistor TFT (described later) is to be formed. The additional film 120 can suppress changes in the characteristics of the thin film transistor TFT due to light intrusion from the back surface of the channel of the thin film transistor TFT, or can provide a back-gate effect to the thin film transistor TFT by forming the additional film 120 from a conductive material and applying a predetermined potential. Here, after forming the first inorganic film 111, the additional film 120 is formed in an island shape in accordance with the location where the thin film transistor TFT is to be formed, and then the second inorganic film 112 and the third inorganic film 113 are laminated to form the additional film 120 in the barrier inorganic film 110. However, this is not limited thereto, and the additional film 120 may be formed first on the resin substrate 100, and then the barrier inorganic film 110 may be formed.

[0036] A thin-film transistor TFT is formed on the barrier inorganic film 110 for each pixel PX. The thin-film transistor TFT includes a semiconductor layer 131, a gate electrode 132, a source electrode 133, and a drain electrode 134. While only an N-channel transistor is shown here using a polysilicon thin-film transistor as an example, a P-channel transistor may also be formed at the same time. The semiconductor layer 131 of the thin-film transistor TFT has a structure in which a low-concentration impurity region or an intrinsic semiconductor region is provided between the channel region and the source / drain regions. The gate electrode 132 is the portion where the gate line GCL is electrically connected to the semiconductor layer 131 in each pixel PX. Similarly, the source electrode 133 is the portion where the signal line SGL is electrically connected to the semiconductor layer 131 in each pixel PX.

[0037] A gate insulating film 140 is provided between the semiconductor layer 131 and the gate electrode 132. Here, a silicon oxide film is used as the gate insulating film 140. The gate electrode 132 is part of a first wiring layer W1 formed from MoW. In addition to the gate electrode 132, the first wiring layer W1 has a first storage capacitance line CsL1. A part of the storage capacitance Cs is formed between the first storage capacitance line CsL1 and the semiconductor layer 131 (source / drain region) via the gate insulating film 140.

[0038] An interlayer insulating film 150 is formed on the gate electrode 132. The interlayer insulating film 150 has a structure in which a silicon nitride film and a silicon oxide film are stacked. In the area corresponding to the bent region BA, the barrier inorganic film 110 to the interlayer insulating film 150 are removed by patterning. In the area corresponding to the bent region BA, the polyimide constituting the resin substrate 100 is exposed. When the barrier inorganic film 110 is removed by patterning, the polyimide surface may be partially eroded, resulting in a reduction in film thickness.

[0039] Wiring patterns are formed below the step portions at the ends of the interlayer insulating film 150 and the step portions at the ends of the barrier inorganic film 110. The routing wiring RW formed in the next step passes over the wiring patterns when crossing the step portions. For example, a gate electrode 132 is present between the interlayer insulating film 150 and the barrier inorganic film 110, and for example, an additional film 120 is present between the barrier inorganic film 110 and the resin substrate 100, so these layers are used to form the wiring patterns.

[0040] A second wiring layer W2 including portions that will become the source electrode 133, the drain electrode 134, and the routing wiring RW is formed on the interlayer insulating film 150. A three-layer stacked structure of Ti, Al, and Ti is employed here. Another portion of the storage capacitor Cs is formed by a first storage capacitance line CsL1 (part of the first wiring layer W1) and a second storage capacitance line CsL2 (part of the second wiring layer W2) via the interlayer insulating film 150. The routing wiring RW extends to a terminal area TA via a bent area BA, forming a terminal portion T for connecting a flexible printed circuit board 300 or the like.

[0041] The lead wiring RW is formed to cross the bent region BA and reach the terminal portion T, and therefore crosses the step portion of the interlayer insulating film 150 and the barrier inorganic film 110. As described above, a wiring pattern is formed in the step portion using, for example, the additional film 120. Therefore, even if the lead wiring RW is disconnected at the recess of the step, electrical connection can be maintained by contacting the wiring pattern.

[0042] A planarization film 160 is provided so as to cover the source electrode 133, the drain electrode 134, and the interlayer insulating film 150. The planarization film 160 is made of a resin such as photosensitive acrylic, as this has superior surface flatness compared to inorganic insulating materials formed by CVD (Chemical Vapor Deposition), etc. The planarization film 160 is removed in the pixel contact portion 170, the upper electrode contact portion 171, the bent region BA, and the terminal region TA.

[0043] A transparent conductive film 190 made of indium tin oxide (ITO) is formed for each pixel PX on the planarization film 160. The transparent conductive film 190 includes a first transparent conductive film 191 and a second transparent conductive film 192 that are separated from each other.

[0044] The first transparent conductive film 191 covers the second wiring layer W2 whose surface is exposed by removing the planarization film 160 in the pixel contact portion 170. An inorganic insulating film (silicon nitride film) 180 is provided on the planarization film 160 so as to cover the first transparent conductive film 191. The inorganic insulating film 180 has an opening in the pixel contact portion 170.

[0045] On the other hand, the second transparent conductive film 192 is provided below the lower electrode 210 (further below the inorganic insulating film 180) and next to the pixel contact portion 170. The second transparent conductive film 192, the inorganic insulating film 36, and the lower electrode 210 overlap each other, and form an additional capacitance Cad.

[0046] It should be noted that a third transparent conductive film 193 may be formed on the surface of the terminal portion T. The third transparent conductive film 193 formed on the surface of the terminal portion T may be provided one of the purposes of protecting the exposed wiring portion from damage in subsequent processes.

[0047] The configuration of the circuit layer CL provided on the substrate 100 has been described above. Next, the organic photoelectric conversion layer OPL provided on the circuit layer CL in the display area DA will be described. Hereinafter, the description will be made using FIG. 5 in addition to FIG. 4. FIG. 5 is a partial cross-sectional view schematically illustrating an enlarged view of the periphery of the OPL in FIG. 4.

[0048] A lower electrode 210 is provided for each pixel PX on the inorganic insulating film 180 so as to be electrically connected to the drain electrode 134 through an opening in the inorganic insulating film 180 in the pixel contact section 170. Each lower electrode 210 has a bottom surface 210a that contacts the inorganic insulating film 180, a side surface 210b that faces an adjacent lower electrode 210, and a top surface 210c that faces an upper electrode 230 (described later). The lower electrode 210 is formed as a reflective electrode and has a three-layer stacked structure of an indium zinc oxide film, an Ag film, and an indium zinc oxide film. Here, an indium tin oxide film may be used instead of the indium zinc oxide film. The lower electrode 210 extends laterally from the pixel contact section 170 to above the thin-film transistor TFT.

[0049] An organic material layer 220 is provided on the lower electrode 210. The organic material layer 220 includes, from bottom to top, a lower carrier transport layer 221, an organic light-receiving layer 222, and an upper carrier transport layer 223. When a front-illuminated structure is adopted, the lower carrier transport layer 221 serves as a hole transport layer, and the upper carrier transport layer 223 serves as an electron transport layer. However, when a back-illuminated structure is adopted, the lower carrier transport layer 221 serves as an electron transport layer, and the upper carrier transport layer 223 serves as a hole transport layer. The organic light-receiving layer 222 may be formed by vapor deposition or by coating on a solvent dispersion. Here, it is formed solidly over the entire surface covering the detection area DA, but this is not limited to this.

[0050] The organic material layer 220 has an electrode covering portion 240 for each pixel PX. Each electrode covering portion 240 includes a first electrode covering portion 241 included in the lower carrier transport layer 221, a second electrode covering portion 242 included in the organic light receiving layer 222, and a third electrode covering portion 243 included in the upper carrier transport layer 223. The second electrode covering portion 242 is provided to overlap the first electrode covering portion 241, and the third electrode covering portion 243 is provided to overlap the second electrode covering portion 242.

[0051] The plurality of first electrode covering portions 241 cover at least the upper surface 210c of a corresponding one of the plurality of adjacent lower electrodes 210. Here, the plurality of first electrode covering portions 241 cover the upper surface 210c and the side surface 210b of a corresponding one of the plurality of adjacent lower electrodes 210. On the other hand, the bottom surface 210a of the lower electrode 210 is in contact with the inorganic insulating film 180 and is not covered by the first electrode covering portion 241. Note that a configuration in which the plurality of first electrode covering portions 241 cover only the upper surface 210c of a corresponding one of the plurality of adjacent lower electrodes 210 may also be used.

[0052] Between adjacent first electrode covering portions 241, there is provided a carrier movement suppression portion 250 that suppresses carrier movement between adjacent first electrode covering portions 241. In the first embodiment, the carrier movement suppression portion 250 is sandwiched between adjacent electrode covering portions 240. By providing the carrier movement suppression portion 250 between adjacent first electrode covering portions 241 in this manner, it is possible to suppress leakage current that occurs between adjacent lower electrodes 210 via the lower carrier transport layer 221.

[0053] The carrier migration suppression portion 250 has a bottom surface 250 a, a side surface 250 b, and an upper surface 250 c. In the first embodiment, the bottom surface 250 a of the carrier migration suppression portion 250 is in contact with the inorganic insulating film 180, the side surface 250 b of the carrier migration suppression portion 250 is in contact with the electrode covering portion 240, and the upper surface 250 c of the carrier migration suppression portion 250 is in contact with the upper electrode 230. In other words, the organic material layer 220 is not provided between the bottom surface 250 a of the carrier migration suppression portion 250 and the inorganic insulating film 180, and between the upper surface 250 c of the carrier migration suppression portion 250 and the upper electrode 230. With this configuration, the organic material layer 220 is physically and electrically separated for each pixel PX, thereby more reliably suppressing leakage current between the pixels PX.

[0054] In addition, as long as the provision of the carrier movement suppression portion 250 can suppress leakage current between adjacent pixels PX, an organic material layer 220 may be provided between the bottom surface 250a of the carrier movement suppression portion 250 and the inorganic insulating film 180.

[0055] In addition, the multiple first electrode covering portions 241 may be configured to cover only the upper surface 210c of a corresponding one of the multiple adjacent lower electrodes 210, and the side surface 250b of the carrier movement suppression portion 250 may be configured to contact the side surface 210b of the lower electrode 210.

[0056] An upper electrode 230 is formed on the organic material layer 220 in common with each pixel PX. When a front-illuminated structure is employed, the upper electrode 230 must be transparent. Here, PEDOT:PSS is formed on the surface in contact with the organic material layer 220, and then the upper electrode 230 is formed as a thin film that allows incident light to pass through using a metal material such as Ag or Al. The upper electrode 230 is formed from the organic material layer 220 in the detection area DA to the upper electrode contact portion 171 in the frame area PA. The upper electrode 230 is then electrically connected to the routing wiring RW of the second wiring layer W2 at the upper electrode contact portion 171 and ultimately led out to the terminal portion T.

[0057] A sealing film 260 is formed on the upper electrode 140. One of the functions of the sealing film 260 is to protect the organic material layer 220 from moisture and other elements that may enter from the outside, and a high level of gas barrier property is required. Here, the laminated structure including the silicon nitride film is a laminated structure of a silicon nitride film, an organic resin, and a silicon nitride film. A silicon oxide film or an amorphous silicon layer may be provided between the silicon nitride film and the organic resin to improve adhesion. However, since this is a film provided on the light-receiving surface side, a material that does not have an effect such as absorption of light of the wavelength to be detected is preferred.

[0058] Next, a process for forming the carrier migration suppression portion 250 according to the first embodiment will be described. FIG. 6A is a schematic cross-sectional view illustrating a process for forming the carrier migration suppression portion 250 according to the first embodiment. FIG. 6B is a table showing an example of laser conditions used when forming the carrier migration suppression portion 250 according to the first embodiment. In the example shown in FIG. 6A , a laser beam 510 is irradiated onto the organic material layer 220 from a light source device 500, thereby removing portions of the organic material layer 220 that lie between adjacent lower electrodes 210. Through this process, an electrode covering portion 240 is formed in the organic material layer 220 for each pixel PX.

[0059] Depending on the material of the organic material layer 220, if the distance between adjacent lower electrodes 210 is too close, leakage current may occur even if that portion is removed. Therefore, it is desirable to make the distance between adjacent lower electrodes 210 somewhat wider (for example, 30 μm). Furthermore, in consideration of accuracy, it is desirable to perform laser patterning at a distance of, for example, approximately 20 μm or less.

[0060] After the laser patterning, a material is applied between the adjacent electrode covering portions 240, and the resulting applied layer is cured to form the carrier migration suppression portion 250. Any appropriate method such as an inkjet method or a screen printing method may be used to apply the material.

[0061] The material used to form the carrier mobility suppression portion 250 is one that has a lower carrier mobility than at least the material that forms the lower carrier transport layer 221. Carrier mobility is a physical quantity that indicates the ease of movement of carriers (electrons or holes) in a substance. In the organic material layer 220, the carrier mobility of the organic light receiving layer 222 is lower than the carrier mobility of the lower carrier transport layer 221 and the upper carrier transport layer 223. In the first embodiment, the carrier mobility suppression portion 250 is formed of a material (e.g., an insulating material such as polyimide) different from the material that forms the organic material layer 220.

[0062] In the process described above, the carrier migration suppression portion 250 is formed by laser patterning without using a mask, but in consideration of accuracy, formation by laser patterning using a mask and line scanning is more preferable. Therefore, next, the form of the carrier migration suppression portion 250 formed by laser patterning using a mask will be described.

[0063] Fig. 7A is an enlarged plan view of another example of region A surrounded by a dashed line in Fig. 1. Specifically, Fig. 7A is an enlarged plan view of region A in the case where carrier migration suppression portion 250 is formed by laser patterning using a mask. Fig. 7B is a schematic diagram showing an example of a film formation mask used in the process of forming carrier migration suppression portion 250.

[0064] 7A , in a plan view, the carrier movement suppression unit 250 is partially provided along the direction in which the edge of the lower electrode 210 extends. In the example shown in FIG. 7A , one of the directions in which the edge of the lower electrode 210 extends is the row direction of the multiple pixels PX (here, the first direction Dx), and the other direction in which the edge of the lower electrode 210 extends is the column direction of the multiple pixels PX (here, the second direction Dy). That is, in the example shown in FIG. 7A , the carrier movement suppression unit 250 has a plurality of first carrier movement suppression units 251m provided along the first direction Dx and a plurality of second carrier movement suppression units 252m provided along the second direction Dy.

[0065] Bridges 270 are provided between adjacent first carrier movement suppression portions 251m and between adjacent second carrier movement suppression portions 252m. The bridges 270 are inevitably formed during laser patterning using a mask. That is, as shown in FIG. 7B , the deposition mask 600 structurally has non-irradiated portions 610 between portions corresponding to the electrode covering portions 240. The laser beam is not irradiated onto the portions of the organic material layer 220 corresponding to the non-irradiated portions 610, resulting in the formation of the bridges 270. The shape and arrangement of the bridges 270 are not limited to those shown in FIG. 7A and may vary depending on the shape and arrangement of the non-irradiated portions of the deposition mask used. From the perspective of suppressing leakage current between pixels PX, it is preferable to arrange the bridges 270 at the corners of the pixels PX.

[0066] Second Embodiment Finally, a second embodiment will be described. Fig. 8 is a partial cross-sectional view showing a cross section taken along line IV-IV in Fig. 1 according to the second embodiment. Fig. 9 is a partial cross-sectional view schematically showing an enlarged view of the OPL periphery in Fig. 8. Note that a description of the same configuration as in the first embodiment will be omitted.

[0067] 8, the configuration from the substrate 100 to the lower electrode 210 and the configuration from the upper electrode 230 to the sealing film 260 are the same as those in the first embodiment. Also, the organic material layer 220 is disposed on the lower electrode 210, which is the same as in the first embodiment.

[0068] On the other hand, the second embodiment differs from the first embodiment in that the organic light-receiving layer 222 and the upper carrier transport layer 223 are solidly formed. Therefore, in the second embodiment, the organic light-receiving layer 222 does not have the second electrode-covering portion 242, and the upper carrier transport layer 223 does not have the third electrode-covering portion 243.

[0069] The second embodiment also differs from the first embodiment in that a portion of the organic light receiving layer 222, which is an upper layer of the lower carrier transport layer 221, constitutes the carrier mobility suppression portion 250. As described above, the carrier mobility of the organic light receiving layer 222 is lower than that of the lower carrier transport layer 221. Therefore, even if a portion of the organic light receiving layer 222 constitutes the carrier mobility suppression portion 250, it is possible to suppress leakage current that occurs between adjacent lower electrodes 210 via the lower carrier transport layer 221. By adopting such a configuration, it is no longer necessary to separate the formation process of the organic light receiving layer 222 from the formation process of the carrier mobility suppression portion 250, and therefore the effect of suppressing leakage current between adjacent pixels PX can be obtained without reducing productivity.

[0070] In the second embodiment, a carrier migration suppression portion 250 formed of a part of the organic light receiving layer 222 is provided between adjacent first electrode covering portions 241. Here, a bottom surface 250a of the carrier migration suppression portion 250 is in contact with the inorganic insulating film 180, and a side surface 250b of the carrier migration suppression portion 250 is in contact with the first electrode covering portion 241. In other words, the organic material layer 220 is not provided between the bottom surface 250a of the carrier migration suppression portion 250 and the inorganic insulating film 180. With this configuration, the lower carrier transport layer 221 is physically and electrically separated for each pixel PX, thereby more reliably suppressing leakage current between the pixels PX.

[0071] In addition, as long as the provision of the carrier movement suppression portion 250 can suppress leakage current between adjacent pixels PX, a lower carrier transport layer 221 may be provided between the bottom surface 250a of the carrier movement suppression portion 250 and the inorganic insulating film 180.

[0072] In addition, the multiple first electrode covering portions 241 may be configured to cover only the upper surface 210c of a corresponding one of the multiple adjacent lower electrodes 210, and the side surface 250b of the carrier movement suppression portion 250 may be configured to contact the side surface 210b of the lower electrode 210.

[0073] Finally, a process for forming the carrier migration suppression portion 250 according to the second embodiment will be described. FIG. 10A is a cross-sectional schematic view illustrating a process for forming the carrier migration suppression portion 250 according to the second embodiment. FIG. 10B is a table showing examples of laser conditions used when forming the carrier migration suppression portion 250 according to the second embodiment. Unlike the first embodiment, in this embodiment, laser patterning is performed after the lower carrier transport layer 221 is formed on the circuit layer CL and before the organic light-receiving layer 222 and the upper carrier transport layer 223 are formed. The laser patterning method is the same as in the first embodiment, and therefore will not be described here. After the laser patterning, the organic light-receiving layer 222 is collectively applied to the lower carrier transport layer 221, and the resulting applied layer is cured to form the carrier migration suppression portion 250 between adjacent first electrode covering portions 241.

[0074] In the second embodiment, similarly to the first embodiment described in FIG. 7A, laser patterning using a mask may be performed, and the carrier movement suppression portion 250 may be configured to be partially provided along the direction in which the edge of the lower electrode 210 extends in a planar view.

[0075] As a modified example, the carrier movement suppression portion 250 may have a configuration that combines the first and second embodiments. That is, the carrier movement suppression portion 250 may be configured by a material (e.g., an insulating material such as polyimide) having a lower carrier mobility than the material forming at least the lower carrier transport layer 221, and a part of the organic light receiving layer 222.

[0076] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, the configurations shown in the above-described embodiment can be replaced with configurations that are substantially the same as those shown in the above-described embodiment, that have the same effects, or that can achieve the same purpose.

[0077] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the present invention. For example, to the above-described embodiments, a person skilled in the art may appropriately add, delete, or modify components, or add, omit, or change conditions of steps, and these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

Claims

1. a plurality of bottom electrodes adjacent to each other; an organic material layer including a lower carrier transport layer having a plurality of first electrode covering portions each covering at least an upper surface of a corresponding one of the plurality of lower electrodes; a carrier movement suppressing portion provided at least partially between adjacent first electrode covering portions and configured to suppress carrier movement between the adjacent first electrode covering portions; A detection device having:

2. the first electrode covering portion covers a side surface of the lower electrode; The detection device according to claim 1 .

3. In a plan view, the carrier movement suppression portion is partially provided along a direction in which an edge of the lower electrode extends.

3. The detection device according to claim 1 or 2.

4. the carrier migration suppressing portion is formed of a material different from a material forming the organic material layer and having a carrier mobility lower than that of a material forming at least the lower carrier transport layer; 3. The detection device according to claim 1 or 2.

5. the organic material layer further includes an organic light-receiving layer having a plurality of second electrode-covering portions respectively overlapping the first electrode-covering portions, the carrier movement suppression portion is sandwiched between the adjacent second electrode covering portions; 3. The detection device according to claim 1 or 2.

6. the organic material layer further includes an upper carrier transport layer having a plurality of third electrode-covering portions respectively overlapping the second electrode-covering portions, the carrier movement suppression portion is sandwiched between adjacent third electrode covering portions; The detection device according to claim 5 .

7. the organic material layer further includes an organic light-receiving layer provided on the lower carrier transport layer, a part of the organic absorption layer constitutes the carrier migration suppression portion; 3. The detection device according to claim 1 or 2.