Imaging device and distance estimation device

Abstract

To obtain accurate distance image data by removing noise and to obtain distance image data in a short time by reducing the number of integrations, and to provide a distance image processing system that includes a solid-state image sensor that can be used for three-dimensional object recognition for use in autonomous driving of passenger cars and the like.SOLUTION: To process images including distance information obtained by a TOF solid-state image sensor, commonly known as a TOF camera by using deep learning, and reduce noise and enables highly accurate distance images to be obtained by deep learning.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof, or to an imaging device. Further, the present invention relates to a distance estimation device and a distance estimation method.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all included in the category of semiconductor devices. [Background technology]

[0004] In recent years, various research efforts have been made to utilize 3D information. A commonly known method is to construct 3D information from multi-viewpoint images by arranging two or more cameras in parallel. This method can be implemented at low cost, but it is insufficient for autonomous driving, and it is difficult to measure distances with high accuracy.

[0005] As a means of measuring distance, a method (also known as the TOF method) that irradiates an object with light such as infrared light and uses the reflected light to obtain 3D information is gaining attention. TOF distance measurement consists of a light source and a photodetector (sensor or camera). The camera used in this TOF method is called a time-of-flight camera, or TOF camera. A TOF camera can obtain information about the distance from the light source that emits light to an object based on the time-of-flight (time-of-flight) of the reflected light from the light irradiated on the object.

[0006] There are two types of TOF: a direct TOF measurement method that measures TOF directly in the time domain, and an indirect TOF measurement method that measures changes in physical quantities that depend on TOF and a time reference for converting these changes into temporal changes.

[0007] However, TOF cameras can only receive weak light reflected from distant objects for a very short period of time, making the signal prone to being buried in noise.

[0008] Patent Document 1 discloses that a solid-state imaging device uses transistors using oxide semiconductors for both the reset transistor and the transfer transistor.

[0009] In addition, a dataset and a method for correcting images taken in dark environments using machine learning are described in Non-Patent Document 2. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 [Non-patent literature]

[0011] [Non-Patent Document 1] VLSI2018, Panasonic, S Koyama et al., “A 220m-Range Direct Time- of- flight 688×384 CMOS Image Sensor with Sub-photon Signal Extraction Pixels Using Vertical Avalanche Photo-Diodes and 6kHz Light pulse Counter”

[0012] [Non-patent document 2] CVPR 2018, Chen Chen et al., “Learning to See in the Dark” Summary of the Invention [Problem to be solved by the invention]

[0013] If the signal is buried in noise, it becomes difficult to image-recognize a measurement target with low reflectance.

[0014] Distance image data is obtained by accumulating the charges generated by the light receiving element when light from a light source is reflected by the object, and then calculating the distance to the object. To improve resolution, measurements may be repeated multiple times, and the data may be averaged.

[0015] One object of the present invention is to obtain accurate range image data by removing noise, and another object of the present invention is to obtain range image data in a short time by reducing the number of integrations.

[0016] One of the challenges is to provide a range image processing system that includes a solid-state imaging element that can be used for three-dimensional object recognition, in order to be used in autonomous driving of passenger cars and the like.

[0017] To improve the distance resolution of a TOF camera, it is necessary to increase the time resolution. Increasing the time resolution shortens the exposure time, resulting in a decrease in signal strength. To increase this signal strength, multiple measurements can be performed to repeatedly accumulate charge, but this poses a leakage problem for transistors made of single-crystal silicon. Furthermore, transistors made of single-crystal silicon also suffer from variations in leakage current when turned off. The off-current is particularly susceptible to change. Therefore, when constructing charge-retention semiconductor devices such as solid-state imaging devices, there is a need for devices that can ensure a sufficient potential retention period regardless of the environment and have reduced off-current characteristics.

[0018] Furthermore, there is a problem of noise due to leakage when a transistor using single crystal silicon is turned off. Since leakage when a transistor using single crystal silicon is turned off cannot be reduced, there is a problem that noise cannot be eliminated.

[0019] Furthermore, there is a demand for integration and miniaturization of semiconductor circuits used in TOF cameras. [Means for solving the problem]

[0020] Deep learning is used to process images including distance information obtained by a TOF solid-state image sensor, also known as a TOF camera. Deep learning reduces noise and enables the acquisition of highly accurate distance images.

[0021] Distance information consists of multiple spatial slices, and each spatial slice can be used to create a single distance image by overlaying object information for multiple distances across the entire space to be recognized. In the TOF method, light from a light source is irradiated onto an object, and the reflected light is used. For example, by acquiring object images for each distance, such as object information for distances from the solid-state imaging element of 1 m to less than 45 m, object information for distances from 45 m to less than 90 m, and object information for distances from 90 m to less than 135 m, and overlaying these images, a single distance image for distances from 1 m to less than 135 m can be obtained.

[0022] The invention disclosed in this specification is a distance estimation device having a light source that irradiates an object in a measurement space, a light-receiving area of ​​a solid-state imaging element that receives reflected light from the object, an image generation unit that generates first three-dimensional image data based on carriers generated from the light-receiving area, an input unit that inputs the first three-dimensional image data, an estimation unit that performs image processing on the first three-dimensional image data with a processor using a learning model learned from teacher data, and an output unit that generates second three-dimensional image data that is more accurate than the first three-dimensional image data.

[0023] In the above configuration, the training data used for the learning model is a large number of data that have been accumulated more times than the first 3D image data. The 3D image data that have been accumulated more times are trained, and a learning model that has the highest accuracy is used in the output unit.

[0024] A learning model may be constructed in advance by learning the positional relationship between the TOF camera and the three-dimensional coordinates of the object.

[0025] In the above configuration, the second three-dimensional image data is a depth map of the measurement space.

[0026] In the above configuration, image processing is performed by a deep convolutional neural network. Specifically, a U-shaped network, or the so-called U-Net method, is used. The U-Net method is one of the classification and extraction methods used for 2D images. The FCN (Fully Convolutional Network) method can also be used. The U-Net method is an improved version of the FCN method. In addition, the 3D-Net method and the V-Net method, which are three-dimensional extensions of the U-Net method, can also be used.

[0027] A neural network is a mathematical model that aims to represent the characteristics of a biological brain through computer simulation. A convolutional neural network is a forward propagation network with a convolutional layer in which layers with multiple units are connected in one direction from the input stage to the output stage, and the output unit is connected to a specific unit on the adjacent input side.

[0028] In addition, in the above configuration, the distance to the object is estimated by dividing the time range corresponding to the distance from the light source into multiple measurement sections, and based on the time it takes for the light emitted from the light source to reflect from the measurement section in which the object is located and reach the light receiving area.

[0029] The image generation unit calculates an integrated value or average value of the electrical output corresponding to the amount of light received by the solid-state imaging element, and estimates the distance using this value. The image generation unit also calculates the distance using the amount of charge obtained by integrating the current over multiple detection periods for each light-receiving period, and sets this distance as the pixel value of the distance image.

[0030] When the solid-state imaging device is used in a fixed camera installation for security purposes, by using images obtained by increasing the number of integrations as learning data, it is possible to obtain distance images with the same accuracy as images obtained by increasing the number of integrations using imaging data with fewer integrations.Furthermore, by using images obtained by increasing the number of integrations after image processing to reduce noise as learning data, it is possible to obtain distance images with accuracy higher than that of images obtained by increasing the number of integrations using imaging data with fewer integrations.

[0031] The estimation unit can be, for example, a microcomputer. A microcomputer is a program that can execute algorithms such as calculations ported to a microcomputer or microprocessor. A microcomputer is a small computer that consists of a microprocessor, memory, peripheral chips, etc.

[0032] The estimation unit may also be configured as an LSI (Large Scale Integration) integrated and manufactured on a single chip. The integrated circuit method is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. Processors that can be used include 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit processors. Processors include microprocessors, coprocessors, and floating-point processors. Alternatively, a field programmable gate array (FPGA) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within the LSI, may also be used.

[0033] The weighting parameters and pixel values ​​are stored in the memory of the estimation unit, specifically in a read-only memory (ROM) or a random-access memory (RAM), for example, allowing the estimation unit to calculate a distance image more accurately.

[0034] Furthermore, a distance image processing method comprising multiple steps, including neural network processing, can be realized. The distance image processing method can also be realized as a computer program that causes a computer to execute each step. Such a computer program can also be stored and executed on a recording medium or in a cloud via an Internet communication network.

[0035] The configuration of the invention disclosed in this specification is an imaging device having a light-receiving region, a plurality of charge accumulation regions around the light-receiving region, a transistor using an oxide semiconductor that at least partially overlaps the charge accumulation region, and a light-shielding plate that overlaps the plurality of charge accumulation regions and the transistor.

[0036] Another invention provides an imaging device having a light-receiving region, a charge accumulation region, a semiconductor wafer in which at least a first transistor is embedded, and a second transistor at least partially overlapping the charge accumulation region, wherein the second transistor has an oxide semiconductor in a channel formation region.

[0037] The above-described structure further includes a light-shielding plate, which overlaps with the charge accumulation region, the first transistor, and the second transistor.

[0038] A sensor with n rows and m columns (n ​​× m) of pixels is configured, with one light receiving area as one pixel. Note that n or m is a natural number of 2 or more, for example, n may be 32 and m may be 32. When the numbers n and m become large, the circuit scale tends to become enormous. When the circuit scale becomes enormous, it becomes difficult to maintain the simultaneity of measurement between pixels, making it difficult to achieve high time resolution.

[0039] By stacking a transistor using an oxide semiconductor layer on the charge storage region and partially overlapping it, the circuit area can be reduced without changing the circuit scale, leading to chip miniaturization. Furthermore, stacking can achieve high time resolution.

[0040] In each of the above configurations, the light receiving region corresponds to the light receiving area of ​​the embedded photodiode or the light receiving area of ​​the avalanche photodiode.

[0041] Avalanche photodiodes, which detect single photons, are also called SPADs (Single Photon Avalanche Diodes). When a large negative voltage is applied to the cathode, the electrons generated by the incidence of a single photon undergo avalanche multiplication, causing a large current to flow. An electron pulse is generated starting from the arrival time of the single photon. Because the speed of avalanche multiplication is extremely fast, the arrival time of the photon can be determined from the timing of the electron pulse generation, and this can be used to measure the time of flight of light.

[0042] Furthermore, by using a transistor including an oxide semiconductor layer, leakage current can be reduced, and the influence of noise can be reduced.

[0043] The oxide semiconductor layer preferably contains, for example, indium, and more preferably contains In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf).

[0044] The electric field control electrodes are used for high-speed charge transfer. Applying a voltage to a pair of electric field control electrodes generates a fringing electric field, which moves photoelectrons generated in the light-receiving region to the charge accumulation region. A potential gradient is created by controlling the potentials of the multiple electric field control electrodes, and photoelectrons generated in the light-receiving region are moved to the desired charge accumulation region. A stack of insulating layers is provided on the charge accumulation region, and the stack of insulating layers has an opening that partially overlaps the light-receiving region. The stack of insulating layers is formed when forming a transistor using an oxide semiconductor layer. If the stack of insulating layers remains stacked in a position overlapping the light-receiving region, incident infrared rays will be refracted, reducing the amount of light reaching the light-receiving region. Therefore, the stack of insulating layers may be removed. Forming an opening in the stack of insulating layers overlapping the light-receiving region allows infrared rays to be efficiently incident on the light-receiving region.

[0045] A reset transistor is also connected to one of the charge storage regions to reset the charge in the charge storage region.

[0046] The delay time (optical time of flight) of the received optical pulse relative to the output optical pulse can be measured by a known method using multiple photodiodes. Also, the distance corresponding to the delay time (optical time of flight) can be measured by a known method.

[0047] A schematic diagram of a TOF camera is shown in Figure 1. In Figure 1, illumination unit 11 is a light source such as an LED, and object A and object B are at different distances from the light source and are objects illuminated by the light emitted from illumination unit 11. The light reflected from object A and object B is sensed by sensor unit 12, each having a solid-state image sensor. Sensor unit 12 is a sensor in which multiple solid-state image sensors are arranged on a two-dimensional plane, with each pixel consisting of a solid-state image sensor.

[0048] The indirect TOF measurement method involves irradiating object A or object B with light modulated at a high frequency, for example, 10 MHz (high frequency modulated light) as signal light from a light source, capturing the reflected light from the high frequency modulated light as a signal, and measuring the distance between object A or object B and sensor unit 12 and irradiation unit 11 from the phase shift between the high frequency modulated light from irradiation unit 11 and the reflected light.

[0049] The phase shift is determined and measured using the data obtained by the sensor unit 12 and the data from the signal generating unit 13, using the correlation and evaluation unit 14. The irradiation unit 11 emits light in response to an instruction from the signal generating unit 13.

[0050] The phase shift, or phase delay, is converted to a measured distance using the period length and the speed of light. This is done pixel by pixel to calculate the difference in distance between object A and object B.

[0051] In this specification, the TOF camera refers to a device including not only the sensor unit 12 but also the illumination unit 11, the correlation and evaluation unit 14, the signal generation unit 13, etc., and is referred to as an imaging device. [Effects of the Invention]

[0052] Deep learning can be used to obtain high-precision range images from noisy range images, making it useful for applications such as autonomous vehicles and manufacturing machines that use range image data, such as industrial robots.

[0053] For example, when a TOF camera is installed in a vehicle, the model and parameters obtained through neural network learning can be transferred to the vehicle's microcomputer or microprocessor (hereinafter referred to as a microcomputer), making it possible to estimate a distance image from the vehicle and output that distance image.

[0054] Noise due to leakage when a transistor using single crystal silicon is turned off can be reduced, and high time resolution can be achieved.

[0055] This allows for integration or miniaturization of the semiconductor circuits used in TOF cameras. [Brief explanation of the drawings]

[0056] [Figure 1] FIG. 1 is a schematic diagram showing one embodiment of the present invention. [Figure 2] FIG. 2A is an example of a circuit diagram illustrating one embodiment of the present invention, and FIG. 2B is a timing chart. [Figure 3] FIG. 3 is an example of a potential diagram showing one embodiment of the present invention. [Figure 4] FIG. 4 is an example of a circuit diagram illustrating one embodiment of the present invention. [Figure 5] FIG. 5 is an example of a timing chart illustrating one embodiment of the present invention. [Figure 6] FIG. 6A is a top view of a solid-state imaging element showing one embodiment of the present invention, and FIG. 6B is a cross-sectional view. [Figure 7] FIG. 7 is a cross-sectional view of a solid-state imaging device showing one embodiment of the present invention. [Figure 8] FIG. 8A is a top view illustrating a transistor used in a solid-state imaging device according to one embodiment of the present invention, and FIG. 8B is a cross-sectional view. [Figure 9] FIG. 9A is a cross-sectional view of a transistor used in a solid-state imaging device according to one embodiment of the present invention, FIG. 9B is a top view of an oxide semiconductor layer 130 of the transistor, and FIGS. 9C and 9D are cross-sectional views. [Figure 10] 10A and 10B are examples of flow diagrams illustrating one embodiment of the present invention. [Figure 11] FIG. 11 is a block diagram showing one embodiment of the present invention. [Figure 12] Figure 12 is a schematic diagram of the U-Net network architecture. [Figure 13] 13A, 13B, 13C, 13D, 13E, and 13F are diagrams showing how the present invention is used. DETAILED DESCRIPTION OF THE INVENTION

[0057] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the embodiments and details. Furthermore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0058] (Embodiment 1) 2A shows a circuit diagram illustrating one pixel configuration. The pixel circuit shown in FIG. 2A includes at least a photodiode, a plurality of transistors, and a capacitor. The cathode of the photodiode is electrically connected to one of the source and drain of a transistor 22. The gate of the transistor 22 is electrically connected to a wiring TX1, and the other of the source and drain is electrically connected to one electrode of a capacitor 41, one of the source and drain of a transistor 25, and the gate of a transistor 31. The one of the source and drain of the transistor 25 is electrically connected to a wiring VRS.

[0059] For one pixel, one photodiode (PD), one reset transistor (21), and three charge transfer transistors (22, 23, 24) are fabricated on a silicon wafer, with oxide semiconductor transistors (25, 26, 27) stacked on top of them. Capacitors 41, 42, 43 may be fabricated on the silicon wafer or on a layer above that.

[0060] The three charge transfer transistors (22, 23, 24) are each connected to a retention node FD. Time is measured by changing the timing at which charge is stored in the retention node. The reset transistor 21 resets the photodiode PD at times other than the time at which charge is desired to be stored in the retention node. Figure 2B also shows an example of a timing chart for the signals applied to the wires TX1, TX2, TX3, and TX4.

[0061] Conventionally, the photodiode and readout circuit are fabricated on a silicon wafer, so the total chip area is the sum of the areas occupied by the photodiode and the readout circuit. Transistors 31, 32, and 33 are part of the readout circuit. In this embodiment, transistors 31, 32, and 33 and capacitors 41, 42, and 43 are fabricated on the silicon wafer in areas that do not overlap with the light-receiving region and are electrically connected.

[0062] Furthermore, by configuring the readout circuit or a part of it with a transistor using an oxide semiconductor, the area occupied by stacking can be reduced, which makes it possible to expand the area occupied by the light-receiving region of the embedded photodiode and reduce the size of the entire chip.

[0063] FIG. 3 shows a potential diagram for a case where a Si-embedded photodiode is used. In the potential diagram, the downward direction (depth direction) of the diagram represents the positive direction of the electric potential. When charge is stored in FD, there are two leakage paths: a path from the photodiode PD to the retention node FD via the transistor 22 (dotted arrow 45 in FIG. 3 ), and a path from the retention node FD to the wiring VRS via the transistor 25 (dotted arrow 46 in FIG. 3 ). The gate RS of the transistor 25 controls the supply of charge from the wiring VRS to the retention node FD. The first leakage path from the photodiode PD should pose almost no problem if reset via the wiring TX4, but the second leakage path, leakage from the retention node FD to the wiring VRS, is problematic. To solve this problem, a transistor using an oxide semiconductor is used in this embodiment. The transistor 25 using an oxide semiconductor has low leakage, reducing noise due to leakage and enabling high-precision measurements.

[0064] Moreover, instead of the photodiode PD, an avalanche photodiode that can detect energy with lower intensity than a buried photodiode can be used.

[0065] Furthermore, in this embodiment, an example in which there are three charge transfer transistors (22, 23, 24) has been shown, but there is no particular limitation, and there may be two, or four or more transistors.

[0066] Although a silicon wafer is used in the example shown, the present invention is not limited to silicon, and for example, a compound semiconductor substrate can also be used.

[0067] (Embodiment 2) In the present embodiment, an example will be shown below in which an avalanche photodiode, which can detect even smaller light energy than a PIN photodiode, is used as the photodiode.

[0068] An example of a pixel circuit using an avalanche photodiode APD is shown in Figure 4. An example of a timing chart of the signals applied to the wiring TX1, TX2, TX3, and TX4 is shown in Figure 5. The avalanche photodiode APD has the function of multiplying carriers generated inside the element by applying a negative voltage to the cathode, and can obtain a multiplication factor that corresponds to the applied bias.

[0069] Even when using an avalanche photodiode (APD), if the number of incident photons is small, noise can be reduced by measuring and integrating multiple times. When integrating, repeated accumulation is possible if the capacitance on the retention node (FD) side is sufficiently large compared to the capacitance on the avalanche photodiode (APD) side.

[0070] In this embodiment, since the capacitance on the avalanche photodiode APD side is large, a transistor 44 is added to the avalanche photodiode APD side to reduce the capacitance. When the wiring (one of TX1, TX2, and TX3) of transistors 22, 23, and 24 is set to High to transfer charge, the capacitance can be reduced by controlling the gate TR of this transistor 44 to be in the off state. In this case, charge remains in the avalanche photodiode APD, so the avalanche photodiode APD needs to be reset each time charge is transferred.

[0071] In this embodiment, the transistor 44 is fabricated on a silicon wafer, similar to the three charge transfer transistors (22, 23, 24). The transistors (25, 26, 27) using an oxide semiconductor are fabricated above the silicon wafer. By configuring a part of a driver circuit, such as a readout circuit, using a transistor using an oxide semiconductor, the size of each pixel can be reduced. Furthermore, by configuring a part of a driver circuit, such as a readout circuit, using a transistor using an oxide semiconductor, the area of ​​the light-receiving region can be increased when compared for the same pixel size.

[0072] Using this device, it is possible to create a range image sensor that uses the direct TOF measurement method.

[0073] Furthermore, in this embodiment, an example in which there are three charge transfer transistors (22, 23, 24) has been shown, but there is no particular limitation, and there may be two, or four or more transistors.

[0074] (Embodiment 3) 1 shows an example of a solid-state imaging device including a photodiode fabricated on the silicon wafer shown in the first embodiment.

[0075] FIG. 6A shows an example of a layout in which multiple charge accumulation regions 64, which are n-type regions formed by adding impurity elements or the like to a p-type silicon wafer, a charge discharge region 65, a photodiode light receiving region 90, and multiple transfer gate pairs are arranged. Although not shown in FIG. 6A, a light shielding plate is arranged and fixed above the light receiving region surrounded by a dotted line, with the region overlapping with the light receiving region 90 as an opening. For simplicity, FIG. 6A does not show the layout of transistors using oxide semiconductors formed on the silicon wafer below the light shielding plate. However, transistors using oxide semiconductors can be arranged on the silicon wafer via an insulating layer below the light shielding plate, allowing for integration.

[0076] In addition, in Figures 6A and 6B, multiple transfer gate pairs and wiring TX1, TX2, TX3, and TX4 are illustrated as islands, but they are not floating electrodes, but rather wiring is connected to each of them above, and the wiring is laid out so that a desired voltage can be applied to each.

[0077] Furthermore, a microlens may be provided above the light receiving area 90 at a position overlapping with the opening of the light blocking plate 91. The microlens can collect reflected light from an object far from the light source and irradiate it onto the light receiving area 90. Note that the light blocking plate having an opening overlapping with the light receiving area is not shown in FIG. 6A.

[0078] FIG. 6B is a schematic cross-sectional view taken along the dashed line in FIG. 6A.

[0079] In FIG. 6B, the light-receiving region 90 has openings in the insulating layer stacks, formed by selectively removing some of the insulating layers (insulating layer stacks) at positions overlapping the light-receiving region 90 to facilitate light reception. The process for forming the openings in the insulating layer stacks can be performed using the same process as for fabricating transistors using oxide semiconductors, so there is little increase in the number of steps. In this embodiment, openings are provided above the light-receiving region 90 to reduce the influence of the refractive index caused by the insulating layer stacks at positions overlapping the light-receiving region 90. However, openings may be omitted if sufficient infrared light reflected from the target can be received. In FIG. 6B, the light-receiving region 90 is covered only by the first insulating layer 70 and the second insulating layer 75. The first insulating layer 70 and the second insulating layer 75 are made of a highly transparent insulating inorganic material, such as silicon oxide. Alternatively, the first insulating layer 70 may be a field oxide film. The upper surfaces of the first insulating layer 70 and the second insulating layer 75 are preferably planarized by a CMP (Chemical Mechanical Polishing) method or the like, if necessary.

[0080] Furthermore, in order to separate each transistor, element isolation is performed by the p-well region 66. The p-well region 66 can also form a guard ring.

[0081] The light-receiving region 90 is embedded in a silicon wafer. As shown in FIG. 6B, the wafer itself includes a p-type region 60, on which a p-region 61, an n-type surface-buried region 62, a p+ region 63, a first insulating layer 70, and a second insulating layer 75 are stacked. This photodiode structure generates majority carriers in the n-type surface-buried region 62. By sequentially changing the depletion potential of the n-type surface-buried region 62, the destination of the majority carriers is controlled to one of three charge accumulation regions 64, thereby capturing a distance image. This control is performed by appropriately adjusting the voltages applied to the wiring TX1, TX2, TX3, and TX4 and the first transfer gate pair 71, second transfer gate pair 72, third transfer gate pair 73, and fourth transfer gate pair 74.

[0082] If the movement of majority carriers can be controlled by the wirings TX1, TX2, TX3, and TX4, the first transfer gate pair 71, the second transfer gate pair 72, the third transfer gate pair 73, and the fourth transfer gate pair 74 do not need to be provided.

[0083] 6B does not include a transistor using an oxide semiconductor, an example of a cross-sectional structure in which a transistor 25 using an oxide semiconductor is provided and which partially corresponds to FIG. 7 is shown. The insulating layers used in FIG. 7 are the same as those in FIG. 6B, and the same reference numerals are used for the same parts in the description.

[0084] In FIGS. 6A and 6B, a first transfer gate pair 71, a second transfer gate pair 72, a third transfer gate pair 73, and a fourth transfer gate pair 74 use polysilicon wiring or metal wiring.

[0085] Applying voltages to the first transfer gate pair 71, the second transfer gate pair 72, the third transfer gate pair 73, and the fourth transfer gate pair 74 helps to quickly transfer photoelectrons generated in the light receiving region 90 to the charge accumulation region 64.

[0086] The reset transistor can function as a reset transistor that initializes the potential of the light-receiving region 90. By applying a voltage to the wiring TX4, which serves as the gate of the reset transistor, charges are rapidly transferred to the charge drain region 65, where they are drained, thereby performing a reset. Note that a transistor using the wiring TX4 as its gate is fabricated using a known CMOS fabrication process. Transistors using the wirings TX1, TX2, and TX3 as their gates are also fabricated using a known CMOS fabrication process. While this embodiment illustrates a configuration in which one pixel has three charge accumulation regions 64 and one charge drain region 65, this is not particularly limited, and multiple charge drain regions may be provided. Note that the charge accumulation region 64 and the charge drain region 65 are n+ regions fabricated using the same process, and the reset transistor is connected to the charge drain region; the different names are merely used to distinguish them.

[0087] 7 illustrates a transistor having a wiring TX1 as its gate among the transistors formed by embedding in a silicon wafer, with a charge storage region 64 functioning as a source region or a drain region. The transistor having a wiring TX1 as its gate is electrically connected to one of a source electrode or a drain electrode of a transistor 25 using an oxide semiconductor, one of which functions as a storage node FD and the other of which is electrically connected to a wiring VRS via a connection electrode 76. The transistor 25 using an oxide semiconductor partially overlaps with the charge storage region 64. By stacking a transistor using an oxide semiconductor layer on the charge storage region and partially overlapping it, the circuit area can be reduced, leading to chip miniaturization.

[0088] The solid-state imaging device shown in this embodiment has a structure with three transistors for charge transfer and three retention nodes for charge accumulation, and is an element corresponding to the circuit shown in FIG. 2 described in the first embodiment.

[0089] 7 illustrates an example in which the transistor 25 has a back gate, but the transistor 25 may not have a back gate. The back gate may be electrically connected to the front gate of the transistor provided opposite to the back gate. Alternatively, a fixed potential different from that of the front gate may be supplied to the back gate.

[0090] The transistor 25 can be a transistor whose active layer is formed using an oxide semiconductor (hereinafter referred to as an OS transistor).

[0091] Since OS transistors have extremely low off-state current, the dynamic range of imaging can be expanded.

[0092] Furthermore, the low off-state current of the transistor 25 can significantly extend the period during which charges can be held in the charge accumulation region 64. Furthermore, leakage can be reduced.

[0093] Furthermore, OS transistors have smaller temperature dependence of electrical characteristics than transistors that use silicon in the channel formation region (hereinafter referred to as Si transistors), and can therefore be used over an extremely wide temperature range. Therefore, solid-state imaging devices and semiconductor devices that include OS transistors are suitable for use in automobiles, aircraft, spacecraft, and the like.

[0094] (Fourth embodiment) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described with reference to drawings. Note that in the drawings in this embodiment, some elements are enlarged, reduced, or omitted for clarity.

[0095] 8A and 8B are a top view and a cross-sectional view of a transistor used in a solid-state imaging element according to one embodiment of the present invention. FIG. 8A is a top view, and FIG. 8B corresponds to a cross section taken along dashed-dotted line B1-B2 in FIG. 8A. FIG. 9A corresponds to a cross section taken along dashed-dotted line B3-B4 in FIG. 8A. The dashed-dotted line B1-B2 direction may be referred to as a channel length direction, and the dashed-dotted line B3-B4 direction may be referred to as a channel width direction. FIG. 9B shows a top view of an oxide semiconductor layer 130 of the transistor. FIG. 9C corresponds to a cross section taken along dashed-dotted line A1-A2 in FIG. 9B. FIG. 9D corresponds to a cross section taken along dashed-dotted line A3-A4 in FIG. 9B.

[0096] The transistor 101 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, conductive layers 140 and 150 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the conductive layer 140, the conductive layer 150, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The insulating layer 180 may function as a planarization film, if necessary.

[0097] Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer.

[0098] The substrate 115 can be a semiconductor substrate, for example, a silicon substrate on which a transistor having single crystal silicon in a channel formation region is formed, or a silicon substrate on which an insulating layer, a wiring, a conductor that functions as a contact plug, or the like is formed.

[0099] The insulating layer 120 not only serves to prevent the diffusion of impurities from elements contained in the substrate 115, but also to supply oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, when the amount of released oxygen converted to oxygen atoms is 1.0×10 by thermal desorption spectroscopy (TDS), 19 atoms / cm 3 The film is preferably a film having a surface temperature of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower, during the TDS analysis. Furthermore, when the substrate 115 is a substrate on which other devices are formed as described above, the insulating layer 120 also functions as an interlayer insulating film. In this case, it is preferable to perform a planarization process using a CMP (Chemical Mechanical Polishing) method or the like to make the surface flat.

[0100] For example, the insulating layer 120 can be made of an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixture of these materials. Alternatively, the insulating layer 120 can be made of a stack of the above materials.

[0101] In this embodiment, the details will be mainly described for a case where the oxide semiconductor layer 130 of the transistor has a three-layer structure in which the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side.

[0102] Note that in the case where the oxide semiconductor layer 130 is a single layer, a layer corresponding to the oxide semiconductor layer 130b described in this embodiment may be used.

[0103] When the oxide semiconductor layer 130 has two layers, a stack of a layer corresponding to the oxide semiconductor layer 130a and a layer corresponding to the oxide semiconductor layer 130b described in this embodiment may be used, which are stacked in this order from the insulating layer 120. In this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b can be interchanged.

[0104] When the oxide semiconductor layer 130 has four or more layers, for example, another oxide semiconductor layer may be added to the oxide semiconductor layer 130 having a three-layer structure described in this embodiment.

[0105] For example, the oxide semiconductor layer 130b uses an oxide semiconductor having a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than the oxide semiconductor layers 130a and 130c. The electron affinity can be calculated by subtracting the energy difference (energy gap) between the bottom of the conduction band and the top of the valence band from the energy difference (ionization potential) between the vacuum level and the top of the valence band.

[0106] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c preferably contain one or more metal elements constituting the oxide semiconductor layer 130b and are formed of an oxide semiconductor whose conduction band minimum energy is closer to the vacuum level than that of the oxide semiconductor layer 130b by, for example, 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more and 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less.

[0107] In such a structure, when an electric field is applied to the conductive layer 170, a channel is formed in the oxide semiconductor layer 130b, which has the lowest energy at the bottom of the conduction band in the oxide semiconductor layer 130.

[0108] Furthermore, since the oxide semiconductor layer 130a contains one or more metal elements included in the oxide semiconductor layer 130b, interface states are less likely to be formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a than at the interface between the oxide semiconductor layer 130b and the insulating layer 120. The interface states may form a channel, which may cause a change in the threshold voltage of the transistor. Therefore, by providing the oxide semiconductor layer 130a, variations in the electrical characteristics of the transistor, such as the threshold voltage, can be reduced. Furthermore, the reliability of the transistor can be improved.

[0109] Furthermore, since the oxide semiconductor layer 130c contains one or more metal elements constituting the oxide semiconductor layer 130b, carrier scattering is less likely to occur at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c than at the interface between the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160). Therefore, by providing the oxide semiconductor layer 130c, the field-effect mobility of the transistor can be increased.

[0110] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c can be made of a material containing, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at a higher atomic ratio than the oxide semiconductor layer 130b. Specifically, the atomic ratio is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. The above elements bond strongly to oxygen and thus function to suppress the formation of oxygen vacancies in the oxide semiconductor layer. In other words, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are less likely to form oxygen vacancies than the oxide semiconductor layer 130b.

[0111] An oxide semiconductor that can be used for the oxide semiconductor layers 130a, 130b, and 130c preferably contains at least indium (In) or zinc (Zn), or preferably contains both In and Zn. Furthermore, to reduce variations in the electrical characteristics of transistors using the oxide semiconductor, the oxide semiconductor preferably contains a stabilizer in addition to the elements.

[0112] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr), as well as lanthanides such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0113] Examples of oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, and In-Nd In-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide can be used.

[0114] Here, for example, In-Ga-Zn oxide refers to an oxide containing In, Ga, and Zn as its main components. Metal elements other than In, Ga, and Zn may also be included. In this specification, a film made of In-Ga-Zn oxide is also referred to as an IGZO film.

[0115] In addition, InMO3(ZnO) m (m>0 and m is not an integer) may be used. M represents one or more metal elements selected from Ga, Y, Zr, La, Ce, or Nd. In addition, In2SnO5(ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0116] When the oxide semiconductor layers 130a, 130b, and 130c are made of an In-M-Zn oxide containing at least indium, zinc, and M (a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), the oxide semiconductor layer 130a has an atomic ratio of In:M:Zn=x1:y1:z1, the oxide semiconductor layer 130b has an atomic ratio of In:M:Zn=x2:y2:z2, and the oxide semiconductor layer 130c has an atomic ratio of In:M:Zn=x3:y3:z3. It is preferable that y1 / x1 and y3 / x3 be larger than y2 / x2. The ratios y1 / x1 and y3 / x3 are 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more larger than y2 / x2. In the oxide semiconductor layer 130b, when y2 is equal to or greater than x2, the electrical characteristics of the transistor can be stabilized. However, if y2 is three times or more of x2, the field effect mobility of the transistor decreases, and therefore, y2 is preferably less than three times x2.

[0117] In the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, excluding Zn and O, the atomic ratios of In and M are preferably less than 50 atomic % In and 50 atomic % or more M, more preferably less than 25 atomic % In and 75 atomic % or more M. In the oxide semiconductor layer 130b, the atomic ratios of In and M, excluding Zn and O, are preferably 25 atomic % or more In and less than 75 atomic % M, more preferably 34 atomic % or more In and less than 66 atomic % M.

[0118] The oxide semiconductor layer 130b preferably has a higher indium content than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c. In an oxide semiconductor, s orbitals of heavy metals mainly contribute to carrier conduction, and an increase in the In content causes more s orbitals to overlap. Therefore, an oxide having a composition in which In is higher than M has higher mobility than an oxide having an In content equal to or lower than M. Therefore, by using an oxide having a high indium content for the oxide semiconductor layer 130b, a transistor with high field-effect mobility can be realized.

[0119] The thickness of the oxide semiconductor layer 130a is 3 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 5 nm to 25 nm. The thickness of the oxide semiconductor layer 130b is 3 nm to 200 nm, preferably 10 nm to 150 nm, and more preferably 15 nm to 100 nm. The thickness of the oxide semiconductor layer 130c is 1 nm to 50 nm, preferably 2 nm to 30 nm, and more preferably 3 nm to 15 nm. The oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c.

[0120] In order to provide stable electrical characteristics to a transistor using an oxide semiconductor layer as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is 1×10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 more preferably less than 1×10 13 / cm 3 It means that it is less than.

[0121] In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Silicon contributes to the formation of impurity levels in the oxide semiconductor layer. These impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentrations in the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c and at their interfaces.

[0122] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a silicon concentration of 1×10 or more at a certain depth or in a certain region of the oxide semiconductor layer is required to be measured by SIMS (Secondary Ion Mass Spectrometry). 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 The hydrogen concentration is, for example, 2×10 or more at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19atoms / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 Less than or equal to 1×10 17 atoms / cm 3 The nitrogen concentration is, for example, 5×10 or more at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Less than or equal to 5 x 10 16 atoms / cm 3 That's all.

[0123] In addition, when the oxide semiconductor layer contains crystals, the crystallinity of the oxide semiconductor layer may be reduced if silicon or carbon is contained at a high concentration. In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, for example, the silicon concentration is set to 1×10 or less at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer. 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 For example, the carbon concentration may be 1×10 or more at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than 6 x 10 17 atoms / cm 3 It is sufficient if the above-mentioned parts are included.

[0124] Furthermore, the off-state current of a transistor using the purified oxide semiconductor layer for a channel formation region as described above is extremely small. For example, when the voltage between the source and drain is about 0.1 V, 5 V, or 10 V, the off-state current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm.

[0125] For example, the oxide semiconductor layers 130a and 130c may be made of In-Ga-Zn oxides with an atomic ratio of In:Ga:Zn=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6. The oxide semiconductor layer 130b may be made of In-Ga-Zn oxides with an atomic ratio of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or 3:1:2. The atomic ratios of the oxide semiconductor layers 130a, 130b, and 130c each include an error of plus or minus 20%.

[0126] 8B can function as a source region, a region 232 as a drain region, and a region 233 as a channel formation region. The regions 231 and 232 are in contact with the conductive layers 140 and 150, respectively. For example, if the conductive layers 140 and 150 are made of a conductive material that easily bonds with oxygen, the resistance of the regions 231 and 232 can be reduced.

[0127] Specifically, oxygen vacancies are generated in the oxide semiconductor layer 130 when the oxide semiconductor layer 130 comes into contact with the conductive layer 140 and the conductive layer 150, and due to the interaction between the oxygen vacancies and hydrogen remaining in the oxide semiconductor layer 130 or diffusing from the outside, the regions 231 and 232 become low-resistance n-type.

[0128] The conductive layer 140 acting as the source electrode layer and the conductive layer 150 acting as the drain electrode layer can be formed of a single layer or a laminate of a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of these metal materials. Typically, Ti, which is particularly susceptible to bonding with oxygen, or W, which has a high melting point, is more preferable because it allows for relatively high subsequent process temperatures. Alternatively, a laminate of the above materials with low-resistivity Cu or an alloy such as Cu-Mn may be used.

[0129] The above material has the property of extracting oxygen from the oxide semiconductor layer. Therefore, oxygen in the oxide semiconductor layer is released from a part of the oxide semiconductor layer that is in contact with the above material, forming oxygen vacancies. The oxygen vacancies combine with the small amount of hydrogen contained in the film, making the region significantly n-type. Therefore, the n-type region can function as the source or drain of a transistor.

[0130] Furthermore, when W is used for the conductive layer 140 and the conductive layer 150, nitrogen may be doped. By doping with nitrogen, the oxygen-extracting property can be weakened appropriately, and the n-type region can be prevented from expanding into the channel formation region.

[0131] Furthermore, the conductive layer 140 and the conductive layer 150 are stacked with an n-type semiconductor layer, and the n-type semiconductor layer is brought into contact with an oxide semiconductor layer, which can also prevent the n-type region from expanding into the channel formation region. As the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like can be used.

[0132] Note that the functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are used or when the direction of current flow changes during circuit operation. For this reason, the terms "source" and "drain" can be used interchangeably in this specification. Furthermore, an "electrode layer" can also be referred to as a "wiring."

[0133] Furthermore, although the conductive layer 170 is shown as being formed of two layers, the conductive layer 171 and the conductive layer 172, it may be formed of one layer or a laminate of three or more layers.

[0134] Although the conductive layer 140 and the conductive layer 150 are shown as being formed as a single layer, they may be formed as a laminate of two or more layers.

[0135] The insulating layer 160, which functions as a gate insulating film, can be an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer 160 may also be a stack of the above materials. The insulating layer 160 may also contain lanthanum (La), nitrogen, zirconium (Zr), or the like as impurities.

[0136] Next, an example of a stacked structure of the insulating layer 160 will be described. The insulating layer 160 contains, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it is preferable that the insulating layer 160 contains hafnium oxide, silicon oxide, or silicon oxynitride.

[0137] Hafnium oxide and aluminum oxide have a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, the thickness of the insulating layer 160 can be increased compared to when silicon oxide is used, thereby reducing the leakage current due to tunneling current. That is, a transistor with a low off-state current can be realized. Furthermore, hafnium oxide having a crystalline structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, hafnium oxide having a crystalline structure is preferably used to obtain a transistor with a low off-state current. Examples of the crystalline structure include a monoclinic system and a cubic system. However, one embodiment of the present invention is not limited to these.

[0138] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are preferably films that release a small amount of nitrogen oxide. When an insulating layer that releases a large amount of nitrogen oxide is in contact with an oxide semiconductor, the density of states due to nitrogen oxide may increase. The density of states due to nitrogen oxide may be formed in the energy gap of the oxide semiconductor. For the insulating layer 120 and the insulating layer 160, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film that releases a small amount of nitrogen oxide may be used.

[0139] A silicon oxynitride film that releases a small amount of nitrogen oxide is a film that releases more ammonia than nitrogen oxide in the TDS method, and typically releases ammonia at a rate of 1×10 18 / cm 3 5x10 or more 19 / cm 3 The amount of ammonia released is the amount released by heat treatment at a film surface temperature of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower.

[0140] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, a shift in the threshold voltage of the transistor can be reduced, and fluctuations in the electrical characteristics of the transistor can be reduced.

[0141] The conductive layer 170, which functions as a gate electrode layer, can be made of a conductive film of, for example, Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, or W. Alloys of the above materials or conductive nitrides of the above materials may also be used. A laminate of multiple materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials may also be used. Typical examples include tungsten, a laminate of tungsten and titanium nitride, and a laminate of tungsten and tantalum nitride. Low-resistivity alloys such as Cu or Cu-Mn, or a laminate of the above materials and alloys such as Cu or Cu-Mn may also be used. In this embodiment, the conductive layer 170 is formed using tantalum nitride for the conductive layer 171 and tungsten for the conductive layer 172.

[0142] A silicon nitride film, an aluminum nitride film, or the like containing hydrogen can be used for the insulating layer 175. A nitride insulating film also functions as a blocking film for moisture and the like, and can improve the reliability of the transistor.

[0143] Alternatively, an aluminum oxide film can be used as the insulating layer 175. An aluminum oxide film has a high blocking effect of preventing impurities such as hydrogen and moisture, and oxygen from permeating the film. Therefore, an aluminum oxide film is suitable for use as a protective film that prevents impurities such as hydrogen and moisture from entering the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents unnecessary release of oxygen from the insulating layer 120 during and after the transistor manufacturing process. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

[0144] An insulating layer 180 is preferably formed over the insulating layer 175. The insulating layer can be an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a stack of the above materials.

[0145] Here, like the insulating layer 120, the insulating layer 180 preferably contains more oxygen than the stoichiometric composition. Oxygen released from the insulating layer 180 can diffuse into the channel formation region of the oxide semiconductor layer 130 via the insulating layer 160, and thus oxygen vacancies formed in the channel formation region can be filled with oxygen. Therefore, stable electrical characteristics of the transistor can be obtained.

[0146] Although miniaturization of transistors is essential for increasing the integration density of semiconductor devices, it is known that miniaturization of transistors leads to deterioration of their electrical characteristics, and in particular, the on-state current decreases significantly as the channel width decreases.

[0147] Furthermore, in the transistor of one embodiment of the present invention, the gate electrode layer (conductive layer 170) is formed so as to electrically surround the oxide semiconductor layer 130 in the channel width direction as described above, and therefore, a gate electric field is applied from the side in addition to the gate electric field from the vertical direction to the oxide semiconductor layer 130. In other words, the gate electric field is applied to the entire channel formation layer, which increases the effective channel width and further increases the on-state current.

[0148] In a transistor having a two-layer or three-layer oxide semiconductor layer 130 according to one embodiment of the present invention, the oxide semiconductor layer 130b, in which a channel is formed, is formed over the oxide semiconductor layer 130a, which has an effect of making it difficult for interface states to be formed. In a transistor having a three-layer oxide semiconductor layer 130 according to one embodiment of the present invention, the oxide semiconductor layer 130b is positioned as the middle layer of the three-layer structure, which also has an effect of eliminating the influence of impurities mixed in from above and below. Therefore, in addition to the above-described improvement in the on-state current of the transistor, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Therefore, power consumption can be reduced. Furthermore, the stabilized threshold voltage of the transistor can improve the long-term reliability of the semiconductor device. Furthermore, the transistor according to one embodiment of the present invention can be suppressed from deteriorating in electrical characteristics due to miniaturization, and therefore can be considered suitable for forming a highly integrated semiconductor device.

[0149] The various films described in this embodiment, such as the metal film, semiconductor film, and inorganic insulating film, can be formed typically by sputtering or plasma CVD, but may also be formed by other methods, such as thermal CVD, such as MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (Atomic Layer Deposition).

[0150] The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

[0151] In addition, in the thermal CVD method, the source gas and the oxidizing agent may be fed into a chamber simultaneously, the chamber may be kept at atmospheric pressure or reduced pressure, and the reaction may be carried out near or on the substrate, resulting in deposition on the substrate, thereby forming a film.

[0152] In the ALD method, a chamber is maintained at atmospheric or reduced pressure, and source gases for the reaction are sequentially introduced into the chamber. This gas introduction sequence may be repeated to form a film. For example, two or more source gases are sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). An inert gas (e.g., argon or nitrogen) is introduced simultaneously with or after the first source gas to prevent mixing of the multiple source gases, followed by the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the second source gas is introduced. The first source gas adsorbs onto the substrate surface to form a first layer, which then reacts with the second source gas introduced later, forming a thin film. Repeating this gas introduction sequence multiple times until the desired thickness is achieved allows for the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness control, making this method suitable for fabricating miniaturized FETs.

[0153] Thermal CVD methods such as MOCVD and ALD can form various films, including metal films, semiconductor films, and inorganic insulating films, as disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is Zn(CH3)2. Furthermore, the combinations are not limited to these, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc.

[0154] For example, when forming a hafnium oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide solution or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH)), and ozone (O3) as an oxidizer. The chemical formula for tetrakisdimethylamidohafnium is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethylmethylamido)hafnium.

[0155] For example, when forming an aluminum oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)), and H2O as an oxidizer. The chemical formula for trimethylaluminum is Al(CH3)3. Other material liquids include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0156] For example, when forming a silicon oxide film using a film formation device that uses ALD, hexachlorodisilane is adsorbed onto the surface to be formed, the chlorine contained in the adsorbed material is removed, and radicals of oxidizing gases (O2, nitrous oxide) are supplied to react with the adsorbed material.

[0157] For example, when forming a tungsten film using an ALD deposition system, WF6 gas and B2H6 gas are introduced in sequence and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced in sequence and repeatedly to form the tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0158] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film formation system using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. These gases may also be mixed to form mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers. Note that while HO gas obtained by bubbling water with an inert gas such as Ar may be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Furthermore, In(CH3)3 gas may be replaced with In(C2H5)3 gas. Furthermore, Ga(CH3)3 gas may be replaced with Ga(C2H5)3 gas. Furthermore, Zn(CH3)2 gas may also be used.

[0159] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0160] (Embodiment 5) In this embodiment, an example of combining an AI (Artificial Intelligence) system with the TOF camera shown in FIG. 1 will be described with reference to FIGS. 10, 11, and 12. FIG.

[0161] FIG. 10A shows an example of a flow for constructing a learning model in a distance estimation device, specifically in an estimation unit.

[0162] First, to obtain training data, depth image data is acquired using a TOF camera (Step 1: S1).

[0163] Then, distance image data with a large number of integrations and distance image data with a small number of integrations are collected (Step 2: S2).

[0164] Then, the distance image data with a large number of integration times is used as training data to build a learning model in the estimation unit (Step 3: S3).

[0165] A learning model learned in accordance with the flow shown in FIG. 10A is constructed in advance in the estimation unit, and desired range image data is obtained in accordance with the flow shown in FIG. 10B.

[0166] First, the TOF camera is used to acquire range image data with a small number of integrations (Step 4: S4).

[0167] An estimated value is then obtained using a pre-constructed learning model (Step 5: S5). Specifically, a probability is generated for each distance level (also called a measurement section) for each pixel of the input image data. For example, a probability map can be created for each of multiple distance levels, such as a 20% probability for distances between 1m and 45m, a 70% probability for distances between 45m and 90m, and a 10% probability for distances between 90m and 135m.

[0168] Finally, based on the learning results, the range image data with fewer integrations is processed (step 6: S6). As the output result, the data with the highest probability is selected, and ultimately range image data equivalent to or superior to the range image data with more integrations can be obtained.

[0169] FIG. 11 is a block diagram showing the data processing procedure in step 6.

[0170] In order to improve resolution, conventional TOF cameras may repeat measurements many times, accumulating the data and performing average processing. That is, they attempt to reduce noise by increasing the number of accumulations and averaging. In this embodiment, data on the amount of charge accumulated for each light-receiving period based on carriers generated from the light-receiving region of the solid-state imaging element of the TOF camera is used. This data is called range image data (input data) with a small number of accumulations. This range image data with a small number of accumulations is obtained by the image generation unit.

[0171] Further, preprocessing may be performed on depth image data with a small number of integrations to make estimation easier in the estimation unit.

[0172] As shown in Fig. 11, this input data is stored in the input unit 100, image processing is performed in the estimation unit 102, and a learning model that will achieve the highest accuracy is used in the output unit 103. Furthermore, it is preferable to use a learning model that will reduce noise.

[0173] In this embodiment, a U-net is used as a learning model, and discrimination is performed based on the learned content. In this case, the estimation unit 102 has a U-shaped shortcut structure (nested structure) similar to the U-net. The estimation unit 102 creates a feature map while reducing the number of elements using a convolutional layer, a pooling layer, and an activation layer. Then, the input data 110 is downsampled multiple times, and then upsampled multiple times to obtain a depth map.

[0174] Fig. 12 is a schematic diagram of the U-Net network architecture. While Fig. 12 shows an example of a five-stage learning process, there is no particular limitation, and two-stage, three-stage, four-stage, six-stage or more learning processes may be performed as needed.

[0175] A feature amount (or a region of interest) of input data 110 is extracted, or so-called convolution is performed, to obtain a plurality of depth maps 111.

[0176] It is also possible to estimate the object in the measurement space from the feature values ​​(or region of interest) of the input data 110 or the depth map 111. The shape of the object in the measurement space is estimated from the feature values ​​extracted using a learning model, and if there is a high probability of identifying the object, the shape of the object can be estimated and the relative value of the distance can be predicted. This can also improve the accuracy of the distance image.

[0177] It is also possible to use a TOF camera with a lower resolution than the performance of the TOF camera used for training. Even if the TOF camera has a lower resolution, if the training data used in the training model is obtained with a high-precision TOF camera, the output results can be made to approximate the results obtained when a high-precision TOF camera is used. Furthermore, better output results can be obtained by performing image processing on the training data to remove noise.

[0178] Specifically, a high-precision TOF camera refers not only to a camera with a large number of pixels but also to a camera with a large light-receiving area per pixel. Therefore, even if a TOF camera has a small light-receiving area per pixel, by using this embodiment, it is possible to obtain a high-precision depth map 112 that is an output result equivalent to or better than that of a TOF camera with a large light-receiving area per pixel.

[0179] Furthermore, this embodiment is useful not only for still images but also for moving images. Since data with a small number of integrations can be used as input data, data can be acquired at a high frame frequency, making it suitable for moving images.

[0180] (Embodiment 6) An example of an electronic device including a distance estimation device according to an embodiment of the present invention or an imaging device according to an embodiment of the present invention will be described with reference to FIG.

[0181] Examples of electronic devices using the distance estimation device according to one aspect of the present invention or the imaging device according to one aspect of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, DVDs (Digital Versatile Examples of such devices include image playback devices that play back still images or videos stored on recording media such as CDs, portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, mobile phones, car phones, portable game consoles, tablet terminals, large game consoles such as pachinko machines, calculators, portable information terminals (also referred to as "mobile information terminals"), electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids.

[0182] Mobile bodies propelled by electric motors using power from power storage devices are also included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid vehicles (HVs) that combine an internal combustion engine with an electric motor, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0183] The electronic device may have sensors (including those that can measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), etc.

[0184] 13A to 13F show an example of an electronic device.

[0185] 13A shows an example of a wristwatch-type mobile information terminal. The mobile information terminal 6100 includes a housing 6101, a display unit 6102, a band 6103, operation buttons 6105, and the like. The mobile information terminal 6100 also includes a secondary battery and an imaging device or electronic component according to one embodiment of the present invention. For example, a distance estimation device according to one embodiment of the present invention or an imaging device according to one embodiment of the present invention can be installed in part of the wristwatch-type mobile information terminal, thereby incorporating a TOF camera.

[0186] 13B shows an example of a mobile phone. A mobile information terminal 6200 includes a display portion 6202 incorporated in a housing 6201, operation buttons 6203, a speaker 6204, a microphone 6205, and the like.

[0187] The portable information terminal 6200 also includes a fingerprint sensor 6209 in an area overlapping with the display portion 6202. The fingerprint sensor 6209 may be an organic optical sensor. Since fingerprints are different for each person, personal authentication can be performed by acquiring a fingerprint pattern with the fingerprint sensor 6209. Light emitted from the display portion 6202 can be used as a light source for acquiring the fingerprint pattern with the fingerprint sensor 6209.

[0188] The portable information terminal 6200 also includes a secondary battery and an imaging device or electronic component according to an embodiment of the present invention. For example, an imaging device according to an embodiment of the present invention can be installed in a part of the portable information terminal 6200 to incorporate a TOF camera. The TOF camera can be used to acquire information corresponding to the user's appearance (including the contours of the face, etc.) and perform personal authentication.

[0189] 13C shows an example of a cleaning robot. The cleaning robot 6300 has a display unit 6302 arranged on the top surface of a housing 6301, a plurality of cameras 6303 arranged on the side, a brush 6304, an operation button 6305, various sensors, and the like. Although not shown, the cleaning robot 6300 is provided with tires, a suction port, and the like. The cleaning robot 6300 can move by itself, detect dust 6310, and suck up the dust from a suction port arranged on the bottom surface.

[0190] For example, the cleaning robot 6300 can analyze an image captured by the camera 6303 and determine whether or not there is an obstacle such as a wall, furniture, or a step. Furthermore, if an object that may become tangled in the brush 6304, such as a wire, is detected through image analysis, the cleaning robot 6300 can stop rotation of the brush 6304. The camera 6303 may use imaging devices of various types. By using the distance estimation device according to one embodiment of the present invention or the imaging device according to one embodiment of the present invention as one of the cameras 6303, distance information can be obtained from imaged information, and malfunction of the cleaning robot 6300 can be reduced.

[0191] Fig. 13D shows an example of a robot. The robot 6400 shown in Fig. 13D includes a computing device 6409, an illuminance sensor 6401, a microphone 6402, an upper camera 6403, a speaker 6404, a display unit 6405, a lower camera 6406, an obstacle sensor 6407, and a movement mechanism 6408.

[0192] The microphone 6402 has a function of detecting the user's voice, environmental sounds, etc. The speaker 6404 has a function of emitting sound. The robot 6400 can communicate with the user using the microphone 6402 and the speaker 6404.

[0193] The display unit 6405 has a function of displaying various information. The robot 6400 can display information desired by the user on the display unit 6405. The display unit 6405 may be equipped with a touch panel. The display unit 6405 may also be a detachable information terminal, which can be installed in a fixed position on the robot 6400 to enable charging and data transfer.

[0194] The upper camera 6403 and the lower camera 6406 have a function of capturing images of the surroundings of the robot 6400. A variety of types of imaging devices may be used as the upper camera 6403 and the lower camera 6406. By using a distance estimation device according to an embodiment of the present invention or an imaging device according to an embodiment of the present invention as one of the upper camera 6403 and the lower camera 6406, distance information can be obtained from captured image information, thereby reducing malfunctions during movement of the robot 6400. Furthermore, the obstacle sensor 6407 can detect the presence or absence of an obstacle in the direction of travel of the robot 6400 when the robot 6400 moves forward using the movement mechanism 6408. The robot 6400 can recognize the surrounding environment and move safely using the upper camera 6403, the lower camera 6406, and the obstacle sensor 6407.

[0195] Fig. 13E shows an example of an aircraft. Aircraft 6500 shown in Fig. 13E has propeller 6501, camera 6502, battery 6503, etc., and has the function of flying autonomously.

[0196] For example, image data captured by the camera 6502 is stored in the electronic component 6504. The electronic component 6504 can analyze the image data and detect the presence or absence of an obstacle when moving. Imaging devices of multiple types may be used as the camera 6502. By using an imaging device according to one embodiment of the present invention as one of the cameras 6502, distance information can be obtained from captured information, and malfunctions of the flying object 6500 when it moves can be reduced.

[0197] 13F illustrates an example of an automobile. The automobile 7160 includes an engine, tires, brakes, a steering system, and multiple cameras. By using an imaging device according to an embodiment of the present invention as one or more of the multiple cameras installed on the automobile 7160, distance information between the automobile and an object in the external world can be obtained from captured image information, and the traveling direction of the automobile 7160 or the positional relationship between the automobile 7160 and objects around the automobile 7160 can be recognized. By using a distance estimation device according to an embodiment of the present invention or an imaging device according to an embodiment of the present invention in the automobile 7160, the autopilot function of the automobile 7160 can be assisted.

[0198] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with the structures, configurations, methods, and the like described in other embodiments. [Explanation of symbols]

[0199] 11: illumination unit, 12: sensor unit, 13: signal generation unit, 14: correlation and evaluation unit, 21: transistor, 22: transistor, 23: transistor, 24: transistor, 25: transistor, 31: transistor, 32: transistor, 33: transistor, 41: capacitance, 42: capacitance, 43: capacitance, 44: transistor, 45: dotted arrow, 46: dotted arrow, 60: p-type region, 61: p- region, 62: n-type surface buried region, 63: p+ region, 64: charge storage region, 65: charge Discharge region, 66: p-well region, 70: insulating layer, 71: transfer gate pair, 72: transfer gate pair, 73: transfer gate pair, 74: transfer gate pair, 75: insulating layer, 76: connection electrode, 90: light receiving region, 91: light shielding plate, 100: input section, 101: transistor, 102: estimation section, 103: output section, 110: input data, 111: depth map, 112: high-precision depth map, 115: substrate, 120: insulating layer, 130: oxide semiconductor layer, 130a: oxide semiconductor layer, 130b: oxide semiconductor layer, 130c: Oxide semiconductor layer, 140: conductive layer, 150: conductive layer, 160: insulating layer, 170: conductive layer, 171: conductive layer, 172: conductive layer, 175: insulating layer, 180: insulating layer, 231: region, 232: region, 233: region, 6100: mobile information terminal, 6101: housing, 6102: display unit, 6103: band, 6105: operation button, 6200: mobile information terminal, 6201: housing, 6202: display unit, 6203: operation button, 6204: speaker, 6205: microphone, 6209: fingerprint sensor, 6300: sweeper Removal robot, 6301: housing, 6302: display unit, 6303: camera, 6304: brush, 6305: operation button, 6310: dust, 6400: robot, 6401: illuminance sensor, 6402: microphone, 6403: upper camera, 6404: speaker, 6405: display unit, 6406: lower camera, 6407: obstacle sensor, 6408: movement mechanism, 6409: computing unit, 6500: flying object, 6501: propeller, 6502: camera, 6503: battery, 6504: electronic component, 7160: automobile

Claims

1. A photodiode; first to tenth transistors; first to third capacitances; a cathode of the photodiode is electrically connected to one of a source or a drain of the first transistor, one of a source or a drain of the second transistor, one of a source or a drain of the third transistor, and one of a source or a drain of the fourth transistor; the other of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, one of the source and the drain of the fifth transistor, and a gate of the sixth transistor; the other of the source and the drain of the second transistor is electrically connected to one electrode of the second capacitor, one of the source and the drain of the seventh transistor, and the gate of the eighth transistor; the other of the source and the drain of the third transistor is electrically connected to one electrode of the third capacitor, one of the source and the drain of the ninth transistor, and a gate of the tenth transistor; a channel formation region of each of the first to fourth transistors, the sixth transistor, the eighth transistor, and the tenth transistor includes silicon; an imaging device in which channel formation regions of the fifth transistor, the seventh transistor, and the ninth transistor each include an oxide semiconductor; a silicon wafer having the silicon and having a region in which the light receiving region of the photodiode is embedded; a first insulating layer having an area in contact with the upper surface of the silicon wafer and overlapping the light receiving area; a second insulating layer having a region located above the first insulating layer and not overlapping the light receiving region; a first oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the fifth transistor.

2. In claim 1, a second oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and having a channel formation region of the seventh transistor; a third oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the ninth transistor.

3. In claim 1 or claim 2, The imaging device, wherein the oxide semiconductor includes indium oxide.

4. In any one of claims 1 to 3, The first insulating layer is a light-transmitting layer.

5. In any one of claims 1 to 4, The imaging device, wherein the second insulating layer comprises oxygen.

6. In any one of claims 1 to 5, an insulating layer including a first insulating layer and a second insulating layer, the first insulating layer including a first region functioning as a gate insulating film for each of the first to fourth transistors, the sixth transistor, the eighth transistor, and the tenth transistor;

7. In any one of claims 1 to 6, a third insulating layer having a region in contact with the top surface of the first insulating layer; the third insulating layer has a region overlapping the light receiving region and the second insulating layer, The third insulating layer is a light-transmitting layer.

8. An imaging device comprising: an imaging device according to any one of claims 1 to 7; and an estimation unit; The estimation unit is a distance estimation device having a function of estimating the distance between the imaging device and an object based on information obtained by the imaging device.

9. In claim 8, The estimation unit is a distance estimation device having a function of estimating the distance using a pre-constructed learning model.

Images