Neuromorphic computing device and operating method thereof

Abstract

To provide a neuromorphic computing device that can be connected to both excitatory and inhibitory synapses and adjust a firing rate and an operating method thereof.SOLUTION: Each of a plurality of artificial neurons 141 connected to a synapse array, may include: a ferroelectric transistor FeFET having a gate connected to a first node N1, and connected between a power terminal configured to receive a power supply voltage VDD and a second node N2 configured to output an output spike; a first input transistor M1exc having a gate configured to receive a first input spike, and connected between a first input power terminal configured to receive a first input power supply voltage Vex and the first node; a second input transistor M1inh having a gate configured to receive a second input spike, and connected between a second input power terminal configured to receive a second input power supply voltage Vin and the first node; an adjustment transistor M2 having a gate receiving a Vadj adjustment voltage and connected between the second node and ground terminal; and a reset transistor M3 having a gate receiving a reset voltage Vrst, and connected between the first node and ground terminal.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a neuromorphic computing device and a method of operating the same. [Background technology]

[0002] A spiking neural network (SNN) is a type of artificial neural network modeled on biological neural networks. This network operates by mimicking the way biological neurons fire (spiking). Each neuron generates an electrical signal at regular intervals, and these signals are transmitted through connections with other neurons. SNNs have several key features that distinguish them from conventional artificial neural networks. First, SNNs operate by taking into account temporal information. The firing time and interval of neurons play an important role in information processing. Second, SNNs use event-driven processing, which activates only when an event occurs. This allows only activated neurons to participate in calculations, thereby efficiently using power and computing resources. Third, the strength of synapses in SNNs can change over time. This allows for effective adjustment of synaptic strength to improve learning and memory functions. Fourth, SNNs integrate input signals over time, firing neurons only when a threshold is exceeded. This allows them to process changes in input patterns and their temporal characteristics. SNNs can be applied to a variety of application fields, such as sensor data processing, pattern recognition, and temporal information processing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 10-2018-0133061 Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the present invention to provide a novel neuromorphic computing device and method of operation thereof.

[0005] An object of the present invention is to provide a neuromorphic computing device that can be connected to excitatory synapses and inhibitory synapses, and a method for operating the same.

[0006] It is an object of the present invention to provide a neuromorphic computing device that regulates firing rates and a method for operating the same. [Means for solving the problem]

[0007] A neuromorphic computing device according to an embodiment of the present invention includes a plurality of artificial neurons connected to a synapse array, each of the plurality of artificial neurons including: a ferroelectric transistor having a gate connected to a first node and connected between a power supply terminal receiving a power supply voltage and a second node outputting an output spike; a first input transistor having a gate receiving a first input spike and connected between a first input power supply terminal receiving a first input power supply voltage and the first node; a second input transistor having a gate receiving a second input spike and connected between a second input power supply terminal receiving a second input power supply voltage and the first node; an adjustment transistor having a gate receiving an adjustment voltage and connected between the second node and ground; and a reset transistor having a gate receiving a reset voltage and connected between the first node and the ground.

[0008] According to another embodiment of the present invention, a neuromorphic computing device includes a synapse array in which excitatory synapses, each having a first ferroelectric transistor connected between an excitatory bit line and an excitatory source line, and inhibitory synapses, each having a second ferroelectric transistor connected between an inhibitory bit line and an inhibitory source line, are alternately arranged; a presynaptic neuron circuit that provides input spikes corresponding to word lines connected to gates of the first ferroelectric transistor and the second ferroelectric transistor; a bit line driver that provides a first bit line voltage to the excitatory bit line and a second bit line voltage to the inhibitory bit line; and an artificial neuron that receives an excitatory input spike from any of the excitatory source lines and an inhibitory input spike from any of the inhibitory source lines, and outputs an output spike by performing a leaky integration-and-fire (LIF) operation.

[0009] A method for operating a neuromorphic computing device having an artificial neuron connected to an excitatory synapse and an inhibitory synapse according to an embodiment of the present invention may include training input spikes through the excitatory synapse and the inhibitory synapse, adjusting the firing rate of the artificial neuron, and training output spikes of the artificial neuron using the adjusted firing rate.

[0010] According to another embodiment of the present invention, a neuromorphic computing device includes a first ferroelectric transistor connected between an excitatory bit line and an excitatory source line and disposed in each of stacked layers; a second ferroelectric transistor connected between an inhibitory bit line and an inhibitory source line and disposed in each of the stacked layers; a bit line driver that provides bit line voltages corresponding to the excitatory bit line and the inhibitory bit line; and an artificial neuron connected to the excitatory source line and the inhibitory source line, wherein the artificial neuron receives a first input spike via the excitatory source line and a second input spike received via the inhibitory source line and performs a leaky integration-and-fire (LIF) operation to output an output spike. [Effects of the Invention]

[0011] A neuromorphic computing device and an operating method thereof according to an embodiment of the present invention can increase model flexibility by enabling excitatory synapses and inhibitory synapses to be connected.

[0012] A neuromorphic computing device and an operating method thereof according to an embodiment of the present invention can increase model flexibility by improving the firing rate adjustment method.

[0013] The neuromorphic computing device and its operating method according to the present invention can reduce chip area by 3D stacking, and can increase model flexibility by flexible neuron configuration. [Brief explanation of the drawings]

[0014] The drawings attached below are intended to aid in understanding the present embodiments and, together with the detailed description, provide the embodiments. [Figure 1]1 is a diagram illustrating the function of a general artificial neuron. [Figure 2] 1 is a diagram illustrating an example of a spiking neuron of a general SNN. [Figure 3] 1 is a diagram illustrating an example of a general FeFET-based spiking neuron circuit. [Figure 4] 1 is a diagram illustrating an exemplary neuromorphic computing device according to an embodiment of the present invention. [Figure 5] 1 is a diagram illustrating an example of an artificial neuron according to an embodiment of the present invention. [Figure 6] 1 is a diagram illustrating an example of a spike propagation process for each layer in a general SNN. [Figure 7] 1 is a diagram illustrating an example of timing for obtaining output spikes by training input spikes in an SNN. [Figure 8a] 1 is a diagram illustrating an example of a firing rate control method based on power supply voltage control and a firing rate control method according to an embodiment of the present invention; [Figure 8b] 1 is a diagram illustrating an example of a firing rate control method based on power supply voltage control and a firing rate control method according to an embodiment of the present invention; [Figure 9] 10 is a diagram illustrating an exemplary neuromorphic computing device according to another embodiment of the present invention. [Figure 10] 10 is a diagram for explaining flexible artificial neuron configuration for each layer shown in FIG. 9. [Figure 11] 1 is a diagram illustrating an example of flexible artificial neuron configuration for each stacked layer. [Figure 12] 1 is a flowchart illustrating an exemplary operation of a neuromorphic computing device according to an embodiment of the present invention. [Figure 13] 1 is a simplified diagram of a spiking neural network according to an embodiment of the present invention. [Figure 14] 1 is a diagram illustrating an example of an electronic device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0015] The present invention will be described below in detail and clearly with reference to the accompanying drawings so that those skilled in the art can easily carry out the invention.

[0016] Neuromorphic computing is a computer system that mimics the operating principles of neurons and synapses in the human brain. It typically uses an artificial neural network (ANN) to process and store information. The brain has the ability to process large amounts of information simultaneously. Neuromorphic computing mimics this parallel processing ability. The brain can handle highly complex tasks with efficient energy usage. Neuromorphic computing, designed to mimic this energy efficiency, can save energy compared to traditional computing. Neuromorphic computing creates a learning and flexible system that can process a variety of tasks without being limited to specific tasks. Neuromorphic computing has attracted much attention in the fields of machine learning and artificial intelligence and can be applied to various applications such as pattern recognition, speech recognition, image processing, and autonomous driving.

[0017] Neuromorphic computing mainly includes the Analog MAC (Multiply-and-Accumulate) method, which is similar to the NPU (Neural Processing Unit), and the SNN (Spiking Neural Network) method, which is closer to the brain's operation. The main components of the SNN include artificial synapses and artificial neurons. Artificial synapses and artificial neurons can be realized with various memory devices.

[0018] The present invention discloses an artificial neuron based on FeFET (Ferroelectric Field Effect Transistor) that can be applied to realizing SNN. In particular, the present invention discloses an architecture based on FeFET synapse arrays and an architecture based on FeMBCFET (Ferroelectric Multi-Bridge Channel Field Effect Transistor) synapses that can be stacked in three dimensions.

[0019] Figure 1 explains the function of a typical artificial neuron. An artificial neuron accepts an input signal, multiplies it by a weight, and then transforms the result through an activation function to generate an output. In this way, an artificial neuron models and learns complex patterns and relationships. For example, the function of a spiking neuron in an SSN includes an inference process and a learning process. The inference process accumulates inputs and fires when the inputs exceed a reference value, thereby outputting a spike. The learning process updates the weight of the corresponding synapse according to the time difference between the input spike and the output spike.

[0020] Generally, an artificial neuron is an electronic device designed to mimic the behavior of a neuron. To improve computational performance and integration, most neuron devices mimic the simplest model, Leaky Integration-and-Fire (LIF) behavior. LIF behavior gradually integrates signals in response to pulse input, then leaks signals again when there is no input. During operation, if the signal exceeds a threshold voltage, a strong spike signal is fired.

[0021] Ferroelectrics are materials that have been widely used in memory devices due to their two polarization states. Ferroelectrics do not simply have two polarization states, but rather partial polarization occurs depending on the accumulation of input signals, making them suitable for neuron device applications using the accumulation of input signals. Neurons have not only excitatory connections that accumulate membrane potential in response to input, but also inhibitory connections that attenuate membrane potential and suppress firing. When neurons are connected to form a neural network, the inhibitory connections make it easier to control neuron behavior, greatly improving the overall operational efficiency of the neural network.

[0022] Figure 2 is an example diagram of a spiking neuron in a general SNN. The general operating principle of an SNN is as follows: When a synapse receives an action potential, also known as a spike, from a pre-synaptic neuron, it emits a post-synaptic potential (PSP). The PSP in turn stimulates the membrane potential of the post-synaptic spiking neuron. The neuronal membrane potential exhibits a temporal evolution that integrates the PSP. When the membrane potential exceeds a threshold voltage, the post-synaptic neuron is activated, i.e., it fires an output spike. Considering a general LIF neuron, the membrane potential u is determined by the following equation:

number

[0023] Figure 3 is an example diagram of a typical FeFET-based spiking neuron circuit. Referring to Figure 3, the LIF neuron is implemented with one FeFET and three transistors (M1 to M3). The additional transistors (M4 to M6) support adaptation. As shown in Figure 3, whenever an input spike is input to transistor M1, a power supply voltage (VDD) is applied to the gate of the FeFET neuron. The ferromagnetic material of the FeFET is polycrystalline and consists of multiple domains. When an input spike is input, the polarization state of some of the ferromagnetic domains changes. This lowers the threshold voltage of the FeFET neuron. When the threshold voltage is sufficiently low and the FeFET neuron is turned on, it outputs a spike in the form of a voltage through load transistor M2. The spike output fires, and transistor M3 restores the polarization of the FeFET neuron, raising the threshold voltage.

[0024] An input spike (e.g., PSP) is applied to PMOS transistor M1. Initially, the node voltages (V0) and (V1) are all 0V. The application of the input spike increases the node voltage (V0), applying a negative coercive voltage pulse to the gate of the FeFET. With successive pulses, the FeFET reaches a high threshold voltage (V T ) state to the lower threshold voltage (V T ) state, and the drain current (I D ) increases, causing an output spike and an increase in the node voltage (V1). When the output spike is generated, a reset signal is applied to transistor M3. During the interval between spikes, transistor M1 is turned off, causing the node voltage (V0) to fall back to 0V. This creates a negative gate-source voltage (VGS) across the FeFET, reversing the polarization and causing the FeFET to have a high threshold voltage (V T ) state.

[0025] Additionally, additional transistors (M4-M6) implement a bioinspired adaptive mechanism that regulates the activity of the artificial neuron, slowing its firing rate after every output spike. P ) is the parasitic capacitor of the corresponding node. During every output spike event, when the node voltage (V1) becomes high, the transistor (M4) turns on, which in turn increases the node voltage (V2). The discharge rate of the node voltage (V2) can be controlled by adding an additional transistor. As the node voltage (V2) increases, the transistor (M5) gradually turns on with each output spike. As a result, the discharge rate of the node voltage (V0) increases.

[0026] A neuromorphic computing device according to an embodiment of the present invention may include a FeFET / FeMBCFET synapse array, an artificial neuron receiving an excitatory synapse and an inhibitory synapse, or a layer buffer for flexible neuron configuration. The neuromorphic computing device of the present invention may increase model flexibility by enabling connection of excitatory synapses and inhibitory synapses. The neuromorphic computing device of the present invention may also increase model flexibility by improving a neuron firing rate adjustment method. The neuromorphic computing device of the present invention may also reduce chip area by 3D stacking. The neuromorphic computing device of the present invention may also increase model flexibility by flexible neuron configuration.

[0027] 4 is a diagram illustrating a neuromorphic computing device 100 according to an embodiment of the present invention. Referring to FIG. 4, the neuromorphic computing device 100 may include a synapse array 110, a presynaptic neuron circuit 120, a bit line driver 130, and a spiking neuron circuit 140.

[0028] The synapse array may include at least one first string 111 (excitatory synapse) and at least one second string 112 (inhibitory synapse). The first string 111 may include a plurality of first ferroelectric transistors connected to an excitatory bit line BLe and an excitatory source line SLe. Each of the first ferroelectric transistors may include a gate connected to a word line (WL1 to WL8). Each of the word lines (WL1 to WL8) may transmit an input spike. While the number of word lines shown in FIG. 4 is eight, the present invention is not limited thereto. The second string 112 may include a plurality of second ferroelectric transistors connected to an inhibitory bit line BLi and an inhibitory source line SLe. Each of the second ferroelectric transistors may include a gate connected to a word line (WL1 to WL8). Each of the word lines (WL1 to WL8) may transmit an input spike.

[0029] The pre-synaptic neuron circuit 120 can be implemented to generate input spikes corresponding to data and transmit the input spikes to each of the corresponding word lines (WL1-WL8).

[0030] The bit line driver 130 may be implemented to provide corresponding bit line voltages on the excitatory bit line BLe and the inhibitory bit line BLi. In some embodiments, the bit line voltages may be different or the same.

[0031] The spiking neuron circuit 140 may include a plurality of artificial neurons, each of which may be implemented to receive an excitatory signal from an excitatory source line SLe coupled to a first string, an inhibitory signal from an inhibitory source line SLi coupled to a second string, and output an output spike by performing an LIF operation on the excitatory signal and the inhibitory signal.

[0032] A neuromorphic computing device 100 according to an embodiment of the present invention may include an FeFET-based synapse array 110 and artificial neurons. Here, the FeFET-based synapse array 110 arranges excitatory synapse columns (first string) and inhibitory synapse columns (second string) in pairs, and a corresponding artificial neuron processes each pair.

[0033] 5 is a diagram illustrating an example of an artificial neuron 141 according to an embodiment of the present invention. Referring to FIG. 5, the artificial neuron 141 may include a first input transistor M1exc, a second input transistor M1inh, an adjustment transistor M2, a reset transistor M3, and a ferroelectric transistor FeFET.

[0034] The first input transistor M1exc may be connected between the first node N1 and a first power supply terminal. The first power supply terminal may receive a first input power supply voltage Vex. Here, the first input power supply voltage Vex may be greater than OV. The first input transistor M1exc may include a gate that receives an excitatory signal. In this embodiment, the first input transistor M1exc may be implemented as a P-type transistor.

[0035] The second input transistor M1inh may be connected between the first node N1 and a second power supply terminal. The second power supply terminal may receive a second input power supply voltage Vin. Here, the second input power supply voltage Vin may be less than OV. The second input transistor M1inh may include a gate that receives an inhibitory signal. In this embodiment, the second input transistor M1inh may be implemented as an N-type transistor.

[0036] The adjustment transistor M2 may be coupled between the second node N2 and the ground terminal GND, and may include a gate receiving the adjustment voltage Vadj.

[0037] The reset transistor M3 may be coupled between the first node N1 and the ground terminal GND, and may include a gate receiving a reset voltage Vrst.

[0038] The ferroelectric transistor FeFET may be coupled between a power supply terminal VDD and a second node N2. The ferroelectric transistor FeFET may include a gate coupled to a first node N1 that receives a gate voltage Vg. In an embodiment, the ferroelectric transistor FeFET may be implemented in a common source / well structure.

[0039] 5 is comprised of transistors receiving an excitatory signal from an excitatory synapse and an inhibitory signal from an inhibitory synapse. However, the present invention is not limited thereto. It should be understood that the artificial neuron of the present invention can also be realized with a single transistor receiving both the excitatory and inhibitory signals.

[0040] Generally, an excitatory synapse increases the membrane voltage of a neuron to promote firing, while an inhibitory synapse decreases the membrane voltage of a neuron to inhibit firing. Thus, in the artificial neuron 141, the PMOS transistor to which the excitatory synapse is input can be connected to a Vex power supply with a positive voltage, and the NMOS transistor to which the inhibitory synapse is input can be connected to a Vin power supply with a negative voltage. In this case, a spike from the excitatory synapse lowers the threshold voltage of the ferroelectric transistor (FeFET), and a spike from the inhibitory synapse raises the threshold voltage of the ferroelectric transistor (FeFET). When the threshold voltage is lower than a reference value, the ferroelectric transistor fires (i.e., outputs an output spike), and when the threshold voltage is higher than the reference value, the ferroelectric transistor does not fire. The artificial neuron 141 can process excitatory and inhibitory synapses in this manner.

[0041] At this time, the polarization change due to the spike is the result of the write operation of the FeFET neuron. Conventional FeFET neurons adjust their firing rate by adjusting the power supply voltage VDD. The artificial neuron of the present invention can lower the write voltage by using a common source / well structure to make the channel voltage the same as the source voltage. The artificial neuron of the present invention can adjust its firing rate using the input power supply voltage (Vex, Vin), the gate voltage Vadj of the adjustment transistor M2, or the gate voltage Vrst of the reset transistor M3.

[0042] The neuromorphic computing device 100 of the present invention can be realized so that the adjustment means for the firing rate of the artificial neuron can be varied in various ways, separate from the power supply voltage VDD. Meanwhile, the neuromorphic computing device 100 of the present invention can also adjust the firing rate using the first and second input power supply voltages, the gate voltage of the adjustment transistor, or the gate voltage of the reset transistor while linking with the power supply voltage VDD.

[0043] 6 is a diagram illustrating an example of a spike transmission process for each layer in a typical SNN. A neuromorphic computing device 100 encodes data into spikes using a spike encoder 101, trains the input spikes using a synapse array, receives the trained input spikes and outputs output spikes using artificial neurons, repeats the output spike training, and outputs data corresponding to the output spikes using a spike decoder 102.

[0044] In general, the firing rate of artificial neurons is a very important regulatory factor in SNNs. SNNs rely on the firing of artificial neurons in each layer. An artificial neuron receives multiple spikes as input and outputs a single spike. This results in an overall lower frequency of output spikes than input spikes. Therefore, the more layers you add, the lower the spike frequency and the less information is transmitted.

[0045] Figure 7 is a diagram showing an example of the timing of obtaining output spikes by training input spikes in an SNN. As shown in Figure 7, training input spikes can increase synaptic current. The current also increases the potential of the artificial neuron. When the potential of the artificial neuron is equal to or greater than a reference value, an output spike may fire.

[0046] 8a and 8b are diagrams illustrating exemplary firing rate adjustment methods according to an embodiment of the present invention. The firing rate adjustment method shown in FIG. 8a (VDD adjustment method: 2.1 → 2.2 → 2.3) results in different spiking frequencies for each layer, with the spiking frequency decreasing toward later layers. On the other hand, the firing rate adjustment methods shown in FIG. 8b (Vex / Vin adjustment method: 2.1 → 2.2 → 2.3, Vrst adjustment method: 2.0 → 1.5 → 1.5, Vadj adjustment method: 0.5 → 0.5 → 1.0) result in relatively high spiking frequencies. Generally, a large number of spikes are required for data presentation. Therefore, the artificial neuron of the present invention advantageously includes various spiking rate adjustment methods.

[0047] Meanwhile, synapse arrays according to embodiments of the present invention can be realized in three dimensions.

[0048] 9 is a diagram illustrating a neuromorphic computing device 200 according to another embodiment of the present invention. Referring to FIG. 9, the neuromorphic computing device 200 may be implemented with a 3D synapse array 210, a bit line driver 230, and a spiking neuron circuit 240.

[0049] The 3D synapse array 210 has stacked layers. Each layer may include a first cell transistor 211 connected between an excitatory bit line BLe and an excitatory source line SLe and a second cell transistor 212 connected between an inhibitory bit line BLi and an inhibitory source line SLi. The first cell transistor 211 (excitatory synapse layer) and the second cell transistor 212 (inhibitory synapse layer) may be implemented as non-volatile memory transistors. For example, each of the first cell transistor 211 and the second cell transistor 212 may be implemented as a ferroelectric transistor. Here, the first cell transistor 211 and the second cell transistor 212 may include a gate connected to a corresponding one of substrate-type word lines (WL_L1 to WL_L4).

[0050] The spiking neuron circuit 240 can include artificial neurons 241 and 242. Each of the artificial neurons 241 and 242 can be implemented as an artificial neuron that performs the LIF operations described in FIGS.

[0051] In some embodiments, the neuromorphic computing device 200 may further include control logic for adjusting the firing rate of the artificial neuron. In some embodiments, the neuromorphic computing device 200 may further include a layer buffer storing adjustment information for adjusting the firing rate of the artificial neuron corresponding to each stacked layer. In some embodiments, the cell transistor may be implemented as a Ferroelectric Multi-Bridge Channel Field Effect Transistor (FeMBCFET).

[0052] Generally, an SNN has an artificial neuron in each layer. At this time, the input spike pattern differs for each layer of the SNN. Therefore, the firing frequency of the artificial neuron differs. If the firing frequency is too high or too low, the firing rate needs to be adjusted for each layer. The neuromorphic computing device 100 according to an embodiment of the present invention can be realized to adjust the firing rate via Vex, Vin, Vrst, and Vadj.

[0053] Figure 10 is a diagram illustrating the flexible configuration of artificial neurons by layer shown in Figure 9. The neuromorphic computing device may encode data into spikes by a spike encoder by layer, train the input spikes by a synapse array by layer, receive the trained input spikes, output output spikes by an artificial neuron by layer, repeat such output spike training by layer, and output data corresponding to the output spikes by a spike decoder by layer.

[0054] 10, the neuromorphic computing device 200 may further include a control unit 250 and a layer buffer 260. The control unit 250 may be implemented to adjust a firing rate via Vex, Vin, Vrst, and Vadj. The layer buffer 260 stores the values ​​of Vex, Vin, Vrst, and Vadj for each layer and adjusts the firing rate of each layer by applying corresponding voltages to neurons of each layer via the control unit 250. In an embodiment, the layer buffer 260 may be implemented as a volatile / non-volatile memory.

[0055] 11 is a diagram illustrating an example of flexible artificial neuron configuration for each stacked layer. As shown in FIG. 11, Vex, Vin, Vrst, and Vadj can be configured for each of the six layers. Meanwhile, such layer-by-layer adjustment information can be varied according to environmental information of the neuromorphic computing device. Here, the environmental information can be the device temperature, data processing amount, data processing speed, operating frequency, etc.

[0056] The present invention first discloses an FeFET synapse array and FeFET neurons that can simultaneously process excitatory synapses and inhibitory synapses, second discloses a 3D synapse array based on FeMBCFET, and third discloses a flexible neuron setting method that can adjust the firing rate by layer.

[0057] FIG. 12 is a flowchart illustrating an exemplary operation of a neuromorphic computing device according to an embodiment of the present invention. Referring to FIGS. 1 to 12, the operation of a neuromorphic computing device having an artificial neuron connected to an excitatory synapse and an inhibitory synapse may be performed as follows. The neuromorphic computing device may train input spikes of the artificial neuron through the excitatory synapse and the inhibitory synapse (S110). The neuromorphic computing device may adjust the firing rate of the artificial neuron in various ways (S120). For example, the neuromorphic computing device may adjust the firing rate of the artificial neuron by adjusting at least one of the power supply voltage, the first input power supply voltage, the second input power supply voltage, the adjustment voltage, and the reset voltage. The neuromorphic computing device may train output spikes of the artificial neuron using the controlled firing rate (S130).

[0058] In an embodiment, each of the artificial neurons includes a ferroelectric transistor having a gate coupled to a first node and coupled between a power supply terminal receiving a power supply voltage and a second node outputting an output spike; a first input transistor having a gate receiving a first input spike from a corresponding excitatory synapse and coupled between a first input power supply terminal receiving a first input power supply voltage and the first node; a second input transistor having a gate receiving a second input spike from a corresponding inhibitory synapse and coupled between a second input power supply terminal receiving a second input power supply voltage and the first node; an adjustment transistor having a gate receiving an adjustment voltage and coupled between the second node and ground; and a reset transistor having a gate receiving a reset voltage and coupled between the first node and ground.

[0059] In an embodiment, the neuromorphic computing device can generate input spikes corresponding to digital data and output digital data corresponding to each of the output spikes. In an embodiment, the excitatory synapses and inhibitory synapses can be realized with three-dimensionally stacked Ferroelectric Multi-Bridge Channel Field Effect Transistors (FeMBCFETs).

[0060] Meanwhile, the artificial neuron according to the embodiment of the present invention can be used in a spiking neural network.

[0061] 13 is a diagram illustrating a spiking neural network (SNN) according to an embodiment of the present invention. Referring to FIG. 13, a spiking neural network 10 can be modeled with a presynaptic neuron 12, a control circuit 14, a synapse array 16, and a post-synaptic neuron 18.

[0062] The presynaptic neuron 12 receives the input spike (sp <j>, j is an integer greater than or equal to 0). The presynaptic neuron 12 may also be a postsynaptic neuron of a previous layer in a multi-layer spiking neural network (SNN).

[0063] The control circuit 14 detects simultaneous and multiple input spikes (sp <j>) to the string selection signal (S <j>, j is an integer equal to or greater than 0). That is, the control circuit 14 converts input spikes (sp <j>) to the string select signal (S <j>) The control circuit 14 converts any input spike (sp <j>) the pulse width of the string selection signal (S <j>That is, the control circuit 14 generates a string selection signal (S <j>) is generated. Therefore, the string selection signal (S <j>The pulse width of the string select signal (S) corresponds to the time required to read one memory cell multiplied by the number of memory cells (k) in the string. For example, in response to the first input spike, the control circuit 14 activates the string select signal (S) for the string select time (Δ). <0> ) is generated, where the string selection time (Δ) can be the time required to sequentially read all of the memory cells included in one string.

[0064] The post-synaptic neurons 18 include "k" neurons for accumulating synaptic weights Ws transmitted through the synaptic array 16. The post-synaptic neurons 18 receive "p" string selection signals (S <j>), it integrates the current reflecting the synaptic weight Ws provided by the synapse array 16 according to the input signal, and fires an output spike according to the accumulated value. If "k" neurons are included in the postsynaptic neuron 18, "k" output spikes (Output_0 to Output_k-1) can be generated simultaneously. When the spiking neural network 10 is composed of multiple layers, the postsynaptic neuron 18 can be regarded as a pre-synaptic neuron of the subsequent layer.

[0065] The spiking neural network 10 of the present invention can use a memory element array of a nonvolatile memory as a synapse element array. That is, the string selection signal (S <j>) is a signal for selecting a string of nonvolatile memory, and the synapse array 16 for transmitting the synaptic weight Ws can be realized as data stored in each memory cell. The postsynaptic neuron 18 can be realized as a plurality of sensing circuits that accumulate currents transmitted according to the weights in the plurality of strings and generate output spikes according to the magnitude of the accumulated current.

[0066] A vertically stacked three-dimensional nonvolatile memory can be used to implement the above-described spiking neural network 10. The large memory capacity allows for the implementation of a spiking neural network 10 that is easy to expand the synaptic weights Ws.

[0067] Meanwhile, the neuromorphic computing device and the operating method thereof according to the embodiment of the present invention can be implemented in an electronic device.

[0068] 14 is a diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Referring to FIG. 14, the electronic device 1000 may analyze input data in real time using a neural network to extract useful information, and may make situational decisions based on the extracted information or control the configuration of a device in which the electronic device 1000 is installed. For example, the electronic device 1000 may be applied to robotic devices such as drones and advanced driver assistance systems (ADAS), smart TVs, smartphones, medical devices, mobile devices, image display devices, measuring devices, IoT devices, and the like, and may also be installed in at least one of various other types of devices.

[0069] The electronic device 1000 may include a processor 1100, a RAM (Random Access Memory) 1200, a neural network device 1300, a memory device 1400, a sensor module 1500, and a communication device 1600. The electronic device 1000 may further include an input / output module, a security module, a power control device, etc. A portion of the hardware configuration of the electronic device 1000 may be mounted on at least one semiconductor chip.

[0070] The processor 1100 controls the overall operation of the electronic device 1000. The processor 1100 may include one processor core (single core) or multiple processor cores (multi-core). The processor 1100 may process or execute programs or data stored in the memory device 1400. In some embodiments, the processor 1100 may control the functions of the neural network device 1300 by executing programs stored in the memory device 1400. The processor 1100 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), or the like.

[0071] The RAM 1200 can temporarily store programs, data, or instructions. For example, the programs or data stored in the memory device 1400 can be temporarily stored in the RAM 1200 under the control of the processor 1100 or boot code. The RAM 1200 can be implemented with memories such as dynamic RAM (DRAM) or static RAM (SRAM).

[0072] The neural network device 1300 can perform neural network operations based on received input data and generate information signals based on the execution results. The neural network can include, but is not limited to, CNN, RNN, FNN, LSTM (long short-term memory), SNN (stacked neural network), SSDNN (state-space dynamic neural network), DBN (deep belief networks), RBM (restricted Boltzmann machines), etc. The neural network device 1300 can be a dedicated neural network hardware accelerator itself or a device including the same. The neural network device 1300 can perform not only neural network operations but also read and write operations.

[0073] The neural network device 1300 can be implemented to perform the neuromorphic computing described in Figures 1 to 13. The neural network device 1300 can implement weights having linear state change characteristics, thereby increasing the accuracy of neural network operations performed by the neural network device 1300 and realizing a more precise neural network.

[0074] The information signal may include one of various types of recognition signals, such as a voice recognition signal, an object recognition signal, a video recognition signal, a biometric information recognition signal, etc. For example, the neural network device 1300 may receive frame data included in a video stream as input data and generate a recognition signal for an object included in an image represented by the frame data from the frame data. However, the present invention is not limited thereto, and the neural network device 1300 may receive various types of input data and generate a recognition signal according to the input data depending on the type and function of the device in which the electronic device 1000 is installed.

[0075] The neural network device 1300 may execute machine learning models such as linear regression, logistic regression, statistical clustering, Bayesian classification, decision trees, principal component analysis, or expert systems, or ensemble techniques such as random forests. Such machine learning models may be used to provide various services, such as video classification services, biometric or biometric data-based user authentication services, advanced driver assistance systems (ADAS), voice assistant services, and automatic speech recognition (ASR) services.

[0076] The memory device 1400 serves as a storage location for storing data, and can store an operating system (OS), various programs, and various data. In an embodiment, the memory device 1400 can store intermediate results generated during the execution of operations by the neural network device 1300.

[0077] The memory device 1400 may be, but is not limited to, a DRAM. The memory device 1400 may include at least one of a volatile memory or a non-volatile memory. Non-volatile memory includes read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable and programmable read-only memory (EEPROM), flash memory, phase-change RAM (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM). Volatile memory includes dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), phase-change RAM (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FeRAM). In an embodiment, the memory device 1400 may include at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), or a memory stick.

[0078] The sensor module 1500 may collect information about the surroundings of the electronic device 1000. The sensor module 1500 may sense or receive signals (e.g., video signals, audio signals, magnetic signals, biosignals, touch signals, etc.) from outside the electronic device 1000 and convert the sensed or received signals into data. To this end, the sensor module 1500 may include at least one of various types of sensing devices, such as a microphone, an imaging device, an image sensor, a LIDAR (light detection and ranging) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, and a touch sensor.

[0079] The sensor module 1500 can provide the converted data as input data to the neural network device 1300. For example, the sensor module 1500 can include an image sensor that captures an external environment of the electronic device 1000 to generate a video stream and sequentially provides successive data frames of the video stream as input data to the neural network device 1300. However, the sensor module 1500 is not limited thereto, and can provide various types of data to the neural network device 1300.

[0080] The communication device 1600 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication device 1600 may include a communication interface connectable to a wired local area network (LAN), a wireless local area network (WLAN) such as Wi-fi (Wireless Fidelity), a wireless personal area network (WPAN) such as Bluetooth, a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio-frequency identification (RFID), power line communication (PLC), or a mobile cellular network such as 3rd generation (3G), 10th generation (4G), or long term evolution (LTE).

[0081] The devices described above may be implemented using hardware components, software components, or a combination of hardware and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as a processor, controller, arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable gate array (FPGA), programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, although a single processing device may be described, those skilled in the art will understand that the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors or one processor and one controller. Other processing configurations are also possible, such as parallel processors.

[0082] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to operate as desired or may instruct the processing device, either individually or collectively. The software or data may be embodied in some type of machine, component, physical device, virtual device, computer storage medium, or device to be interpreted by the processing device or to provide instructions or data to the processing device. The software may also be stored or executed in a distributed manner, distributed across computer systems coupled via a network. The software and data may be stored on one or more computer-readable recording media.

[0083] A neuromorphic computing device and its operating method according to an embodiment of the present invention discloses a flexible neuron configuration method that starts with an FeFET-based 2D synapse array and an artificial neuron that is an improvement over conventional FeFET neurons, starts with an FeMBCFET-based 3D synapse array, and adjusts the firing rate of the artificial neuron for each layer.

[0084] Neuromorphic computing devices according to embodiments of the present invention may be implemented so that artificial neurons receive both excitatory and inhibitory signals. Neuromorphic computing devices according to embodiments of the present invention may include a circuit for adjusting the firing rate of the artificial neurons. Neuromorphic computing devices according to embodiments of the present invention may be implemented as ferroelectric transistors with a multi-bridge channel FET (MBCFET; nanosheet) structure. Meanwhile, neuromorphic computing devices according to embodiments of the present invention may also be implemented as ferroelectric transistors with a planar FET structure, a ferroelectric transistor with a FinFET structure, a ferroelectric transistor with a GAA (Gate-All-Around) FET (Nanowire) structure, a ferroelectric transistor with a forksheet structure, or a complementary FET (CFET).

[0085] Meanwhile, the above-described content of the present invention is merely a specific embodiment for carrying out the invention. The present invention includes not only specific and practically usable means themselves, but also technical ideas that are abstract and conceptual ideas that can be utilized as technology in the future. [Explanation of symbols]

[0086] 100 Neuromorphic Computing Device 110 Synapse Array 120 Presynaptic Neuron Circuits 130-bit line driver 140 Spiking Neuron Circuits 141, 142 Artificial neurons< / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. 1. A neuromorphic computing device having a plurality of artificial neurons connected in a synaptic array, Each of the plurality of artificial neurons a ferroelectric transistor having a first gate coupled to a first node and coupled between a power supply terminal receiving a power supply voltage and a second node outputting an output spike; a first input transistor having a second gate for receiving a first input spike and coupled between a first input power supply terminal for receiving a first input power supply voltage and the first node; a second input transistor having a third gate for receiving a second input spike and coupled between a second input power supply terminal for receiving a second input power supply voltage and the first node; an adjustment transistor having a fourth gate for receiving an adjustment voltage and connected between the second node and ground; a reset transistor having a fifth gate for receiving a reset voltage, the reset transistor coupled between the first node and the ground;

2. the first input spike is received from an excitatory synapse; The neuromorphic computing device of claim 1 , wherein the second input spike is received from an inhibitory synapse.

3. the first input transistor includes a PMOS (P-channel Metal Oxide Semiconductor) transistor; The neuromorphic computing device of claim 1 , wherein the second input transistor comprises an NMOS (N-channel Metal-Oxide Semiconductor) transistor.

4. The neuromorphic computing device of claim 1 , wherein the ferroelectric transistor is implemented with a commonly tied source and well.

5. the first input power supply voltage is a positive voltage; The neuromorphic computing device of claim 1 , wherein the second input power supply voltage is a negative voltage.

6. The neuromorphic computing device of claim 1 , wherein the firing rate of the artificial neuron is adjusted by varying the power supply voltage.

7. 2. The neuromorphic computing device of claim 1, wherein the firing rate of the artificial neuron is adjusted by varying the first input power supply voltage, the second input power supply voltage, the regulated voltage, or the reset voltage.

8. The neuromorphic computing device of claim 7 further comprising a control unit for regulating the firing rate.

9. The neuromorphic computing device according to claim 1 , wherein the synapse array includes excitatory synapses and inhibitory synapses arranged in a two-dimensional structure.

10. The neuromorphic computing device of claim 1 , wherein the synapse array includes excitatory synapses and inhibitory synapses arranged alternately in a three-dimensional structure.

11. a synapse array in which excitatory synapses each having a first ferroelectric transistor connected between an excitatory bit line and an excitatory source line and inhibitory synapses each having a second ferroelectric transistor connected between an inhibitory bit line and an inhibitory source line are alternately arranged; a pre-synaptic neuron circuit providing an input spike corresponding to a word line coupled to the gates of the first ferroelectric transistor and the second ferroelectric transistor; a bit line driver that provides a first bit line voltage to the excitatory bit line and a second bit line voltage to the inhibitory bit line; a neuromorphic computing device including an artificial neuron that receives an excitatory input spike from any of the excitatory source lines, receives an inhibitory input spike from any of the inhibitory source lines, and outputs an output spike by performing a leaky integration-and-fire (LIF) operation;

12. The neuromorphic computing device of claim 11 , wherein the first bit line voltage and the second bit line voltage are different from each other.

13. The neuromorphic computing device of claim 11 , further comprising a control unit that adjusts the firing rate of each of the artificial neurons.

14. the word lines are disposed in stacked layers; The neuromorphic computing device of claim 13 , wherein the control unit adjusts the firing rate according to each of the stacked layers.

15. Each of the artificial neurons a ferroelectric transistor having a first gate coupled to a first node and coupled between a power supply terminal receiving a power supply voltage and a second node outputting an output spike; a first input transistor having a second gate for receiving a first input spike and coupled between a first input power supply terminal for receiving a first input power supply voltage and the first node; a second input transistor having a third gate for receiving a second input spike and coupled between a second input power supply terminal for receiving a second input power supply voltage and the first node; an adjustment transistor having a fourth gate for receiving an adjustment voltage and connected between the second node and ground; 15. The neuromorphic computing device of claim 11, further comprising a reset transistor having a fifth gate for receiving a reset voltage, the reset transistor being coupled between the first node and the ground terminal.

16. 1. A method of operating a neuromorphic computing device having an artificial neuron coupled to an excitatory synapse and an inhibitory synapse, comprising: training input spikes through the excitatory synapse and the inhibitory synapse; adjusting the firing rate of the artificial neuron; training the output spikes of the artificial neuron in response to the adjusted firing rate in the adjusting step.

17. Each of the artificial neurons a ferroelectric transistor having a first gate coupled to a first node and coupled between a power supply terminal receiving a power supply voltage and a second node outputting an output spike; a first input transistor having a second gate for receiving a first input spike from a corresponding excitatory synapse, the first input transistor being coupled between a first input power supply terminal for receiving a first input power supply voltage and the first node; a second input transistor having a third gate for receiving a second input spike from a corresponding inhibitory synapse, the second input transistor being coupled between a second input power supply terminal for receiving a second input power supply voltage and the first node; an adjustment transistor having a fourth gate for receiving an adjustment voltage and connected between the second node and ground; 17. The method of claim 16, further comprising a reset transistor coupled between the first node and ground, the reset transistor having a fifth gate for receiving a reset voltage.

18. generating input spikes corresponding to digital data; 18. The method of claim 17, further comprising outputting digital data corresponding to each of the output spikes.

19. The step of adjusting the firing rate comprises:

20. The method of claim 17, comprising adjusting at least one of the first input power supply voltage, the second input power supply voltage, the regulation voltage, and the reset voltage.

20. 20. The method of claim 17, wherein the excitatory synapse and the inhibitory synapse are realized with three-dimensionally stacked FeMBCFETs.

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