Power converter control loop gain adaptation

Abstract

To prevent ripple on the output voltage and current in transitioning from a first operational mode to a second operational mode in response to load changes (e.g., light load to heavy load, or heavy load to light load).SOLUTION: Described embodiments include a circuit having a comparator 324 with first and second comparator inputs and a comparator output. The second comparator input is coupled to a ripple reference voltage terminal. A switch 318 is coupled between the first comparator input and a ground terminal, and has a switch control terminal that is coupled to the comparator output. A capacitor 322 is coupled between the first comparator input and the ground terminal. A first current source 314 is coupled between a supply terminal and the first comparator input, and has a first current control terminal.SELECTED DRAWING: Figure 3

Description

[Background technology]

[0001] This description relates to switching power converters. A switching power converter receives a direct current (DC) input voltage and provides an output at a specified DC voltage within a specified current limit. A typical switching converter includes a power stage having a switch, an output capacitor, and an inductor. A typical switching converter may also include a converter control circuit for controlling the switch of the power stage. The power converter may include the ability to transition from a first operating mode to a second operating mode in response to a load change (e.g., from a light load to a heavy load, or from a heavy load to a light load). However, these mode transitions can sometimes be problematic by causing inefficient operation and introducing ripple into the output voltage and current.

[0002] Some switching power converters operate in both pulse-width modulation (PWM) and pulse-frequency modulation (PFM) modes. In some current-mode power converters, a timer-based PFM mode can be used to adjust the PFM frequency. The gain of the control loop while operating in PFM mode typically depends on the PFM pulse size and the gain of the PFM timer. However, the PFM pulse size can vary depending on the duty cycle ratio and inductance of the output inductor while operating in PWM mode. Summary of the Invention

[0003] In a first example, a circuit includes a comparator having a first comparator input, a second comparator input, and a comparator output. The second comparator input is coupled to a ripple reference voltage terminal. A switch is coupled between the first comparator input and a ground terminal, the switch having a switch control terminal coupled to the comparator output.

[0004] A capacitor is coupled between the first comparator input and a ground terminal, a first current source is coupled between the supply terminal and the first comparator input, the first current source having a first current control terminal, and a second current source is coupled between the current output terminal and the ground terminal, the second current source having a second current control terminal.

[0005] In a second example, the control circuit includes a clock circuit having a clock output and a logic circuit having first, second, third, and fourth logic circuit inputs and first, second, and third logic circuit outputs. The first logic circuit input is coupled to the clock output. A digital-to-analog converter (DAC) has a DAC input and a DAC output. The DAC input is coupled to the first logic circuit output. A voltage-to-current converter (V2I) has first and second V2I inputs and first, second, and third V2I outputs, with the first V2I input coupled to the DAC output.

[0006] a timer circuit having first, second, and third timer outputs, the first timer output coupled to the first V2I input, the second timer output coupled to the second V2I input, and the third timer output coupled to the third logic circuit input; an amplifier having first and second amplifier inputs and an amplifier output, the first amplifier input coupled to the voltage feedback terminal, the second amplifier input coupled to the voltage reference terminal, and the amplifier output coupled to the second V2I input; [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows a block diagram for an example power converter.

[0008] [Figure 2] 1 shows a diagram of inductor current versus time for an example voltage converter system operating in pulse frequency mode.

[0009] [Figure 3] 1 shows a block diagram for an example PFM timing circuit.

[0010] [Figure 4] 1 shows a schematic diagram of an example PFM timing circuit with adapted reference voltage.

[0011] [Figure 5] 1 shows a block diagram for an example buck power converter having a PFM timing circuit with an adapted reference voltage.

[0012] [Figure 6] 1 shows a block diagram of an example circuit for a buck control logic circuit. DETAILED DESCRIPTION OF THE INVENTION

[0013] In this description, the same reference numbers denote the same or similar features (in terms of function and / or structure).The drawings are not necessarily drawn to scale.

[0014] Some switching power converters are designed to operate in both pulse-width modulation (PWM) and pulse-frequency modulation (PFM) modes, transitioning from one mode to the other during operation. Typically in valley-current-mode buck power converters, a control loop adapts the inductor current valley point while operating in PWM mode. When operating in PFM mode, the same control loop can be used to adapt the frequency of the PFM pulses by controlling a PFM timer. The PFM timer uses the output voltage of the loop filter error amplifier to determine the frequency of the PFM pulses.

[0015] When using a PFM timer to control the switching frequency in PFM mode, the control loop gain depends on the PFM pulse size. Variations in the inductance of the output inductor, the duty cycle ratio, and the PWM switching frequency cause variations in the control loop gain. This variation in gain in PFM mode can cause poor load transient performance, voltage disturbance, and mode bouncing during entry and exit of PFM mode.

[0016] 1 is a block diagram for an example power converter 100. Power converter 100 includes a power supply 102, a power stage 106, and an output capacitor C OUT 144, a load 142, and a controller 148. Power stage 106 includes a high-side (HS) switch 120, a low-side (LS) switch 128, and an inductor 136 coupled to HS switch 120 and LS switch 128 at switching terminal 135. In at least some examples, HS switch 120, LS switch 128, and associated drivers are components of an integrated circuit (IC), and inductor 136 is an external component separate from the IC. In at least one example, power converter system 100 is a buck power converter, which generates an output voltage (V OUT ) is the input voltage (V IN ) means lower than

[0017] The HS switch 120 is connected to the input voltage terminal V IN 104 and the LS switch 128, and has a control terminal for receiving a control signal HS_CS 152. The power supply 102 receives an input voltage V IN 104 to the HS switch 120. The LS switch 128 has a control terminal coupled between the LS switch 128 and a ground terminal and receiving a control signal LS_CS 154. The HS switch 120 is connected to a voltage V SW LS switch 128 at switching terminal 135 having a voltage V. In at least one example, HS switch 120 and LS switch 128 are p-channel field effect transistors ("PFETs"). Inductor 136 couples switching terminal 135 to output voltage V. OUT An output capacitor C is connected between the output voltage terminal 140 and the ground terminal. OUT 144 is coupled between the output voltage terminal 140 and a ground terminal. A load 142 is coupled between the output voltage terminal 140 and a ground terminal.

[0018] Controller 148 includes valley control circuitry 155, peak control circuitry 158, light load detection circuitry 164, mode control logic 170, and driver circuit 184. Controller 148 has a first input coupled to power supply 102, the first input being connected to input V IN 104. The controller 148 is coupled to the switching terminal 135 to provide a switching voltage V SW The controller 148 has a second input that receives the output voltage V OUT and a third input coupled to an output voltage terminal 140 that receives the

[0019] Valley control circuitry 155 has an input that receives a control signal CS1. In some examples, CS1 includes a valley threshold and an inductor current sense signal, and CS1 can be one or more signals. In at least one example, the valley threshold and the inductor current sense signal can be ramped. Peak control circuitry 158 receives a control signal CS2. In some examples, CS2 includes a peak threshold and an inductor current sense signal. Light load detection circuitry 164 receives a control signal CS3. In at least one example, CS3 includes a control voltage and a light load threshold. In some examples, the control voltage controls the output current of power stage 106 and indicates the output current level. Thus, one option for detecting a light load condition involves monitoring the control voltage against a threshold.

[0020] Mode control logic 170 has a first input coupled to the output of valley control circuitry 155, a second input coupled to the output of peak control circuitry 158, and a third input coupled to the output of light load detection circuitry 164. Mode control logic 170 has a first output coupled to a first input of driver circuit 184 and a second output coupled to a second input of driver circuit 184. Mode control logic 170 is configured to provide a ripple control signal Sel_i_ripple 178 at its third output. Driver circuit 184 has a first output HS_CS 152 coupled to the control terminal of HS switch 120. Driver circuit 184 has a second output LS_CS 154 coupled to the control terminal of LS switch 128.

[0021] The controller 148 controls the voltage V IN , V SW , V OUT , and ground and the operation of valley control circuitry 155, peak control circuitry 158, light load detection circuitry 164, mode control logic 170, and driver circuit 184 to provide HS_CS 152 and LS_CS 154, respectively. In some examples, controller 148 may be configured to sense the inductor current of the power stage and adjust the offset between the valley and peak thresholds in response to a light load condition being detected by light load detection circuitry 164. Controller 148 may be configured to transition from PWM mode to PFM mode in response to a light load condition combined with a comparison indicating the sensed inductor current has reached the peak threshold. The comparison may be made, for example, by peak control circuitry 158.

[0022] Power stage 106 outputs an output voltage V at output voltage terminal 140. OUT provides the voltage V IN 104, HS_CS 152, and LS_CS 154 at switching terminal 135. SWHS switch 120 couples the input voltage terminal 104 to switching terminal 135 in response to HS_CS 152, which increases the current in inductor 136. LS switch 128 couples the ground terminal to switching terminal 135 in response to LS_CS 154, which decreases the current in inductor 136. The load current provided to load 142 is the average current through inductor 136.

[0023] The PFM pulse size may be selected to achieve good efficiency and avoid high output voltage ripple or mode bouncing between PFM and PWM modes. In some examples, controller 148 is configured to optimize efficiency by entering PFM mode at light loads when the inductor current falls below zero current while operating in PWM mode. At light loads, bouncing between PWM and PFM modes is avoided and the output voltage V OUT The maximum PFM output current is chosen to be greater than the load current to avoid overshoot or undershoot at 140. The PFM pulse is chosen to be greater than the current ripple in PWM mode.

[0024] When operating in PWM mode, conditions that can cause variations in inductor current ripple include the input voltage V IN 104, output voltage V OUT 140, the operating frequency, and the inductance of inductor 136. In some cases, the inductance of inductor 136 may vary by up to + / - 30%, and the example operating frequency may vary by up to + / - 20%. Also, in at least one example, the input voltage V IN 104 can vary from 2.5V to 40V. An example output voltage V OUT140 can vary from 0.3 to 6 V. Each of these variations can change the inductor current ripple. Due at least in part to variations in inductor current ripple, a PFM pulse with a suitable peak current value for a high ripple condition can cause significant voltage ripple in a low ripple condition. Conversely, a PFM pulse with a suitable peak current value for a low ripple condition can cause inefficiency and mode bounce in a high ripple condition.

[0025] The controller 148 adjusts the PFM pulse peak current value according to the inductor current ripple in PWM mode. In at least some examples, the peak control circuitry 158 controls the peak current limit in PWM mode and defines the PFM pulse peak current value in PFM mode. For example, the peak threshold may be the valley current level plus an offset. In some examples, the offset is digitally controlled. In PFM mode, the controller 148 may set the valley current level to zero, and the reference level of the PFM peak current value is determined by the offset.

[0026] In PWM mode, the controller 148 regulates the output voltage V by adjusting the valley current as needed. OUT A fixed frequency valley current mode is used to regulate 140. For current-mode buck power converters operating in timer-based PFM mode, a current control loop is used to adapt the PFM frequency. The PFM pulses are adapted based on the inductor current ripple in PWM mode to optimize output voltage ripple and converter efficiency.

[0027] 2 shows a graph 200 of inductor current versus time for an example voltage converter system operating in pulse frequency mode (PFM). Graph 210 shows the peak output current level of voltage converter I_peak. Graph 220 shows the average output current level of voltage converter I_out. Graph 202 shows the inductor current being delivered to the output voltage terminals versus time. Graph 230 shows the Start_PFM_pulse 230, which triggers the start of each PFM cycle, versus time.

[0028] At time t0, a pulse occurs on the Start_pfm_pulse signal 230. In response to this pulse, the high-side switch is turned on to couple the input voltage from the power supply to the switching terminal. This causes current to flow through the inductor to the output capacitance, creating a ramp in the inductor current 202. The inductor current 202 continues to rise until it reaches a peak output current level I_peak 210. In response to the inductor current 202 reaching the peak output current level I_peak 210, the high-side switch is turned off and the low-side switch is turned on, coupling the switching terminal to ground. The inductor current begins to decrease and continues to decrease until it reaches zero. The converter remains in a high impedance state, and the inductor current 202 remains at zero until the next pulse occurs on the Start_pfm_pulse signal 230.

[0029] The time from the rising edge of the Start_pfm_pulse signal 230 until the inductor current 202 ramps down to zero and back down is T_pulse 212. Subsequently, another pulse occurs on the Start_pfm_pulse signal 230 and the inductor current 202 begins to ramp up again until it reaches the peak output current level I_peak 210. The time from the rising edge of a particular Start_pfm_pulse signal 230 to the rising edge of the subsequent Start_pfm_pulse signal 230 is the PFM pulse period, T_pulse 212. SW216. The average output current I_out 220 is determined by the period (or frequency) and magnitude of the PFM pulse. I OUT 220 is the average inductor current, the value of which can be calculated using equation (1) as half the peak current multiplied by the ratio of the pulse width to the period between successive pulses. TIFF2025143211000002.tif624

[0030] 3 shows a block diagram of an example PFM timing circuit 300. An amplifier 306 has a first input coupled to a feedback voltage terminal that provides a feedback voltage V_fb 302. The feedback voltage V_fb 302 is a voltage proportional to the output voltage of the power converter. The amplifier 306 has a second input coupled to a reference voltage terminal that provides a reference voltage V_ref 304. The reference voltage V_ref 304 is proportional to a desired voltage at the output voltage terminal. The amplifier 306 has an output coupled to a control terminal of a current source gm_pfm 314. A resistor 310 and a capacitor 312 are coupled in series between the output of the amplifier 306 and a ground terminal.

[0031] Current source gm_pfm 314 has a first terminal coupled to the voltage source, a second terminal coupled to switch 318 and capacitor C_pfm 322, and a control terminal that receives signal V_ctrl 308 from the output of amplifier 306. Comparator 324 has a first input coupled to the second terminal of current source gm_pfm 314 and receives signal V_timer_ramp 320. Comparator 324 has a second input coupled to the reference voltage terminal and receives reference voltage V_ref 304. Capacitor 322C_pfm is coupled between the first input of comparator 324 and a ground terminal. Comparator 324 provides signal Start_pfm_pulse 326 at its output.

[0032] Circuit elements in PFM timing circuit 300 convert the compensation voltage V_ctrl 308 at the output of amplifier 306 into a time period. This conversion is accomplished by using compensation voltage V_ctrl 308 to control the amount of current provided by current source gm_pfm 314 to capacitor C_pfm 322, which creates a voltage V_timer_ramp 320 across capacitor C_pfm 322. Voltage V_timer_ramp 320 is provided to comparator 324, which compares it to a reference voltage V_ref 304. The comparison of V_timer_ramp 320 to V_ref 304 controls the length of pulse period t_sw 216. Once pulse period t_sw has elapsed, a subsequent PFM pulse is triggered by Start_pfm_pulse 326.

[0033] Resistor 310 and capacitor 312 are coupled in series with the output of amplifier 306 to form a proportional-integral (PI) compensator for voltage V_ctrl 308. This voltage controls the transconductance (gm) of a timer that acts similar to a voltage-controlled oscillator, with voltage V_ctrl 308 controlling the oscillation frequency.

[0034] The Start_pfm_pulse signal 326 is provided by the output of the comparator 324. The Start_pfm_pulse signal 326 is provided to a control terminal of the switch 318 to control the switch. In response to the Start_pfm_pulse signal 326 causing the switch 318 to open, current from the current source gm_pfm 314 begins to charge the capacitor C_pfm 322, causing the voltage V_timer_ramp 320 to increase linearly. In response to the voltage V_timer_ramp 320 crossing the reference voltage V_ref 304, the output of the comparator 324 goes high, triggering the Start_pfm_pulse 326.

[0035] The buck controller generates Start_pfm_pulse 326 and switch 318 is opened. The power stage of the voltage converter generates a current pulse through the output inductor and the voltage timer ramp cycle begins again with the subsequent rising Start_pfm_pulse 326. As the voltage at V_ctrl 308 increases, the current provided by current source gm_pfm 314 increases, causing the voltage ramp of V_timer_ramp 320 across C_pfm 322 to become steeper (i.e., higher slew rate). The steeper the voltage ramp of V_timer_ramp 320 becomes, the earlier Start_pfm_pulse 326 triggers, which generates a faster pulse and increases the average output current I OUT Increase 220.

[0036] Output current I OUT As demand on amplifier 306 increases, the output voltage may begin to drop. The drop in output voltage causes a drop in feedback voltage V_fb 302, which increases the voltage V_ctrl 308 at the output of amplifier 306. The increase in voltage V_ctrl 308 increases the amount of current provided by current source gm_pfm 314, charging capacitor C_pfm 322 more quickly and tripping the output of comparator 324 sooner. As a result, the inductor current is zero for a shorter period of time, causing a new Start_pfm_pulse 326 to be generated sooner, which in turn increases the average output current I OUT 220 increases.

[0037] The PFM gain is the ratio of the average output current I to the change in the voltage V_ctrl 308 at the output of the amplifier 306. OUT The PFM gain is the ratio of the change in the voltage V_ctrl 308 to the current output from the current source gm_pfm 414. This circuit element forms a voltage-to-current converter. The formula for calculating the PFM gain is given by equation (2). TIFF2025143211000003.tif737 The PFM gain depends on the pulse width, the transconductance of the current source, the capacitance of C_pfm 322, and the reference voltage V_ref 304. Different applications may have different input and output voltages, and different tolerances for the inductance of the inductor.

[0038] These variations in parameters can result in higher current ripple in some applications or lower current ripple in other applications. The magnitude of the current ripple affects the PFM gain, significantly changing the gain from the voltage V_ctrl 308 at the output of the amplifier 306 to the output current. This variation in gain can cause serious problems, including increased output current and voltage ripple, control loop instability, and unstable transitions between PWM and PFM modes.

[0039] A potential solution to the problem caused by PFM gain variation is to change the pulse frequency based on the inductor current ripple. The reference voltage level provided to the PFM timer comparator can be adapted and changed in response to the PFM pulse amplitude. This makes the reference voltage V_ref no longer a constant DC level voltage, but rather adjustable.

[0040] FIG. 4 shows a schematic diagram of an example PFM timing circuit with an adapted reference voltage. Signal V_ctrl 408 is a signal proportional to the voltage difference between the regulator's output voltage and a reference voltage representing the desired output voltage. In at least one case, signal V_ctrl 408 is provided from the output of a voltage error amplifier. Signal V_ctrl 408 is provided to the control terminal of current source gm_pfm 414.

[0041] Current source gm_pfm 414 has a first terminal coupled to the voltage source, a second terminal coupled to switch 418, and a control terminal that receives signal V_ctrl 408. Comparator 424 has a first input coupled to the second terminal of current source gm_pfm 414 that receives signal V_timer_ramp 420. Comparator 424 has a second input that receives reference voltage V_ripple 436.

[0042] A capacitor 422C_pfm is coupled between a first input of a comparator 424 and a ground terminal. The comparator 424 provides at its output a signal Start_pfm_pulse 426 that is coupled to a control terminal of a switch 418. The switch 418 is coupled between the current source gm_pfm 414 and a ground terminal, and has a control terminal coupled to the output of the comparator 424. A capacitor C_pfm 422 is coupled between the first input of the comparator 424 and the ground terminal.

[0043] A digital-to-analog converter (DAC) 434 has an input that receives a digital signal Sel_i_ripple 432. In one example, digital signal Sel_i_ripple 432 includes six bits, although Sel_i_ripple 432 may include more or less than six bits in other examples. An output of DAC 434 is coupled to a second input of comparator 424 and to a control terminal of current source 438. DAC 434 provides at its output a signal V_ripple 436 that is a digital-to-analog conversion of Sel_i_ripple 432. Signal V_ripple 436 is also provided to a control terminal of current source 438. Current source 438 provides a current signal I_ripple 440.

[0044] The magnitude of V_CTRL 408 controls the magnitude of the current provided by current source gm_pfm 414 to charge capacitor C_pfm 422. The output of DAC 434, signal V_ripple 436, provides the reference voltage to which signal V_timer_ramp 420 is compared using comparator 424. Signal V_ripple 436 also controls the reference current level for the output current peak comparator. The reference current level is set by controlling the magnitude of the current provided by current source 438 as signal I_Ripple 440. The reference current level for I_peak is equal to the sum of I_ripple and I_CTRL. The value of I_CTRL defines the valley current level, and the value of I_ripple defines the current ripple across the comparator.

[0045] Signal V_ripple 436 is the output of DAC 434 and determines the peak current of the PFM pulse and provides the input to comparator 424. At its output, comparator 424 provides Start_pfm_pulse, which triggers each respective PFM pulse. The current ripple in PWM mode is measured, and the difference between the peak and valley values ​​is used to generate a reference voltage for comparator 424, allowing the PFM gain to remain constant under different operating conditions. The control loop gain can be designed to be the same in PFM mode as in PWM mode.

[0046] FIG. 5 shows a block diagram of an example buck power converter 500 having a PFM timing circuit with an adapted reference voltage. A switch clock generator 502 provides a clock signal Clk_SW, which is a first input to buck control logic 508. A second input to buck control logic 508 is Valley_Comp 504, which is the output signal of a current comparator that detects the zero current level in PFM mode. In PWM mode, a valley comparator defines the controlled valley current level. A third input to buck control logic 508 is Peak_comp 506, which is the output of a current comparator that detects the peak inductor current level. A fourth input to buck control logic 508 is signal Start_pfm_pulse 426. Buck control logic 508 may include digital logic gates or may be a processor or microcontroller.

[0047] A first output of the buck control logic circuit 508 is Buck_pwm 510, which is provided as a first input to the driver circuit 184. A second output of the buck control logic circuit 508 is Buck_hiz, which is provided as a second input to the driver circuit 184. A first output HS_CS 152 of the driver circuit 184 is coupled to a control terminal of the HS switch 120. A second output LS_CS 154 of the driver circuit 184 is coupled to a control terminal of the LS switch 128. The HS switch 120 is coupled to the LS switch 128 at a switching terminal SW 135. An inductor 136 couples the switching terminal SW 135 and the output voltage terminal V OUT 140. The output capacitor C OUT 144 is the output voltage terminal V OUT 140 and the ground terminal.

[0048] 6 shows a block diagram of an example circuit 600 for the buck control logic 508. The buck control logic 508 includes switch control circuitry 616, state machine circuitry 610, and ripple control circuitry 618. The switch clock signal Clk_SW is a first input to the switch control circuitry 616. The second input to the switch control circuitry 616 is Valley_Comp 504, and the third input to the switch control circuitry 616 is Peak_comp 506. The fourth input to the switch control circuitry 616 is the signal Start_pfm_pulse 426.

[0049] A first input of the state machine circuitry 610 is coupled to a third input of the switch control circuitry 616 and receives the Peak_comp 506 signal. A second input of the state machine circuitry 610 receives the signal PFM_Entry_Comp 608. A first output of the state machine circuitry 610 provides a signal PFM_Peak_Detection 614 to the ripple control circuitry 618. A second output of the state machine circuitry 610 provides a signal PFM_Mode 612, which is provided as a second input to the ripple control circuitry 618 and as a fifth input to the switch control circuitry 616.

[0050] State machine circuitry 610 is configured to receive Peak_comp 506 and PFM_entry_comp 608 and to provide a PFM mode signal PFM_mode 612 and a PFM peak detection signal PFM_peak_detection 614. Ripple control circuitry 618 is configured to receive PFM_peak_detection 614 and PFM_mode 612 and to provide a ripple control signal Sel_I_ripple 432. After PFM_peak_detection 614 is asserted, ripple control circuitry 618 periodically decreases the ripple control signal Sel_I_ripple 432 until signal PFM_mode 612 is asserted or PFM mode entry is canceled. Switch control circuitry 616 is configured to receive CLK_SW, Valley_comp 504, Start_pfm_pulse 426, Peak_comp 506, and PFM_mode 612, and to provide Buck_pwm 510 and Buck_hiz 520.

[0051] An input of the DAC 434 is coupled to the buck control logic circuit 508 and receives the ripple control signal Sel_I_ripple 432. In at least one example, the ripple control signal Sel_I_ripple 432 is a 6-bit digital word, although Sel_I_ripple 432 may be more or less bits in other examples. An output of the DAC 434 is coupled to a first input of the voltage-to-current (V2I) circuit 524.

[0052] The amplifier 306 has a first input coupled to a feedback voltage terminal that provides a feedback voltage V_fb 302. The feedback voltage V_fb 302 is a function of the output voltage V of the power converter. OUT 140. Amplifier 306 has a second input coupled to a reference voltage terminal that provides a reference voltage V_ref 304. Reference voltage V_ref 304 is coupled to an output voltage terminal V OUT140. Amplifier 306 has an output coupled to a second input of V2I circuit 524. Resistor 310 and capacitor 312 are coupled in series between the output of amplifier 306 and a ground terminal. PFM timer circuit 526 has first, second, and third outputs. The first and second outputs are coupled to the first and second inputs, respectively, of V2I circuit 524, and the third output provides Start_pfm_pulse signal 426.

[0053] Duplicating switch 530 includes LS duplicating switch 532 and HS duplicating switch 534. A first output of V2I circuit 524 is coupled to a first input of LS duplicating switch 532 and a first input of HS duplicating switch 534 and provides control signal I_CTRL 518. A second output of V2I circuit 524 is coupled to a second input of LS duplicating switch 532 and provides signal I_OFFSET 526. A third output of V2I circuit 524 is coupled to a second input of HS duplicating switch 534 and provides signal I_RIPPLE 528.

[0054] The HS replica switch 534 generates differential sense and reference signals HS_sw_sense 540 and HS_vdd_sense 542 based on the current through the HS switch 120 and the control signals I_CTRL 518 and I_RIPPLE 528. The control signals I_CTRL 518 and I_RIPPLE 528 generate a voltage drop across the HS replica switch 534, which is related to the voltage drop across the HS switch 120. The LS replica switch 532 generates differential sense and reference signals LS_sw_sense 536 and LS_gnd_sense 538 based on the current through the LS switch 128 and the control signals I_CTRL 518 and I_OFFSET 526. The control signals I_CTRL 518 and I_OFFSET 526 and the ramp signal from the artificial ramp circuit 522 generate a voltage drop across the LS replica switch 532, which is related to the voltage drop across the LS switch 128.

[0055] Artificial ramp circuit 522 has a first output coupled to a first input of duplicating switch 530 and a second output coupled to a second input of duplicating switch 530. The first output of duplicating switch 530 provides signal LS_sw_sense 536. The second output of duplicating switch 530 provides signal LS_gnd_sense 538. The third output of duplicating switch 530 provides signal HS_sw_sense 540. The fourth output of duplicating switch 530 provides signal HS_vdd_sense 542.

[0056] A comparator 544 has a first input coupled to the first output of duplicating switch 530 and receives signal LS_sw_sense 536. A second input of comparator 544 is coupled to the second output of duplicating switch 530 and receives signal LS_gnd_sense 538. An output of comparator 544 is coupled to a second input of buck control logic 508 and provides signal Valley_comp 504. A comparator 546 has a first input coupled to a third output of duplicating switch 530 and receives signal HS_sw_sense 540. A second input of comparator 546 is coupled to a fourth output of duplicating switch 530 and receives signal HS_vdd_sense 542. An output of comparator 546 is coupled to a third input of buck control logic 508 and provides signal Peak_comp 504.

[0057] The peak current through the HS switch 120 and the valley current through the LS switch 128 are measured while the power converter is operating in PWM mode before entering PFM mode. This information is provided to the buck control logic circuit 508, which generates the digital output Sel_i_ripple 432. The signal Sel_i_ripple 432 is provided as an input to the DAC 434. The value of Sel_i_ripple 434 is ramped down until the inductor current flowing through the HS switch 120, as measured by the HS replica switch 534 and comparator 546, is equal to the reference level I_peak 210. The output of the DAC 434 is provided as an input to the V2I circuit 524 and the PFM timer circuit 525.

[0058] When operating in PFM mode, when a Start_pfm_pulse occurs, the inductor current rises until it reaches a reference level I_peak 210 defined by the DAC 434, causing the Peak_comp signal 506 at the output of the comparator 546 to be asserted. In response to the inductor current reaching the level of I_peak 210, the inductor current begins to decrease. In response to the inductor current reaching a zero current level, the comparator 544 generates a signal Valley_Comp 504 at its output, which causes the buck control logic circuit 508 to generate the Buck_hiz signal 520 to be asserted. The assertion of Buck_hiz 520 places the output of the driver circuit 184 in a high impedance state, preventing current from flowing through the HS switch 120 and the LS switch 128. A subsequent Start_pfm_pulse 426 is triggered, and the PFM cycle repeats.

[0059] The input to DAC 434 determines the magnitude of I_Ripple 528, which controls the reference voltage level for comparator 546. The output of DAC 434 is used in the PFM timer to define the reference level for the timer comparator in PFM timer circuit 525, which affects the frequency of the PFM pulses. However, in at least one example, a separate DAC can be used for the PFM timer circuit reference level. Advantages that buck power converter 500 may offer include lower ripple on the output current and voltage signals, as well as better stability and cleaner transition switching between PWM and PFM modes.

[0060] In this description, the terms "terminal," "node," "interconnect," "lead," and "pin" are used interchangeably. Unless otherwise specified, these terms generally refer to an interconnection between or between the ends of device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0061] In this description, "ground" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description.

[0062] The term "couple" in this description may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform a certain action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0063] Although operations may be described in a particular order in this description, some operations may be optional and operations are not necessarily required to be performed in that particular order to achieve a particular result. In some embodiments, multitasking and parallel processing may be advantageous. Also, the separation of various system components in the above-described embodiments does not necessarily require such separation in all embodiments.

[0064] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. A circuit comprising: a comparator having first and second comparator inputs and a comparator output, the second comparator input being coupled to a ripple reference voltage terminal; a switch coupled between the first comparator input and a ground terminal, the switch having a switch control terminal coupled to the comparator output; a capacitor coupled between the first comparator input and the ground terminal; a first current source coupled between a supply terminal and the first comparator input, the first current source having a first current control terminal; a second current source coupled between the current output terminal and the ground terminal, the second current source having a second current control terminal; The circuit includes:

2. 10. The circuit of claim 1, further comprising a digital-to-analog converter (DAC) having a DAC input and a DAC output, the DAC input coupled to a ripple control signal terminal and the DAC output coupled to the second comparator input and the second current control terminal.

3. 3. The circuit of claim 2, further comprising a control logic circuit having first, second, and third control logic inputs and a control logic output, the first control logic input coupled to a clock source, the second control logic input coupled to the comparator output, and the control logic output coupled to the ripple control signal terminal.

4. 4. The circuit of claim 3, wherein the DAC input receives a digital ripple control signal from the ripple control signal terminal, and the DAC output provides an analog conversion of the digital ripple control signal.

5. 5. The control circuit of claim 4, wherein the digital ripple control signal comprises 6 bits.

6. 5. The circuit of claim 4, further comprising an amplifier having a first amplifier input and a second amplifier input, the first amplifier input coupled to a voltage regulator feedback terminal, the second amplifier input coupled to a voltage regulator reference terminal, and the amplifier output coupled to the first current control terminal.

7. 7. The circuit of claim 6, wherein the capacitor is a first capacitor, the circuit further comprising a resistor and a second capacitor coupled in series between the amplifier output and the ground terminal.

8. A control circuit comprising: a clock circuit having a clock output; a logic circuit having first, second, third, and fourth logic circuit inputs and first, second, and third logic circuit outputs, the first logic circuit input coupled to the clock output; a digital-to-analog converter (DAC) having a DAC input and a DAC output, the DAC input coupled to the first logic circuit output; a voltage-to-current converter (V2I) having first and second V2I inputs and first, second, and third V2I outputs, the first V2I input coupled to the DAC output; a timer circuit having first, second and third timer outputs, the first timer output coupled to the first V2I input, the second timer output coupled to the second V2I input, and the third timer output coupled to the third logic circuit input; an amplifier having first and second amplifier inputs and an amplifier output, the first amplifier input coupled to a voltage feedback terminal, the second amplifier input coupled to a voltage reference terminal, and the amplifier output coupled to the second V2I input; a control circuit.

9. 9. The control circuit of claim 8, further comprising a replication circuit having first, second, third, fourth, fifth, sixth, and seventh replication circuit inputs and first, second, third, and fourth replication circuit inputs; the first replica circuit input is coupled to the first V2I output, the second replica circuit input is coupled to the second V2I output, the third replica circuit input is coupled to the first V2I output, the fourth replica circuit input is coupled to the third V2I output, and the fifth replica circuit input is coupled to a ground terminal.

10. 10. The control circuit of claim 9, a first comparator having first and second comparator inputs and a first comparator output, the first comparator input coupled to the first replica circuit output, the second comparator input coupled to the second replica circuit output, and the first comparator output coupled to the second logic circuit input; a second comparator having third and fourth comparator inputs and a second comparator output, the third comparator input coupled to the third replica circuit output, the fourth comparator input coupled to the fourth replica circuit output, and the second comparator output coupled to the fourth logic circuit input; Further comprising: Control circuit.

11. 10. The control circuit of claim 9, further comprising a lamp circuit having first and second lamp terminals, the first lamp terminal coupled to the first replica circuit input and the second lamp terminal coupled to the second replica circuit input.

12. 11. The control circuit of claim 10, further comprising a driver circuit having first and second driver circuit inputs and first and second driver circuit outputs, the first driver circuit input coupled to the second logic circuit output and the second driver circuit input coupled to the third logic circuit output.

13. 13. The control circuit of claim 12, a high side transistor coupled between an input voltage terminal and a switching terminal, the high side transistor having a high side control terminal, the high side control terminal coupled to the first driver circuit output; a low-side transistor coupled between the switching terminal and a ground terminal, the low-side transistor having a low-side control terminal coupled to the second driver circuit output; Further comprising: the sixth replica circuit input is coupled to the switching terminal and the seventh replica circuit input is coupled to the input voltage terminal; Control circuit.

14. 14. The control circuit of claim 13, an inductor coupled between the switching terminal and an output voltage terminal; a capacitor coupled between the output voltage terminal and the ground terminal; a control circuit further comprising:

15. 14. The control circuit of claim 13, wherein the first comparator output is asserted when the current through the switching terminal drops to zero.

16. 16. The control circuit of claim 15, wherein the second comparator output is asserted when the current through the switching terminal reaches a peak value.

17. 9. The control circuit of claim 8, further comprising a resistor and a capacitor coupled in series between the amplifier output and a ground terminal.

18. 13. The control circuit of claim 12, wherein the driver circuit goes high impedance in response to a signal at the second driver circuit input.

19. 9. The control circuit of claim 8, wherein the signal at the first logic circuit output is a digital ripple control signal.

20. 20. The control circuit of claim 19, wherein the digital ripple control signal comprises 6 bits.

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