Systems and methods for signal modulation of a plurality of downlink signals representative of communication signal

Abstract

To provide systems and methods for modulating downlink signals representative of a communication signal.SOLUTION: A signal modulation method comprises: receiving an input signal; in a first one or more processing blocks in one or more processes 315, performing a first modulation operation on first data packets of the input signal based on a modulation scheme for a receiver of a downlink signal; in a second one or more processing blocks in one or more processors in parallel with the first one or more processing blocks, performing a second modulation operation on second data packets of the input signal based on the modulation scheme; and generating a waveform as the downlink signal based on performing the first and second modulation operations.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This disclosure relates to signal processing, and more particularly to implementing distributed computing using general-purpose processors to achieve high speed processing. [Background technology]

[0002] 2. Description of Related Art In some examples, satellite communication signals may require large ground stations and other facilities to transmit and / or receive and process data locally, which may include large antenna arrays, associated radio frequency terminals (RFTs), and significant electronic equipment (modems, signal processors, etc.) to receive data from associated satellites and process and use the received data. Summary of the Invention

[0003] The present disclosure provides an improved communication system. The following summary is not intended to define all aspects of the invention; other features and advantages of the disclosure will become apparent from the following detailed description, including the drawings. This disclosure is intended to be linked as an integrated document, and it should be understood that all combinations of features described herein are contemplated, even if the combinations of features are not found together in the same sentence or paragraph or section of the disclosure. Furthermore, the present disclosure includes, as an additional aspect, all embodiments of the invention that are narrower in scope in any respect than the variations specifically mentioned herein.

[0004] As disclosed herein, digital signal processing (DSP) can be performed in many different ways using a general purpose processor or a central processing unit (CPU). Examples of techniques implemented on a general purpose processor to achieve high speed processing capable of performing the disclosed functions include: Using multiple CPUs to process data in parallel across multiple cores on each CPU, Employing Single Instruction Multiple Data (SIMD) technology; Feed-forward processing to break the feedback loop; Pre-computing metadata (or state information) to split the heavy lifting among several CPUs, Combining multiple functions into a single function in a way that improves CPU performance or reduces memory bandwidth usage, and These include, but are not limited to:

[0005] One way to improve the throughput of a general-purpose CPU is to utilize as many cores as possible on the CPU. Adding more CPU cores can improve processing throughput, although careful attention must be paid to ensuring that data is shared appropriately between the several cores within a CPU. It is also possible to use several CPUs on the same system, with each CPU containing multiple cores. All embodiments within this disclosure take advantage of using multiple cores within a CPU, and some embodiments take advantage of having multiple CPUs per system and / or even per system in a server environment.

[0006] Another way to achieve high processing speeds is to take advantage of the single instruction, multiple data (SIMD) capabilities of general-purpose CPUs. This allows a single CPU core to perform up to 16 floating-point operations with a single instruction, as with AVX512 SIMD operations. One example of employing SIMD is using a finite impulse response (FIR) filter function, which calculates 16 floating-point results at once. Another example is multiplying complex numbers. Instead of calculating one pair of quadrature signals (IQ data), AVX512 allows for the calculation of eight IQ pairs at once. Complex multiplication is used in nearly all of the processing algorithms described in this disclosure.

[0007] Some processing systems implement various forms of feedback, often involving phase-locked loops (PLLs) or delay-locked loops (DLLs). However, as with PLLs and DLLs, feedback can generally be problematic because the very nature of the feedback creates a bottleneck. The feedback loop forces all incoming data to be processed through a single (e.g., linear) process that cannot be easily divided or otherwise separated. In addition to feedback, there are other obstacles to overcome using PLLs and DLLs, including the frequency with which the error term is calculated. The feedback loop can be replaced with a feedforward loop. In a feedforward loop, an error condition is processed on a block of data, and then the calculated error term is fed forward to another block that applies the error term. With appropriate overlap, the error calculation and application can be split across several CPU cores to further improve throughput. An example of this is in a diversity combiner, where timing and phase corrections are calculated in one block, timing adjustments are applied in another block, and phase corrections are applied in yet another block. This method can be parallelized across several CPU cores as a set to further improve throughput.

[0008] In addition to the feedforward approach to processing data, it can also be beneficial to perform metadata precalculation in a single block and then split the processing of the data across several CPU cores. This method is similar to the feedforward method already described, but in this case, rather than breaking the loop (e.g., a feedback loop), it simply leverages more CPU cores to increase the amount of data that can be processed. In this way, the block performing the precalculation does not perform CPU-intensive processing, but instead calculates the necessary steps, such as iterations in a for loop, the starting index, and the slope point between interpolated phase values. One such example is Doppler compensation performed in a diversity combiner. The necessary phase adjustments are made in the first block, but the CPU-intensive calculations to perform the phase adjustments are handed off to subsequent downstream blocks. If the second part of the processing is CPU-intensive, this allows for the utilization of any number of CPU cores, thereby increasing processing speeds that would otherwise be unachievable within a single block.

[0009] Another technique that can be employed in general-purpose CPUs to achieve high throughput is the use of function sets and memory types used. In some cases, memory bandwidth is the limiting factor for performance. In this case, the objective is to limit the amount of data that needs to be transferred to and from random access memory (RAM) (as opposed to faster memory such as the CPU cache). To do this, functions must be collapsed so that they are executed all together instead of individually, with the goal of requiring as few accesses to the slower RAM as possible compared to accesses to the faster CPU cache. Another way to reduce memory bandwidth is to utilize well-spaced memory types, for example, using int8 instead of float or double when possible.

[0010] In one embodiment, provided herein is a method for modulating a plurality of downlink signals representing communication signals, the method including receiving an input signal, performing, in one or more first processing blocks within one or more processors, a first modulation operation on first data packets of the input signal based on a modulation scheme for a receiver of the downlink signals, performing, in parallel with the one or more first processing blocks, in one or more second processing blocks within the one or more processors, a second modulation operation on second data packets of the input signal based on the modulation scheme, and generating a waveform as the downlink signal based on performing the first and second modulation operations.

[0011] In another embodiment, a system for modulating a plurality of downlink signals representing a communication signal is provided, the system including at least one memory configured to store instructions and one or more processors communicatively coupled to the at least one memory, the one or more processors having a plurality of processing blocks, the one or more processors operable to execute instructions for performing the above-described method.

[0012] In another embodiment, an apparatus is provided for modulating a plurality of downlink signals representing communication signals, the apparatus including: means for receiving an input signal; one or more means for performing a first modulation operation on first data packets of the input signal based on a modulation scheme for a receiver of the downlink signals; one or more means for performing a second modulation operation on second data packets of the input signal based on the modulation scheme, the one or more means for performing the second modulation operation operating in parallel with the one or more means for performing the first modulation operation; and means for generating a waveform as the downlink signals based on performing the first and second modulation operations.

[0013] The details of the present invention, both as to their structure and operation, can be gleaned in part from study of the accompanying drawings, in which like reference numerals refer to like parts and in which: [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a graphical representation of an example of a communication system according to embodiments disclosed herein. [Figure 2] 2 is a functional block diagram of a wired or wireless communication device for use as one or more components of the system of FIG. 1. [Figure 3] 1 is a graphical representation of an example of feedforward or pre-computed signal processing according to embodiments disclosed herein. [Figure 4] 1 is a graphical representation of another example of feedforward or pre-computed signal processing according to embodiments disclosed herein. [Figure 5] FIG. 2 is a functional block diagram of an example digital signal diversity combiner according to embodiments disclosed herein. [Figure 6] FIG. 2 is a functional block diagram of another example of a digital signal diversity combiner according to embodiments disclosed herein. [Figure 7] FIG. 2 is a functional block diagram of an example timing and carrier recovery method according to embodiments disclosed herein. [Figure 8] FIG. 10 is a functional block diagram of another example timing and carrier recovery method according to embodiments disclosed herein. [Figure 9] FIG. 2 is a functional block diagram of an example of a channel simulator, according to embodiments disclosed herein. [Figure 10] FIG. 2 is a functional block diagram of an example signal modulator according to embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0015] Disclosed are embodiments of an improved communications system that uses a general-purpose processor to achieve high-speed processing. The embodiments disclosed herein provide an improved communications system that can efficiently achieve high-speed signal processing by utilizing a general-purpose processor. After reading this description, it will become apparent to one skilled in the art how the invention can be implemented in various alternative embodiments and applications. However, while various embodiments of the present invention are described herein, it is understood that these embodiments are presented by way of example and illustration only, and not limitation. As such, this detailed description of various embodiments should not be construed as limiting the scope or breadth of the present invention, as set forth in the appended claims.

[0016] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0017] Although communication systems are used as the primary example throughout the description, the application of the disclosed methods is not limited thereto. For example, any wireless or radio communication system requiring the use of digital signal processing, modems, etc. may implement the systems, methods, and computer-readable media described herein.

[0018] This disclosure provides systems and methods for performing digital signal processing using general-purpose central processing units (CPUs) in either standard server or virtual cloud environments. In some examples, the systems can employ single-instruction, multiple-data (SIMD) techniques to achieve high throughput, including SSE, SSE2, SSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX512 instruction sets. This disclosure describes how data processing is managed across multiple processing cores of a processor (e.g., a CPU) to achieve the required throughput without the use of specialized signal processing hardware, such as a field-programmable gate array (FPGA), or high-performance computing (HPC) hardware, such as a graphics processing unit (GPU). Because this processing can be performed on general-purpose server CPUs, including, but not limited to, x86 architectures from Intel and AMD microprocessors, as well as ARM processors such as Cortex-A76, NEON, and AWS Graviton and Graviton2, these functions can be deployed within general-purpose cloud processing environments using virtualized processing architectures without the need for specialized hardware. Processing by a general-purpose CPU is made possible by a digital IF appliance that samples the analog signal and provides the digitized samples to the CPU via an Ethernet connection. The digital IF appliance can also accept digitized samples and convert them to an analog signal, similar to that described in U.S. Patent No. 9,577,936, entitled "Packetized Radio Frequency Transport System," issued February 21, 2017, the contents of which are incorporated by reference in their entirety.

[0019] 1 is a graphical representation of one embodiment of a communications system. Communications system (system) 100 may include a platform 110 and a satellite 111 communicating with multiple ground stations. Platform 110 may be an aircraft (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV), missile, boat, etc.). Multiple ground stations 120, 130, 140 may be associated with a terrestrial radio frequency (RF) antenna 122 or one or more satellite antennas 132, 142. Ground station 120 may include an antenna 122 coupled to a digitizer 124. Digitizer 124 may include one or more analog-to-digital (A2D) converters for converting analog signals received at antenna 122 into a digital bit stream for transmission over a network. Digitizer 124 may also include corresponding digital-to-analog (D2A) converters for operation in the uplink to platform 110 and satellite 111.

[0020] Similarly, ground station 130 may have an antenna 132 and a digitizer 134 , and ground station 140 may have an antenna 142 and a digitizer 144 .

[0021] In the receive chain, ground stations 120, 130, and 140 can receive downlink signals 160 (labeled 160a, 160b, and 160c) from platform 110 and downlink signals 170 (labeled 170a, 170b, and 170c) from satellite 111, respectively. In the transmit chain, ground stations 120, 130, and 140 can also transmit uplink signals via antennas 122, 132, and 142, respectively. Digitizers 124, 134, and 144 can digitize the received downlink signals 160 and 170 as digital bitstream 154 for transmission. Digital bitstream 154 can then be transmitted to a cloud processing system via network 152.

[0022] In some examples, the ground stations 120, 130, 140 can process all data (e.g., contained in the downlink signal) locally, but this can be very expensive in terms of time, resources, and efficiency. Therefore, in some embodiments, the downlink signal can be digitized and transmitted as a digital bit stream 152 to a remote signal processing server (SPS) 150. In some implementations, the SPS 150 can be located in a physical location, such as a data center located in an off-site facility accessible via a wide area network (WAN). Such a WAN can be, for example, the Internet. The SPS 150 can demodulate the downlink signal from the digital bit stream 152 and output data or information bits from the downlink signal. In some other implementations, the SPS 150 can use cloud computing or cloud processing to perform the signal processing and other methods described herein. The SPS 150 can also be referred to as a cloud server.

[0023] The SPS 150 can then provide the processed data to a user or transmit it to another site. The data and information can be mission dependent. Additionally, the information contained in the data can be the primary purpose of the satellite, including weather data, image data, and satellite communications (SATCOM) payload data. As noted above, although SATCOM is used as the primary example herein, any communications or signal processing system that uses a DSP can implement the methods described herein.

[0024] To achieve high processing speeds in software, a phase-locked loop (PLL) or delay-locked loop (DLL) approach can be problematic due to feedback within the loop. The feedback loop forces all incoming data (e.g., downlink signals 160 and / or 170) to be processed by a single (e.g., linear) process that cannot be easily divided or otherwise separated. In addition to feedback, there are other obstacles to overcome using a PLL / DLL, including the frequency at which error terms must be calculated.

[0025] Figure 2 is a functional block diagram of a wired or wireless communication device for use as one or more components of the system of Figure 1. Processing device (device) 200 may be implemented, for example, as SPS 150 of Figure 1. Device 200 may be implemented as needed to perform one or more of the signal processing methods or steps disclosed herein.

[0026] The device 200 may include a processor 202 that controls operation of the device 200. The processor 202 may also be referred to as a CPU. The processor 202 may, for example, direct and / or execute functions attributed to the SPS 150. Certain aspects of the device 200, including the processor 202, may be implemented as various cloud-based elements, such as cloud-based processing. Thus, the processor 202 may represent cloud processing distributed across several different processors over a network (e.g., the Internet). Alternatively, certain components may be implemented in hardware. The processor 202 may be implemented by any combination of one or more of a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gate logic, discrete hardware components, a dedicated hardware finite state machine, or any other suitable entity capable of performing calculations or other manipulations of information.

[0027] The processor 202 may have one or more cores 204 (illustrated as core 204a through core 204n) capable of performing calculations. In implementations using cloud processing, the cores 204 may represent multiple iterations of distributed cloud processing. In some embodiments, the processor 202 may be a complex integrated circuit that performs all calculations for the receiver using hardware. As used herein, each core 204 may be one processing element of the processor 202. The processor 202 may implement multiple cores 204 to perform the parallel processing required for the methods disclosed herein. In some embodiments, the processor 202 may be distributed across multiple CPUs, such as in cloud computing.

[0028] The device 200 may further include a memory 206 operably coupled to the processor 202. The memory 206 may be cloud-based storage or local hardware storage. The memory 206 may include both read-only memory (ROM) and random access memory (RAM) and may provide instructions and data to the processor 202. A portion of the memory 206 may also include non-volatile random access memory (NVRAM). The processor 202 typically performs logical and arithmetic operations based on program instructions stored in the memory 206. The instructions in the memory 206 may be executable to implement the methods described herein. The memory 206 may further include removable media or multiple distributed databases.

[0029] The memory 206 may also include a machine-readable medium for storing software. Software shall be broadly construed to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or the like. The instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable code format). The instructions, when executed by the processor 202 or one or more cores 204, cause the device 200 (e.g., the SPS 150) to perform various functions described herein.

[0030] The device 200 may also include a transmitter 210 and a receiver 212 that enable transmission and reception of data between the communication device 200 and a remote location. Such communications may occur, for example, between the ground station 120 and the SPS 150 over the network 152. Communications such as these may occur wirelessly or via wired communications. The transmitter 210 and the receiver 212 may be combined into a transceiver 214. The transceiver 214 may be communicatively coupled to the network 152. In some examples, the transceiver 214 may include or be part of a network interface card (NIC).

[0031] Device 200 may further include a user interface 222. User interface 222 may include a keypad, a microphone, a speaker, and / or a display. User interface 222 may include any element or component that conveys information to and / or receives input from a user of device 200.

[0032] The various components of device 200 described herein may be coupled together by a bus system 226. The bus system 226 may include, for example, a power bus, a control signal bus, and a status signal bus in addition to a data bus. In some embodiments, the bus system 226 may be communicatively coupled to the network 152. The network 152 may provide, for example, a communications link between the device 200 (e.g., the processor 202) and the ground station 120. Those skilled in the art will understand that the components of device 200 may be coupled together or may accept or provide input to each other using some other mechanism, such as a local area network or a wide area network for distributed processing.

[0033] 3 is a schematic block diagram graphical depiction of one embodiment of feedforward or pre-computed signal processing 300. Method 300 can be performed as a generalized process incorporating multiple functions, for example, by processor 202. Processor 202 can execute multiple functions in a serial or parallel arrangement, as shown, to perform one or more desired processes. Each function may refer to a block or collection of instructions or software executable by processor 202 and stored in memory 206.

[0034] The first function 302 may be executed by the processor 202. In some embodiments, the second function 304 may be executed serially following the first function 302. Thus, the processor 202 may divide blocks of data having different functions for processing across multiple cores 204 to execute the first function 302 and the second function 304.

[0035] The processor 202 can perform distributed processing of the third function 306 (illustrated as 306a, 306b, ... 306n) in parallel, following the second function 304. To indicate that various numbers of functions 306a-306n may operate in parallel, three paths are depicted with three dots vertically between them, indicating that any number of paths may be included, such as, but not limited to, four, five, six, etc. Parallel processing of the third function 306 may include, for example, dividing blocks of data associated with the same function across several cores 204 (e.g., processing blocks) of the processor 202. For example, a "block of data" may refer to a group of samples that need to be processed.

[0036] The term "parallel" is used herein to describe processing occurring simultaneously in blocks 306a-306n. Because packets being processed may be of different lengths from one block 306a-306n to another, processing of packets may have the same rate or speed from one block 306a-306n to the next. As shown below, some of the blocks 306a-306n may proceed faster or slower than other blocks. Thus, the term parallel should not be limited to simultaneous or concurrent processing within blocks 306a-306n.

[0037] The processor 202 can then serially execute the fourth function 308 and the fifth function 309. Similar to the first function 302 and the second function 304, serial performance of the fourth function 308 and the fifth function 309 can include dividing up blocks of data associated with different functions for processing across multiple cores 204. Generally, each of the first function 302, the second function 304, the third function 306, the fourth function 308, and the fifth function 309 can be executed in a different processing block. As used herein, a processing block can refer to a particular task performed on a block of data. A processing block can be associated with one or more cores 204, for example.

[0038] Thus, method 300 may, for example, divide blocks of data having the same function for processing across multiple cores 204. Similarly, method 300 may divide blocks of data having different functions for processing across multiple cores 204.

[0039] In some other implementations of method 300, the same processing block (e.g., core 204), whether for the same or different functions, may perform single instruction multiple data (SIMD) processing of data.

[0040] In other implementations, embodiments of method 300 can support processing of data blocks with minimal state information by using overlapping data. As used herein, state information can include variables needed during feedback (e.g., feedback processing), data frame boundaries, etc. For example, in the case of a feedback loop, the state information can include variables calculated within the loop needed during feedback when processing a continuous data stream. The state information can also include the location of frame boundaries within the data stream. Other examples can include things like FIR filters, whose state information includes buffered values ​​(e.g., potentially many delay elements) needed to maintain a continuous data flow.

[0041] By ignoring state information and overlapping portions of adjacent data blocks, processes can use variable levels of overlap between data blocks to exploit parallelism.

[0042] FIG. 4 is a graphical depiction of one embodiment of the method for feedforward or pre-computed signal processing of FIG. 3. Method 400 can use the principles of method 300 for serial-parallel and / or parallel-serial processing into multiple functions grouped as processes 315. In one example, first function 302 (FIG. 3) can be data capture function 305, where processor 202 receives data for processing. Second function 304 (FIG. 3) can be data partitioning function 310, where processor 202 can parse data in overlapping data blocks. The overlapping data blocks can then be processed in parallel in various parallel iterations of multiple functions as processing blocks 315a-315n. For example, a first data block can be processed by a group of functions in processing block 315a, and another data block can be processed by a group of functions in another processing block 315b-315n executed in parallel with processing block 315a. Multiple processing blocks 315a-315n can be executed in parallel and are not limited to two such processing blocks. Duplication in data blocks can provide a level of redundancy that relies less (or even at all) on state information. The less state information required, the easier it is to process data blocks in parallel as opposed to a continuous stream. To indicate that various numbers of processing blocks 315a-315n can operate in parallel, three paths are depicted with three dots vertically between them, indicating that any number of paths may be included, such as, but not limited to, four, five, six, etc.

[0043] The term "parallel" is used herein to describe processing occurring simultaneously in processing blocks 315a-315n. Because processed packets may be of different lengths from one processing block 315a-315n to another, processing of packets may have the same rate or speed from one processing block 315a-315n to the next. As shown below, some of the blocks 315a-315n may proceed faster or slower than other blocks. Thus, the term parallel should not be limited to simultaneous or parallel processing within processing blocks 315a-315n.

[0044] The method 400 may further include a data combining function 320, similar to the fourth function 308 (FIG. 3), that combines the processed data, and a data output function 325, similar to the fifth function 309 (FIG. 3).

[0045] In a further example, the adjustable series-parallel or parallel-series arrangement of the various functions of method 300 provides several ways of implementing feedforward processing to replace feedback loops, which is advantageous because it can increase throughput and avoid bottlenecks caused by delays in feedback processing.

[0046] An additional advantage of the serial-parallel or parallel-serial processing provided by method 300 and method 400 is that placing one or more desired algorithms within a processing block (e.g., one of the five processing blocks of method 300) allows processor 202 to distribute the processing load (e.g., across multiple cores 204) without concern for the speed of a given algorithm within a processing block (e.g., core 204). Thus, each core 204 shares the exact same processing load, eliminating bottleneck problems caused by individual algorithms.

[0047] Further advantages of embodiments of method 300 may include customizing the ordering of specialized algorithms (e.g., processing blocks) to reduce computational load within processor 202. As described below, the overall multi-step processing of a given process may not depend on the ordering of multiple sub-processes. Thus, in some examples, ordering fourth function 308 may have particular advantages if it is performed before third function 306.

[0048] The method 300 can further implement different variable types, such as int8, int16, and float, for memory bandwidth optimization, which can accelerate certain algorithms (e.g., type-based algorithms), and can further improve flexibility and maximize memory bandwidth.

[0049] 5 and 6 are functional block diagrams of embodiments of a digital signal diversity combiner. Diversity combining methods 500 and / or 600 may include feedforward block processing as described above in connection with FIGS. 3 and 4. Methods 500 and / or 600 may include multiple blocks. In some examples, each block represents a functional block and may perform a function in a manner similar to functional blocks 306a, 306b, ... 306n (FIG. 3), etc. In another example, two or more of the multiple blocks in FIGS. 5 and / or 6 may be grouped together as a single "process" 315 that performs a function in a manner similar to processing blocks 315a, 315b, ... 315n (FIG. 4), etc.

[0050] Figure 9 is a functional block diagram of one embodiment of a channel simulator. The channel simulation method 900 may include feedforward block processing as described above in connection with Figures 3 and 4. The method 900 includes multiple blocks. In some examples, each block represents a functional block and may perform a function in a manner similar to functional blocks 306a, 306b, ... 306n (Figure 3), etc. In another example, two or more of the multiple blocks in Figure 9 may be grouped together as a single "process" 315 that performs a function in a manner similar to processing blocks 315a, 315b, ... 315n (Figure 4), etc.

[0051] Figure 10 is a functional block diagram of an embodiment of a signal modulator for waveform generation. The signal modulation method 1000 includes feedforward block processing as described above in connection with Figures 3 and 4. The method 1000 includes multiple blocks. In some examples, each block represents a functional block and may perform a function in a manner similar to functional blocks 306a, 306b, 306n (Figure 3), etc. In another example, two or more of the multiple blocks in Figure 10 may be grouped together as a single "process" 315 that performs a function in a manner similar to processing blocks 315a, 315b, ... 315n (Figure 4), etc.

[0052] In block 305, the SPS 150 may capture or otherwise receive (e.g., over the network 152) the digital bitstream 152. The data capture in block 305 may receive the digital bitstream data from a network connection (e.g., Ethernet).

[0053] In block 310, the data can be split into parallel data streams by a data splitter. In some embodiments, the processor 202 can perform the data splitting function required in block 310. In some other embodiments, a separate data splitting component (e.g., a data splitter) can be included in the device 200 (FIG. 2). Splitting the data into multiple parallel streams allows for parallel processing of downlink signals, such as downlink signals 160, 170. Thus, the method 300 can utilize feedforward or pre-computation processing to split the incoming digitized signal data into smaller portions before processing by multiple cores 204. The digital bit stream 152 can be split to form overlapping packets in in-phase / quadrature (I / Q) pairs. In some embodiments, "overlapping packets" can include data packets where successive packets overlap with adjacent data packets. In some embodiments, the data packets may all be the same length, but may overlap. The overlap in a data packet can be at the beginning or end of the data packet. Furthermore, a data packet can overlap with both a preceding data packet and a following data packet. The data packets may also have different lengths (e.g., varying amounts of data), and thus a first packet sent to processing block 315a may overlap or otherwise repeat certain data in a second packet sent to processing block 315b.

[0054] The amount of overlap, or overlap size, between packets is programmable and can be set as needed. In some examples, the overlap can be set to one percent (1%) of the packet size. This overlap size can be increased or decreased as needed. For example, one particular parameter that can affect the overlap size is the uncertainty in the symbol rate in the digital bit stream 152. For most signals, the worst-case uncertainty is less than 1%, so a 1% overlap covers most cases. In some other embodiments, the overlap can be as high as 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%, or anywhere in between, as needed. It is also possible to have an overlap of less than 1% as well. If the uncertainty in the data rate is less than 0.1%, the overlap can be 0.1% or less.

[0055] The processor 202 can implement single instruction, multiple data (SIMD) processing on the digital bitstream 152. In some examples, SIMD can include Advanced Vector Extensions (AVX-512) using 512 bits, enabling 16 floating-point operations on a single CPU core with a single CPU instruction. For example, AVX-512 enables a CPU (e.g., CPU 202) to process vast amounts of data. For example, the processor 202 (and device 200) can receive a data stream with a 500 MHz bandwidth. The 500 MHz bandwidth is significant in some respects because it is the generally accepted practical limit for a 10 Gigabit Ethernet link. Using 8-bit samples for the I / Q pairs, sampling data including parity bits at 500 MHz could saturate a 10 Gigabit Ethernet link. The 500 MHz example is not intended to limit the present disclosure. Data pipes larger than 10 Gigabit Ethernet links are possible. Furthermore, the process can be divided into n parallel blocks (eg, block 315) to accommodate any amount of data.

[0056] Process 315 is shown with dashed lines and illustrates processing steps of method 300. Process 315 is shown to be performed in multiple parallel steps or processing blocks 315a, 315b, ... 315n.

[0057] As used herein, a process 315 may refer to a collection of processing functions performed by, for example, the processor 202. The digital bitstream 152 may be split and sent to multiple parallel processing blocks 315a, 315b, ... 315n to distribute the processing load across several cores 204. Each individual processing block 315a, 315b, ... 315n may represent an individual iteration of cloud processing. Thus, each processing block 315a-315n may be associated with a (cloud-based) core 204a-204n. The number of processing blocks 315a-315n required varies based on the amount of data to be processed. In some embodiments, the number of processing blocks 315a-315n may be limited by the number of available logical cores, either over the network 152 or within the processor 202 in the case of local hardware processing. In other embodiments, memory bandwidth constraints may cause bottlenecks during signal processing. Memory bandwidth may refer to the rate at which data can be read from or stored into a semiconductor memory (eg, memory 206) by a processor (eg, processor 202).

[0058] In some embodiments, the number of processing blocks 315a-315n can vary. Generally, the fewer processing blocks 315a-315n there are, the more appropriate it is to limit the number of cores required for the overall process. This further enables the system to fit into smaller virtual private cloud (VPC) machines, which are less expensive to operate. A VPC may include, for example, an SPS 150 with several CPUs. In some embodiments, eight processing blocks 315a-315n can be used for a 10 Gbit Ethernet link. Such an embodiment may not include a forward error correction processing block. In other embodiments, the only practical limit on the number of processing blocks 315a-315n required is the bit rate and bandwidth (e.g., pipe size) of the communications link. Thus, any number (n) of processing blocks 315a-315n is possible. However, in some embodiments, there may be a practical limit on the number (n) of processing blocks 315a-315n based on the number of threads that can be executed on a CPU or the number of cores 204 in the processor 202. However, if limitations are reached within a single CPU, multiple CPUs (e.g., processors 202) within the SPS 150 (e.g., VPC) together can have an unlimited number of cloud-based CPUs or cores 204 to perform processing. Additionally, processor 202 can create new processing blocks 315a-315n as needed. Processing cores 204 can be distributed across multiple distributed processors (e.g., processors 202) as needed for throughput and efficiency.

[0059] The processing blocks 315a-315n are arranged in such a way that it does not matter which processing block 315a, 315b, ... 315n executes slowest (or fastest). Because method 300 can share the processing load across processing blocks 315a-315n, it can mitigate any processing delays caused by bottleneck issues in individual processing blocks 315a-315n. For example, the individual subprocesses of processing blocks 315a-315n (see the description of FIG. 4 below) may not execute (e.g., some faster than others) or may execute at equal rates. Thus, for example, the larger process of method 400 (FIG. 4) can account for variations in performance or processing time. Processing blocks 315 can be created as many times as needed to process incoming data.

[0060] In some embodiments, each processing block 315a-315n may represent a collection of signal processing algorithms executed by processor 202. As used herein, an algorithm may refer to the smallest collection of functions or method steps that perform a desired function. Several exemplary algorithms are described herein.

[0061] An exemplary advantage of method 300 is the ability to create more processing blocks 315a-315n as needed. Generally, processing blocks 315a-315n can be implemented in software and therefore can be created or removed as needed to suit a given data rate or processing load. Each processing block 315a-315n can be rearranged to suit the needs of different received waveforms (e.g., downlink signals 160 and / or 170) and associated digital bitstreams 154.

[0062] In block 320, the processed signal data from the multiple processing blocks 315 may be recombined to form the original data that is encoded and modulated on the downlink signals 160, 170. In some embodiments, the processor 202 may perform the function of a data recombiner. In other embodiments, the device 200 may have additional components for performing such functions. Each data packet or processed data block may have a timestamp. A data recombiner (e.g., the processor 202) may order the data blocks based on the timestamp and compare the phase between the ordered blocks. The recombiner may further adjust the phase of adjacent blocks to reorder the data stream. In some embodiments, the phase of a subsequent data block may be adjusted to match the phase of a preceding data block.

[0063] Every processing block shown in process 315 has at least four options for execution: 1) execution of multiple blocks, where each sub-element within a processing block 315 (e.g., each block 315a-315n) gets its own core (e.g., cores 204a-204n); 2) execution of multiple blocks, where processing block 315 gets only one dedicated core for the entire block; 3) single block execution, where each sub-element within the processing block gets its own core; and 4) Single block execution, where the processing block gets only one dedicated core for the entire block.

[0064] The more cores you can run on, the higher the rate you can achieve.

[0065] In block 325, the device 200 may output the data to an appropriate receiver. In some examples, such receivers may be one or more mission operations centers. This data may be mission dependent (e.g., satellite objectives) and may include weather data, image data, and SATCOM payload data, among others.

[0066] In a general-purpose CPU, there are at least three main factors that can limit high-rate performance: 1) data ingestion, 2) CPU capacity, and 3) memory bandwidth utilization. Data ingestion refers to how quickly data can be supplied to the CPU. CPU capacity is determined by the CPU clock speed and the number of cores in the CPU. Memory bandwidth refers to how quickly data can be transferred between the CPU and external DDR RAM (not the CPU cache). Memory bandwidth may be determined by the number of memory lanes and the clock speed of the DDR RAM. In certain cases, the limiting factor for achieving high-rate processing is CPU capacity, while in other cases it is memory bandwidth. Care must be taken to determine which of the above cases is affecting performance and whether memory bandwidth is limited, and the embodiments described below are non-limiting examples of how memory bandwidth utilization can be reduced within the proposed patented approach.

[0067] Function calls within a given processing block can be arranged in a manner that optimizes CPU computation or memory bandwidth utilization. For example, referring to the function calls (illustrated as blocks) shown in FIG. 5, in the given example, the various function calls (e.g., timing recovery block, carrier recovery block, correlator block, time adjustment block, phase rotation block, power and Es / No estimator block, amplitude adjustment block, and weighted combiner block) can be grouped in a manner that minimizes memory bandwidth. These function calls can be called independently, simplifying each function by completing each function on the data set before starting another function. In another example, multiple or all function calls can be combined into a single block, so that data is not transferred to RAM after each function is executed, resulting in much smaller memory bandwidth for the combined function before being called independently. When functions are called independently, the first function call (e.g., timing recovery) may be performed across the entire data set before the second function call (e.g., correlator) occurs. In the case of combination, only a portion of the data is processed during the first function call before the second function call is executed. In this way, memory bandwidth is reduced. This method can be applied to any grouping of functions, not just the functions shown in Figure 5. For example, this method may be applied to the method shown in Figure 6, or to any other grouping of function calls executed within the blocks disclosed herein (e.g., the various function call blocks shown in Figures 7-10).

[0068] Another way to improve memory bandwidth utilization may be to collapse several function call blocks into one block, similar to the approach above. For example, as described in more detail below with reference to FIG. 5, multiple functions may be required to perform timing and carrier recovery. Typically, for ease of operation and CPU optimization, each function requires its own block, but to reduce memory bandwidth utilization, all functions can be synthesized into one processing block. This tradeoff results in reduced memory bandwidth utilization for a CPU performance hit.

[0069] A post-digital signal detection diversity combiner that employs parallel processing across multiple cores to run on a general-purpose CPU and achieve high-throughput operation in cloud environments: As mentioned above, FIGS. 5 and 6 are functional block diagrams of exemplary implementations of methods 500 and 600. In various examples, each of methods 500 and 600 may be an example of a diversity combiner method. To indicate that various numbers of signals may be processed in parallel, two paths are depicted with three dots vertically between them, indicating that any number of paths, such as four, eight, etc., may be used. Diversity combining may be used to optimize the transfer of combined information to multiple input signals A through N by combining multiple antenna feeds together such that all signals are aligned in time and phase and weighted based on signal quality. Signal quality may be determined using one or more of, for example, but not limited to, a signal-to-noise ratio, an energy-to-noise power spectral density ratio per symbol (Es / N0), a power estimate, a received signal strength indicator (RSSI), etc. The multiple antenna feeds may be from one or more remote locations, such as the platform 110 or a satellite 111. Although satellites are used herein as an example, other wireless transmission systems may be implemented, such as radio antennas (e.g., antenna 122) or other types of transmitters, and therefore the use of satellites is not intended to limit the present disclosure.

[0070] For satellites such as those shown in FIG. 1, diversity combining can be used during an antenna handover event even if platform 110 and satellite 111 are visible from the same ground station (e.g., ground station 122), but, for example, satellite 111 is below the horizon (e.g., in the east) and platform 110 is rising above the horizon (e.g., in the west). To properly combine the downlink signals, several calculations must be performed. The disclosed system can digitize the signals and convert them to digital samples, which are then transported to a signal processing element. The system can also calculate and compensate for Doppler effects. The system can also determine the residual phase and frequency delta (e.g., difference) between the downlink signals, as well as the time difference and estimated signal-to-noise ratio of each signal. Following these operations, the signals are combined together.

[0071] There are many approaches that can be used to combine signals. For example, signals may be combined using a pre-detection (Pre-D) diversity combiner and / or a post-detection (Post-D) diversity combiner. A Pre-D diversity combiner may be configured to combine signals before performing a match filter (e.g., also called a detector). An exemplary implementation of a Pre-D diversity combiner is described in PCT / US2020 / 65351, the disclosure of which is incorporated herein by reference in its entirety. A Post-D diversity combiner may be configured to combine signals after the match filter function is completed. Thus, a Post-D diversity combiner may offer a simplified method for performing diversity combining over Pre-D methods because the signals and data packets are discrete digital samples. Therefore, the functions and complexity may be reduced compared to a Pre-D diversity combiner. For example, Post-D may be simpler because it is performed after the match filter and the combining is performed in the symbol space. That is, time adjustment can be done in only one whole symbol step, no sub-sample adjustment is required, which is not the case for Pre-D.

[0072] Implementations of a Post-D diversity combiner can include a Post-D End (referred to herein as Post-DE, an illustrative example of which is shown in FIG. 5 ) and a Post-D Mid (referred to herein as Post-DM, an illustrative example of which is shown in FIG. 6 ). As used herein, Post-DE may refer to a combiner in which signals are combined after match filtering has been performed, e.g., after full demodulation, including carrier and timing recovery. That is, combining in a Post-DE method occurs after both timing recovery and carrier recovery are locked. As used herein, the term “locked” refers to error-free demodulation of signals in which proper timing and / or carrier alignment are achieved via timing recovery and / or carrier recovery, respectively. As used herein, Post-DM may refer to a combiner in which input signals are combined after partial execution of the full demodulation process, e.g., after timing recovery of the demodulation processing chain and match filter, but before carrier recovery of the demodulation processing chain. Thus, the Post-DM method enables combining after timing recovery is locked, but before carrier recovery. A non-limiting example advantage of Post-DM is that the combined signal can achieve a higher Es / N0 and / or signal-to-noise ratio (SNR) before carrier recovery is performed. Because carrier recovery may fail at a higher Es / N0 than timing recovery, Post-DM methods may improve overall system Es / N0 sensitivity. However, Post-DM methods may involve increased implementation complexity costs. On the other hand, Post-DE methods may be simpler to set up and execute, but may require carrier recovery to be locked before combining, which is typically the limiting factor in receiver sensitivity. This may limit how low the Es / N0 and / or SNR a diversity combiner can operate, limiting the usefulness of power forward error correction (FEC) as used in some waveform standards such as DVB-S2.

[0073] The Post-DM and Post-DE methods disclosed herein represent two possible high-level examples of Post-D diversity combiner methods. It will be understood that the embodiments herein are not limited to only these two methods. Other methods are also possible.

[0074] 5 illustrates an exemplary Post-DE diversity combiner as a method 500. As shown in FIG. 5, method 500 receives input samples from multiple antenna feeds (e.g., downlink signals 160 and / or 170 are received by antennas, sampled, and provided to method 500), combines the inputs together, and outputs a combined signal such that the signals are aligned in time and phase and weighted based on signal quality, thereby optimizing information transfer combined with the multiple signals. Method 500 may be performed, for example, by a processor implemented as SPS 150 of FIG. 1 (e.g., processor 202 of FIG. 2).

[0075] The method 500 includes a plurality of functional blocks, such as a plurality of timing recovery blocks 510a-510n (collectively referred to as timing recovery block(s) 510 or block(s) 510), a plurality of carrier recovery blocks 520a-520n (collectively referred to as carrier recovery block(s) 520 or block(s) 520), one or more correlator block(s) 530, a plurality of time adjustment blocks 540a-540n (collectively referred to as time adjustment block(s) 540 or block(s) 540), and a plurality of carrier recovery blocks 520a-520n (collectively referred to as carrier recovery block(s) 520 or block(s) 520). 0), a plurality of phase rotation blocks 550a to 550n (collectively referred to as phase rotation block(s) 550 or block(s) 550), a plurality of amplitude adjustment blocks 560a to 560n (collectively referred to as amplitude adjustment block(s) 560 or block(s) 560), a plurality of power and Es / No estimator blocks 565a to 560n (collectively referred to as power and Es / No estimator block(s) 565 or block(s) 565), and one or more combiner block(s) 570. In the illustrated example, multiple blocks 510a-510n, 520a-520n, 540a-540n, 550a-550n, 560a-560n, and 565a-565n are shown to perform functions on samples of multiple downlink signals received via multiple antenna feeds, with each block operating on a corresponding signal. While any number of signals is possible, examples herein are described with reference to two signals (e.g., sample A and sample N).

[0076] In the illustrative example of FIG. 5, a given timing recovery block 510 and a corresponding carrier recovery block 520 may be part of an overall demodulation process, including match filters for the respective input signals. For example, blocks 510a and 520a may be part of an overall demodulation process for signal A, and blocks 510n and 520n may be part of an overall demodulation process for signal N. Each block 510 and block 520 may be configured to demodulate a respective input signal and may be referred to herein as a demodulator processing chain. Thus, the Post-DE method shown in FIG. 5 is configured to combine the input signals at the end of the demodulator chain (e.g., following execution of the demodulator chain). Thus, the combiner logic is after overall demodulation but before forward error correction.

[0077] As mentioned above, the multiple blocks of method 500 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). For example, as shown in the exemplary implementation of FIG. 5, correlator block 530 may be implemented as function 306 of FIG. 3 and may divide such data from carrier recovery blocks 520a-520n into data blocks for processing by parallel functions 306a-306n. Similarly, as shown in FIG. 5, combiner block 570 may be implemented as function 306 and may be implemented as multiple functions 306a-306n for processing multiple data blocks in parallel. While specific examples of blocks are shown implemented as function 306, these examples are not intended to be limiting, and any block of method 500 may be implemented as function 306.

[0078] In another example, several blocks shown in FIG. 5, alone or in combination, can be grouped together as a single "process" 515 that performs a function in a manner similar to process 315 of FIG. 4. That is, several blocks in FIG. 5 can be grouped together as process 515 and executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (FIG. 4). For example, different portions of method 500 can be grouped together as process 515 and executed in serial-parallel and / or parallel-serial processing, as described above in connection with FIG. 4. In the illustrative example shown in FIG. 5, a timing recovery block 510n and a carrier recovery block 520n for implementing a match filter along the processing path of signal N are grouped together as process 515. In this case, referring to Figure 4, input samples may be taken in block 305 and divided into overlapping sample blocks in block 310, where each of the overlapping data blocks may be processed in multiple parallel iterations of timing recovery block 510n and carrier recovery block 520n as processing blocks 315a-315n. The processed overlapping data blocks are then output to data combiner 320 to combine the processed data, which is then output by block 325 for processing by subsequent blocks in method 500. Data combiner block 320 in Figure 4 should not be confused with combiner block 570. While block 320 combines the parallel processing blocks 315a-315n, combiner block 570 performs diversity combining, as described below. Similarly, as exemplarily shown in FIG. 5, a time adjustment block 540n, a phase rotation block 550n, and a power and Es / No estimator block 565, as well as an amplitude adjustment block 560n, are shown grouped together as processing block 315.

[0079] While particular examples of blocks are shown grouped together as process 515, these examples are not intended to be limiting, and any grouping of one or more blocks of method 500 may be grouped together as process 515 and performed in parallel as described in connection with Figure 4. For example, one or more of time adjustment block 540n, phase rotation block 550n, and amplitude adjustment block 560n may be implemented as process block 315.

[0080] Furthermore, although only the portions of the paths corresponding to inputs from the signal N input are shown grouped together in Figure 5, it will be understood that the various blocks of the signal A path can also be grouped together and executed in parallel as process 515. For example, blocks 510a and 520b can be grouped together as a first process 515, and blocks 540a-540n can be grouped together as a second process 515. As noted above, other groupings are possible.

[0081] In various examples, multiple blocks in Figure 5 may be implemented using SIMD processing techniques, as described throughout this disclosure. SIMD techniques may be shown to increase throughput and minimize memory bandwidth requirements. Increasing the functionality of each processing block performed using SIMD techniques may be useful to increase the minimization of memory bandwidth requirements.

[0082] In blocks 510 and 520, the processor 202 (e.g., one or more cores 204) can perform timing and carrier recovery on each input sample from the downlink from each antenna feed. An example of a timing and carrier recovery method is illustratively shown in Figures 7 and 8.

[0083] Figure 7 is a flowchart of an example of a timing and carrier recovery method implemented by the signal processing method of Figure 3 and / or Figure 4. Figure 7 shows a method 700 including multiple blocks, one or more of which may be implemented as process 315, such as processing a grouping of blocks in each of processing blocks 315a-315n of Figure 4. Each block of method 700 may be implemented as a function 306, thereby performing a single block across functions 306a-306n of Figure 3. The execution of the blocks according to Figure 3 may be performed separately or in combination with the execution of the process according to Figure 4.

[0084] Method 700 can be used for standard waveform processing, as opposed to offset waveforms described below. For example, standard waveform processing can be used on the waveform, mapping bits to symbols and modulating those symbols onto a carrier. Examples of standard waveforms include binary phase shift keying (BPSK), quaternary phase shift keying (QPSK), 8PSK, 16APSK, 32APSK, and 64APSK, as well as quadrature amplitude modulation (QAM) waveforms. Method 700 can be the example timing recovery processing block 510 and the example carrier recovery block 520 of FIG. 5 .

[0085] In block 705, the processor 202 (e.g., one or more cores 204) can perform a timing recovery error calculation on the received data packets (e.g., samples of the digitized bit stream 154 or the digitized downlink signals 160 and / or 170). The timing recovery error calculation can provide the phase information necessary to properly align a matched filter to the incoming data stream (e.g., the digitized bit stream 134). The matched filter is used to match the transmitted waveform in the time domain and is aligned with the timing error to capture all energy in the received signal, optimizing performance. The timing recovery error calculation can include three parameters: 1) starting phase (degrees), 2) frequency adjustment (Hertz (Hz)), and 3) Doppler rate adjustment (Hz / second). The aforementioned units are exemplary and not limiting of the present disclosure. Other equivalent units are possible.

[0086] In block 710, processor 202 (e.g., one of cores 204) performs timing recovery on the packet to align the internally generated matched filters to the received samples generated by the respective matched filters of the modulators. The alignment is based on the calculations of block 705. The output of block 710 is the synchronized (e.g., time corrected) symbols in the data packet received in block 705.

[0087] Examples of the timing recovery error calculation block 705 and the timing recovery block 710 are described in U.S. Patent No. 10,790,920, the disclosure of which is incorporated herein by reference as if fully set forth. For example, as known in the art, an estimated Gardner timing error detector can be applied to the incoming data to produce timing information. In another embodiment, the incoming sample stream can be delayed by one sample. The undelayed data can then be multiplied by the conjugate of the delayed data (conjugate multiplication). Each implementation has its advantages and disadvantages, so the trade-off is often a trade-off. The timing spikes generated by the Gardner timing error detector can be mixed with a timing estimate or a symbol rate estimate. The mixed signal may be decimated to reduce the sampling rate. A phase unwrap calculation may be performed on the decimated samples. Additionally, a curve-fitting calculation can be performed to determine phase, frequency, and Doppler rate offset information that can be applied to update the timing estimate.

[0088] In block 715, the processor 202 (eg, one of the cores 204) may perform carrier recovery error calculations on the packet to determine phase and frequency information.

[0089] In block 720, processor 202 (e.g., one of cores 204) may perform carrier recovery on the packets based on the calculations of block 715. Carrier recovery compensates for unknown frequency, Doppler rate, and phase offsets in downlink signals (e.g., downlink signals 160 and / or 170) from a spacecraft (e.g., satellite 110). The two most common sources of uncertainty are Doppler effects from spacecraft motion and Doppler effects from imperfect oscillators within the spacecraft. Processor 202 may apply the phase, frequency, and Doppler rate corrections from block 715 to form synchronization symbols corresponding to the modulated data in the downlink signals (e.g., downlink signals 160 and / or 170) at the output of block 720.

[0090] Examples of the carrier recovery error calculation block 715 and the carrier recovery block 720 are also described in U.S. Pat. No. 10,790,920, the disclosure of which is incorporated herein by reference as if fully set forth. For example, the incoming signal may be boosted to a particular power based on the modulation type. The mixed signal may be decimated to reduce the sampling rate. A phase unwrap calculation may be performed on the decimated samples. A curve fitting calculation may be performed to determine phase, frequency, and Doppler rate offset information that may be applied to update the carrier recovery algorithm. Curve fitting may also be used to update (and improve) the carrier frequency estimate.

[0091] In some implementations, blocks 705 and 710 may be grouped together as a single processing block, for example, as timing recovery processing block 510 as shown in Figure 5. Similarly, in some implementations, blocks 715 and 720 may be grouped together as a single processing block, for example, as carrier recovery processing block 510 as shown in Figure 5. In some implementations, one or more additional processing blocks may be performed between block 710 and block 705, for example, as shown in Figure 6.

[0092] Additionally, timing recovery error calculation 705 and timing recovery block 710 may be grouped together as process 315 in FIG. 4. If timing recovery is performed across multiple processing blocks 315a-315n, the signals may be combined via block 320 prior to execution of the grouped block (e.g., process 315) and output by block 325 in FIG. 4 as a single-threaded operation per signal. While blocks 305, 310, 320, and 325 are not shown in FIG. 7, it will be understood that such blocks may be present to take input data (305), split (310), perform grouping functions as processing blocks 315a-315n, and combine (320) and output (325) the resulting processed data for downstream processing. As shown in FIG. 7, the output signal is now in symbol space, and downstream functions can be performed on the resulting output symbols. The more processing blocks that are executed, the higher the processing rate that can be achieved, and the greater the throughput.

[0093] After transforming from sample space to symbol space in block 710, the signal symbols may be corrected by blocks 715 and 720. Blocks 715 and 720 may be grouped together as process 315 in Figure 4. Thus, the symbols output from block 710 may be fed back into carrier recovery process 315, which may be executed across processing blocks 315a-315n, with block 710 being implemented as a separate process and / or function from block 715, e.g., as described above.

[0094] As another example, each of blocks 705-720 may be grouped as a single processing block 315, e.g., as described above in connection with Figure 5, and may be executed across processing blocks 315a-315n of Figure 4. Furthermore, each block 705-720 may be implemented as a function 306 and may be executed across core 204 as functions 306a-306n.

[0095] FIG. 8 is a flowchart of an embodiment of another method for timing and carrier recovery implemented by the signal processing method of FIGS. 3 / 4 (the processes occurring in each of blocks 315a-315n). FIG. 8 illustrates another method 800 that may be similar to method 700 (FIG. 7) in that some functional blocks are combined and rearranged. Like method 700, method 800 can be used for offset waveform processing. For example, offset waveform processing can be used for waveforms that have an offset or stagger between the in-phase (I) and quadrature (Q) channels, such as offset quaternary phase shift keying (OQPSK), minimum shift keying (MSK), Gaussian minimum shift keying (GMSK), and shaped offset quaternary phase shift keying (SOQPSK).

[0096] In block 805, the processor 202 (e.g., one or more cores 204) can perform timing and carrier recovery error calculations on the packets. The timing recovery error calculations and carrier recovery error calculations are similar to those performed in blocks 705 and 715 (FIG. 7). However, in method 800, carrier recovery is performed before timing recovery of the symbols. The input to method 800 is the samples, and the output is the corrected synchronization symbols.

[0097] In block 810, the processor 202 (e.g., one or more cores 204) can perform carrier recovery operations based on the calculations from block 805. An example of the timing and carrier recovery error calculation block 810 is also described in U.S. Pat. No. 10,790,920, the disclosure of which is incorporated herein by reference as if fully set forth. For example, when a digitized bitstream is squared, spikes can occur in the frequency domain. Each spike can be mixed with a mixing signal created from a composite estimate of the carrier frequency and symbol rate. Both mixing signals can then be decimated to reduce the sampling rate. Phase unwrapping and curve fitting calculations can be performed on both mixing signals, and the results can be passed to the carrier recovery and timing recovery algorithms to update the information.

[0098] Referring back to FIG. 5, the corrected symbols for each input signal output from each block 520a-520n are provided to block 530. In block 530, processor 202 (e.g., one or more cores 204) can calculate the time and phase relationship between the input signals (two input signals in this example). For example, block 530 can perform a correlator function using a Fast Fourier Transform (FFT) on the corrected symbols, outputting both time and phase information indicating the respective offset or stagger between the input signals from the same operation. After performing a coarse correlation using an FFT, fine correlations can be performed on smaller data sets to ensure the time and phase alignment has not changed.

[0099] Coarse correlation may refer to performing timing and phase difference between two signals over many symbols to determine the time uncertainty between the two signals. For a single satellite and two antennas, this time is usually short (e.g., microseconds or less) and can vary based on cable length and analog equipment timing differences. For rates below 1 megasymbol per second (Msps), the coarse timing estimate may only need to cover + / - 1 symbol. For a symbol rate of 100 Msps, the coarse timing estimate may need to cover + / - 100 symbols. For example, in an antenna handover scenario with two satellites and two antennas, the timing difference between the two signals may be 100 milliseconds or more. For 1 Msps, the coarse timing estimate may need to cover at least + / - 100k symbols. For 100 Msps, the coarse timing estimate may need to cover 10M symbols. The fine correlation may need to be performed over at least one symbol, but may be performed over 3 to 15 symbols to ensure that the timing alignment once determined by the coarse correlation is not lost. For each acquisition mode, once the timing is known, it is possible to determine the phase difference between the two signals by comparing either the phase of the FFT results, as in the case of coarse correlation, or the phase of a properly time-aligned correlator, as in the case of fine correlation.

[0100] Block 540 provides timing information from block 520 to block 540 and processor 202 (e.g., one or more cores 204) to adjust the timing of the input signals based on the timing information. Because the signals have already been properly demodulated and passed through matched filters and are now simply symbols, time alignment is straightforward, requiring only delays of an integer number of symbols instead of a fractional number of samples, as in Pre-D combining. Block 540 can apply delays based on the timing offset between the input signals calculated in block 530 to properly align the input signals. That is, for example, a delay corresponding to the timing offset between input signal A and input signal N is applied to align the symbols of each signal in the time domain. For example, block 520 can calculate time relationships to align the symbol streams from blocks 520a-520n so that each symbol from one signal chain matches the symbols of another symbol chain in terms of symbol order. For example, in a system including a single satellite (e.g., satellite 111 or platform 110) and two antennas (e.g., antennas 122, 132, and / or 142), each symbol from the satellite transmitter can be labeled with a number that corresponds to all symbols transmitted. Correlator 530 determines that the first symbol is symbol 1, the 100th symbol is symbol 100, and so on. Time alignment block 540 then ensures that symbol 1 from signal A is aligned with symbol 1 from signal N.

[0101] The phase offset information calculated in block 530 is provided to block 540, where the processor 202 (e.g., one or more cores 204) rotates the phase of at least one input signal to align the signals. Block 550 can remove the Doppler effect by rotating one of the signals to properly align it with the other signal(s) based on the phase offset information from block 530. This operation can be accomplished using complex multiplication, as known in the art. In some cases, if the phase change is + / - 90 degrees or 180 degrees, swapping and / or inverting the combination of the in-phase (I) and quadrature (Q) channels can be performed. As an illustrative example, the phase of the first signal A needs to be appropriately adjusted to match the phase of signal N. For example, in the case of QPSK, there are four possible phases possible per symbol. Because the demodulator does not guarantee how these four phase possibilities will align after demodulation, one of the signal's phases needs to be adjusted to match the other's phase. Block 530 calculates this adjustment. For example, suppose the phase of signal A for symbol 1 is 45 degrees and the phase of signal N for symbol 1 is 135 degrees. Block 530 determines that signal N needs to be adjusted by negative 90 degrees so that symbol 1 of signal N (and all other symbols) aligns with symbol 1 of signal N, and passes this information to block 550, which rotates the phase of the signals accordingly.

[0102] In block 565, the processor 202 (e.g., one or more cores 204) estimates the signal power and Es / N for each input signal. Block 565 can measure Es / N using any one of several approaches. One illustrative example for measuring Es / N is calculating (C / N) x (B / fs), where C / N is one of the carrier-to-noise ratios or signal-to-noise ratios, B is the channel bandwidth in Hertz, and fs is the symbol rate or number of symbols per second. However, it will be understood that any approach for measuring Es / N is equally applicable to the embodiments disclosed herein. In another example, block 565 can estimate signal quality, such as a signal-to-noise ratio, a power estimate, a received signal strength indicator (RSSI), etc. These estimates can be provided to block 570 to appropriately weight each input signal for combining.

[0103] The power and Es / N estimates from block 565 may be provided to block 560 along with amplitude information indicating the difference in signal amplitudes from block 530. As another example, the amplitude information may be applied directly by the demodulation process (e.g., blocks 510 and 520) because these blocks may include automatic gain control (AGC) loops. In either case, in block 560, processor 202 (e.g., one or more cores 204) adjusts the amplitude of each signal, for example, by multiplying the amplitude of the input signal based on the power and Es / N estimates provided from block 565. In subsequent combining, signals A-N are weighted by the difference in Es / N between them. For example, if both signals have the same Es / N, a 50 / 50 weighting may be applied, scaling each signal by 0.5 (or weighting it by 50%) before combining. If the difference in Es / No between the signals is 3 dB, a 66 / 34 weighting may be applied, with the higher Es / No signal scaled by 0.66 (or weighted by 66%) and the lower Es / no scaled by 0.34 (or weighted by 34%) before being combined.

[0104] Once the signals have been aligned in time and phase and amplitude adjusted as described above, in block 570, processor 202 (e.g., one or more processors 204) can apply scaling based on the Es / No estimates and power estimates calculated in block 565. For example, a signal having a better signal-to-noise ratio compared to another signal can be assigned a higher weight than the other signal and scaled accordingly. Similarly, a higher Es / No estimate and / or power estimate can be assigned a larger weight and scaled accordingly. SIMD techniques can be employed to efficiently scale and combine multiple signals (e.g., two signals in this example). Block 570 can sum the signals after all adjustments have been made.

[0105] Although blocks 540, 550, and 560 are illustratively performed in a particular order, it will be understood that embodiments herein are not limited to only the illustrated order. Blocks 540, 550, and 560 may be performed in any order and / or in parallel as desired.

[0106] Figure 6 illustrates an exemplary Post-DM diversity combiner as a method 600. As shown in Figure 6, the method 600 receives input samples from multiple antenna feeds, combines the inputs together, and outputs a combined signal in a manner substantially similar to the method of Figure 5.

[0107] Method 600 includes the same blocks as method 5 configured to perform substantially the same functions, but in the order shown in FIG. 6. For example, method 600 includes a timing recovery block 510, a carrier recovery block 520, one or more correlator block(s) 530, a time adjustment block 540a, a phase rotation block 550, an amplitude adjustment block 560, and one or more combiner block(s) 570. Like method 500, method 600 includes multiple blocks 510a-510n, 540a-540n, 550a-550n, 565a-565n, and 560a-560n, each for performing a function on samples of multiple signals received via multiple input antenna feeds. While any number of signals are possible, examples herein are described with reference to two signals.

[0108] Method 600 differs from method 500 in that it combines the input signals after performing timing recovery in block 510, but before performing carrier recovery in block 520 of the demodulator processing chain. Thus, combining occurs during demodulation. For example, as shown in FIG. 6, carrier recovery block 520 is performed on the combined signal output from combiner block 570.

[0109] As discussed above in connection with FIG. 5, multiple blocks of method 600, each representing a function 306, may be performed in parallel as one or more of functions 306a, 306b, ..., 306n (FIG. 3). That is, for example, correlator block 530 of FIG. 6, weighted combiner block 570 of FIG. 6, etc., may be performed in parallel as one or more functions 306a-306n. Similarly, multiple blocks shown in FIG. 6 may be grouped together as a single "process" (e.g., process 515 and / or 315) that performs a function in a manner similar to processing blocks 315a, 315b, ..., 315n (FIG. 4). That is, for a given signal processing chain, timing recovery block 510 may be grouped together as process 515 (e.g., timing recovery error calculation block 705 and timing recovery block 710), and blocks 540-565 may be grouped together as another process 515. Similarly, blocks 570 and 520 of Figure 6 may be grouped together as yet another process 515. Various other combinations are possible. Additionally, several blocks of Figure 6 may be implemented using SIMD processing techniques, as described throughout this disclosure.

[0110] 5 and 6 show two possible high-level examples of Post-D diversity combiner methods, it will be understood that embodiments herein are not limited to only these two methods and that other methods are possible. That is, embodiments herein provide methods for performing any functionality of the diversity combiner as functions 306 performed in parallel as functions 306a-306n (FIG. 3) and / or methods for grouping one or more functionality of the diversity combiner as process 315 performed in parallel as processing blocks 315a-315n.

[0111] A channel simulator that runs on a general-purpose CPU using parallel processing across multiple cores, achieving high-throughput operation in cloud environments: As mentioned above, FIG. 9 is a functional block diagram of an exemplary implementation of method 900. In various examples, method 900 may be an example of a channel simulation method. A channel simulator is used to simulate one or more different distortions and / or effects of a transmitter and / or receiver moving in a wireless environment. For example, with reference to FIG. 1 , an embodiment of the channel simulator may be used to simulate a transmitter on a satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)) moving in its environment relative to a receiver (e.g., one or more of antennas 122, 132, and 142). As another example, an embodiment of the channel simulator may be used to simulate a receiver on a satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)) moving in its environment relative to a transmitter (e.g., one or more of antennas 122, 132, and 142). In yet another example, an embodiment of the channel simulator may be used to simulate a transmitter on a satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)) moving in its environment relative to a receiver on the satellite 111 and / or platform 110 (e.g., an airplane, helicopter, or unmanned aerial vehicle (UAV)).

[0112] The channel simulator method simulates at least one, and possibly all, of the above possible environmental effects due to either an imperfect transmitter, environmental effects, or moving vehicles. Possible transmitter impairments that can be simulated include, but are not limited to, phase noise, nonlinear distortion (AM-PM), in-phase / quadrature (I / Q) imbalance, imperfect matched filters, timing jitter, etc. Possible environmental effects include, but are not limited to, rain fade, scintillation, multipath, etc. Possible motion effects include, but are not limited to, adjusting the signal center frequency, adjusting the time delay, and adjusting the power. The channel simulator can also add additive white Gaussian noise (AWGN) or any other type of noise that the channel may impart to the signal.

[0113] An exemplary channel simulator is shown in FIG. 9 as method 900. To simulate all necessary channel effects, method 900 may include one or more function blocks 910-960 for several operations performed on a signal. For example, in the illustrative example of FIG. 9, method 900 includes one or more of a signal distortion block 910, a phase noise block 920, a center frequency adjustment block 930, a timing adjustment block 940, a gain adjustment block 950, and an additive noise block 960. The function blocks included in method 900 may depend on the distortion or effect desired to be simulated. Method 900 may include one, more than one, or all of blocks 910-960, and in some embodiments, additional blocks may be added to simulate other distortions and / or effects.

[0114] As noted above, the blocks of method 900 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). In another example, two or more of the blocks may be grouped together as a single "process" 915 that performs the function in a manner similar to process 315 of FIG. 4. That is, the blocks of FIG. 9 may be grouped together as process 915 and may be executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (FIG. 4), etc. For example, as shown in FIG. 9, all function blocks 910-960 are grouped into a single process 915, and the grouped functions are replicated across multiple processing blocks 315a-315n. The number of processing blocks 315a-315n may be replicated as many times as desired to achieve the required processing rate and throughput. Although blocks 305, 310, 320, and 325 are not shown in FIG. 9, it will be understood that such blocks may be present to take input data (305), split it (310), and perform process 915 as processing blocks 315a-315n, and may combine the resulting processed data (320) and output it (325) for downstream processing.

[0115] 9 shows all of the function blocks grouped into process 915, embodiments herein are not so limited. The function blocks 910-960 can be grouped in many different ways. For example, fewer than all (e.g., two or more) of the function blocks 910-960 can be grouped into a process (e.g., process 915). As an illustrative example, the function blocks 910 and 920 can be grouped together into a first process 915 and distributed across one or more first processing blocks 315a-315n, and the function blocks 930-960 can be grouped together into a second process 915 and distributed across one or more second processing blocks 315a-315n. Additionally, while blocks 305, 310, 320, and 325 are not shown in FIG. 9, it will be understood that such blocks may precede each process 915 to take in (305), split (310) input data, perform the grouping function of process 915 (as processing blocks 315a-315n), and combine (320) the resulting processed data and output (325) for downstream processing.

[0116] In various examples, multiple blocks in Figure 9 may be implemented using SIMD processing techniques, as described throughout this disclosure. SIMD techniques may be shown to increase throughput and minimize memory bandwidth requirements. Increasing the functionality of each processing block performed using SIMD techniques may increase the minimization of memory bandwidth requirements.

[0117] In block 910, the processor 202 (e.g., one or more cores 204) can simulate signal distortions on the input signal. The block 910 can simulate one or more of nonlinear distortions (AM-PM), in-phase / quadrature (I / Q) imbalance distortions, scintillation distortions, and multipath distortions on the input signal, thereby simulating a signal subjected to such distortions. For example, a complex finite impulse response (FIR) filter can be used to simulate the above distortions, excluding AM-PM distortions. An example FIR filter can be implemented using SIMD technology to improve throughput. The FIR filter coefficients can be configured to achieve the desired simulation of the distortion. For AM-PM distortions, a nonlinear operation, such as a lookup table, may be performed to perform the complex nonlinear operation.

[0118] In block 920, the processor 202 (e.g., one or more cores 204) can simulate phase noise on the input signal. To simulate phase noise, block 920 can apply a phase noise simulation to the input signal. For example, colored noise can be added to a carrier that is mixed with the input signal. One way to create colored noise is to shape white noise using an FIR filter (which can be the same FIR filter in block 910 or a different FIR filter) to achieve the desired noise shape. The noise can be created in 10 steps, creating a band from 0.1 to 1 Hz, then interpolating and adding another stage of noise spanning 1 Hz to 10 Hz. This process can be repeated as many times as needed to cover the required phase noise bandwidth. At each step, SIMD techniques can be used to achieve noise generation, filtering, and interpolation. This colored noise is then used to adjust the phase of either the carrier signal or a complex vector starting from (1,0). This phase-adjusted signal or vector is then multiplied with the input signal, adding the phase noise to the input signal.

[0119] In block 930, processor 202 (e.g., one or more cores 204) can perform carrier adjustment by adjusting the phase of the input signal over time. Block 930 can be performed in a manner similar to block 920, except that in block 930, the phase of the mixed carrier is varied over time to achieve a desired carrier frequency and phase adjustment. Block 930 may be used to simulate, without limitation, changes in carrier frequency from the motion of a moving platform (e.g., platform 110 and / or satellite 111 of FIG. 1 ) or, more commonly, the motion of either the transmitter or receiver, referred to as the Doppler effect.

[0120] In block 940, processor 202 (e.g., one or more cores 204) can perform timing adjustments to simulate the effect of a moving platform (e.g., platform 110 and / or satellite 111). For example, such movement may stretch or lengthen the length of the input signal in time. Block 940 can apply a polyphase filter using adjustable delay taps. Block 940 can be similar to time adjustment block 540 of FIGS. 5 and 6, except that user input drives the timing information of block 940 to simulate the desired effect, instead of the result of analyzing the input signal.

[0121] In block 950, the processor 202 (e.g., one or more cores 204) may perform gain adjustments to simulate rain fades or other effects that may affect signal power. Block 950 may be performed by multiplying the amplitude of the input signal.

[0122] In block 960, the processor 202 (e.g., one or more cores 204) can add noise to the input signal. For example, block 960 can simulate additive Gaussian white noise (or any type of noise, such as a Rayleigh-like colored distribution or other type of distribution) and apply the noise to the input signal. There are many ways to generate Gaussian white noise, and the Box-Muller method is one method known in the art.

[0123] Although blocks 910-960 are shown in a particular order, it will be understood that embodiments herein are not limited to the order shown. Blocks 910-960 may be performed in any order and / or in parallel with the input signal as desired.

[0124] Signal modulator that runs on a general-purpose CPU using parallel processing across multiple cores, enabling high-throughput operation in cloud environments: As mentioned above, FIG. 10 is a functional block diagram of an exemplary implementation of method 1000. In various examples, method 1000 may be an example of a signal modulation method. A modulator may be used to generate a waveform to transmit information from one location to another. For example, a downlink signal (e.g., downlink signals 160 and / or 170 of FIG. 1) may be modulated according to method 1000. For example, the information may be separated into digital information or into analog signals such as those used for AM and FM radio. While digital signal generation is used as an example herein, the same approach may also be used to generate analog signals.

[0125] An exemplary signal modulation is shown in Figure 10 as method 1000. Method 1000 is a phase shift keying (PSK) modulator method that supports modulation types such as B / Q / SQ / 8 / 16A / 32APSK / etc., quadrature amplitude modulation (QAM), or any similar digital modulation waveform. While Figure 10 shows one exemplary modulation method, the same approach to signal processing (e.g., as described in Figures 3 and 4) can be applied to other modulation methods.

[0126] The method 1000 includes multiple functional blocks as shown in Figure 10. For example, in the illustrative example of Figure 10, the method 1000 includes one or more of a frame builder block 1010, a forward error correction (FEC) block 1020, a pulse shaper block 1030, a center frequency adjustment block 1040, and a sweeper block 1050.

[0127] While specific blocks and configurations are shown in Figure 10, specific modulation schemes may require different blocks. Thus, Figure 10 illustrates a high-level modulation method and is not a catch-all configuration. One or more additional functional blocks can be added to method 1000 as needed to implement different modulation schemes. To the extent that a specific modulation scheme is not included in the configuration of Figure 10, those skilled in the art will understand that the concepts disclosed in connection with various embodiments throughout this disclosure apply equally to any modulation scheme, not just the modulation method of Figure 10.

[0128] As noted above, the blocks of method 1000 may each represent a function and may be implemented as one or more of functions 306a, 306b, ... 306n (FIG. 3). In another example, two or more of the blocks may be grouped together as a single "process" 1015 that performs a function in a manner similar to process 315 of FIG. 4. That is, the blocks of FIG. 10 may be grouped together as process 1015 and executed in multiple parallel iterations as processing blocks 315a, 315b, ... 315n (FIG. 4), etc. For example, as shown in FIG. 10, function blocks 1010 and 1020 may be grouped together as a first process 1015 and then replicated as multiple first processing blocks 315a-315n, and function blocks 1030-1050 may be grouped together as a second process 315 and then replicated as multiple second processing blocks 315a-315n. 10 shows certain functional blocks grouped into separate processes 1015, embodiments herein are not so limited. The functional blocks 1010-1050 can be grouped in many different ways. For example, all of the functional blocks 1010-1050 can be grouped together.

[0129] Method 10 also illustratively includes a data ingestion block 1005 and a data division block 1010 before each process 1015. Each data ingestion block 1005 can be substantially similar to data ingestion block 305 (FIG. 4), and each data division block 1010 can be substantially similar to data division block 310 (FIG. 4). Thus, input data can be ingested (1005), received, processed, and divided (1010) by processor 202, and the data can be parsed by processor 202 into overlapping data blocks, for example, as described in connection with FIG. 4. Furthermore, after each process 1015, method 10 also illustratively includes a data combination block 1020 and a data output block 1025. Each data combination block 1020 can be substantially similar to data combination block 320 (FIG. 4), and each data output block 1025 can be substantially similar to data output block 325 (FIG. 4). Thus, the process 1015 outputs and combines (1020) the overlapping data blocks and outputs (1025) the data, for example as described in connection with FIG.

[0130] In various examples, multiple blocks in Figure 10 may be implemented using SIMD processing techniques, as described throughout this disclosure. SIMD techniques may be shown to increase throughput and minimize memory bandwidth requirements. Increasing the functionality of each processing block performed using SIMD techniques may increase the minimization of memory bandwidth requirements.

[0131] In block 1010, the processor 202 (e.g., one or more cores 204) can convert the incoming data of the input signal into a predetermined format based on a desired modulation scheme (e.g., the modulation scheme of a receiver, such as antennas 122, 132, and / or 134). For example, a particular modulation scheme requires a particular format, and block 1010 converts the data of the input signal into that format. The modulator method 1000 can support many different waveform standards, such as, but not limited to, DVB-S2, DVB-S2x, as well as less standardized cases using Reed-Solomon coding, turbo coding, convolutional coding, etc. For simplicity, waveform standards are grouped into two cases: streaming data and frame data. The streaming data case is when the incoming data is a continuous, uninterrupted stream, such as uncoded or convolutionally coded. The frame data case is for incoming data that requires frame data or blocks of data, such as DVB-S2 or Reed-Solomon. Block 1010 may construct frames (eg, in the case of frame data) or data streams (eg, in the case of streaming data) by converting the incoming data into a format corresponding to the modulation scheme.

[0132] In block 1020, processor 202 (e.g., one or more cores 204) generates coding corresponding to the modulation scheme of method 1010, including, but not limited to, BCH and LDPC for DVB-S2, LDPC coding for CCSDS, Reed-Solomon, Turbo coding, Polar coding, and convolutional coding. Block 1020 may be one of the more complex blocks of modulation method 1000 and, therefore, may benefit from all of the signal processing methods (e.g., FIG. 3 and / or FIG. 4) and SIMD techniques disclosed throughout this disclosure.

[0133] In block 1030, the processor 202 (e.g., one or more cores 204) converts the symbol data into samples, for example, by applying a pulse shaping filter. Block 1030 can create any pulse shape, for example, a root raised cosine (RRC). The pulse shaper may be a combination of a polyphase filter and a numerically controlled oscillator (NCO). Block 1030 may also be a complex block and, therefore, may benefit from all of the signal processing methods (e.g., FIGS. 3 and / or 4) and SIMD techniques disclosed throughout this disclosure.

[0134] In block 1040, the processor 202 (e.g., one or more cores 204) can use complex multiplication to change the center frequency of the carrier of the sample data from block 1030. In block 1040, the processor 202 (e.g., one or more cores 204) can change the phase and frequency over time based on a predetermined profile corresponding to the modulation scheme. In some implementations, block 1050 is performed while the center frequency is being adjusted by block 1040.

[0135] Other Aspects The accompanying claims and their equivalents are intended to cover such forms or modifications as fall within the scope of the present disclosure. The various components shown in the figures may be implemented, for example, but not limited to, as software and / or firmware on a processor or dedicated hardware. Also, the features and attributes of the specific exemplary embodiments disclosed above may be combined in various ways to form additional embodiments, all of which are within the scope of the present disclosure.

[0136] The foregoing method descriptions and process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be understood by one of ordinary skill in the art, the order of operations in the foregoing embodiments can be performed in any order. Words such as "then," "then," and "next" are not intended to limit the order of operations; these words are merely used to guide the reader through the method descriptions. Furthermore, any reference to a claim element using the article "a," "an," or "the" in the singular should not be construed as limiting the element to the singular.

[0137] The operations of the various illustrative logical blocks, modules, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the inventive concept.

[0138] The various exemplary logic, logic blocks, and modules described in connection with the various embodiments disclosed herein may be implemented or performed by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof intended to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of a DSP and a receiving device, such as a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such combination of components. Alternatively, some operations or methods may be performed by circuitry dedicated to a given function.

[0139] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable or processor-readable storage medium. The operations of a method or algorithm disclosed herein may be embodied in processor-executable instructions, which may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable storage medium may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium usable to store desired program code in the form of instructions or data structures and accessible by a computer. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. These disks typically reproduce data magnetically, while discs reproduce data optically with a laser. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Furthermore, the operations of a method or algorithm may reside as one or any combination or set of code and / or instructions in a non-transitory processor-readable and / or computer-readable storage medium, which may be embodied in a computer program product.

[0140] It is understood that the specific order or hierarchy of blocks in the disclosed processes / flowcharts is illustrative of example approaches. It is understood that the specific order or hierarchy of blocks within the processes / flowcharts can be rearranged based on design preferences. Also, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0141] The previous description is provided to enable one skilled in the art to practice the various aspects of the invention described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects.

[0142] Accordingly, the scope of the claims is not intended to be limited to the embodiments set forth herein, but is intended to be accorded the full scope consistent with the language of the claims, and reference to an element in the singular is not intended to mean "one and only one," unless expressly so stated, but rather "one or more."

[0143] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Unless otherwise specified, the term "some" refers to one or more.

Claims

1. 1. A method for modulating a downlink signal representing a communication signal, the method comprising: receiving an input signal; dividing the digital bit stream into data packets, each of said data packets containing a duplication of data from adjacent packets; In one or more first processing blocks in one or more processors, performing a modulation operation on a first data packet of the input signal based on a modulation scheme for a receiver of the downlink signal; In parallel with the one or more first processing blocks, one or more second processing blocks within the one or more processors performing the modulation operation on second data packets of the input signal based on the modulation scheme; combining the modulated first data packets and the modulated second data packets in an order corresponding to the order in which the digital bit stream was received; generating a waveform as the downlink signal based on the combined modulated first data packet and the modulated second data packet; A method comprising:

2. 2. The method of claim 1, wherein the one or more first processing blocks include one or more first central processing unit (CPU) cores, and the one or more second processing blocks include one or more second CPU cores.

3. 3. The method of claim 1, wherein the one or more processors comprise a plurality of processors, the one or more first processing blocks being included in a first processor of the plurality of processors, and the one or more second processing blocks being included in a second processor of the plurality of processors.

4. 3. The method of claim 1, wherein the one or more processors include a plurality of processors, each of the plurality of processors being a single processor having the one or more first processing blocks and the one or more second processing blocks.

5. The method of any one of claims 1 to 4, wherein the one or more first processing blocks and the one or more second processing blocks operate in parallel.

6. 6. The method of claim 1, wherein the modulation operation comprises one or more first functions, the one or more first processing blocks comprising a plurality of first processing blocks, and at least two of the one or more first functions being performed in parallel by separate processing blocks of the plurality of first processing blocks.

7. The one or more first functions are converting a first data packet of the input signal into a predetermined format based on the modulation scheme; generating coding corresponding to said modulation scheme; converting first symbol data of the first data packet into first sample data of the downlink signal; The method of claim 6 , comprising at least one of:

8. 7. The method of claim 6, wherein the modulation operation includes one or more second functions, the one or more second processing blocks include a plurality of second processing blocks, and at least two of the one or more second functions are performed in parallel by separate processing blocks of the plurality of second processing blocks.

9. The one or more second functions are converting second data packets of the input signal into a predetermined format based on the modulation scheme; generating coding corresponding to said modulation scheme; converting second symbol data of the second data packet into second sample data of the downlink signal; The method of claim 8 , comprising at least one of:

10. The method of any one of claims 1 to 9, wherein the one or more processors are one or more general purpose central processing units (CPUs).

11. The method of any one of claims 1 to 10, wherein the one or more processors employ Single Instruction Multiple Data (SIMD) technology to achieve high throughput.

12. 1. A system for modulating a downlink signal representing a communication signal, the system comprising: at least one memory configured to store instructions; one or more processors communicatively coupled to the at least one memory, the one or more processors having a plurality of processing blocks and operable to execute instructions for performing the method of any one of claims 1 to 11; Including, the system.

13. 1. An apparatus for modulating a downlink signal representing a communication signal, the apparatus comprising: means for receiving an input signal; means for dividing the digital bit stream into data packets, each of said data packets containing a duplication of data from adjacent packets; one or more means for performing a modulation operation on a first data packet of the input signal based on a modulation scheme for a receiver of the downlink signal; one or more means for performing the modulation operation on second data packets of the input signal based on the modulation scheme, wherein the one or more means for performing the modulation operation on the second data packets are operated in parallel with the one or more means for performing the modulation operation on the first data packets; means for combining the modulated first data packets and the modulated second data packets in an order corresponding to the order in which the digital bit stream was received; means for generating a waveform as the downlink signal based on the combined modulated first data packet and the modulated second data packet; 1. An apparatus comprising:

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