Transistor

Abstract

To provide a display device and a transistor capable of performing excellent display without causing delay or dullness of signals.SOLUTION: A display device includes a first gate driver 103A and a second gate driver 103B. Each of the first gate driver and the second gate driver includes a plurality of flip-flop circuits Fk (k is an odd number of 3 or more) and a plurality of transfer signal generation circuits Tk. The flip-flop circuit and the transfer signal generation circuit are circuits that both output signals input to a first input terminal with a delay corresponding to a half clock period. An output terminal of the transfer signal generation circuit is directly coupled to the first input terminal of the flip-flop circuit in a subsequent stage. Therefore, the delay or dullness of the signal input from the transfer signal generation circuit to the flip-flop circuit can be reduced.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device driven by an active matrix method. The present invention relates to an electronic device equipped with the display device. [Background technology]

[0002] In a display device driven by the active matrix method, each pixel has a switch such as a transistor. When the switch is turned on, the element is electrically connected to the pixel, and the image is projected onto the pixel. The drive circuit (source driver) that outputs the image signal and the and a drive circuit (gate driver).

[0003] In addition, it is possible to configure not only the switches for each pixel but also the gate drivers using transistors. Therefore, a transistor formed using a non-single-crystal semiconductor provided on an insulating substrate is Display devices have also been developed that use transistors to configure the switches and gate drivers for each pixel. There are.

[0004] The above-mentioned gate driver is provided in the vicinity of the pixel portion of the display device. When a gate driver is provided close to one side of the pixel section, the display section is biased to one side of the display device. Therefore, display devices have been developed that have gate drivers divided into left and right sides of the pixel section. It has been published (see, for example, Patent Document 1).

[0005] The configuration of the display device disclosed in Patent Document 1 is shown in FIG. 10. The display device shown in FIG. 10 has the following features: The pixel section 1001 is sandwiched between a first gate driver 1002A and a second gate driver 1002B. The first gate driver 1002A is provided opposite the odd-numbered rows. The second gate driver 1002B has an output terminal electrically connected to the gate lines of the even-numbered rows. The output terminal is electrically connected to the first gate line. A electrically connects the pixels arranged in odd-numbered rows of the pixel section 1001 to the source driver. The second gate driver 1002B controls the pixels arranged in the even-numbered rows of the pixel section. The electrical connection between the pixel and the source driver is controlled.

[0006] Furthermore, the first gate driver 1002A and the second gate driver 1002B Each of them has multiple shift registers. The output terminal of the first shift register (SRC1) is , one of the input terminals of the second shift register (SRC2) is connected via the first gate line 10031. The output terminal of the second shift register (SRC2) is electrically connected to the second gate It is electrically connected to one of the input terminals of the third shift register (SRC3) via line 10032. Similarly, the k-th shift register (SRC k ) output terminal is the kth gate line 1003 k The k+1th shift register (SRC k+1 ) to one of the input terminals. In other words, each pixel arranged in a row is electrically connected to the source driver. The signal to electrically connect the output terminals to the pixels arranged in the next row is This is used as a start pulse signal for the shift register. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 4163416 Summary of the Invention [Problem to be solved by the invention]

[0008] Various parasitic capacitances and parasitic resistances occur in the gate lines extending within the pixel area. As the resolution of the display increases, the influence of parasitic capacitance and parasitic resistance occurring in the gate lines increases. As described above, the display device shown in FIG. 10 receives the start pulses of the shift register via the gate lines. Therefore, the display device shown in FIG. Therefore, it can be said that this is a display device that is likely to have a delayed or blurred signal.

[0009] In view of the above-described problems, one aspect of the present invention provides a display device capable of displaying a good image. This is one of the challenges.

[0010] In one embodiment of the present invention, a gate driver is configured using transistors having the same conductivity type. An object of the present invention is to provide a display device.

[0011] Another embodiment of the present invention provides a display device including a gate driver with a reduced circuit area. One of our goals is to provide [Means for solving the problem]

[0012] One aspect of the present invention is a gate electrode comprising a plurality of gate lines arranged parallel or approximately parallel to each other; a first gate driver electrically connected to each of the odd-numbered rows of gate lines; and a second gate driver electrically connected to the first gate driver. The first input terminal is electrically connected to the k-th gate line (k is an odd number equal to or greater than 3), and the second input terminal is k-2 transfer signal generating circuit, and the second input terminal is electrically connected to the output terminal of the transfer signal generating circuit. the third input terminal is electrically connected to the k-th flip-flop circuit stop pulse a k-th flip-flop circuit electrically connected to the kth signal line and an output terminal of the k+2th flip-flop circuit; a first input terminal of the flip-flop circuit, the first input terminal being electrically connected to the kth flip-flop circuit; a second input terminal electrically connected to the output terminal of the flip-flop circuit and receiving an inverted clock signal; a third input terminal electrically connected to the line, and a stop pulse signal for the k-th transfer signal generating circuit; a k-th transfer signal generating circuit electrically connected to the line, and the second gate driver , the output terminal is electrically connected to the (k+1)th gate line, and the first input terminal is connected to the (k-1)th transfer line. a second input terminal electrically connected to the output terminal of the signal generating circuit, and a second input terminal electrically connected to the inverted clock signal line; and the third input terminal is electrically connected to the stop pulse for the k+1-th flip-flop circuit. a k+1-th flip-flop circuit electrically connected to the k+1 signal line; and an output terminal of the k+1-th flip-flop circuit. The first input terminal is electrically connected to the first input terminal of the flip-flop circuit of the third embodiment. a second input terminal electrically connected to the output terminal of the (k+1)th flip-flop circuit; The third input terminal is electrically connected to the clock signal line, and the third input terminal is a stop for the k-th transfer signal generation circuit. a (k+1)th transfer signal generating circuit electrically connected to the transfer pulse signal line; It is a location.

[0013] Furthermore, the kth flip-flop circuit and the kth transfer signal generating circuit have the same circuit configuration. The display device is also one aspect of the present invention.

[0014] The stop pulse signal line is a line that inputs a stop pulse signal to each circuit. is.

[0015] Specifically, the kth transfer signal is used as a stop pulse signal for the kth flip-flop circuit. The output signal of the signal generation circuit can be applied.

[0016] In addition, the k+1th flip-flop circuit is used as a stop pulse signal for the kth flip-flop circuit. The output signal of a flop circuit can also be applied.

[0017] Similarly, the k+2th flip-flop is used as the stop pulse signal for the kth transfer signal generation circuit. The output signal of the loop circuit can be applied.

[0018] In addition, the k+1th transfer signal generator is used as a stop pulse signal for the kth transfer signal generator. The output signal of the circuit may also be applied.

[0019] Furthermore, an electronic device including a display device having the above structure is also one embodiment of the present invention. [Effects of the Invention]

[0020] The first gate driver and the second gate driver included in the display device of one embodiment of the present invention are The transfer signal generating circuit delays the input signal by half a clock period and outputs it. Therefore, a display device capable of displaying a good image without causing delay or distortion of the signal is provided. can be provided. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 illustrates a display device described in Embodiment 1. [Figure 2] FIG. 1 shows a configuration of a gate driver described in the first embodiment. [Figure 3] FIG. 1 is a timing chart of a gate driver described in the first embodiment. [Figure 4] FIG. 10 illustrates a specific example of a circuit configuration described in Embodiment 2. [Figure 5] FIG. 10 is a timing chart of a circuit described in Embodiment 2. [Figure 6] FIG. 10 illustrates a specific example of a circuit configuration described in Embodiment 3. [Figure 7] FIG. 10 illustrates a specific example of an inverter circuit described in Embodiment 3. [Figure 8] FIG. 10 illustrates a specific example of a circuit configuration described in Embodiment 4. [Figure 9] FIG. 10 illustrates a specific example of a control circuit described in Embodiment 4. [Figure 10] FIG. 1 is a diagram illustrating the configuration of a gate driver disclosed in Patent Document 1. [Figure 11] 10A to 10C illustrate specific examples of electronic devices described in Embodiment 6. [Figure 12] 10A to 10C illustrate specific examples of electronic devices described in Embodiment 6. [Figure 13] 10A to 10C illustrate specific examples of electronic devices described in Embodiment 6. [Figure 14] 1A and 1B are diagrams showing a conventional circuit configuration and a circuit configuration according to the present specification, respectively, which are explained in Example 1. [Figure 15] FIG. 3 is a diagram showing output signals of a flip-flop circuit of a conventional gate driver described in Example 1 and output signals of a flip-flop circuit of a gate driver disclosed in this specification. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0023] (Embodiment 1) In this embodiment, an example of a display device according to one embodiment of the present invention will be described. An active matrix display device having a first gate driver and a second gate driver is shown in FIGS. 3 will be used to explain.

[0024] <Example of display device configuration> FIG. 1 is a diagram showing an active matrix display device 100. The display device 100 is , a pixel section 101, a source driver 102, a first gate driver 103A, and a second The gate driver 103B and m (m is a positive integer) of the gate electrodes arranged parallel or approximately parallel to each other. Source lines 1041-104 m and n (n is a positive integer) arranged parallel or approximately parallel to each other. Gate lines 1051-105 n The pixel portion 101 of the display device 100 The source driver 102 is provided in the vicinity of one side of the pixel section 101. The first gate driver 103A and the second gate driver 103B are connected to the source driver 10 2 is provided on a side different from the side on which the pixel unit 101 is provided, and the pixel unit 101 is disposed between the side on which the pixel unit 101 is provided. The source driver 102 is provided with m source lines 1041 to 1044. m Through The first gate driver 103A is electrically connected to the pixel section 101 through n gate lines. 1051~105 n are electrically connected to the pixel section 101 through the odd-numbered gate electrodes 101a and 101b, and The gate driver 103B is connected to n gate lines 1051 to 105 n through the even-numbered pixels 101 is electrically connected to the

[0025] In addition, the source driver 102, the first gate driver 103A, and the second gate driver The driver 103B receives signals from the outside via flexible printed circuit boards 106A and 106B. (clock signal, start pulse signal, etc.) is input.

[0026] Furthermore, the pixel unit 101 includes n×m pixels 107 11 ~107 nm In addition, element 107 11 ~107 nm are arranged in n rows and m columns. ~104 m Each of the n gate lines 11 is electrically connected to n pixels arranged in each column. 051~105 n Each of the electrodes is electrically connected to m pixels arranged in each row. and pixel 1 located in the i-th row and j-th column (i and j are positive integers, where 1≦i≦n, 1≦j≦m). 05 ij is source line 104 j and gate line 105 i is electrically connected to

[0027] That is, the source driver 102 has m source lines 1041 to 1044. m Through the pixel The first gate driver 103A is electrically connected to each pixel of the pixel circuit 101. Gate lines 1051-105 n The odd-numbered rows of the pixel section 101 are arranged through the odd-numbered rows. The second gate driver 103B is electrically connected to each of the n gate lines 10 51~105 n through the even-numbered rows of the pixel section 101. are electrically connected.

[0028] <Example of display device operation> In the display device 100, the source driver 102 controls each pixel 10 included in the pixel section 101. 7 11~107 nm The first gate driver 103A is a circuit for outputting a video signal to the The second gate driver 103B connects the source driver 102 and the pixel 107 11 ~107 n m It is a circuit that controls the electrical connection of

[0029] The display device 100 has n×m pixels 107 11 ~107 nm Input the video signal to each of By this, an image is displayed on the pixel portion 101. This is described below.

[0030] First, the first gate driver 103A selects m pixels arranged in the first row (source The driver 102 and the m pixels arranged in the first row are electrically connected to each other, and the source line 104 1~104 m The m pixels 107 arranged in the first row are 11 ~107 1m Video signal Next, the second gate driver 103B drives the m pixels arranged in the second row. Select the source and source lines 1041 to 104 m , m pixels 10 arranged in the second row. 7 21 ~107 2m A video signal is input to the first gate driver 1. The first gate driver 103A and the second gate driver 103B alternately select m pixels in each row, and The display device 100 performs the above operations continuously to display the image. Showing the image.

[0031] <Gate driver configuration example> FIG. 2 shows a first gate driver 10 included in an active matrix display device 100. 3A and a block diagram showing a detailed configuration example of a second gate driver 103B.

[0032] The first gate driver 103A and the second gate driver 103B have at least three A flip-flop circuit having one input terminal and one output terminal and a transfer signal generating circuit are There are multiple of each.

[0033] The first gate driver 103A has a first flip-flop circuit (F1) that outputs The first input terminal is electrically connected to the first gate line 1051, and the second input terminal is electrically connected to the first start The second input terminal is electrically connected to the pulse signal (SP1) line, and the second input terminal is electrically connected to the clock signal (CK) line. The third input terminal is electrically connected to the first flip-flop circuit. (STP(F1)) Electrically connected to the line.

[0034] The first gate driver 103A has a first transfer signal generation circuit (T1). The output terminal is electrically connected to a first input terminal of a third flip-flop circuit (F3), The input terminal of the first flip-flop circuit (F1) is electrically connected to the output terminal of the second flip-flop circuit (F2). The second input terminal is electrically connected to the inverted clock signal (CKB) line, and the third input terminal is It is electrically connected to the stop pulse signal (STP(T1)) line for the transfer signal generation circuit of 1. .

[0035] The second gate driver 103B has a second flip-flop circuit (F2) that outputs The terminal is electrically connected to the second gate line 1052, and the first input terminal is connected to the second start The second input terminal is electrically connected to the inverted clock signal (CKB ) line, and the third input terminal is electrically connected to the stop pulse for the second flip-flop circuit. It is electrically connected to the service signal (STP(F2)) line.

[0036] The second gate driver 103B has a second transfer signal generation circuit (T2). The output terminal is electrically connected to a first input terminal of a fourth flip-flop circuit (not shown). The first input terminal is electrically connected to the output terminal of the second flip-flop circuit (F2). The second input terminal is electrically connected to a clock signal (CK) line, and the third input terminal is The signal line is electrically connected to the stop pulse signal (STP(T2)) line for the transfer signal of No. 2.

[0037] The kth (k is an odd number equal to or greater than 3) flip-flop of the first gate driver 103A Circuit (F k ) is the output terminal of the kth gate line 105 k and a first input terminal electrically connected to the The child is the k-2nd transfer signal generation circuit (T k-2 ) and the second input The k-th flip-flop is electrically connected to the k-th input terminal of the clock signal (CK) line. Stop pulse signal for flop circuit (STP(F k )) is electrically connected to the line.

[0038] In addition, the kth transfer signal generation circuit (T k ) is out The output terminal is the k+2th flip-flop circuit (F k+2 ) and the first input The terminal is the kth flip-flop circuit (F k ) and the second input The terminal is electrically connected to the inverted clock signal (CKB) line, and the third input terminal is Stop pulse signal for signal generation circuit (STP(T k )) is electrically connected to the line.

[0039] The k+1-th flip-flop circuit (F k+1 ) The output terminal is the (k+1)th gate line 105. k+1 and a first input terminal is electrically connected to The k-1th transfer signal generation circuit (T k-1 ) and a second input terminal The first input terminal is electrically connected to the inverted clock signal (CKB) line, and the third input terminal is electrically connected to the k+1th frame. Stop pulse signal for flip-flop circuit (STP(F k+1 )) electrically connected to the wire do.

[0040] In addition, the k+1th transfer signal generation circuit (T k+1 ) is the flip-flop circuit whose output terminal is the k+3th (F k+3 ) to the first input terminal The first input terminal is connected to the k+1-th flip-flop circuit (F k+1 ) output terminal the first input terminal is electrically connected to a clock signal (CK) line; The third input terminal is the stop pulse signal for the k+1th transfer signal (STP(T k+1 )) on the line are electrically connected.

[0041] The above-mentioned first gate driver 103A and second gate driver 103B have multiple The electrical connections of the multiple flip-flop circuits and multiple transfer signal generation circuits are There are some commonalities and some differences, the specific differences of which are listed below.

[0042] First, a flip-flop circuit and a transfer signal generation circuit included in the first gate driver; In the flip-flop circuit and the transfer signal generation circuit of the second gate driver, The differences in electrical connection relationships will be described below.

[0043] The second input terminal of the flip-flop circuit of the first gate driver 103A is a clock. The second input terminal of the transfer signal generation circuit is electrically connected to the inverted clock signal (CK) line. The second gate driver 103B is electrically connected to the clock signal (CKB) line. The second input terminal of the flip-flop circuit is electrically connected to the inverted clock signal (CKB) line. The second input terminal of the transfer signal generation circuit is electrically connected to the clock signal (CK) line. To be continued.

[0044] Next, in all the flip-flop circuits and the transfer signal generation circuit, the electrical connection relationship This section explains the differences between the two.

[0045] The output terminal of the first flip-flop (F1) circuit is electrically connected to the first gate line 1051. The output terminals of each flip-flop circuit are connected to the gates in the same row. On the other hand, the output terminal of the first transfer signal generating circuit (T1) is electrically connected to the third The first input terminal of the flip-flop circuit (F3) is electrically connected to the first input terminal of the flip-flop circuit (F4). The output terminal of the transmission signal generating circuit is connected to the first input terminal of the flip-flop circuit provided in the lower stage. In addition, the first flip-flop which does not have a transfer signal generating circuit in the upper stage is electrically connected to the The first input terminals of the flip-flop circuit (F1) and the second flip-flop circuit (F2) are The first start pulse signal (SP1) line and the second start pulse signal (SP2 ) wire.

[0046] In addition, the third input terminals of all the flip-flop circuits and the third input terminals of the transfer signal generation circuit The input terminals are electrically connected to different stop pulse signal (STP) lines.

[0047] <Gate driver operation example> 3 is a timing chart showing the clock signal (CK) , inverted clock signal (CKB), first start pulse signal (SP1), second start The pulse signal (SP2), the output signal (F1OUT) of the first flip-flop circuit, The output signal (F4OUT) of the flip-flop circuit and the output of the first transfer signal generation circuit 10 shows the output signal (T1OUT) to the output signal (T4OUT) of the fourth transfer signal generating circuit. The clock signal (CK) alternates between high (hereafter referred to as H) and low at regular intervals. It is a signal that repeats a signal of the C (hereinafter referred to as L) level, and is an inverted clock signal (CKB) is a signal in which the H and L levels of the clock signal are inverted.

[0048] During the period T1, the first start pulse signal (SP1) rises to H level. The signal of the flip-flop circuit (F1) is input to a first input terminal of the first flip-flop circuit (F1).

[0049] During the period T2, the second start pulse signal (SP2) rises to the H level. The signal of the flip-flop circuit (F2) is input to a first input terminal of the second flip-flop circuit (F3). The first flip-flop circuit (F1) outputs a high-level signal. The H-level signal output from the flip-flop circuit (F1) is applied to the first gate line 1051. Each pixel 107 in the first row arranged in the pixel section 101 is 11 ~107 1m Entered in As a result, each pixel 107 in the first row 11 ~1071m and the source driver 102 The source driver 102 is electrically connected to each pixel 107 arranged in the first row. 11 ~1071 m A video signal is input to the first input terminal of the first transfer signal generating circuit (T1). The H-level signal output from the first flip-flop circuit (F1) is also input.

[0050] During the period T3, the second flip-flop circuit (F2) outputs a high-level signal. As in the case where the output signal of the first flip-flop circuit (F1) is at H level, The H-level signal output from the second flip-flop circuit (F2) is input to the second gate line 1052, each pixel 107 in the second row arranged in the pixel section 101 21 ~107 2m to As a result, each pixel 107 in the second row 21 ~107 2m and Source Driver 10 2 are electrically connected to each pixel 107 arranged in the second row from the source driver 102. 21 ~ 107 2m A video signal is input to the first transfer signal generating circuit (T1). The signal of the third flip-flop circuit (F3) is input to the first input terminal of the third flip-flop circuit (F4). do.

[0051] In the period T4 and after, the above-described operation is repeated. The flip-flop circuits after flop circuit (F3) sequentially output H-level signals, Accordingly, video signals are input to the arrayed pixels row by row.

[0052] The display device described in this embodiment is an active element having first and second gate drivers. The display device is a matrix type. The first and second gate drivers each have a plurality of and a plurality of transfer signal generating circuits. Both the first and second input terminals of the transfer signal generating circuit are configured to receive a signal at half the frequency of the clock signal. The output terminal of the transfer signal generation circuit is a circuit that outputs the signal with a time delay. The transfer signal is directly connected to the first input terminal of the flop circuit. The delay or distortion of the signal input to the flop circuit can be reduced.

[0053] In this embodiment, the display device has one source driver and two gate drivers. Although an example of a display device has been shown, the embodiment of the present invention is not limited to this configuration. , a configuration in which the display device has only two gate drivers and a video signal is input from an external device; It has one source driver and two gate drivers, and the video signal is Each pixel is electrically connected to the gate driver via two gate lines. Such a configuration is also an aspect of the present invention.

[0054] (Embodiment 2) In this embodiment, the flip-flop circuit and the transfer signal generation circuit shown in Embodiment 1 are Specific examples of circuits applicable to the above will be explained with reference to FIGS. 4 and 5. An example of configuring a flip-flop circuit and a transfer signal generating circuit using a register will be described. The source and drain terminals of the transistor are determined by the structure and operating conditions of the transistor. It is difficult to identify which is the source terminal and which is the drain terminal because they change depending on the Therefore, in the following, one of the source terminal and the drain terminal is referred to as the first terminal, The other of the source and drain terminals will be referred to as the second terminal to distinguish it from the other.

[0055] <Circuit configuration example> FIG. 4 shows the kth flip-flop of the first gate driver 103A shown in the first embodiment. Flop circuit (F k ) and the kth transfer signal generating circuit (T k An example of a circuit that can be applied to It should be noted that the k-th flip-flop circuit (F k ) is the first The k-th transfer signal generation circuit (T k ) includes a fifth transistor 405 to an eighth transistor 408. In this embodiment, the stop pulse signal (STP(F k ))and The output signal (T k OUT), the kth transfer signal generation circuit Stop pulse signal (STP(T k )) as the output of the k+2th flip-flop circuit Signal (F k+2 OUT) is used.

[0056] The first transistor 401 has a gate terminal and a first terminal connected to the (k-2)th transfer signal generating circuit. The output terminal of the power supply is electrically connected to the power supply terminal of the power supply.

[0057] The second transistor 402 has a gate terminal connected to the k-th transfer signal generating circuit (T k ) output terminal The first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the is electrically connected to the second terminal of the first transistor 401.

[0058] The third transistor 403 has a gate terminal connected to the second terminal of the first transistor 401 and The second terminal of the second transistor 402 is electrically connected to the second terminal of the second transistor 402, and the first terminal of the second transistor 402 is electrically connected to the second terminal of the second transistor 402. K) line, and the second terminal is electrically connected to the k-th transfer signal generating circuit (T k ) first input terminal The power supply is electrically connected to the power supply.

[0059] The fourth transistor 404 has a gate terminal connected to the k-th transfer signal generating circuit (T k ) output terminal The first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the is the kth transfer signal generation circuit (T k ) and the first input terminal of the third transistor 403 It is electrically connected to two terminals.

[0060] The fifth transistor 405 has a gate terminal and a first terminal connected to the k-th flip-flop circuit. (F k ) is electrically connected to the output terminal of the

[0061] The sixth transistor 406 has a gate terminal connected to the k+2-th flip-flop circuit (not shown). The first terminal is electrically connected to the output terminal of the power supply (not connected to the power supply), and the second terminal is electrically connected to the ground potential (VSS) line. and the second terminal is electrically connected to the second terminal of the fifth transistor 405.

[0062] The seventh transistor 407 has a gate terminal connected to the second terminal of the fifth transistor 405 and a first terminal electrically connected to the second terminal of the sixth transistor 406 and a second terminal electrically connected to the inverted clock signal (CKB) line, and the second terminal is electrically connected to the k-th flip-flop circuit (F k ) The third input terminal and the first input terminal of the k+2 flip-flop circuit (not shown) are connected to the power supply. electrically connected.

[0063] The eighth transistor 408 has a gate terminal connected to the k+2-th flip-flop circuit (not shown). The first terminal is electrically connected to the output terminal of the power supply (not connected to the power supply), and the second terminal is electrically connected to the ground potential (VSS) line. The second terminal is connected to the k-th flip-flop circuit (F k )'s third input terminal, the k+2th a first input terminal of a flip-flop circuit (not shown), and a seventh transistor 407 The second terminal of the

[0064] As shown in FIG. 4, the k-th flip-flop circuit (F k ) and the kth transfer signal generation circuit ( T k ) can be applied to circuits with the same configuration. However, when designing the circuit, It is preferable to pay attention to this point.

[0065] The k-th flip-flop circuit (F k ) is a circuit that drives the k-th gate line, and Transfer signal generation circuit (T k ) is the circuit that drives the (k+2)th flip-flop circuit. As described above, the k-th gate line has various parasitic resistances and parasitic capacitances. Therefore, the kth flip-flop circuit (F k ) is the load of the kth transfer signal generation circuit (T k )of In other words, when designing the circuit described above, the first transistor 40 It is preferable that the current driving capability of the first transistor is higher than the current driving capability of the fifth transistor 405. For example, the channel width of the first transistor 401 is set to be equal to the channel width of the fifth transistor 405. For the same reason, the current drive of the second transistor 402 can be increased by The current driving capability of the sixth transistor 406 is higher than that of the third transistor 408. The current driving capability of the fourth transistor 403 is higher than that of the seventh transistor 407. The current driving capability of the transistor 404 is higher than the current driving capability of the eighth transistor 408. For example, the current driving capability is preferably determined by the ratio of the channel width to the channel length (channel It is possible to improve this by increasing the channel width / channel length (W / L). do.

[0066] Also, the k-th flip-flop circuit (F k ) have first to fourth transistors 401 to 404 Among the transistors 404, the third transistor directly involved in driving the k-th gate line is It is preferable that the current driving capability of the k-th transfer signal generating circuit is the highest. Road (T k Among the fifth transistor 405 to the eighth transistor 408 included in the The voltage of the seventh transistor 407 directly involved in driving the (k+2)th flip-flop circuit is The highest flow driving capacity is preferred.

[0067] In addition, the first gate driver 103A has a first flip-flop circuit (F1) and The circuit configuration shown in FIG. 4 can be applied to the first transfer signal generating circuit (T1). However, in the first flip-flop circuit (F1), the first transistor 401 The gate terminal and the first terminal of the first start pulse signal (SP1) are electrically connected to the first start pulse signal (SP1) line. This differs from the configuration in Figure 4.

[0068] In addition, the k+1-th flip-flop circuit (F k +1) and the k+1 transfer signal generation circuit (T k+1 ) also applies the circuit configuration shown in Figure 4. However, the k+1th flip-flop circuit (F k+1 ) and k+1 Transfer signal generation circuit (T k+1 ) the first terminal of the third transistor 403 is inverted The seventh transistor 407 is electrically connected to the clock signal (CKB) line. The difference from the configuration in FIG. 4 is that it is electrically connected to a clock signal (CK) line.

[0069] In addition, the second gate driver 103B has a second flip-flop circuit (F2) and The circuit configuration shown in FIG. 4 can also be applied to the first transfer signal generating circuit (T1) and the second transfer signal generating circuit (T2). However, in the second flip-flop circuit (F2) and the second transfer signal generation circuit (T2), In this case, the gate terminal and the first terminal of the first transistor 401 are connected to the second start pulse signal. The first terminal of the third transistor 403 is electrically connected to the signal line (SP2). The seventh transistor 407 is electrically connected to the inverted clock signal (CKB) line. 4 in that the terminals are electrically connected to the clock signal (CK) line.

[0070] In this embodiment, the stop pulse signal for the k-th transfer signal generation circuit (STP(T k )) as the output signal (F k+2 OUT) is used. Therefore, for a plurality of pixels arranged in n rows, the first gate driver 103A has , the (n+1)th flip-flop circuit is provided as a dummy circuit, and the second gate driver 103B needs to have the (n+2)th flip-flop circuit provided as a dummy circuit. The dummy circuit only supplies a stop pulse signal for the transfer signal generation circuit. A flip-flop circuit that drives the gate line and does not drive the gate line can also be applied. By providing wiring (dummy gate lines) that are not involved in display together with the dummy circuits, As the dummy circuit, a stop pulse signal for the transfer signal generating circuit is supplied and the wiring is driven. A flip-flop circuit that takes charge of the above can also be applied.

[0071] <Circuit operation example> FIG. 5 shows the k-th flip-flop circuit (F k ) and k transfer signal generation circuit Road (T k ) is a timing chart of the input and output signals of the kth Flip-flop circuit (F k ) and the kth transfer signal generating circuit (T k ) operation. Reveal.

[0072] During the period t1, the output signal (T k-2 OUT) is H level This turns on the diode-connected first transistor 401. As a result, the potential of the gate terminal of the third transistor 403 rises to the H level. The L-level signal, which is the clock signal (CK) during the time t1, is input to the k-th flip-flop circuit. The output signal of the circuit (F k OUT).

[0073] In the period t2, the output signal (T k-2 OUT) is L level As the voltage drops to the low level, the clock signal (CK) rises to the high level. The first transistor 401 connected to the ground is turned off, and the third transistor 402 is in a floating state. The potential of the gate terminal of the third transistor 403 is equal to the H level input to the first terminal of the third transistor 403. The signal from the bell causes it to rise (bootstrap action) and further increase. The third transistor 403 remains on, and the H-level signal is input to the k-th flip-flop Circuit (F k ) output signal (F k OUT) This H level signal is output as the fifth The voltage Vcc is input to the gate terminal and the first terminal of the transistor 405. The connected fifth transistor 405 is turned on, and the gate terminal of the seventh transistor 407 Therefore, the potential of the inverted clock signal (CKB ) is the output signal (T k OUT) will be done.

[0074] During the period t3, the clock signal (CK) falls to the L level and the inverted clock signal (CK) This causes the fifth diode-connected transistor The seventh transistor 405 is turned off, and the potential of the gate terminal of the seventh transistor 407, which is in a floating state, is , which is raised by the H-level signal input to the first terminal of the seventh transistor 407. (bootstrap operation) and the voltage further rises. The state is maintained, and the H-level signal is output to the k-th transfer signal generating circuit (T k ) output signal (T k OU This H-level signal is output as a signal from the second transistor 402 and the fourth transistor 403. The second transistor 402 is connected to the gate terminal of the second transistor 404. The potential of the gate terminal of the third transistor 403 drops to the L level. The third transistor 403 is turned off. Also, the fourth transistor 404 is turned on. Therefore, the L-level signal is input to the k-th flip-flop circuit (F k ) output signal (F k OUT) and and output.

[0075] During the period t4, the output signal (F k+2 OUT) This causes the sixth transistor 406 to turn on and the seventh transistor Therefore, the potential of the gate terminal of the seventh transistor 407 drops to the L level. Also, the eighth transistor 408 is turned on, so that the L level signal is applied to the first k transfer signal generation circuit (T k ) output signal (T k OUT).

[0076] The first flip-flop circuit, the first transfer signal generation circuit, and the (k+1)th flip-flop circuit a flip-flop circuit, a (k+1)th transfer signal generating circuit, a second flip-flop circuit, and The circuit operation of the second transfer signal generation circuit is the k-th flip-flop circuit (F k ) and and the k-th transfer signal generation circuit (T k ) is the same as

[0077] <Modification> In this embodiment, the stop pulse signal for the k-th flip-flop circuit (STP(F k )) and the kth transfer signal generating circuit stop pulse signal (STP(T k )) as, Each k-th transfer signal generation circuit (T k ) output signal and the k+2 flip-flop circuit ( F k+2) is applied, but the configuration of this embodiment is not limited to this configuration.

[0078] For example, the stop pulse signal (STP(F k )) and k transfer signal generation circuit stop pulse signal (STP(T k )) as the kth + 1 flip-flop circuit (F k+1 ) output signal and the k+1 transfer signal generation circuit (T k+1 ) output signal can be applied. In this case, the kth flip-flop circuit Road stop pulse signal (STP(F k )) and k transfer signal generation circuit stop pulse signal (STP(T k )) will result in a delayed or dull signal compared to the above configuration, but The kth flip-flop circuit (F k ) and the kth transfer signal generating circuit (T k ) The output signal is at L level, so the delay and dullness of the stop pulse signal (STP) are a problem. It will never be.

[0079] (Embodiment 3) In this embodiment, the flip-flop circuit and the transfer signal generation circuit shown in Embodiment 1 are A specific example of a circuit applicable to the present invention, which is different from that of the second embodiment, will be described with reference to FIGS. 6 and 7. do.

[0080] <Circuit configuration example> FIG. 6 shows the kth flip-flop of the first gate driver 103A shown in the first embodiment. Flop circuit (F k ) and the kth transfer signal generating circuit (T k An example of a circuit that can be applied to The k-th flip-flop circuit (F k) is the first transaction The k-th transistor 601 to the fifth transistor 605 and the inverter circuit 600 are included. Transfer signal generation circuit (T k ) are the sixth transistor 606 to the eighth transistor 608 The circuit shown in FIG. 6 is the same as the k-th flip-flop circuit (F k ) an inverter circuit 600 and a fifth transistor 605 are provided, and a k-th transfer signal Generation circuit (T k ) is a circuit in which the eighth transistor 408 is deleted. It is possible.

[0081] A first transistor 601, a second transistor 602, and a third transistor 60 The electrical connection relationship of the circuit shown in FIG. 3 is the same as that of the circuit shown in FIG. 4, so the explanation of the second embodiment is omitted. It will be used.

[0082] The inverter circuit 600 has an input terminal connected to the second terminal of the first transistor 601 and a second terminal of the second transistor 602. a second terminal of the second transistor 602 and a gate terminal of the third transistor 603; To be continued.

[0083] The fourth transistor 604 has a gate terminal electrically connected to the output terminal of the inverter circuit 600. the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the third The second terminal of the transistor 603 and the kth transfer signal generating circuit (T k ) to the first input terminal. electrically connected.

[0084] The fifth transistor 605 has a gate terminal electrically connected to the output terminal of the inverter circuit 600. the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the first transistor. The second terminal of the second transistor 601, the second terminal of the second transistor 602, the third transistor The gate terminal of the inverter 603 and the input terminal of the inverter circuit 600 are electrically connected to each other.

[0085] The k-th transfer signal generation circuit (T k ) is the kth transfer signal generation circuit shown in FIG. Road (T k ) except that the eighth transistor 408 is removed. The electrical connection relationship is the same as that of the circuit shown in FIG. 4, so the description of the second embodiment is applicable. It will be decided.

[0086] However, when designing the circuit shown in Figure 6, it is necessary to design it as follows.

[0087] The k-th flip-flop circuit (F k ) (diode-connected first transistor 6 01), when a high-level signal is input, a high-level signal is input to the input terminal of the inverter circuit 600. It is necessary to design the fifth transistor so that the signal is input reliably. The current driving capability of the first transistor 601 must be higher than the current driving capability of the second transistor 605. For example, the channel width of the first transistor 601 is set to be equal to that of the fifth transistor 605. The channel width must be larger than the

[0088] In addition, during the period t4 shown in FIG. 5, the output signal (T k OU T) must be designed to be at the L level. The current driving capability of the eighth transistor 608 must be higher than that of the eighth transistor 607. As a result, an H-level signal is input to the gate terminal of the seventh transistor 607. This turns on the seventh transistor 607, and the ground potential (VSS) is applied to the eighth transistor 608. The signal is input to the gate terminal of the eighth transistor 608, and the eighth transistor 608 is turned off. Before this is done, the inverted clock signal (CKB) is first raised to the L level in period t4. k transfer signal generation circuit output signal (T k OUT) can be reduced.

[0089] Also, when designing the circuit shown in FIG. 6, it is important to take note of the points described in the second embodiment. It is preferable that:

[0090] That is, the current driving capability of the first transistor 601 is The current driving capability of the second transistor 602 is higher than that of the seventh transistor. The current driving capability of the third transistor 603 is higher than that of the third transistor 607. is preferably higher than the current driving capability of the eighth transistor 608.

[0091] Also, the k-th flip-flop circuit (F k ) have first to fifth transistors 601 to 605 Among the transistors 605, the third transistor 603 has the highest current driving capability. , the kth transfer signal generation circuit (T k The sixth transistor 606 to the eighth transistor 608 Among the transistors 608, it is preferable that the eighth transistor 608 has the highest current driving capability. stomach.

[0092] In addition, in FIG. 6, the kth flip-flop circuit (F k ) and the kth transfer signal generating circuit (T k ) is shown, but the k+1th flip-flop circuit and the k+1th transfer signal generation However, as described in the second embodiment, the circuit of FIG. The electrical connection relationship of the terminals is different. The specific difference in the connection relationship will be explained in the second embodiment. It will be used.

[0093] 7A and 7B are specific examples of circuits applicable to the inverter circuit 600 shown in FIG. In addition, in Fig. 7(A) and (B), the wiring marked "IN" is the input The wiring marked with "OUT" is the output wiring.

[0094] The inverter circuit 600A shown in FIG. 7A includes a diode-connected transistor 7 It is composed of a transistor 701A and a transistor 702A.

[0095] The gate terminal and the first terminal of the transistor 701A are electrically connected to the power supply potential (VDD) line. The first terminal is electrically connected to the output terminal of the inverter circuit 600A, and the second terminal is electrically connected to the output terminal of the inverter circuit 600A.

[0096] The gate terminal of transistor 702A is electrically connected to the input terminal of inverter circuit 600A. The first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is connected to the inverter circuit. The output terminal of the circuit 600A and the second terminal of the transistor 701A are electrically connected to each other.

[0097] The inverter circuit 600A shown in FIG. 7A includes two transistors 701A and 702. A, the increase in circuit area can be kept to a minimum.

[0098] However, the inverter circuit 600 in FIG. 6 may be replaced by the inverter circuit shown in FIG. 7(A). When 600A is applied, when the transistor 702A is on, the output signal is at the L level. More specifically, the current driving capability of the transistor 702A must be It is necessary to make the current driving capability of the transistor 701A higher than that of the transistor 701B. The channel length of the transistor 702A is made smaller than the channel length of the transistor 701A. Alternatively, the channel width of the transistor 702A may be set larger than the channel width of the transistor 701A. It is necessary to

[0099] The inverter circuit 600B shown in FIG. 7B includes a diode-connected transistor 7 7. It is composed of transistors 701B and 702B, 703B, and 704B.

[0100] The gate terminal and the first terminal of the transistor 701B are electrically connected to the power supply potential (VDD) line. To be continued.

[0101] The gate terminal of transistor 702B is electrically connected to the input terminal of inverter circuit 600B. The first terminal is electrically connected to a ground potential (VSS) line, and the second terminal is connected to a transistor 701B.

[0102] The gate terminal of transistor 703B is connected to the second terminal of transistor 701B and the The first terminal is electrically connected to the power supply potential (VDD) line. The first terminal is electrically connected to the output terminal of the inverter circuit 600B.

[0103] The gate terminal of transistor 704B is electrically connected to the input terminal of inverter circuit 600B. The first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is connected to the inverter circuit. The output terminal of the circuit 600B is electrically connected to the second terminal of the transistor 703B.

[0104] The inverter circuit 600B shown in FIG. 7B includes a diode-connected transistor 7 01B is not directly connected to the output terminal of the inverter circuit 600B. This prevents the voltage from dropping below the ground potential (VDD) or increasing above the ground potential (VSS). Cut.

[0105] However, the inverter circuit 600 in FIG. 6 may be replaced by the inverter circuit shown in FIG. 7(B). When the transistor 700B is applied, when the transistor 702B is on, the transistor 703 More specifically, the current drive of transistor 702B must be designed so that B is turned off. It is necessary to make the driving capability of the transistor 701B higher than the current driving capability of the transistor 701B. , the channel length of the transistor 702B is set to be shorter than the channel length of the transistor 701B. Alternatively, the channel width of the transistor 702B is set to be smaller than the channel width of the transistor 701B. also needs to be made larger.

[0106] <Differences from the circuit shown in the second embodiment> The k-th flip-flop circuit (F k ) is an inverter circuit 600 and a gate The first terminal is electrically connected to the output terminal of the inverter circuit 600, and the second terminal is connected to the ground potential (V SS) line, and the second terminal is electrically connected to the input terminal of the inverter circuit 600. The inverter circuit 600 and the fifth transistor 605 are connected to each other. The fifth transistor 605, which is electrically connected to the When the fifth transistor 605 is in an on state, the gate of the third transistor 603 Therefore, the potential of the third transistor is kept at the ground potential (VSS). Even if noise enters the gate terminal of the third transistor 603, the third transistor 603 In other words, there is no problem with the image or video on the display device. The performance of the display device can be improved.

[0107] The k-th transfer signal generation circuit (T k ) are three transistors 606 to 608 Therefore, the circuit area can be reduced.

[0108] <Modification> In this embodiment, the flip-flop circuit includes five transistors 601 to 605 and an inverter. The inverter circuit 600 is configured, and the transfer signal generating circuit is configured with three transistors 606 to 608. However, the embodiment is not limited to this configuration. k flip-flop circuit (F k ) and the kth transfer signal generating circuit (T k ) are shown in Figure 6. The k-th flip-flop circuit (F k ) or the kth transfer signal generation circuit (T k ) The circuit shown in the second embodiment (FIG. 4) and the circuit shown in the present embodiment (FIG. 6) and the circuit shown in Fig. 6) to form a flip-flop circuit and a transfer signal generation circuit. That's fine.

[0109] In this embodiment, the stop pulse signal for the k-th flip-flop circuit (STP (F k )) and the kth transfer signal generating circuit stop pulse signal (STP(T k )) as , respectively, the k-th transfer signal generation circuit (T k ) and the output signal of the k+2 flip-flop Circuit (F k+2) output signal is applied, but the configuration of this embodiment is not limited to this configuration. stomach.

[0110] (Fourth embodiment) In this embodiment, the flip-flop circuit and the transfer signal generation circuit shown in Embodiment 1 are 8 and 9, a specific example of a circuit applicable to the present invention, which is different from the second and third embodiments, will be described. explain.

[0111] <Circuit configuration example> FIG. 8 shows the kth flip-flop of the first gate driver 103A shown in the first embodiment. Flop circuit (F k ) and the kth transfer signal generating circuit (T k An example of a circuit that can be applied to The k-th flip-flop circuit (F k ) is the first transaction The k-th transmission / reception circuit includes a fifth transistor 801 to a fifth transistor 805 and a control circuit 800. Signal generation circuit (T k ) includes a sixth transistor 806 to a ninth transistor 809. The circuit shown in FIG. 8 is the circuit shown in FIG. 4 with a control circuit 800 and a fifth transistor. 4. A sixth transistor 806 (the fifth transistor 4 in FIG. 4) is provided. The first terminal of the MOSFET (corresponding to MOSFET 05) is electrically connected to the power supply potential (VDD) line, not the gate terminal. In other words, it is a circuit that has been

[0112] A first transistor 801, a second transistor 802, and a third transistor 80 The electrical connection relationship of 3 is the same as that of the circuits shown in FIGS. 4 and 6. The explanation will be used here.

[0113] The control circuit 800 has a first input terminal connected to the second terminal of the first transistor 801, The second terminal of the third transistor 802 and the gate terminal of the third transistor 803 are electrically connected to The first input terminal is electrically connected to a clock signal (CK) line.

[0114] The fourth transistor 804 has a gate terminal electrically connected to the output terminal of the control circuit 800. The first terminal is electrically connected to a ground potential (VSS) line, and the second terminal is connected to a third transistor. The second terminal of the transfer signal generating circuit (T k ) electrically connected to the first input terminal Connected.

[0115] The fifth transistor 805 has a gate terminal electrically connected to the output terminal of the control circuit 800. The first terminal is electrically connected to a ground potential (VSS) line, and the second terminal is connected to the first transistor. the second terminal of the second transistor 801, the second terminal of the second transistor 802, the third terminal of the third transistor 80 3 and a first input terminal of the control circuit 800.

[0116] The sixth transistor 806 has a gate terminal connected to the k-th flip-flop circuit (F k )'s The first terminal is electrically connected to the power terminal, and the second terminal is electrically connected to a power supply potential (VDD) line.

[0117] The seventh transistor 807, the eighth transistor 808, and the ninth transistor 80 The electrical connection relationship of the sixth transistor 606 and the seventh transistor 609 shown in FIG. The eighth transistor 607 and the eighth transistor 608 are the same as those in the first embodiment. It will be decided.

[0118] However, when designing the circuit shown in Figure 8, it is necessary to design it as follows.

[0119] The k-th flip-flop circuit (F k ) (diode-connected first transistor 8 01), when a high-level signal is input to the input terminal of the control circuit 800, a high-level signal is input to the input terminal of the control circuit 800. More specifically, the fifth transistor 8 Therefore, the current driving capability of the first transistor 801 must be higher than that of the first transistor 805. For example, the channel width of the first transistor 801 is set to be equal to the channel width of the fifth transistor 805. It must be larger than the channel width.

[0120] Also, when designing the circuit shown in FIG. 8, it is important to take note of the points described in the second embodiment. It is preferable that:

[0121] That is, the current driving capability of the first transistor 801 is The current driving capability of the second transistor 802 is higher than that of the seventh transistor. The current driving capability of the third transistor 803 is higher than that of the third transistor 807. is higher than the current driving capability of the eighth transistor 808, and the fourth transistor 804 It is preferable that the current driving capability of the ninth transistor 809 be higher than that of the ninth transistor 809 .

[0122] Also, the k-th flip-flop circuit (F k ) have first to fifth transistors 801 to 805 Among the transistors 805, the third transistor 803 has the highest current driving capability. , the kth transfer signal generation circuit (T k The sixth transistor 806 to the ninth transistor 807 have Among the eighth transistor 809, it is preferable that the eighth transistor 808 has the highest current driving capability. stomach.

[0123] In addition, in FIG. 8, the kth flip-flop circuit (F k ) and the kth transfer signal generating circuit (T k ), but only the k+1th flip-flop circuit (F k+1 ) and k+1 Transfer signal generation circuit (T k+1 ) etc., the circuit of FIG. As mentioned in condition 2, the electrical connection relationships of some terminals are different. The specific differences in the connection relationships are as follows: The description of the second embodiment is to be cited.

[0124] 9A and 9B show specific examples of circuits applicable to the control circuit 800 shown in FIG. In FIGS. 9(A) and 9(B), the wiring marked with "IN" is the first input wiring. The wiring marked "CK" is electrically connected to the clock signal (CK) line. The wiring marked "OUT" is the output wiring.

[0125] The control circuit 800A shown in FIG. 9A includes a capacitor 901A and a transistor 902A. It consists of:

[0126] One terminal of the capacitance element 901A is electrically connected to the clock signal (CK) line, and the other The terminal is electrically connected to the output terminal of the control circuit 800A.

[0127] The gate terminal of transistor 902A is electrically connected to the first input terminal of control circuit 800A. The first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is connected to the control circuit 80. 0A and the other terminal of the capacitive element 901A.

[0128] After the period t3 shown in FIG. 5, the first input terminal of the control circuit 800A receives an L level signal. The signal from the control circuit 800A is input, and the transistor 902A is turned off. Therefore, the output signal of the control circuit 800A is in a floating state. A signal synchronized with the signal (CK) is output.

[0129] However, the control circuit 800A shown in FIG. 9(A) is used as the control circuit 800 in FIG. When the period t2 changes to the period t3, the voltage of one terminal of the capacitance element 901A decreases. The output terminal of the control circuit 800A is designed to be in a floating state after the potential drops to the L level. It is necessary to

[0130] The control circuit 800B shown in FIG. 9B includes a diode-connected transistor 901B and transistors 902B, 903B, and 904B. It is composed of:

[0131] The gate terminal and the first terminal of the transistor 901B are electrically connected to the clock signal (CK) line. Connected.

[0132] The gate terminal of transistor 902B is electrically connected to the first input terminal of control circuit 800B. The first terminal is electrically connected to a ground potential (VSS) line, and the second terminal is connected to a transistor 901B.

[0133] The gate terminal of transistor 903B is connected to the second terminal of transistor 901B and the The first terminal is electrically connected to the clock signal (CK) line. and the second terminal is electrically connected to the output terminal of the control circuit 800B.

[0134] The gate terminal of the transistor 904B is electrically connected to the input terminal of the control circuit 800B. The first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is The output terminal is electrically connected to the second terminal of the transistor 903B.

[0135] However, the control circuit 800B shown in FIG. 9(B) is used as the control circuit 800 in FIG. When the transistor 902B is turned on, the transistor 903B is turned off. More specifically, the current driving capability of the transistor 902B must be designed to be It is necessary to make the current driving capability higher than that of the transistor 901B. The channel length of the transistor 902B is set to be shorter than the channel length of the transistor 901B, or The channel width of the transistor 902B is made larger than the channel width of the transistor 901B. It is necessary.

[0136] <Differences from the circuits shown in the second and third embodiments> The control circuits 800A and 800B shown in FIGS. 9A and 9B are driven by a clock signal (CK) or The third transistor 80 outputs a signal synchronized with the clock signal (CK). Even if noise enters the gate terminal of the third transistor, the fourth transistor 804 and the fifth transistor By turning on the transistor 805, noise can be removed. The fourth transistor 804 and the fifth transistor 805 are not always on, Deterioration of the fourth transistor 804 and the fifth transistor 805 can be suppressed. In other words, the image on the display device is not impaired, and the performance and reliability of the display device are improved. It can be done.

[0137] <Modification> In this embodiment, the flip-flop circuit includes five transistors 801 to 805 and a control The control circuit 800 is configured, and the transfer signal generation circuit is configured with four transistors 806 to 809. However, the embodiment is not limited to this configuration. Flip-flop circuit (F k ) and the kth transfer signal generating circuit (T k ) are shown in Figure 8. The k-th flip-flop circuit (F k ) or the kth transfer signal generation circuit (T k ) with the same configuration In addition, the circuit shown in the second embodiment (FIG. 4) or the third embodiment (FIG. 6) may be used. , and the circuit shown in this embodiment (FIG. 8) are combined to form a flip-flop circuit and a transfer A signal generating circuit may be configured.

[0138] In this embodiment, the stop pulse signal for the k-th flip-flop circuit (STP (F k )) and the kth transfer signal generating circuit stop pulse signal (STP(T k )) as , respectively, the k-th transfer signal generation circuit (T k ) and the output signal of the k+2 flip-flop Circuit (F k+2 ) output signal is applied, but the configuration of this embodiment is not limited to this configuration. stomach.

[0139] (Embodiment 5) In this embodiment, the flip-flop circuit and the transfer signal generation circuit shown in Embodiments 2 to 4 are A specific example of a transistor included in the synthesis circuit will be described.

[0140] As the transistor, transistors made of various materials and structures can be used. In other words, there is no limitation on the type of transistor to be used. For example, amorphous silicon, polycrystalline silicon, Silicon, microcrystalline (also called microcrystalline, nanocrystalline, or semi-amorphous) Thin film transistors (TFTs) with non-single crystal semiconductor films, such as capacitors, are used. It is possible.

[0141] There are various advantages to using thin film transistors to manufacture display devices. Thin film transistors can be manufactured at lower temperatures than transistors that use single-crystal silicon. This makes it possible to reduce the manufacturing cost of the display device or to increase the size of the manufacturing equipment. Because the manufacturing temperature of transistors is low, they can be manufactured on substrates with low heat resistance. Therefore, a transistor can be manufactured on a light-transmitting substrate with low heat resistance. Since the film thickness of the transistor is thin, it is possible to transmit light through a part of the film that forms the transistor. Therefore, the aperture ratio can be improved.

[0142] The transistors in question include MOS transistors, junction transistors, bipolar transistors, and It is also possible to use a MOS type transistor. By using a transistor, the size of the transistor can be reduced. By using a bipolar transistor as the transistor, a large current can be passed. This allows the circuit to operate at high speed. A bipolar transistor and a diode may be formed on the same substrate. This allows for low power consumption, compact size, and high-speed operation.

[0143] In addition, when producing polycrystalline silicon, by using a catalyst (such as nickel), The crystallinity can be further improved, and thin film transistors with good electrical properties can be manufactured. As a result, the gate driver, source driver, and signal processing circuit (signal generation circuit, gamma correction circuit) It is possible to integrate circuits (such as a positive circuit and a DA conversion circuit) on the board.

[0144] In addition, by using a catalyst (such as nickel) when manufacturing microcrystalline silicon, It is possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. In this case, the crystallinity can be improved by simply applying heat treatment without laser irradiation. As a result, part of the source driver (analog switch, etc.) and the gate driver The driver can be integrally formed on the substrate. This reduces the unevenness of the crystallinity of silicon, resulting in an improved image quality. It is possible.

[0145] However, polycrystalline silicon or microcrystalline silicon is produced without using a catalyst (such as nickel). You can also do this.

[0146] It is desirable to improve the crystallinity of silicon throughout the entire silicon. The crystallinity of silicon may be improved only in a part of the region. It is possible to improve the crystallinity by selectively irradiating the material with laser light. For example, the laser light is irradiated only on the gate driver and source driver areas. As a result, the crystallinity of silicon can be improved only in the area where high-speed circuit operation is required. Since there is little need for high-speed operation in the pixel section, the crystallinity does not need to be improved. Even if the pixel circuit is not irradiated with the crystalline Since fewer areas are required, the manufacturing process can be shortened, which improves throughput. Furthermore, the manufacturing cost of the display device can be reduced.

[0147] The transistor is not limited to a transistor using silicon. The transistors are made of compound semiconductors such as silicon germanium and gallium arsenide, or zinc oxide. A transistor using an oxide semiconductor such as zinc oxide containing lead, indium, and gallium Also, thin films of these compound semiconductors or oxide semiconductors can be used. Film transistors can also be applied, as they can be fabricated at low temperatures. For example, it is possible to manufacture transistors at room temperature. For example, a transistor can be formed directly on a plastic substrate or a film substrate. These compound semiconductors or oxide semiconductors can be used in the channel region of a transistor. For example, these compound semiconducting agents can be used for various purposes. Conductors or oxide semiconductors are used as wirings, resistor elements, pixel electrodes, light-transmitting electrodes, etc. They can be formed or deposited simultaneously with the transistors. Therefore, the manufacturing cost of the display device can be reduced.

[0148] The transistor may be a transistor having an organic semiconductor or a carbon nanotube. These allow transistors to be fabricated on flexible substrates. A display device using such a substrate has high impact resistance.

[0149] The method for manufacturing the transistor is not limited. A lithography method, an inkjet method, a printing method, or the like can be applied. The jet method and printing method do not use a mask (reticle) during manufacturing, so the transistor The layout can be easily changed. Furthermore, it can be manufactured without using resist. This reduces material costs and the number of processes. Since this makes it possible to reduce the amount of material wasted, the manufacturing cost of the display device can be reduced.

[0150] In addition, the transistor may have a multi-gate structure with two or more gate terminals. In the case of a multi-gate structure, the channel regions are connected in series. Therefore, the structure is such that multiple transistors are connected in series. This makes it possible to reduce the off-state current of the transistor and improve the withstand voltage (improve reliability). do.

[0151] The transistor has a structure in which gate terminals are arranged above and below the channel region. A transistor with a gate terminal disposed above and below the channel region can also be applied. By using this structure, the circuit configuration becomes like multiple transistors connected in parallel. In other words, the channel area increases, and the current value can be increased. Furthermore, by placing gate terminals above and below the channel region, a depletion layer is easily formed. This reduces the S value, thereby improving it.

[0152] In addition, the transistor has a structure in which a gate terminal is disposed above a channel region. , a structure in which the gate terminal is located under the channel region, a forward staggered structure, an inverse staggered structure, A structure in which the channel region is divided into multiple regions, a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in parallel It is also possible to apply a transistor having a structure in which channel regions are connected in series.

[0153] In addition, the transistor may have a source terminal or a drain terminal in the channel region (or a part thereof). A transistor with an overlapping drain terminal structure can also be used. By using a structure in which the source terminal and drain terminal overlap the channel (or a part of it), This can prevent the operation from becoming unstable due to charge accumulating in a part of the capacitor region.

[0154] Furthermore, a structure in which an LDD region is provided can also be applied to the transistor. By providing a DD region, the off-current can be reduced or the breakdown voltage of the transistor can be improved (reliability can be improved). Furthermore, by providing an LDD region, it is possible to reduce the In other words, even if the voltage between the drain and source changes, the drain current does not change much, and the voltage The slope of the current characteristic can be made flat.

[0155] Note that the transistor can be formed using various substrates. The type of the substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate ( For example, single crystal substrate or silicon substrate), SOI substrate, glass substrate, quartz substrate, plastic Metal substrate, stainless steel substrate, substrate with stainless steel foil , tungsten substrate, substrate with tungsten foil, flexible substrate, bonded film Examples of glass substrates include glass, paper containing fibrous materials, and base films. , barium borosilicate glass, aluminoborosilicate glass, or soda lime glass Examples of flexible substrates include polyethylene terephthalate (PET), polyethylene terephthalate (PE ... Plastics such as polyethylene naphthalate (PEN) and polyethersulfone (PES) Examples of laminated films include flexible synthetic resins such as acrylic and plastic. Examples include polypropylene, polyester, vinyl, polyvinyl fluoride, and vinyl chloride. Examples of the base film include polyester, polyamide, polyimide, and inorganic. In particular, semiconductor substrates, single crystal substrates, or SOI substrates. By manufacturing transistors using the above, variations in characteristics, size, shape, etc. can be eliminated. This allows for the production of transistors with low adhesion, high current capability, and small size. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or the circuit can be made highly efficient. Integration can be achieved.

[0156] Also, a transistor may be formed on one substrate and then transferred to another substrate. The transistor may be placed on one of the substrates to which the transistor is transferred. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, and the like. Fan substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, hemp), synthetic fibers (nylon) , polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, These substrates include recycled polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and low power consumption. This allows for the manufacture of devices that are less likely to break, heat resistant, lightweight, or thin.

[0157] (Sixth embodiment) In this embodiment, an example of an electronic device including the display device described in Embodiment 1 will be described. This will be explained with reference to FIGS.

[0158] 11(A) to 11(F) and 12(A) to 12(D) show the display device according to the first embodiment. These electronic devices are made up of a housing 5000, a display unit 5001, a screen Speaker 5003, LED lamp 5004, operation key 5005 (power switch or operation switch) including a switch), connection terminal 5006, sensor 5007 (force, displacement, position, velocity, acceleration, Angular velocity, rotation speed, distance, visible light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, Functions that measure current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays These electronic devices may include a microphone 5008, etc. The display device described in Embodiment 1 is incorporated in the display portion 5001 .

[0159] FIG. 11(A) shows a mobile computer, which, in addition to the above, also includes a switch. 11B shows a recording medium. 1 is a diagram showing a portable image playback device (for example, a DVD playback device) equipped with the above-mentioned In addition to the above, it may have a second display unit 5002, a recording medium reading unit 5011, etc. FIG. 11(C) shows a projector, which includes a light source 5033, A projection lens 5034, etc. are included. FIG. 11(D) is a diagram showing a portable game machine. In addition to the above, the system may also include a recording medium reading unit 5011. 1(E) shows a television receiver, which includes, in addition to the components mentioned above, a tuner, an image processor, , etc. FIG. 11(F) shows a portable television receiver, In addition to the above, it may have a charger 5017 capable of transmitting and receiving signals, etc. FIG. 12(A) shows a display, which includes, in addition to the above, a support base 5018, FIG. 12(B) shows a camera, and in addition to the above, , an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. Figure 12(C) shows a computer, which can be used to a monitoring device 5020, an external connection port 5019, a reader / writer 5021, etc. FIG. 12(D) shows a mobile phone, which can have the following features in addition to those mentioned above. , antennas, tuners for one-segment partial reception services for mobile phones and mobile terminals, etc. It can have.

[0160] The electronic devices shown in FIGS. 11(A) to 11(F) and 12(A) to 12(D) have various functions. For example, various information (still images, videos, text, images, etc.) can be displayed on the display. Display function, touch panel function, calendar, date or time display function, various Functions that control processing using software (programs), wireless communication functions, wireless communication devices the ability to connect to various computer networks using wireless communication functions, the function of transmitting or receiving data, the program or data recorded on the recording medium It can have a function to read out the information and display it on the display unit. In electronic devices, one display unit is used to mainly display image information, and another display unit is used to A function that mainly displays text information, or displays images that take parallax into account on multiple displays. By using the image receiving unit, it is possible to have a function of displaying a three-dimensional image. In electronic devices, there are functions to take still images, take videos, and store the images. Automatic or manual correction function, saving the captured image to a recording medium (external or built-in to the camera) The camera can have functions such as storing the captured image on the display unit, displaying the captured image on the display unit, etc. Functions that can be possessed by the electronic devices shown in Figs. 11(A) to (F) and 12(A) to (D) is not limited to these and can have various functions.

[0161] Next, an example of an electronic device that is integrated into a building will be explained using Figures 13(A) and 13(B). I will explain.

[0162] FIG. 13(A) is a diagram showing an example of an electronic device that is integrated with a building. The electronic device includes a housing 5022, a display portion 5023, a speaker 5025, and the like. The electronic device can be operated by a remote control device 5024. It is a wall-mounted type that is integrated into the building, so it can be installed without requiring a large space. It is possible to place it.

[0163] FIG. 13(B) is a diagram showing an example of an electronic device that is integrated with a building. The electronic device has a display unit 5026 and is attached near the bathtub 5027. The viewer can then view the display unit 5026.

[0164] In this embodiment, a wall and a bathroom are used as examples of buildings. The display panel can be installed in a variety of buildings, without being limited to these.

[0165] Next, an example in which an electronic device is integrated with a mobile object will be explained using Figs. 13(C) and 13(D). explain.

[0166] 13(C) is a diagram showing an example of an electronic device installed in an automobile. The electronic device is provided with a display unit 5028 and is attached to a body 5029 of the automobile. can display on demand the operation of the vehicle or information input from inside and outside the vehicle. The electronic device may also have a navigation function.

[0167] FIG. 13(D) is a diagram showing an example of electronic equipment installed in a passenger airplane. Specifically, FIG. 13(D) shows the electric power supply provided on the ceiling 5030 above the seats of a passenger airplane. The figure shows the shape of the sub-device when in use. The electronic device is attached to the ceiling 5030 by a hinge. The passengers can move the seats by extending and retracting the hinge part 5032. The electronic device displays information when operated by the passenger. It has a function.

[0168] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (mono It can be installed on a variety of things, including rails, railways, ships, etc.

[0169] The electronic device described in this embodiment has a display unit for displaying some information. The display device described in Embodiment 1 is incorporated in the display portion. [Example]

[0170] In this embodiment, the signal dullness and delay in a gate driver having a transfer signal generation circuit The suppression effect is verified by comparing it with a conventional example through circuit simulation.

[0171] Figure 14 shows the circuit simulation results for a conventional gate driver and the gate driver of this specification. Fig. 14(A) shows the configuration of a conventional gate driver. The output signal of the flip-flop circuit is used as the start pulse signal of the next flip-flop circuit. FIG. 14(B) shows the configuration of the gate driver of this specification, and A transfer signal generating circuit is provided between the drop circuits.

[0172] In this embodiment, the flip-flop circuit and the transfer signal generating circuit are implemented by the circuit shown in FIG. The output signal of the flip-flop circuit when configured as The calculation software used was PSpice. The threshold voltage of the transistors that make up the transfer signal generation circuit is set to 8 (V), and the field effect mobility is set to 0.5 (cm 2 / Vs). Also, each gate line is connected to a 100 (pF) It is assumed that a parasitic capacitance of 30V is formed. (H level potential is 30V, L level potential is 0V), ground potential is 0 (V), clock frequency The wave number was assumed to be 41.7 kHz (period: 24 μs).

[0173] Figure 15 shows the output signal of the flip-flop circuit obtained by circuit simulation. As shown in FIG. 15, the gate driver of this specification reduces signal delay and distortion. It was confirmed that: [Explanation of symbols]

[0174] 100 display device 101 Pixel section 102 Source Driver 103A First Gate Driver 103B Second Gate Driver 1041 source line 104 n Source line 1051 Gate Line 1052 gate lines 1053 Gate Line 105 m Gate line 106A Flexible Printed Circuit Board 106B Flexible Printed Circuit Board 107 11 pixel 107 nm pixel 401 Transistor 402 transistor 403 Transistor 404 Transistor 405 Transistor 406 Transistor 407 Transistor 408 Transistor 600 Inverter Circuit 600A inverter circuit 600B inverter circuit 601 Transistor 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Transistor 607 Transistor 608 Transistor 701A Transistor 701B transistor 702A Transistor 702B transistor 703B transistor 704B transistor 800 Control Circuit 800A control circuit 800B control circuit 801 transistors 802 transistors 803 Transistor 804 transistor 805 transistor 806 Transistor 807 Transistor 808 Transistor 809 Transistor 901A Capacitive Element 901B transistor 902A Transistor 902B transistor 903B Transistor 904B transistor 1001 Pixel unit 1002A First Gate Driver 1002B Second Gate Driver 10031 Gate Line 10032 gate line 1003 k Gate line 5000 cabinets 5001 Display section 5002 2nd display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5015 Shutter button 5016 Image receiving unit 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display section 5027 Bathtub 5028 Display section 5029 Car Body 5030 Ceiling 5031 Display section 5032 Hinge part 5033 Light source 5034 Projection lens

Claims

[Claim 1] A transistor having an oxide semiconductor in a channel region, The transistor has a multi-gate transistor structure in which the channel regions are connected in series.

Images