Back contact battery and method for manufacturing the same

Abstract

To provide a back contact battery relating to the technical field of solar power generation, capable of preventing a first doped semiconductor layer and a second doped semiconductor layer from becoming electrically conductive and shortening the movement distance of a part of carriers.SOLUTION: The back contact battery includes: a silicon substrate; and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed at intervals on a non-light-receiving surface side of the silicon substrate. On the non-light-receiving surface of the silicon substrate, the region corresponding to the first doped semiconductor layer is a first region, and the region corresponding to the second doped semiconductor layer is a second region. The region located between the first region and the second region adjacent to the first region is a spacing region. The surface of the second region is recessed into the silicon substrate with respect to a surface of the first region. The surface of the spacing region is recessed into the silicon substrate with respect to the surface of the second region. Side surfaces of the first doped semiconductor layer and the second doped semiconductor layer that are close to the spacing region are both substantially wavy.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to the field of photovoltaic technology, in particular to back-contact cells and their manufacturing methods. Regarding. [Background technology]

[0002] A back-contact battery is a battery that has no electrodes on the light-receiving surface of the battery cell, and both the positive and negative electrodes are This is a solar cell that is installed on the non-light-receiving side of the battery cell, so that the Reduce the shielding, increase the short circuit current of the battery cell, and improve the energy conversion efficiency of the battery cell. In addition, a surface passivation layer can be applied to the non-light-receiving side of the back-contact cell. By forming a thin film, the carrier recombination rate on the non-light-receiving side of the back-contact cell is reduced. This can improve the photoelectric conversion efficiency of back-contact cells.

[0003] However, conventional back-contact batteries have low carrier collection efficiency, This is disadvantageous for improving the operating performance of the battery. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device that prevents the first doped semiconductor layer and the second doped semiconductor layer from being electrically connected to each other. In this state, a back contact is used to shorten the travel distance of some carriers and improve carrier collection efficiency. To provide a back-contact battery and a manufacturing method thereof, which are advantageous for improving the operating performance of a back-contact battery. This is what we should do.

[0005] To achieve the above object, in a first aspect, the present invention provides a silicon substrate and a silicon substrate. The non-light-receiving side of the plate is provided with alternating first and second doped semiconductor layers. A back-contact cell is provided, comprising a first doped semiconductor layer and a second doped semiconductor layer. On the non-light-receiving side of the silicon substrate, the first doped semiconductor layer is of the opposite conductivity type. The region corresponding to the second doped semiconductor layer is the first region, and the region corresponding to the second doped semiconductor layer is the second region. The region between the first region and the adjacent second region is the spacing region. The surface of the first region is recessed into the silicon substrate relative to the surface of the first region. the surface of the spacing region is recessed into the silicon substrate relative to the surface of the first region, and the surface of the spacing region is the surface of the first region. whereas the depth recessed into the silicon substrate is less than 3000 nm.

[0006] When using the above technical solutions, the back contact battery provided by the present invention The first and second doped semiconductor layers, which have opposite conductivity types, are located on the non-light-receiving side of the silicon substrate. Based on this, the spacing between the non-light receiving surface of the silicon substrate The separation region separates the first doped semiconductor layer from the second doped semiconductor layer, and the first doped semiconductor layer The carrier recombination rate at the lateral boundary between the doped semiconductor layer and the second doped semiconductor layer can be reduced. This is advantageous for improving the photoelectric conversion efficiency of back-contact cells. a layer formed in a first region of the non-light-receiving surface, and a second doped semiconductor layer formed in a second region of the non-light-receiving surface; the surface of the second region is recessed into the silicon substrate relative to the surface of the first region; and In actual manufacturing, if the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, In the process, after selectively etching the first doped semiconductor layer that covers the entire non-light receiving surface side, The portions of the first doped semiconductor layer located in the second region and the spacing region are only completely removed. It is clear that the silicon substrate is also partially etched to a certain thickness. It is ensured that the first doped semiconductor layer does not remain in the region and the space region, and short circuits are prevented. and a first doped semiconductor layer having an opposite conductivity type and located on the non-light-receiving side of the silicon substrate. the doped semiconductor layer and the second doped semiconductor layer are at least partially offset in the thickness direction of the silicon substrate. This is also advantageous in that the risk of leakage on the non-light-receiving side is further reduced, and the power consumption of back-contact batteries is Similarly, the surface of the spacing region is in contact with the surface of the second region within the silicon substrate. In the case where the first doped semiconductor layer, the second region, and the spacing region are recessed in the actual manufacturing process, After selectively etching the second doped semiconductor layer deposited in the region, The first doped semiconductor layer and the portion located in the spacing region are not only completely removed, but also the silicon It is clear that the portions of the silicon substrate corresponding to the gap regions are also etched to a certain thickness. It is ensured that no second doped semiconductor layer remains in the first doped semiconductor layer and the spacing region. , short circuits are prevented.

[0007] As can be seen from the above, on the non-light receiving surface of the silicon substrate, the silicon in the gap region The recess depth into the substrate is the greatest, and the spacing region is the depth of the silicon substrate relative to the surface of the first region. The depth of the recess is less than 3000 nm. The buffer provided by the present invention has a larger recess depth than the case where the recess depth into the silicon substrate is 5 μm. In the case of a contact cell, the recess depth into the silicon substrate in the spacing region is small. Carriers of the corresponding conductivity type enter the first doped semiconductor without bypassing the deep gap region. The doped semiconductor layer or the second doped semiconductor layer can collect some of the carriers. This can shorten the distance traveled by the carriers and improve the carrier collection efficiency, making it possible to fabricate back-contact batteries. This is advantageous for improving dynamic performance.

[0008] In one possible implementation, the surface of the spacing area is flat. The surface is relatively flat. Based on this, back-contact cells can be fabricated with a surface passivation layer. When the surface passivation layer further includes a surface having a flat surface spacing compared to the texture, The thickness of the part formed in the area is larger, and the surface passivation for the spaced area Increasing the passivation effect of the layer and reducing the carrier recombination rate at the surface of the gap region. This is advantageous for improving the photoelectric conversion efficiency of back-contact cells.

[0009] In one possible implementation, per 10,000 square micrometers of the surface of the spacing region The roughness within the gap is less than 30 μm. The beneficial effect is similar to that of a flat surface, and will not be described here.

[0010] In one possible embodiment, the length of the spacing region in the direction of arrangement of the first region and the second region is 20 The thickness is 110 μm or more and 110 μm or less.

[0011] When the above technical solution is used, the length of the spacing region is within the above range, and the spacing is small. This prevents leakage current from occurring between the first doped semiconductor layer and the second doped semiconductor layer. This ensures high electrical reliability of the back-contact battery. The large gap allows the first doped semiconductor layer and / or the second doped semiconductor layer to be separated from the non-light-receiving surface side. The area where the doped semiconductor layer is formed is reduced, and the carriers on the non-light-receiving surface side are transferred to the first doped semiconductor layer and / or the second doped semiconductor layer. The loop semiconductor layer prevents the inability to collect the electrons in a timely manner and to lead them out of the corresponding electrodes. The carrier recombination rate on the non-light-receiving surface side can also be further reduced.

[0012] In one possible implementation, the surface of the second area is flat. The surface is relatively flat, which is advantageous for improving the formation quality of the second doped semiconductor layer formed in the second region. In addition, the surface of the second doped semiconductor layer formed in the second region and the undulations on the surface of the second region are Since the degree is similar, when the surface of the second region is flat, the silicon of the second doped semiconductor layer This is also advantageous for improving the surface flatness on the side away from the substrate. If the pond further includes a surface passivation layer, the surface passivation will be more effective than the texture. The thickness of the portion of the doped semiconductor layer formed on the second doped semiconductor layer, which has a high surface flatness, is larger. and a surface passivation layer on the side of the second doped semiconductor layer facing away from the silicon substrate. Improved passivation effect and carrier recombination rate on the non-light-receiving side of back-contact cells This is advantageous for improving the photoelectric conversion efficiency of back-contact batteries. .

[0013] In one possible implementation, the surface of the second region is recessed into the silicon substrate to a depth of 100 nm or more and 1000 nm or less.

[0014] When the above technical solution is used, the depth of the recess of the surface of the second region into the silicon substrate is increased. The depth of the recess of the surface of the second region into the silicon substrate is small, so that a first doped semiconductor layer and a second doped semiconductor layer, which are located on the non-light-receiving side of the silicon substrate and have opposite conductivity types; The thickness of the silicon substrate is prevented from being shifted too much in the direction of the thickness of the silicon substrate. The risk of electrical leakage can be further reduced. The recessed area is recessed into the silicon substrate, i.e., the recessed area is deeper into the silicon substrate than the second area. Therefore, when the recess depth of the surface of the second region into the silicon substrate is within the above range, The surface of the second region is recessed deeply into the silicon substrate, so that the silicon in the spacer region Preventing a greater recess depth into the substrate and bypassing the spacing region to allow the first doped semiconductor the distance traveled by some of the carriers transported to the first or second doped semiconductor layer is small. Furthermore, the depth of the recesses in the second region and the spacing region into the silicon substrate is large. This can prevent the use of a thick silicon substrate, This reduces the manufacturing cost of back-contact batteries and This is advantageous for realizing sheet production of the above.

[0015] In one possible implementation, the height difference between the surface of the second region and the surface of the spacing region is 30 0 nm or more and less than 2000 nm.

[0016] When the above technical solution is used, the height difference between the surface of the second region and the surface of the spacing region is Since the height difference is within the above range and is small, the second doped semiconductor The etching time must be strictly controlled after the conductive layer is completely removed from the gap. If this is not possible, the etching depth of the etching agent in the gap region of the silicon substrate can be reduced. This prevents the etching process from becoming difficult, and reduces the difficulty of etching. This prevents the travel distance of the corresponding conductive carriers from being significantly reduced, It is also possible to ensure the possibility of improving collection efficiency.

[0017] In one possible implementation, the spacing region between the first and second doped semiconductor layers The side surfaces of the second doped semiconductor layer near the spacing region are all substantially wavy. The corresponding variation in the face is greater than the corresponding variation in the side of the first doped semiconductor layer near the spacing region. The corresponding fluctuation frequency of the side of the second doped semiconductor layer near the spacing region is larger than the first doped semiconductor layer. 1 is smaller than the corresponding fluctuation frequency of the sidewall near the spacing region of the doped semiconductor layer.

[0018] When using the above technical solution, the distance between the first doped semiconductor layer and the second doped semiconductor layer When the side surfaces of the second doped semiconductor layer near the spacing region are both substantially wavy, the corresponding fluctuation range of the side surface of the first doped semiconductor layer near the spacing region is larger than the corresponding fluctuation range of the side surface of the first doped semiconductor layer near the spacing region. The roughness of the first doped semiconductor layer is determined by the roughness of the first doped semiconductor layer in the localized area of ​​the sidewall adjacent to the spacing region of the second doped semiconductor layer. the roughness of the second doped semiconductor layer formed on the surface of the semiconductor substrate is less than the roughness of the local area of ​​the sidewall adjacent to the spacing region of the layer; The number of defects in the region close to the spacing region of the second doped semiconductor layer is reduced, and This is advantageous in reducing the carrier recombination rate in the back contact cell, improving the operability of the back contact cell. The performance will be further improved.

[0019] In one possible implementation, the side walls of the spacing region have a cross section across at least a part of the spacing region. At least a portion of the surface is covered with water so that the area gradually increases in the direction from the light-receiving surface to the non-light-receiving surface. It is provided at an angle to the plane.

[0020] When the above technical solution is used, the cross-sectional area of ​​the light-receiving surface side of the gap region is larger than that of the non-light-receiving surface side of the gap region. a second doped semiconductor layer of opposite conductivity type to the first doped semiconductor layer; This is advantageous for increasing the distance between the back contact cell and the non-light receiving surface. This reduces the risk and ensures high electrical reliability for back-contact cells. The side walls of the area are angled with respect to the horizontal plane, which is advantageous for reflecting light. Therefore, there are more light rays at an angle to the horizontal plane on the sidewall of the spacing region. It is advantageous for the light to enter the silicon substrate from the non-light-receiving side of the back-contact cell under the effect of reflection of the Furthermore, it is advantageous for improving the photoelectric conversion efficiency of back-contact cells.

[0021] In one possible implementation, the back contact cell comprises a first doped semiconductor layer, a second doped semiconductor layer, and a It further includes a surface passivation layer covering the loop semiconductor layer and the spacing region.

[0022] When using the above technical solution, the surface passivation layer is Passivating the non-light-receiving side of the semiconductor to reduce the carrier recombination rate on the non-light-receiving side Also, the gap region with the deepest recess into the silicon substrate is the region with the deepest recess. Since the depth of the hole is less than 3000 nm, the back contact cell can be easily This is advantageous for reducing the degree of depression, and the thickness of the surface passivation layer formed on the non-light-receiving surface side is This increases the passivation effect of the surface passivation layer on the non-light-receiving side. It is advantageous for

[0023] In one possible implementation, the back contact cell comprises a first region of a silicon substrate. The semiconductor device further includes a first passivation layer located between the region and the first doped semiconductor layer.

[0024] When using the above technical solution, the first passivation layer and the first doped semiconductor layer can be selectively A selective contact structure is formed to chemically pad a first region of the non-light-receiving surface of the silicon substrate. and selectively collects carriers of the corresponding conductivity type. It can reduce the carrier recombination rate on the light-receiving surface side, and improve the photoelectric conversion efficiency of back-contact cells. This is advantageous for improving conversion efficiency.

[0025] In one possible implementation, the back contact cell is a second region of a silicon substrate. The semiconductor device further includes a second passivation layer located between the region and the second doped semiconductor layer.

[0026] When using the above technical solution, the second passivation layer and the second doped semiconductor layer can be selectively A selective contact structure is formed to chemically pad a second region of the non-light-receiving surface of the silicon substrate. and selectively collects carriers of the corresponding conductivity type. It can reduce the carrier recombination rate on the light-receiving surface side, and improve the photoelectric conversion efficiency of back-contact cells. This is advantageous for improving conversion efficiency.

[0027] In one possible implementation, the back contact cell includes a first passivation layer, and and when the first passivation layer is a tunnel passivation layer, the first doped semiconductor The layer is a doped polycrystalline silicon layer.

[0028] In one possible implementation, the back contact cell includes a second passivation layer, and and when the second passivation layer is a tunnel passivation layer, the second doped semiconductor The layer is a doped polycrystalline silicon layer.

[0029] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of providing a silicon substrate, the silicon substrate comprising: The non-light receiving surface is provided with first and second regions, and the first and second regions are alternately distributed at intervals. a step of forming a space region between the first region and a second region adjacent to the first region; forming a doped semiconductor layer, and arranging the surfaces of both the spacing region and the second region relative to the surface of the first region; forming a second doped semiconductor layer in the second region and recessing the second doped semiconductor layer in the second region; a surface of the region recessed into the silicon substrate relative to a surface of the second region, and a surface of the spacing region A step of recessing the silicon substrate to a depth of less than 3000 nm relative to the surface of one area. and a back contact battery manufacturing method including:

[0030] In one possible implementation, after the step of providing a silicon substrate, a second region is provided with a first 2. Before forming the doped semiconductor layer, the back contact cell fabrication method is a first doped semiconductor layer provided on the non-light-receiving surface over the entire surface; and a first region of the first doped semiconductor layer. forming a first mask layer located in a portion corresponding to the first mask layer; selectively removing portions of the first doped semiconductor layer located in the spacing region and the second region under irradiation; The surfaces of both the spacing region and the second region are then aligned relative to the surface of the first region into the silicon substrate. and c. recessing.

[0031] In one possible implementation, the material of the first doped semiconductor layer comprises silicon. a first doped semiconductor layer formed on the entire non-light-receiving surface of the silicon substrate; The step of forming a first mask layer located in a portion of the layer corresponding to the first region may include forming a silicon forming a first intrinsic semiconductor layer on a non-light-receiving surface of the semiconductor substrate, the first intrinsic semiconductor layer being provided over the entire surface of the semiconductor substrate; doping the intrinsic semiconductor layer to form a first doped semiconductor layer; and and forming a first doped silicate glass layer over the entire first doped semiconductor layer. Step and laser etching process removes the spaced regions of the first doped silicate glass layer. The portions corresponding to the first and second regions are heat-treated to heat-treat the first doped silicate glass layer. forming a first mask layer on the untreated portion; and forming a first doped silicate glass and removing the portion of the layer that has undergone the heat treatment.

[0032] When the above technical solution is used, when the material of the first doped semiconductor layer contains silicon, The material of the first intrinsic semiconductor layer for producing the first doped semiconductor layer also contains silicon. In any case, after the first intrinsic semiconductor layer is doped, the first doped semiconductor layer can be obtained. In addition, a first doped silicate glass layer is formed on the first doped semiconductor layer. Then, the first doped silica is formed by a laser etching process. In this case, the laser beam in the first doped silicate glass layer is heat-treated. The treated portion becomes less dense and is more easily removed. The untreated portions of the glass layer are dense and difficult to remove. Therefore, after the heat treatment, different portions of the first doped silicate glass layer have different etching properties. A first mask layer having a selectivity is obtained for patterning the first doped semiconductor layer. , additionally forming another mask material to obtain the first mask layer, and depositing another mask; There is no need to form a process, which reduces the manufacturing cost of back-contact batteries and This is advantageous in simplifying the manufacturing flow of contact batteries.

[0033] In one possible implementation, a wet chemical process is carried out under the masking effect of a first mask layer, selectively removing portions of the first doped semiconductor layer located in the spacing region and the second region, and The surfaces of the isolation region and the second region are both recessed into the silicon substrate relative to the surface of the first region. Wherein the process temperature of the wet chemical process is 60°C or more and 80°C or less; / or the process time of the wet chemical process is 40 seconds or more and 200 seconds or less; and / Or, the wet chemical etching solution used in the wet chemical process is alkaline wet chemical etching solution. The etching solution is an alkaline wet chemical etching solution, and the volume of the alkaline component in the alkaline wet chemical etching solution The ratio is 2% or more and 20% or less, and / or the wet method used in wet chemical processes The chemical etching solution contains a polishing additive, and the polishing additive is used as a wet chemical etching solution. The volume ratio of the inside is 0.5% or more and 5% or less.

[0034] When using the above technical solutions, the process temperature and process time of the wet chemical process The surfaces of the spacing region and the second region are both formed by a wet chemical process. This affects the depth of the recess in the silicon substrate relative to the surface. When the process temperature is within the above range, the process temperature is low, and therefore the interval the surface of the first region and the surface of the second region are both recessed into the silicon substrate relative to the surface of the first region. It is possible to prevent the depth from becoming small. The surfaces of the spacing region and the second region are both recessed into the silicon substrate relative to the surface of the first region. After this operation, the gap region and the second The depth to which the surface of the region is recessed into the silicon substrate relative to the surface of the first region is The surface of the second region in the back contact cell is silicon-based relative to the surface of the first region. The depth of the recess into the substrate is equal to the surface of the second region relative to the surface of the first region. Preventing the recessed depth into the silicon substrate from increasing or decreasing Next, the process time and the volume of the alkaline component are The beneficial effect of the ratio being within the above range is observed when the process temperature is 60°C or higher and 80°C or higher. The beneficial effects of the wet chemical process are similar to those of the wet chemical process. When the volume ratio of the polishing additive in the etching solution is within the above range, the gap region and The surface flatness of the two regions is increased, and the surface passivation for the spacing region and the second doped semiconductor layer is provided. This can further enhance the passivation effect of the protection layer.

[0035] In one possible implementation, the surfaces of the spacing region and the second region are both aligned relative to the surface of the first region. After the above step of recessing the silicon substrate, the method of manufacturing the back contact cell is as follows: depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region; forming a second mask layer in a portion corresponding to a second region of the second doped semiconductor layer; a portion of the second doped semiconductor layer corresponding to the first region and the spacing region under the masking effect of the mask layer; and recessing a surface of the spacing region into the silicon substrate relative to a surface of the second region. and

[0036] In one possible implementation, the material of the second doped semiconductor layer comprises silicon. a second doped semiconductor layer is deposited on the doped semiconductor layer, the spacing region and the second region; and The step of forming a second mask layer on a portion of the semiconductor layer corresponding to the second region includes forming a first mask layer on the first dopant. depositing a second intrinsic semiconductor layer on the gap semiconductor layer, the spacing region and the second region; doping the semiconductor layer to form a second intrinsic semiconductor layer as a second doped semiconductor layer; and A second doped silicate glass layer is formed on the second doped semiconductor layer. and removing the first region of the second doped silicate glass layer by a laser etching process. and heat treating the portion corresponding to the gap region to form a second region of the second doped silicate glass layer. forming a second mask layer over the corresponding portion; and forming a second doped silicate glass layer over the corresponding portion. and removing the portion that has undergone the heat treatment.

[0037] When the above technical solution is used, when the material of the second doped semiconductor layer contains silicon, The material of the second intrinsic semiconductor layer for producing the second doped semiconductor layer also contains silicon. In any case, after the second intrinsic semiconductor layer is doped, a second doped semiconductor layer can be obtained. In addition, a second doped silicate glass layer is formed on the second doped semiconductor layer. Then, a second doped silica layer can be formed by a laser etching process. The portions of the glass layer corresponding to the first region and the spacing region are heat-treated. The laser-treated portion of the silicate glass layer becomes less dense and is more likely to be removed. On the other hand, the portion of the second doped silicate glass layer corresponding to the second region is laser-treated. As a result, the density is high and it is difficult to remove. Different portions of the silicate glass layer have different etching selectivities, and the second doped semiconductor A second mask layer for patterning the body layer is obtained, and the second mask layer is obtained by There is no need to additionally form another mask material and to form another mask deposition process. Reduce the manufacturing cost of back contact batteries and simplify the manufacturing flow of back contact batteries. This is advantageous for simplification.

[0038] In one possible implementation, a wet chemical process is performed under the masking effect of the second mask layer, selectively removing portions of the second doped semiconductor layer corresponding to the first region and the spacing region, and The surface of the second region is recessed into the silicon substrate relative to the surface of the second region. The process temperature is 60°C or more and 80°C or less, and / or the wet chemical process The process time is 50 seconds or more and 300 seconds or less, and / or the wet chemical process The wet chemical etching solution used in the process is an alkaline wet chemical etching solution, The volume ratio of alkaline components in the alkaline wet chemical etching solution is 2% or more, and 0% or less and / or in wet chemical etching solutions used in wet chemical processes contains polishing additives, and the volume ratio of polishing additives in the wet chemical etching solution is 0.5% or more and less than 5%.

[0039] When using the above technical solutions, the process temperature and process time of the wet chemical process In both cases, the surface of the spacing region is silicon-bonded to the surface of the second region by a wet chemical process. This affects the depth of the recess in the silicon substrate. When the temperature is within the above range, the process temperature is low, so that the second region on the surface of the interval region can be easily formed. This prevents the depth of the recess into the silicon substrate from becoming smaller relative to the surface of the region. In addition, the high process temperature allows the surface of the space region to be in contact with the surface of the second region. This also prevents the recess depth into the silicon substrate from becoming too large. The depth of the surface of the spacing region recessed into the silicon substrate relative to the surface of the second region is small. See above for the beneficial effects of preventing the growth or enlargement of the Next, the beneficial effects of the process time and the volume ratio of the alkaline component being within the above ranges were investigated. The results are similar to the beneficial effects of a process temperature above 60°C and below 80°C. In addition, the volume ratio of the polishing additive in the wet chemical etching solution is increased. Within the above range, the flatness of the surface of the gap region after the operation can be increased, and the surface packing for the gap region can be improved. This can further enhance the passivation effect of the passivation layer.

[0040] In one possible implementation, after providing a silicon substrate, a first doped semiconductor is doped in the first region. Prior to forming the layer, the method for fabricating a back contact cell includes forming a first passivation layer on the first region. The method further includes forming a silicon layer.

[0041] In one possible implementation, the surfaces of the spacing region and the second region are both aligned relative to the surface of the first region. and recessing the silicon substrate, before forming a second doped semiconductor layer in the second region. Second, the method for manufacturing a back contact battery includes forming a second passivation layer on the second region. The method further includes the steps of:

[0042] In one possible implementation, the surface of the spacing region is inserted into the silicon substrate relative to the surface of the second region. After recessing, the back contact cell manufacturing method includes: The method further includes forming a surface passivation layer covering the conductor layer and the spacing region.

[0043] The beneficial effects of the second aspect of the present invention and its various embodiments are similar to those of the first aspect and its various embodiments. The analysis of the beneficial effects of various embodiments can be found in the following text, and the details are omitted here. do. [Brief explanation of the drawings]

[0044] The drawings described herein are included to provide a further understanding of the invention and are included to constitute a part of the invention. The exemplary embodiments and descriptions thereof are for the purpose of interpreting the present invention and are not intended to be limiting unless otherwise specified. No unduly limiting the invention is intended. A description of the drawings is provided below. [Figure 1] FIG. 1 is a SEM diagram of a longitudinal cross section of the structure of a back-contact battery in the related art. [Figure 2] 1 is a longitudinal cross-sectional view of a back-contact battery structure according to an embodiment of the present invention; FIG. [Figure 3] FIG. 1 is an SEM image (part 1) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 4] FIG. 2 is a SEM image (part 2) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 5] FIG. 3 is a SEM image (part 3) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 6] FIG. 4 is an SEM image (part 4) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 7] FIG. 5 is an SEM image (part 5) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 8] 1 is a structural diagram (part 1) of a back-contact battery according to an embodiment of the present invention during the manufacturing process; [Figure 9] FIG. 2 is a structural schematic diagram (part 2) of the back-contact battery according to the embodiment of the present invention during the manufacturing process. [Figure 10] FIG. 3 is a structural diagram (part 3) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 11] FIG. 4 is a structural schematic diagram (part 4) of the back-contact battery provided by the embodiment of the present invention during the manufacturing process. [Figure 12] FIG. 5 is a structural diagram (part 5) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 13] FIG. 6 is a structural schematic diagram (part 6) of the back-contact battery according to the embodiment of the present invention during the manufacturing process. [Figure 14] FIG. 7 is a structural schematic diagram (part 7) of the back-contact battery according to the embodiment of the present invention during the manufacturing process. [Figure 15] FIG. 8 is a structural diagram (part 8) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 16] 9 is a structural schematic diagram (part 9) of the manufacturing process of the back-contact battery provided by the embodiment of the present invention. [Figure 17] FIG. 10 is a structural schematic diagram (part 10) of the back-contact battery provided by an embodiment of the present invention during the manufacturing process. [Figure 18] FIG. 11 is a structural schematic diagram (part 11) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 19] 12 is a structural schematic diagram (part 12) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 20] FIG. 13 is a structural schematic diagram (part 13) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 21]FIG. 14 is a structural schematic diagram (part 14) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, these descriptions are merely examples. It should be understood that these are illustrative only and are not intended to limit the scope of the present disclosure. In the following description, reference will be made to known structures and techniques to avoid unnecessarily confusing the concepts of the present disclosure. The corresponding explanation will be omitted.

[0046] The drawings show various structural schematics according to embodiments of the present disclosure. These drawings are not to scale. It is not depicted as is, and some details have been enlarged here for clarity. The shapes of the various regions and layers shown in the figures may be omitted. , and the relative sizes and positional relationships between them are merely illustrative and may vary in actuality due to manufacturing tolerances. There may be variations due to technical limitations and those skilled in the art may be able to determine the actual needs. Depending on the design, regions / layers with different shapes, sizes, and relative positions can be designed separately. .

[0047] In the context of this disclosure, when one layer / element is described as being located "on" another layer / element, This layer / element may be located directly on this other layer / element, or there may be an intermediate layer between them. Also, in some orientations, one layer / element may be "on top" of another layer / element. If you place a layer / element in a stack, when you turn it over, that layer / element will be "under" another layer / element. The technical problems to be solved, the technical solutions and the beneficial effects of the present invention can be more clearly understood. For clarity, the present invention will be described in more detail below in combination with the figures and examples. The specific examples described herein are merely for the purpose of illustrating the present invention and should not be construed as limiting the scope of the present invention. It should be understood that this is not intended to limit the invention.

[0048] Additionally, the terms "first" and "second" are for descriptive purposes only and do not indicate relative importance. shall not be understood as implying or indicating the quantity of the technical features described. Therefore, a feature qualified as "first" or "second" clearly includes one or more of the feature. In the description of the present invention, unless expressly and specifically limited, "Plurality" means two or more than two. Unless expressly and specifically limited, "some" means one. means one or more than one.

[0049] In describing the present invention, it should be understood that unless expressly specified or limited, the term " "Attach," "couple," and "connect" should be understood broadly, e.g., to fix may be permanently connected, detachably connected, or integrally connected, The connection may be mechanical, electrical, or direct, or may be via an intermediate The two elements may be indirectly connected via the internal communication or interaction of the two elements. Those skilled in the art will be able to determine the specific meaning of the above terms in the present invention according to the specific circumstances. You can understand the meaning.

[0050] Currently, solar cells are being used widely as a new alternative energy form. Among them, photovoltaic solar cells are devices that convert solar light energy into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, which are then transported to electrodes. This is advantageous for extracting more carriers and therefore for using electrical energy more efficiently.

[0051] Here, both the positive and negative electrodes included in the solar cell are located on the non-light-receiving surface of the solar cell. The solar cell is a back-contact cell. The light-receiving surface of the back-contact cell is made of metal. Since back contact cells are not affected by shielding by electrodes, they are suitable for use in thick cells where the light receiving surface is shielded. Compared to solar cells, they have higher short-circuit current and photoelectric conversion efficiency, and currently, there are no methods to realize high-efficiency crystalline silicon cells. Specifically, as shown in Figure 1, The cells are usually arranged alternately on the silicon substrate 11 and on the non-light-receiving side of the silicon substrate 11 at intervals. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 are distributed in the first doped semiconductor layer 12 and the second doped semiconductor layer 13. The semiconductor layer 12 and the second doped semiconductor layer 13 are of opposite conductivity types.

[0052] In the actual manufacturing process, a first doped semiconductor layer is usually formed on the non-light-receiving side. and selectively etching the first doped semiconductor layer to form a doped semiconductor layer on a portion of the non-light-receiving surface. Then, the first doped semiconductor layer and the non-light-receiving layer are removed. forming a second doped semiconductor layer on the surface exposed to the first doped semiconductor layer; The first doped semiconductor layer and the second doped semiconductor layer are alternately spaced apart on the non-light-receiving surface of the silicon substrate. The second doped semiconductor layer is selectively etched to provide a distribution.

[0053] However, as shown in FIG. 1, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 Since the conductivity types are opposite, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are electrically connected. To prevent short circuits, conventional manufacturing methods involve separating the two layers by wet chemical etching or the like. However, in the conventional back contact battery, a gap region 16 having a certain width is formed between the In the example, the spacing region 16 located between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 Since the recess depth in the silicon substrate 11 is large (for example, greater than 5 μm), Carriers in the silicon substrate 11 must bypass the deep gap region to reach the first doped semiconductor. The conductor layer 12 and the second doped semiconductor layer 13 prevent the carriers from being collected, and the carriers travel a longer distance. The carrier collection efficiency is low and the carrier recombination rate is high, resulting in a This is disadvantageous for improving the operating performance of the contact battery.

[0054] In order to solve the above technical problem, in a first aspect, an embodiment of the present invention provides a back contact As shown in FIG. 2, a back contact provided by an embodiment of the present invention is provided. The cells are arranged alternately at intervals on the silicon substrate 11 and on the non-light-receiving side of the silicon substrate 11. The semiconductor device includes a first doped semiconductor layer 12 and a second doped semiconductor layer 13 disposed therebetween. The doped semiconductor layer 12 and the second doped semiconductor layer 13 are of opposite conductivity types. On the light receiving surface, the region corresponding to the first doped semiconductor layer 12 is the first region 14, and the second doped semiconductor layer 12 is the second doped region 14. The region corresponding to the loop semiconductor layer 13 is the second region 15, which is adjacent to the first region 14 itself. The area between the first area 15 and the second area 16 is the spacing area 16. The surface of the second area 15 is The surface of the spacer region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 14. The silicon substrate 11 is recessed relative to the surface of the first region 15 and is recessed relative to the surface of the first region 14. The depth of the recess into the silicon substrate 11 is less than 3000 nm.

[0055] When the above technical solution is used, as shown in FIG. 2, the embodiment of the present invention provides In a back-contact cell, a first doped semiconductor layer 12 and a second doped semiconductor layer 13 of opposite conductivity types are The layers 13 are distributed alternately at intervals on the non-light-receiving surface side of the silicon substrate 11. The gap region 16 on the non-light-receiving surface of the silicon substrate 11 is formed by the first doped semiconductor layer The first doped semiconductor layer 12 and the second doped semiconductor layer 13 are separated from each other. The carrier recombination rate at the lateral boundaries of layer 13 can be reduced, and the back contact This is advantageous for improving the photoelectric conversion efficiency of the photovoltaic cell. A second doped semiconductor layer 13 is formed in a second region 15 on the non-light-receiving surface. Therefore, the surface of the second region 15 is recessed into the silicon substrate 11 relative to the surface of the first region 14. The surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15. In this case, in the actual manufacturing process, the first doped semiconductor layer 12 that covers the entire non-light receiving surface side is formed. After selectively etching the second region 15 and the spacing region 16 of the first doped semiconductor layer 12, 11 is completely removed, and the silicon substrate 11 is partially removed to a constant thickness. It is clear that the second region 15 and the spacing region 16 are etched with the first doped semiconductor. It is ensured that no conductive layer 12 remains, short circuits are prevented, and both are silicon substrate The first doped semiconductor layer 12 and the second doped semiconductor layer 13 are located on the non-light-receiving side of the first doped semiconductor layer 11 and have opposite conductivity types. It is also advantageous to at least partially offset the conductor layer 13 in the thickness direction of the silicon substrate 11. This further reduces the risk of electrical leakage on the non-light-receiving side, improving the electrical reliability of back-contact batteries. Similarly, the surface of the spacer region 16 is closer to the surface of the second region 15 than the surface of the silicon substrate 11. In the case where the first doped semiconductor layer 12 and the second region 15 are recessed inward, After selectively etching the second doped semiconductor layer 13 deposited in the spacer region 16, The second doped semiconductor layer 13 is completely doped with the first doped semiconductor layer 12 and the portion of the second doped semiconductor layer 13 located in the spacer region 16. Not only is the silicon substrate 11 removed in a uniform thickness, but the portion corresponding to the gap region 16 is also removed in a uniform thickness. It is clear that the first doped semiconductor layer 12 and the spacing region 16 are etched with This ensures that no doped semiconductor layer 13 remains, preventing short circuits. As can be seen from the figure, the silicon substrate 11 in the spaced region 16 on the non-light-receiving surface The recess depth into the first region 11 is the largest, and the spacing region 16 is silicon-bonded to the surface of the first region 14. The depth of the recess into the silicon substrate 11 is less than 3000 nm. In the embodiment of the present invention, the recess depth of the spacer region into the silicon substrate is 5 μm. The back contact cell provided by recessing the spacing region 16 into the silicon substrate 11 In this case, carriers of the corresponding conductivity type bypass the deep spacing region 16. collection by the first doped semiconductor layer 12 or the second doped semiconductor layer without rotation; This reduces the distance some carriers travel and increases carrier collection efficiency. This is advantageous for improving the operating performance of back-contact batteries.

[0056] In actual application, as shown in FIG. 2, the light receiving surface of the silicon substrate 11 is flat. Alternatively, the light receiving surface of the silicon substrate may be textured. Since texture has a light trapping effect, if the light receiving surface of the silicon substrate is textured, the receiving This reduces the reflectivity of the light surface, allowing more light rays to be refracted from the light-receiving surface into the silicon substrate. It is advantageous for use by being absorbed by a contact substrate, and the photoelectric conversion efficiency of back contact cells is improved. It is advantageous for improvement.

[0057] In terms of range, the first region, the second region and the second region on the non-light-receiving surface side of the silicon substrate are The boundary of the spacing region is a virtual boundary. As shown in FIG. 2, the first doped semiconductor layer 12 is Therefore, the first doped semiconductor layer 12 is formed in the region 14, and therefore the formation range requirement of the first doped semiconductor layer 12 in an actual application scenario is The range of the first region 14 on the non-light-receiving surface side of the silicon substrate 11 is determined according to the requirements. Next, the second doped semiconductor layer 13 is formed in the second region 15, so that the actual application Depending on the scenario, the non-receptive area of ​​the silicon substrate 11 may be increased or decreased depending on the required area for forming the second doped semiconductor layer 13. The range of the second region 15 on the light surface side can be determined. As stated above, the spacing region 16 is formed by a first doped semiconductor layer 12 and a second doped semiconductor layer 13 of opposite conductivity types. Therefore, in a practical application scenario, According to the requirement for the leakage prevention gap between the first doped semiconductor layer 12 and the second doped semiconductor layer 13, In this way, the range of the interval region 16 on the non-light-receiving surface side can be determined.

[0058] For example, the length of the spacing region in the arrangement direction of the first region and the second region is 20 μm or more, and For example, the length of the spaced region is 20 μm, 40 μm, 60 μm, 8 μm, or less. In this case, the length of the spaced region may be 0 μm, 100 μm, 110 μm, or the like. The distance is small, so that the first doped semiconductor layer and the second doped semiconductor layer This prevents leakage current from occurring between the battery and the back contact, ensuring high electrical reliability of the battery. In addition, since the distance is large, the first doped semiconductor layer and / or the second doped semiconductor layer can be easily formed. The area where the doped semiconductor layer is formed on the non-light-receiving surface side is reduced, and the carriers on the non-light-receiving surface side are The doped semiconductor layer and / or the second doped semiconductor layer may not be collected in a timely manner and may be conducted from the corresponding electrode. This prevents the inability to emit light and further reduces the carrier recombination rate on the non-light-receiving side. can.

[0059] From the viewpoint of the recess depth, the second region and the interval region of the non-light-receiving surface of the silicon substrate are The depth of the recess into each silicon substrate and the height difference between the surfaces of the second region and the spacing region are actually The second region may be recessed inward relative to the surface of the first region. and the surface of the spacing region is recessed inward relative to the surface of the second region, and the surface of the spacing region is The depth of the surface recessed into the silicon substrate relative to the surface of the first region is less than 3000 nm. All we need to do is ensure that this is the case.

[0060] Illustratively, the recess depth of the surface of the second region into the silicon substrate is 100 nm or more, and For example, the surface of the second region may be recessed into the silicon substrate. Depth: 100nm, 300nm, 600nm, 800nm, 900nm or 1000nm In this case, the depth of the recess in the silicon substrate on the surface of the second region is within the above range. The depth of the recess of the surface of the second region into the silicon substrate is small, so that both The first doped semiconductor layer and the second doped semiconductor layer are located on the non-light-receiving side of the substrate and have opposite conductivity types. The degree of misalignment of the conductor layer in the thickness direction of the silicon substrate is prevented from becoming small, and the leakage on the non-light receiving surface side is reduced. The risk of electrical discharge can be further reduced. The spacing region is recessed into the silicon substrate to a greater depth than the second region. Therefore, if the recess depth of the surface of the second region into the silicon substrate is within the above range, The surface of the region is recessed deep into the silicon substrate, so that the silicon substrate in the spaced region to prevent a larger recess depth into the first doped semiconductor layer by bypassing the spacing region. or ensuring that the travel distance of some of the carriers transported to the second doped semiconductor layer is short. Furthermore, the depth of the recesses in the second region and the spacing region into the silicon substrate is large. This can prevent the use of a thick silicon substrate, This reduces the manufacturing cost of back-contact batteries and This is advantageous for realizing sheet production of the above.

[0061] Illustratively, the height difference between the surface of the second region and the surface of the spacing region is 300 nm or more; For example, the thickness between the surface of the second region and the surface of the spacing region may be less than 2000 nm. The height difference is 300nm, 600nm, 900nm, 1200nm, 1500nm, 180 In this case, the surface of the second region and the surface of the space region may be 0 nm or 2000 nm. The height difference between the two is within the above range, and since the height difference is small, it is possible to After completely removing the portion of the second doped semiconductor layer located in the gap region, the etching time is Unless the etching depth is strictly controlled, the etching depth of the etchant into the gap region of the silicon substrate may be limited. This prevents the thickness from being reduced, and reduces the difficulty of etching. The large difference in height does not significantly reduce the travel distance of the corresponding conductivity type carriers. This can prevent the problem and ensure the possibility of improving the carrier collection efficiency.

[0062] Regarding the recess depth into the silicon substrate of the spacing region, the depth value is the depth of the silicon at the surface of the second region. It may be any value greater than the depth of the recess in the substrate and less than 3000 nm. For example, if the recess depth of the surface of the second region into the silicon substrate is 500 nm, The depth of the isolation region recessed into the silicon substrate relative to the surface of the first region is greater than 500 nm. and any value less than 3000 nm (for example, 1000 nm, 1500 nm, 180 0nm, 2000nm, 2500nm, 2800nm, or 2900nm, etc. stomach.

[0063] From the viewpoint of surface morphology, as shown in FIG. 2, on the non-light-receiving surface of the silicon substrate 11, The surface of the first region 14 is flat. The surface of the second region 15 is flat, but has a texture. Here, as shown in FIGS. 2 to 7, when the surface of the second region 15 is flat, In this case, the surface of the second region 15 is relatively flat, and the second doped semiconductor formed in the second region 15 This is advantageous in improving the quality of the formed semiconductor layer 13. Since the surface of the layer 13 and the surface of the second region 15 have similar undulations, the surface of the second region 15 is flat. In this case, the surface flatness of the second doped semiconductor layer 13 on the side away from the silicon substrate 11 is improved. Based on this, back-contact cells are designed to have a surface passivation layer 17 When the surface passivation layer 17 further includes the following, the surface flatness of the surface passivation layer 17 is improved compared to the texture. The thickness of the portion formed in the highly doped second semiconductor layer 13 is larger, and the second doped semiconductor The surface passivation layer 17 is formed on the side of the dielectric layer 13 facing away from the silicon substrate 11. This enhances the insulation effect and further increases the carrier recombination rate on the non-light-receiving side of back-contact cells. This is advantageous for improving the photoelectric conversion efficiency of back-contact cells.

[0064] As for the spacing region, as shown in FIGS. 2 to 7, the surface of the spacing region 16 is flat. Here, as shown in FIGS. 2 to 7, the surface of the interval region 16 may be a texture. When the surface is flat, the surface of the spacing region 16 is relatively flat. If the contact cell further includes a surface passivation layer 17, the surface The thickness of the surface passivation layer 17 formed in the planar surface of the gap region 16 is The passivation effect of the surface passivation layer 17 on the gap region 16 increases. The carrier recombination rate on the surface of the spacer region 16 can be reduced, and the back contact Specifically, the surface roughness of the spacer region 16 is Passivation of the surface passivation layer 17 for the gap region 16 in the actual application scenario The amount may be determined depending on the requirements for the performance and the actual manufacturing process. do not.

[0065] Illustratively, the area ( The roughness within the area of ​​100 micrometers x 100 micrometers is 30 μm or less. For example, per 10,000 square micrometers of the surface of the spacing region Roughness ranges are 5μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm , 25 μm or 30 μm, etc. The beneficial effect in this case is that the surface of the spacing region is flat. This is similar to the beneficial effect of the surface, and will not be described here.

[0066] Here, when the surface of the second region or the space region is textured, the texture of the surface The size of the texture may be determined according to the depth of the recess of the texture into the silicon substrate. This is not a specific limitation. As can be understood, within a certain range, the silicon The smaller the recess depth into the substrate, the smaller the size of the texture structure on the surface. It should also be noted that if the surface of the second region or the spacing region is textured, The depth of the recess of the surface of the second region or the spacing region into the silicon substrate is is equal to the vertical distance from the center of the texture structure to the surface of the first region.

[0067] Regarding the shape of the sidewall of the spacing region, as shown in FIG. 2, the sidewall of the spacing region 16 is a horizontal plane. Alternatively, as shown in FIG. 13, the sidewalls of the spacing region 16 may be The cross-sectional area of ​​at least a part of the spacing region 16 gradually increases in the direction from the light-receiving surface to the non-light-receiving surface. At least a part of the surface is provided at an angle to the horizontal plane so that the The cross-sectional area of ​​the light-receiving surface side of the partition region 16 is smaller than the cross-sectional area of ​​the non-light-receiving surface side of the partition region 16. The distance between the doped semiconductor layer 12 and the second doped semiconductor layer 13 of the opposite conductivity type is increased. This is advantageous for reducing the risk of leakage current on the non-light-receiving side of back-contact batteries, In addition, the horizontality of the sidewalls of the spacer region 16 is reduced. The part that is angled to the surface is also advantageous for reflecting light, and more light rays are The sidewalls of the spacing region 16 are inclined relative to the horizontal plane, and the reflection of the It is advantageous for the light to enter the silicon substrate 11 from the non-light-receiving side of the black contact cell, and further This is advantageous for improving the photoelectric conversion efficiency of back-contact cells.

[0068] In the above case, the side wall of the spacing region is provided obliquely with respect to the horizontal plane. The angle between the part and the horizontal plane is determined according to the actual manufacturing process and the reflection requirements for the side wall. However, there are no specific limitations here.

[0069] For example, the side wall of the spacing region may have a portion obliquely provided with respect to the horizontal plane and a portion horizontally provided with respect to the horizontal plane. The angle formed with the surface may be 52° or more and 58° or less. The angle between the horizontal plane and the part of the wall that is diagonally installed in relation to the horizontal plane is 52°. The angle may be 53°, 54°, 55°, 56°, 57°, 58°, etc. When the angle is within the above range, more light rays are oblique to the horizontal plane on the side wall of the spacing region. Under the large reflection effect of the part installed in This ensures that the back contact cells are used in a more efficient manner, further improving the light utilization rate of the back contact cells.

[0070] Regarding the first doped semiconductor layer and the second doped semiconductor layer, from the viewpoint of materials, The material of the first doped semiconductor layer or the second doped semiconductor layer is silicon, germanium silicon, or the like. The material may be a semiconductor material such as germanium or gallium arsenide. Therefore, the crystalline phase of the first doped semiconductor layer or the second doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, or the like. The first doped semiconductor layer and the second doped semiconductor layer may be crystalline, single crystalline, polycrystalline, etc. As long as it is ensured that the doped semiconductor layers are of opposite conductivity types, the first doped semiconductor layer or the second doped semiconductor layer may be The conductivity type of the doped semiconductor layer may be the same or opposite to that of the silicon substrate. The thickness of the first doped semiconductor layer and the second doped semiconductor layer may be adjusted according to actual needs. For example, the first doped semiconductor layer or the second doped semiconductor layer may be set as The thickness of the loop semiconductor layer may be 100 nm or more and 500 nm or less.

[0071] In actual application, the first doped semiconductor layer is formed directly on the first region of the silicon substrate. Alternatively, as shown in FIG. 2, a back-contact cell may be formed on the silicon substrate 11. a first passivation layer located between the first region 14 and the first doped semiconductor layer 12; In this case, the first passivation layer 18 and the first doped semiconductor layer 12 are A selective contact structure is formed to contact the first region 14 of the non-light receiving surface of the silicon substrate 11. Chemical passivation is achieved and selective collection of carriers of the corresponding conductivity type is achieved. This reduces the carrier recombination rate on the non-photosensitive side, and the back contact voltage This is advantageous for improving the photoelectric conversion efficiency of the pond.

[0072] Specifically, the material of the first passivation layer is the material of the first doped semiconductor layer, and Selection of first passivation layer and first doped semiconductor layer in practical application scenarios The length may be determined depending on the type of the contact structure, and is not specifically limited here.

[0073] For example, a selective contact structure comprising a first passivation layer and a first doped semiconductor layer is In the case of a tunnel passivation contact structure, the first doped semiconductor layer is doped polycrystalline silicon. The first passivation layer is a tunnel passivation layer. The material of the passivation layer is silicon oxide, aluminum oxide, or titanium oxide. It may include.

[0074] Further, for example, a selective contact structure comprising a first passivation layer and a first doped semiconductor layer. When the first doped semiconductor layer is a hetero-contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped amorphous silicon layer. the first passivation layer is an intrinsic amorphous silicon layer and / or is an intrinsic microcrystalline silicon layer.

[0075] The thickness of the first passivation layer may be set according to actual needs. For example, the thickness of the first passivation layer is 0.5 nm or more, and The thickness may be 3 nm or less.

[0076] Regarding the second doped semiconductor layer, the second doped semiconductor layer is formed on a second region of the silicon substrate. Alternatively, as shown in FIG. 2, the back contact cell may be formed directly on a silicon substrate. A second passivation layer is disposed between the second region 15 of the plate 11 and the second doped semiconductor layer 13. In this case, the second passivation layer 19 and the second doped semiconductor The layer 13 forms a selective contact structure and contacts a second region 15 on the non-light-receiving surface of the silicon substrate 11. and selectivity for the carriers of the corresponding conductivity type. This allows for efficient collection of carriers, reducing the recombination rate on the non-photosensitive side, and This is advantageous for improving the photoelectric conversion efficiency of tactile batteries.

[0077] Specifically, the material and thickness of the second passivation layer are the same as those of the first passivation layer described above. The material and thickness of the insulation layer can be referred to, and the explanation is omitted here.

[0078] In terms of configuration, the embodiment of the present invention has a first doped semiconductor layer and a second doped semiconductor layer. The shape of the side surface near the partition region is not specifically limited, and the back contact provided by the embodiment of the present invention It is sufficient if it can be applied to a contact battery. The side surface of the semiconductor layer near the spacing region may be linear, polygonal, arcuate, or substantially wavy. Here, the shape of the side surface of the first doped semiconductor layer near the spacing region may be the same as that of the second doped semiconductor layer. The shape of the side surface of the semiconductor layer near the spacing region may be the same as or different from that of the side surface.

[0079] In the actual application process, as shown in FIGS. 3 to 7, The side surfaces of the conductor layer 12 and the second doped semiconductor layer 13 near the spacing region 16 are both substantially wavy. Also, there may be a corresponding variation in the side of the second doped semiconductor layer 13 near the spacing region 16. The width is greater than the corresponding variation width of the side of the first doped semiconductor layer 12 near the spacing region 16. and a corresponding variation frequency of the side of the second doped semiconductor layer 13 near the spacing region 16. is smaller than the corresponding fluctuation frequency of the side of the first doped semiconductor layer 12 near the spacing region 16. In this case, a corresponding variation in the side surface of the second doped semiconductor layer 13 close to the spacing region 16 may be The width is greater than the corresponding variation width of the side of the first doped semiconductor layer 12 near the spacing region 16. , the roughness of the local area of ​​the side surface of the second doped semiconductor layer 13 near the spacing region 16 is The roughness of the formed second dopant is smaller than the roughness of the local region of the side surface of the layer 12 near the gap region 16. The number of defects in the portion of the doped semiconductor layer 13 near the spacing region 16 is reduced, and the second doped semiconductor This is advantageous in reducing the carrier recombination rate in the portion of layer 13 near spacing region 16, and This further improves the operating performance of the contact battery.

[0080] Here, the corresponding side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region are The fluctuation range refers to the range of rise and fall of the protruding portion of the side surface relative to the lowest point of the recessed portion of the side surface. corresponding fluctuation frequencies of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region; The frequency of different protrusions on the side surface is shown in Fig. 1. Specifically, the first doped semiconductor When the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region are both substantially wavy, The fluctuation width and frequency of the side surfaces of the doped semiconductor layer and the second doped semiconductor layer near the spacing region are actually The thickness may be determined depending on the manufacturing process of the material, and is not specifically limited here.

[0081] In one possible implementation, as shown in FIG. 2, the back contact battery includes a first dome. a surface passivation covering the doped semiconductor layer 12, the second doped semiconductor layer 13 and the spacing region 16; The surface passivation layer 17 may further comprise a back contact. The non-light-receiving side of the photovoltaic cell is passivated to reduce the carrier recombination rate on the non-light-receiving side. The gap region 16, which has the deepest recess into the silicon substrate 11, is , the corresponding recess depth is less than 3000 nm, so the non-light-receiving of back-contact cells This is advantageous in reducing the degree of unevenness in each region on the surface side, and The thickness of the surface passivation layer 17 formed on the light-receiving surface side is increased, and the passivation layer 17 is formed on the non-light-receiving surface side. This is advantageous in enhancing the oxidization effect.

[0082] Specifically, the material of the surface passivation layer is silicon oxide, aluminum oxide or The insulating material may be any insulating material with passivation properties, such as silicon nitride. The thickness of the surface passivation layer may be determined according to the actual application scenario; There are no specific limitations here.

[0083] In a second aspect, embodiments of the present invention provide a method for fabricating a back-contact battery, as follows: The manufacturing process will be explained based on the cross-sectional views of the operations shown in Figures 2 to 21. The manufacturing method of the back contact battery includes the following steps:

[0084] First, a silicon substrate is prepared, and the non-light receiving surface of the silicon substrate is provided with alternately spaced apart portions. The first and second regions are distributed, and the first region is located between the second region adjacent to the first region itself. It has a spacing area.

[0085] Specifically, the ranges of the first region, the second region and the interval region on the non-light-receiving surface side are as described above. Therefore, the explanation will be omitted here.

[0086] Next, as shown in FIGS. 12 to 14, a first doped semiconductor layer 12 is formed in the first region 14. The surfaces of the spacing region 16 and the second region 15 are both silicon-bonded to the surface of the first region 14. The recess is recessed into the substrate 11.

[0087] In the actual manufacturing process, as shown in FIG. 11, after preparing a silicon substrate 11, A first doped semiconductor layer 12 is provided on the non-light receiving surface of the silicon substrate 11, and a first doped A first mask layer 20 is formed at a portion corresponding to the first region 14 of the semiconductor layer 12. Next, as shown in FIGS. 12 and 13, under the masking effect of the first mask layer 20, The portions of the first doped semiconductor layer 12 located in the spacing region 16 and the second region 15 are selectively removed. and the surfaces of both the spacing region 16 and the second region 15 are aligned relative to the surface of the first region 14. The recess is then recessed into the silicon substrate 11 .

[0088] Here, the material and thickness of the first doped semiconductor layer, and the surface roughness of the spacing region and the second region after the operation are shown in FIG. The depth of the recess into the silicon substrate on each side can be determined by referring to the previous paragraph. Regarding the first mask layer, the material may be any material that has a masking effect. Next, the specifics of the first doped semiconductor layer and the first mask layer will be described. The formation process and specific formation of the first doped semiconductor layer and the first mask layer are determined according to the materials. The process can be determined.

[0089] For example, when the material of the first doped semiconductor layer includes silicon, the non- A first doped semiconductor layer is provided on the light receiving surface in the entire layer, and a first region of the first doped semiconductor layer is provided on the light receiving surface. The step of forming the first mask layer located in the corresponding portion includes the steps of: As shown in FIG. 8, a first true layer is provided on the non-light receiving surface of the silicon substrate 11. Next, as shown in FIG. 9, the first intrinsic semiconductor layer 22 is doped. The first intrinsic semiconductor layer 22 is formed as the first doped semiconductor layer 12, and the first doped A first doped silicate glass layer 23 is formed on the entire semiconductor layer 12. Then, as shown in Figure 10, the first doped silicate glass was removed by a laser etching process. The portions of the silicon layer 23 corresponding to the spacing region 16 and the second region 15 are heat treated to form the first doped silica. The portion of the glass layer 23 that has not been subjected to the heat treatment is formed as a first mask layer 20. As shown in FIG. 11, the heat-treated portion of the first doped silicate glass layer 23 is removed. .

[0090] Specifically, the material of the first doped semiconductor layer contains silicon. It may mean that the material of the first doped semiconductor layer contains only silicon, or that the material of the first doped semiconductor layer contains silicon. This means that it not only includes silicon, but also other semiconductor materials such as germanium silicon. Next, in the actual manufacturing process, a non-photosensitive layer may be formed by a process such as chemical vapor deposition. A first intrinsic semiconductor layer can be formed on the entire surface of the substrate. The first intrinsic semiconductor layer can be doped by the doping process. Not only can a first doped semiconductor layer be obtained, but also a second doped semiconductor layer can be provided on the first doped semiconductor layer. A first doped silicate glass layer can be formed by laser etching. The first doped silicate glass layer is partially heat treated by a heating process. As shown in FIG. 0, the laser-treated portion of the first doped silicate glass layer is dense. On the other hand, the laser damage in the first doped silicate glass layer is reduced. The untreated parts are dense and difficult to remove, which makes it difficult to remove after heat treatment. Different portions of the first doped silicate glass layer have different etching selectivities, A first mask layer 20 for patterning the group semiconductor layer 12 is obtained. To obtain the mask layer 20, other mask materials are additionally formed and other mask deposition steps are performed. This reduces the manufacturing cost of back-contact batteries and eliminates the need for back-contact This is advantageous in simplifying the manufacturing flow of the battery. The necessary conditions may be set according to the actual application scenario, but they are not specifically limited here. do not.

[0091] For example, the lasers used in the laser etching process are nanosecond lasers, picosecond lasers, The laser etching process may be performed using a laser of 10 W or more, or a femtosecond laser. The laser spot diameter is 50 μm or more and 300 μm or less. It may be less than m.

[0092] Of course, the material of the first doped semiconductor layer may contain silicon, or the first doped semiconductor layer may contain silicon. If the material does not contain silicon, it can be made non-receptive by processes such as chemical vapor deposition and doping. A first doped semiconductor layer may be formed on the light-side surface. and etching processes to mask other materials such as silicon nitride. A first mask layer having the following structure can be formed.

[0093] After forming the first mask layer, the first mask layer is formed by a wet chemical process. selectively removing portions of the first doped semiconductor layer located in the spacing region and the second region under irradiation; The surfaces of both the spacing region and the second region are then aligned relative to the surface of the first region into the silicon substrate. The recess prevents damage to the silicon substrate caused by high-temperature lasers, and the back contact This is advantageous for improving the yield of the battery. Specifically, the first doped semiconductor layer is selectively etched. The etching process conditions depend on the etching process used, the material of the first doped semiconductor layer, and based on the depth of the recesses in the silicon substrate of the surfaces of the space region and the second region after the operation, etc. It can be determined, and there are no specific limitations here.

[0094] Illustratively, a first doped semiconductor is deposited by a wet chemical process under the masking effect of the first mask layer. selectively removing portions of the conductor layer located in the spacing region and the second region, and When the surfaces of the two regions are both recessed into the silicon substrate relative to the surface of the first region, the wet The process temperature of the chemical process may be 60°C or more and 80°C or less, and the humidity The process time of the chemical process may be 40 seconds or more and 200 seconds or less, and Therefore, the wet chemical etching solution used in the wet chemical process is alkaline wet chemical etching. The alkaline component in the alkaline wet chemical etching solution may be a etchant. The volume ratio of (e.g., NaOH or KOH) may be 2% or more and 20% or less. For example, the process temperature for wet chemical processes is 60°C, 70°C, 75°C, 78°C or 80°C. The process time for the wet chemical process may be 40 s, 60 s, 80 s, 10 0s, 150s, 200s, etc. Wet chemistry used in wet chemical processes If the etching solution is an alkaline wet chemical etching solution, The volume ratio of alkaline components in the etching solution is 2%, 3%, 6%, 9%, 12%, 15% or In this case, the process temperature and process time of the wet chemical process may be The surfaces of the spacing region and the second region are both formed by a wet chemical process. This affects the depth of the recess into the silicon substrate relative to the surface of the region. When the process temperature of the chemical process is within the above range, the process temperature is low, and therefore, the The surfaces of the isolation region and the second region are both recessed into the silicon substrate relative to the surface of the first region. In addition, it is possible to prevent the depth of the etched area from becoming small due to the high process temperature. The surfaces of the spacing region and the second region are both recessed into the silicon substrate relative to the surface of the first region. After this operation, the gap region and the The depth to which the surfaces of the two regions are recessed into the silicon substrate relative to the surface of the first region is The surface of the second region in the fabricated back contact cell is silicon-bonded to the surface of the first region. The depth of the recess into the silicon substrate is equal to the surface of the second region relative to the surface of the first region. and preventing the recessed depth into the silicon substrate from increasing or decreasing. The beneficial effects of the process time and the amount of alkaline component can be seen in the previous paragraph. The beneficial effect of the volume ratio being within the above range is observed when the process temperature is 60°C or higher and 80 This is similar to the beneficial effect of being 0.1°C or less, and therefore will not be explained here.

[0095] In addition, by adding abrasive additives to the wet chemical etching solution, the interval after the operation and increasing the flatness of the surface of the second region and the spacing region and improving the surface performance of the second doped semiconductor layer. This can further enhance the passivation effect of the insulating layer. The components of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution will depend on the actual application scenario. The polishing additive may be determined depending on the application, and is not specifically limited here. The polishing additives may include sodium benzoate, antifoaming agents and surfactants. The volume ratio in the coating solution may be 0.5% or more and 5% or less.

[0096] Explained, the fabricated back contact cell comprises a first region and a first doped semiconductor. a silicon substrate further including a first passivation layer positioned between the silicon substrate and the body layer; and then, before forming the first doped semiconductor layer in the first region, a method for manufacturing a back-contact cell is The method involves first forming a first passivation layer in a first region by a deposition and etching process. The method further includes the step of:

[0097] Alternatively, as shown in Figure 8, after preparing a silicon substrate, a process such as chemical vapor deposition can be used. Therefore, the first passivation layer 18 may be formed on the entire non-light-receiving surface side. 11 to 13, a first mask layer 20 is formed, and then a first mask layer After selectively etching the first doped semiconductor layer 12 under the mask action of 20, the first passivation layer 13 is formed. In this case, the first passivation layer 18 is selectively etched. There is no need to additionally form a corresponding mask layer to form a back contact cell. The manufacturing process is simplified.

[0098] Next, the surfaces of both the spacing region and the second region are aligned relative to the surface of the first region within the silicon substrate. After the recess, as shown in FIG. 20, a second doped semiconductor layer 13 is formed in the second region 15. The surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, The surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the first region 14. The depth is less than 3000 nm.

[0099] In the actual manufacturing process, as shown in FIG. 18, the surfaces of the space region 16 and the second region 15 Both of these are recessed into the silicon substrate 11 relative to the surface of the first region 14, and then the first doped semiconductor depositing a second doped semiconductor layer 13 on the conductor layer 12, the spacing region 16 and the second region 15; and A second mask layer 21 is formed in a portion corresponding to the second region 15 of the second doped semiconductor layer 13. Next, as shown in FIG. 19, under the masking effect of the second mask layer 21, a second dose is applied. selectively removing portions of the semiconductor layer 13 corresponding to the first region 14 and the spacing region 16; This causes the surface of the spacing region 16 to be recessed into the silicon substrate 11 relative to the surface of the second region 15 .

[0100] Specifically, the material and thickness of the second doped semiconductor layer and the surface of the gap region after the operation The depth of the recess in the silicon substrate can be determined by referring to the previous paragraph, and a detailed description thereof will be omitted here. For the mask layer, the material may be any material that has a masking effect. In the actual manufacturing process, the second doped semiconductor layer and the second mask layer are formed according to the materials of the second doped semiconductor layer and the second mask layer. The process and specific steps for forming the doped semiconductor layer and the second mask layer may be determined.

[0101] For example, when the material of the second doped semiconductor layer includes silicon, the material of the first doped semiconductor layer includes silicon. depositing a second doped semiconductor layer on the body layer, the spacing region and the second region; and The step of forming the second mask layer in the portion corresponding to the second region includes the following steps: As shown in FIG. 15, the first doped semiconductor layer 12, the spacing region 16, and the second region A second intrinsic semiconductor layer 24 is deposited in the region 15. Next, as shown in FIG. doping the layer 24 to form a second intrinsic semiconductor layer 24 as the second doped semiconductor layer 13; , and a second doped silicate glass layer 25 formed on the entire second doped semiconductor layer 13. Next, as shown in FIG. 17, a second doped layer is formed by a laser etching process. The portions of the silicate glass layer 25 corresponding to the first region 14 and the spacing region 16 are heat-treated, The portion of the second doped silicate glass layer 25 corresponding to the second region 15 is treated as a second mask layer 21. Then, as shown in FIG. 18, the second doped silicate glass layer 25 is heat-treated. Remove the processed parts.

[0102] Specifically, the material of the second doped semiconductor layer contains silicon. It may mean that the material of the second doped semiconductor layer contains only silicon, or the material of the second doped semiconductor layer contains silicon. This means that it not only includes silicon, but also other semiconductor materials such as germanium silicon. Next, in the actual manufacturing process, a non-photosensitive layer may be formed by a process such as chemical vapor deposition. A second intrinsic semiconductor layer can be formed on the entire surface of the first semiconductor layer. The second intrinsic semiconductor layer can be doped by the doping process. Not only can a two-doped semiconductor layer be obtained, but also a layer can be formed on the second doped semiconductor layer. A second doped silicate glass layer can then be formed by laser etching. The doping process forms a second doped silicate glass layer in a portion corresponding to the first region and the spacing region. In this case, the laser beam in the second doped silicate glass layer can be heat-treated. The treated area becomes less dense and easier to remove. The portion of the glass layer corresponding to the second region is not laser processed, so it is highly dense and can be easily removed. This allows for a more uniform distribution of the doped silicate glass layer in different areas after heat treatment. The components have different etching selectivities and are used to pattern the second doped semiconductor layer. A second mask layer is obtained, and another mask material is additionally formed to obtain the second mask layer. and other mask deposition steps are not required, reducing the manufacturing cost of back contact cells. This is advantageous in reducing the number of layers and simplifying the manufacturing flow of back-contact batteries. For specific conditions of the etching process, please refer to the previous paragraph. Not limited to specific.

[0103] Of course, the material of the second doped semiconductor layer may contain silicon, or the second doped semiconductor layer may contain silicon. If the material does not contain silicon, it can be made non-receptive by processes such as chemical vapor deposition and doping. A second doped semiconductor layer may be formed on the light-side surface. and etching processes to mask other materials such as silicon nitride. A second mask layer having a thickness of 100 nm can be formed.

[0104] After forming the second mask layer, the mass of the second mask layer is removed by a process such as wet chemistry. Under the action of the quench, a portion of the second doped semiconductor layer located in the spacing region and the first doped semiconductor layer is selected. selectively removing and recessing the surface of the spacing region into the silicon substrate relative to the surface of the second region; This prevents damage to the silicon substrate caused by high-temperature lasers, and reduces the back contact voltage. Specifically, the second doped semiconductor layer is selectively etched. The process conditions depend on the etching process used, the material of the second doped semiconductor layer, and the The thickness may be determined based on the depth of the recess in the silicon substrate on the surface of the isolation region. Not limited to specific.

[0105] Illustratively, a second doped semiconductor is deposited under the masking effect of the second mask layer by a wet chemical process. A portion of the conductor layer corresponding to the spaced region is selectively removed, and the surface of the spaced region is formed into a second region. When recessing into a silicon substrate relative to the surface, the process temperature of the wet chemical process is 6 The temperature may be 0°C or higher and 80°C or lower, and the process time of the wet chemical process may be It may be 50 seconds or more and 300 seconds or less, and is used in wet chemical processes. The wet chemical etching solution is an alkaline wet chemical etching solution, and the alkaline The volume ratio of alkaline components (e.g., NaOH or KOH) in wet chemical etching solutions is For example, the process temperature of a wet chemical process may be 2% or more and 20% or less. The temperature may be 60°C, 70°C, 75°C, 78°C, or 80°C. The process time is 50s, 55s, 60s, 100s, 150s, 200s or 300s etc. The wet chemical etching solution used in the wet chemical process may be an alkaline wet If it is a chemical etching solution, the alkaline component in the alkaline wet chemical etching solution The volume ratio may be 2%, 3%, 6%, 9%, 12%, 15%, 20%, etc. In this case, the process temperature and process time of the wet chemical process are affects the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region. Based on this, if the process temperature of the wet chemical process is within the above range, The lower process temperature allows the surface of the spacing region to be in contact with the surface of the second region. This prevents the depth of the recess from becoming smaller. The surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region. It is also possible to prevent the depth of the gap from increasing. The depth of the recess into the silicon substrate relative to the surface of the silicon substrate becomes smaller or larger. The beneficial effects of preventing this can be seen in the previous paragraph. The beneficial effect of the volume ratio of the soluble component being within the above range is not observed when the process temperature is 60°C or higher. This is similar to the beneficial effect of the temperature being above 80°C and below, and therefore will not be explained here.

[0106] In addition, by adding abrasive additives to the wet chemical etching solution, the interval after the operation Increase the flatness of the area surface and passivate the surface passivation layer for the gap area Specifically, the components of the polishing additive and the wettability of the polishing additive can be further improved. The proportion in the formula chemical etching solution may be determined according to the actual application scenario, where The polishing additives are not specifically limited. For example, the polishing additives may include sodium benzoate, an antifoaming agent, and a surfactant. The volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or more. It may be above 5% and below.

[0107] It should be noted that the fabricated back contact cell may include a second region and a second doped semiconductor. When the semiconductor device further includes a second passivation layer positioned between the semiconductor layer and the second region, the spacing region and the second region After both surfaces of the first region are recessed into the silicon substrate relative to the surface of the first region, Before forming the second doped semiconductor layer, the method for manufacturing a back contact cell includes depositing and first forming a second passivation layer in the second region by an etching process; Further includes:

[0108] Alternatively, as shown in FIG. 15, the surfaces of the spacing region and the second region are both on the surface of the first region. forming a second doped semiconductor layer in the second region after recessing the silicon substrate; and forming a first doped semiconductor layer, a second region, and a spacing region by a process such as chemical vapor deposition. A second passivation layer 19 may be deposited. Then, as shown in FIGS. , a second mask layer 21 is formed, and a second doped semiconductor is deposited under the masking effect of the second mask layer 21. After selectively etching the body layer, the second passivation layer 19 is selectively etched. In this case, a corresponding mask layer is additionally applied to form the second passivation layer 19. This simplifies the manufacturing process of the back contact battery.

[0109] The back contact cell thus fabricated comprises a first doped semiconductor layer, a second doped semiconductor layer, and When the second region further includes a surface passivation layer covering the gap region, the surface of the gap region is After the surface is recessed into the silicon substrate, as shown in Figure 21, a process such as chemical vapor deposition is performed. The process covers the first doped semiconductor layer 12, the second doped semiconductor layer 13 and the spacing region 16. A surface passivation layer 17 can be formed. For the material and thickness, please refer to the previous paragraph.

[0110] The beneficial effects of the second aspect of the present invention and its various embodiments are similar to those of the first aspect and Reference may be had to the analysis of the beneficial effects of the various embodiments thereof, which are described herein. The details are omitted.

[0111] In addition, the present invention also provides a method for manufacturing a back contact battery provided by the present invention. One comparative example and one example are further provided to illustrate the manufacturing process and operational performance. Here, Table 1 shows the test results of the back contact batteries corresponding to Example 1 and Comparative Example 1. . Example 1

[0112] Step 1: Alkaline is applied to a single crystal silicon wafer using a 15% alkaline solution. A potash polishing process is performed to form a smooth and clean silicon surface.

[0113] Step 2: Deposit a tunnel oxide layer on the surface of a single-crystal silicon wafer, and then deposit an intrinsic polycrystalline silicon layer. The silicon layer is then deposited, where the tunnel oxide is 1.8 nm thick and the intrinsic The thickness of the polycrystalline silicon layer is 350 nm.

[0114] Step 3: The deposited intrinsic polysilicon layer is doped with boron to form an intrinsic polysilicon layer. The crystalline silicon layer is formed as a P-type doped polycrystalline silicon layer, and the P-type doped polycrystalline silicon A borosilicate glass layer is formed on the silicon layer, where the boron doping concentration is 8×10 19 / cm 3 is.

[0115] Step 4: A laser etching process heat-treats the borosilicate glass layer to create a specific The mask layer has a pattern as follows: Here, the laser may be a picosecond laser, and the processing The irradiation power may be 40 W and the spot diameter is 200 μm.

[0116] Step 5: Selectively doping a portion of the P-type doped polycrystalline silicon layer under the masking effect of the mask layer. Then, the surface of the single crystal silicon wafer is etched to form a groove structure. The main components of the etching solution used here are alkali and polishing additives. The concentration of alkali in the etching solution is 5%, the etching temperature is 82°C, and the proton The process time is 300 seconds, the volume ratio of the polishing additive is 2%, and the main components of the polishing additive are Contains sodium benzoate, antifoaming agents and surfactants.

[0117] Step 6: A tunnel oxide layer and an N-type doped layer are sequentially stacked at the bottom of the groove structure. Forming a polycrystalline silicon layer, and doping the P-type polycrystalline silicon layer on the monocrystalline silicon wafer. The portion located between the silicon nitride layer and the N-type doped polycrystalline silicon layer is formed by insulating the silicon nitride layer against the bottom surface of the groove of the groove structure. The thickness of the N-type doped polycrystalline silicon layer is 150 nm or more, and the N-type doped polycrystalline silicon layer is recessed into the silicon substrate. The thickness of the tunnel oxide layer is 0.5 nm or more and 3 nm or less. P-type doped polycrystalline silicon layer and N-type doped polycrystalline silicon layer of a single crystal silicon wafer The recess depth into the silicon substrate in the portion located between is less than 3000 nm.

[0118] Step 7: The monocrystalline silicon wafer, the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer are A surface passivation layer is formed covering the crystalline silicon layer. Comparative Example 1

[0119] The manufacturing method corresponding to Comparative Example 1 is the same as the manufacturing flow of Example 1 except for step 6. Here, the manufacturing method provided by Comparative Example 1 is a method of forming a groove structure by sequentially stacking layers on the groove bottom. After forming the tunnel oxide layer and the N-type doped polycrystalline silicon layer, a single crystal silicon wafer is formed. The portion of the wafer located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer The depth of the recess in the silicon substrate is made greater than 5 μm, and the P of the single crystal silicon wafer The surface of the portion located between the N-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer is It's a texture.

[0120] [Table 1]

[0121] From the data shown in Table 1, it can be seen that the back contact formed by the manufacturing method provided by Example 1 In the case of a silicon battery, the recess depth in the gap area into the silicon substrate is small, so the carrier travel distance is The distance can be reduced and back-contact cells have a greater surface passivation layer. When included in the surface passivation layer, the passivation effect of the surface passivation layer on the gap region is enhanced. This allows the back contact electrode obtained by the corresponding manufacturing method of Comparative Example 1 to be The operating efficiency, open circuit voltage, short circuit current and fill factor are higher than those of the embodiment of the present invention. The more back contact the battery provides, the higher its operating performance will be.

[0122] In the above description, the technical details of the structure of each layer, etching, etc. are not explained in detail. However, a person skilled in the art would be able to form layers, regions, etc. in desired shapes by various technical means. It should be understood that the same structure can be formed by a person skilled in the art. It is also possible to design methods that are not exactly the same as those described above. Although each embodiment has been described, it is understood that the measures in each embodiment cannot be advantageously used in combination. It does not mean that.

[0123] The above describes exemplary embodiments of the present disclosure. However, these embodiments are for illustrative purposes only. The scope of the present disclosure is limited to the scope of the appended patents. The scope of the present disclosure is limited only by the claims and their equivalents. Various substitutions and modifications may be made by the skilled artisan, and all such substitutions and modifications are within the scope of the present disclosure. It shall be within the range of. [Explanation of symbols]

[0124] 11 Silicon substrate 12 First doped semiconductor layer 13 Second doped semiconductor layer 14 First area 15 Second area 16 Interval area 17 Surface passivation layer 18 First passivation layer 19 Second passivation layer 20 First mask layer 21 Second mask layer 22 first intrinsic semiconductor layer 23 First doped silicate glass layer 24 Second intrinsic semiconductor layer 25 Second doped silicate glass layer

Claims

1. The semiconductor device includes a silicon substrate, and first and second doped semiconductor layers alternately distributed at intervals on a non-light-receiving surface side of the silicon substrate, the first doped semiconductor layer and the second doped semiconductor layer are of opposite conductivity types, a region on the non-light-receiving surface of the silicon substrate corresponding to the first doped semiconductor layer is a first region, a region on the non-light-receiving surface of the silicon substrate corresponding to the second doped semiconductor layer is a second region, a region located between the first region and a second region adjacent to the first region is a spacing region, a surface of the second region is recessed into the silicon substrate relative to a surface of the first region, a surface of the spacing region is recessed into the silicon substrate relative to a surface of the second region, and side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region are both approximately wavy, A back-contact battery, characterized in that the corresponding fluctuation range of the side surface of the second doped semiconductor layer near the spacing region is larger than the corresponding fluctuation range of the side surface of the first doped semiconductor layer near the spacing region, and / or the corresponding fluctuation frequency of the side surface of the second doped semiconductor layer near the spacing region is smaller than the corresponding fluctuation frequency of the side surface of the first doped semiconductor layer near the spacing region.

2. the surface of the spacing region is recessed into the silicon substrate relative to the surface of the first region to a depth of less than 3000 nm; and / or the surface of the spacing region has a roughness of 30 μm or less per 10,000 square micrometers; and / or The back-contact battery of claim 1 , wherein the length of the spacing region is 20 μm or more and 110 μm or less in the direction of arrangement of the first and second regions.

3. the surface of the second region is planar; and / or the surface of the second region is recessed into the silicon substrate to a depth of 100 nm or more and 1000 nm or less; and / or 2. The back contact battery of claim 1, wherein the height difference between the surface of the second region and the surface of the spacing region is 300 nm or more and less than 2000 nm.

4. 2. The back contact battery of claim 1, wherein at least a portion of the sidewall of the spacing region is oblique to a horizontal plane so that the cross-sectional area of ​​at least a portion of the spacing region gradually increases in a direction from the light-receiving surface to the non-light-receiving surface.

5. and / or a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacing region. and / or a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer.

5. The back contact battery of claim 1, further comprising a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

6. When the back contact cell includes the first passivation layer and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer; and / or 6. The back contact battery of claim 5, wherein when the back contact battery includes the second passivation layer and the second passivation layer is a tunnel passivation layer, the second doped semiconductor layer is a doped polycrystalline silicon layer.

7. preparing a silicon substrate, the non-light receiving surface of the silicon substrate having first and second regions alternately distributed at intervals, and an interval region located between the first region and the second region adjacent to the first region; forming a first doped semiconductor layer in the first region, with surfaces of the spacing region and the second region both recessed into the silicon substrate relative to a surface of the first region; forming a second doped semiconductor layer in the second region and recessing a surface of the spacing region into the silicon substrate relative to a surface of the second region, wherein both sides of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region are substantially wavy; A method for manufacturing a back-contact battery, characterized in that the corresponding fluctuation range of the side surface of the second doped semiconductor layer near the spacing region is larger than the corresponding fluctuation range of the side surface of the first doped semiconductor layer near the spacing region, and / or the corresponding fluctuation frequency of the side surface of the second doped semiconductor layer near the spacing region is smaller than the corresponding fluctuation frequency of the side surface of the first doped semiconductor layer near the spacing region.

8. After the step of providing a silicon substrate and before the step of forming a second doped semiconductor layer in the second region, the method for manufacturing a back-contact cell includes: forming a first doped semiconductor layer provided over the entire surface of the silicon substrate, and a first mask layer located in a portion of the first doped semiconductor layer corresponding to the first region; then selectively removing, under the masking effect of the first mask layer, portions of the first doped semiconductor layer located in the spacing region and the second region, and recessing surfaces of both the spacing region and the second region into the silicon substrate relative to the surface of the first region; After the step of recessing both the surfaces of the spacing region and the second region into the silicon substrate relative to the surface of the first region, the method of manufacturing the back contact battery further comprises: depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region, and forming a second mask layer on a portion of the second doped semiconductor layer corresponding to the second region; Then, selectively removing portions of the second doped semiconductor layer corresponding to the first region and the spacing region under the masking effect of the second mask layer, and recessing a surface of the spacing region into the silicon substrate relative to a surface of the second region; 8. The method for manufacturing a back contact battery of claim 7, comprising:

9. selectively removing portions of the first doped semiconductor layer located in the spacing region and the second region under the masking effect of the first mask layer by a wet chemical process, and recessing surfaces of both the spacing region and the second region into the silicon substrate relative to the surface of the first region; 10. The method for manufacturing a back contact battery according to claim 8, wherein the wet chemical process has a process temperature of 60° C. or higher and 80° C. or lower; and / or the wet chemical process has a process time of 40 seconds or higher and 200 seconds or lower; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower; and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

10. selectively removing portions of the second doped semiconductor layer corresponding to the first region and the spacing region under the masking effect of the second mask layer by a wet chemical process, and recessing a surface of the spacing region into the silicon substrate relative to a surface of the second region; 10. The method for manufacturing a back contact battery according to claim 8, wherein the wet chemical process has a process temperature of 60° C. or higher and 80° C. or lower; and / or the wet chemical process has a process time of 50 seconds or higher and 300 seconds or lower; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower; and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

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