Quantum computation support program, quantum computation support method, and information processing apparatus

Abstract

To improve the correctness of the execution result of a quantum circuit whose output state cannot be returned to an initial state.SOLUTION: An information processing apparatus 10 divides a quantum circuit 2 into a plurality of partial circuits 3a, 3b. The information processing apparatus 10 generates subcircuits 4, 5-1, 5-2, ... for each of the plurality of partial circuits 3a, 3b by adding an inverse circuit after the partial circuit, which causes a quantum computer 1 to execute an operation that is the inverse of the operation of the partial circuit. The information processing apparatus 10 sets the candidate values for each of a plurality of parameter values that are set to cause the quantum computer 1 to execute the quantum circuit 2, and causes the quantum computer 1 to execute each of the subcircuits 4, 5-1, 5-2, ... multiple times. The information processing apparatus 10 determines a value to be set for the parameter when the quantum circuit 2 is executed from among a plurality of candidate values based on the result of comparing the input state and the output state when the subcircuits 4, 5-1, 5-2, ... are executed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a quantum computing assistance program, a quantum computing assistance method, and an information processing device. [Background technology]

[0002] Quantum computers can execute calculations in parallel by utilizing quantum mechanical effects. Calculations that utilize quantum mechanical effects are called quantum computing. Quantum computers are expected to achieve exponential improvements in computational speed compared to classical computers (also known as von Neumann computers) by performing quantum computations.

[0003] Quantum computers perform quantum computations using qubits. A qubit is a unit of information that can be in a superposition of |0> and |1> states. When a qubit is measured, its state changes probabilistically to |0> or |1>. By measuring the state of a qubit multiple times, the state of the qubit before the measurement can be estimated based on the probability of occurrence of |0> and |1>.

[0004] A quantum computing system uses quantum bits to change their state and performs calculations, then obtains the calculation results by statistically processing the measurement results of each calculation. The quantum bits can be changed to a desired state by applying a specific quantum gate.

[0005] The order of quantum gates that act on each qubit to allow a quantum computer to perform a quantum computation can be modeled as a quantum circuit. The quantum computer performs quantum gate operations on the qubits according to the quantum circuit and measures the final qubit state. The measurement results are statistically processed by a classical computer.

[0006] If the state of the quantum bits changes accurately in accordance with the quantum gate operation, the correct calculation result can be obtained. However, quantum bits are susceptible to noise, which causes errors. This makes error correction important, but it is expected to take more than 10 years until a quantum computer capable of error correction is realized. Therefore, the most realistic option with current technology is to make effective use of NISQ (Noisy Intermediate Scale Quantum) computers, which do not have error correction capabilities.

[0007] In NISQ computers, there are many situations where we want to know how accurate the execution results of quantum circuits are. For example, the average fidelity of quantum gate operations for each qubit in a quantum computer is measured. If the average fidelity of a quantum circuit in a certain execution environment is known, it will be possible to optimize the execution environment of the quantum circuit to improve that fidelity. For example, it will be possible to allocate physical qubits in a way that increases the overall fidelity. It will also be possible to schedule pulses to maximize fidelity.

[0008] One way to determine whether the results of running a quantum circuit on an actual quantum computer are correct is to compare them with the results of a quantum simulation. For example, the quantum circuit is run on a simulator using a classical computer, and the results of the calculation by the quantum computer are compared with the results of the simulator. The accuracy of the calculation by the quantum computer can be estimated by whether the results of the comparison match. However, simulations using classical computers can only be performed on small-scale quantum circuits, and there are issues with scalability.

[0009] For a reversible quantum circuit, it is possible to add an inverse circuit that performs the reverse gate operation after the quantum circuit. In this case, it is expected that the state of each qubit after executing the original quantum circuit and the inverse circuit will return to the input state. By repeatedly performing such quantum calculations and calculating the probability of returning to the input state, the correctness of the execution results of the quantum circuit can be evaluated.

[0010] Techniques useful for utilizing NISQ computers have been proposed, such as methods for benchmarking quantum gates and estimating gate dependence of noise, techniques for significantly reducing the error achieved by effective circuit mapping by exploiting the reversibility of quantum algorithms, and techniques for identifying optimal execution schedules for single-qubit gates in quantum circuits. [Prior art documents] [Non-patent literature]

[0011] [Non-Patent Document 1] Easwar Magesan, Jay M. Gambetta, and Joseph Emerson, "Characterizing quantum gates via randomized benchmarking". Physical Review A 85, 11 April 2012 [Non-patent document 2] Tirthak Patel and Devesh Tiwari, "Qraft: reverse your Quantum circuit and know the correct program output", ASPLOS '21: Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages ​​and Operating Systems, Association for Computing Machinery, New York, NY, USA, 17 April 2021, Pages 443-455 [Non-patent document 3] Kaitlin N. Smith, Gokul Subramanian Ravi, Prakash Murali, Jonathan M. Baker, Nathan Earnest, Ali Javadi-Cabhari, and Frederic T. Chong, "TimeStitch: Exploiting Slack to Mitigate Decoherence in Quantum Circuits", ACM Transactions on Quantum Computing, Volume 4, Issue 1, Article No. 8, 21 October 2022, pp 1-27 Summary of the Invention [Problem to be solved by the invention]

[0012] If a quantum circuit allows a gate operation that returns the output state after execution to its initial state, the correctness of the execution results of that quantum circuit can be evaluated. However, there are quantum circuits for which a gate operation to return to the initial state is not possible. For example, irreversible quantum circuits cannot perform the reverse gate operation. Furthermore, for quantum circuits with a large depth, applying the reverse quantum circuit may exceed the limit of the depth that can be executed by a quantum computer. If the correctness of the calculation results of a quantum circuit cannot be evaluated, it is also impossible to optimize the parameters set when the quantum circuit is executed, making it difficult to improve the correctness of the execution results.

[0013] In one aspect, the present invention aims to improve the correctness of the execution result of a quantum circuit that cannot return the output state to an initial state. [Means for solving the problem]

[0014] In one proposal, a quantum computing assistance program is provided that causes a computer to perform the following processes. The computer divides a quantum circuit to be executed by a quantum computer into multiple subcircuits. For each of the multiple subcircuits, the computer generates a subcircuit by adding, after the partial circuit, an inverse circuit that causes the quantum computer to execute an operation that is the inverse of the operation of the partial circuit. The computer sets multiple candidate values ​​for parameters that are set to cause the quantum computer to execute the quantum circuit, and causes the quantum computer to execute the subcircuits generated from each of the multiple subcircuits multiple times. The computer then determines a value to set for the parameter when executing the quantum circuit from among the multiple candidate values ​​based on a comparison result between the input state and the output state when the subcircuit is executed. [Effects of the Invention]

[0015] According to one aspect, the correctness of the execution result of a quantum circuit that cannot return the output state to the initial state is improved. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram illustrating an example of a quantum computing assistance method according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of a quantum computing system. [Figure 3] FIG. 1 is a diagram illustrating an example of hardware of a device that constitutes a quantum computing system. [Figure 4] FIG. 1 is a diagram illustrating an example of a quantum circuit. [Figure 5] FIG. 1 illustrates an example of entangled quantum bits. [Figure 6] FIG. 1 illustrates an example of a quantum circuit with intermediate measurements. [Figure 7] FIG. 10 is a diagram illustrating an example of a conversion process of a native gate. [Figure 8] FIG. 10 is a diagram illustrating an example of quantum bit allocation according to actual machine constraints. [Figure 9] FIG. 10 is a diagram illustrating an example of a pulse schedule. [Figure 10]FIG. 1 is a block diagram illustrating an example of the functionality of a classical computer for quantum computing. [Figure 11] FIG. 1 is a diagram illustrating an example of a quantum circuit to be executed. [Figure 12] FIG. 10 is a diagram illustrating an example of a division result of a quantum circuit. [Figure 13] FIG. 10 is a diagram illustrating an example of a sub-circuit optimization process. [Figure 14] FIG. 10 is a diagram showing a first example of a sub-circuit to which an inverse circuit is added. [Figure 15] FIG. 10 is a diagram showing a second example of a sub-circuit to which an inverse circuit is added. [Figure 16] FIG. 10 is a diagram illustrating an example of an optimized parameter group. [Figure 17] 10 is a flowchart illustrating an example of a procedure for parameter optimization processing. [Figure 18] 10 is a flowchart illustrating an example of a procedure for a sub-circuit optimization process. [Figure 19] 13 is a flowchart illustrating an example of a procedure for a sub-circuit optimization process according to the third embodiment. [Figure 20] 10 is a flowchart illustrating an example of a procedure for random circuit selection processing. [Figure 21] FIG. 10 illustrates an example of real-world constraints for implementing a quantum circuit with intermediate measurements. [Figure 22] FIG. 10 is a diagram illustrating an example of a method for dividing a quantum circuit including intermediate measurements. [Figure 23] FIG. 10 is a diagram showing an example of an allocated and routed quantum circuit. [Figure 24] 10 is a flowchart illustrating an example of the procedure for a parameter optimization process for optimizing the initial allocation and routing of physical quantum bits. [Figure 25] 10 is a flowchart illustrating an example of a procedure for a sub-circuit execution process. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present embodiment will be described below with reference to the drawings. Note that each embodiment can be implemented in combination with a plurality of other embodiments within a range that does not contradict each other. [First embodiment] The first embodiment is a quantum computing assistance method for improving the correctness of the execution result of a quantum circuit that cannot return the output state to the initial state.

[0018] Fig. 1 is a diagram illustrating an example of a quantum-assisted computing method according to a first embodiment. Fig. 1 illustrates an information processing device 10 that implements the quantum-assisted computing method. The information processing device 10 can implement the quantum-assisted computing method by, for example, executing a quantum-assisted computing program.

[0019] The information processing device 10 includes a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or a storage device included in the information processing device 10. The processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing device 10.

[0020] The storage unit 11 stores the quantum circuit 2 to be executed by the quantum computer 1. The quantum circuit 2 is a quantum circuit whose output state cannot be returned to its initial state even if a reverse gate operation is performed. For example, the quantum circuit 2 has mid-circuit measurements made at locations other than the measurement of the output state. A quantum circuit 2 with mid-circuit measurements is irreversible, and cannot be returned to its initial state even if an operation reverse to that of the operation of the quantum circuit 2 is performed.

[0021] When the quantum computer 1 executes the quantum circuit 2, multiple parameter values ​​are set. The parameter values ​​indicate, for example, the execution timing of a quantum gate that has a predetermined range of degrees of freedom in the execution timing. The parameter values ​​also indicate an allocation pattern of physical quantum bits possessed by the quantum computer 1 to quantum bits included in the quantum circuit 2.

[0022] If a quantum circuit can be returned to its initial state by an inverse circuit, it is expected that the state of the quantum bit will return to its initial state if the quantum computer 1 executes the inverse circuit after the quantum circuit. Therefore, the correctness of the execution result of the quantum circuit can be evaluated based on whether the initial state is returned by quantum computation by the quantum computer 1. On the other hand, if the initial state cannot be returned, such as in the case of quantum circuit 2, which has intermediate measurements, it is not easy to evaluate the correctness of the execution result of quantum circuit 2. Therefore, the processing unit 12 evaluates the correctness of the execution result of quantum circuit 2 using the following method and optimizes the parameters to be set when quantum circuit 2 is executed.

[0023] The processing unit 12 divides the quantum circuit 2 to be executed by the quantum computer 1 into multiple sub-circuits 3a and 3b. For example, the processing unit 12 divides the quantum circuit 2 at intermediate measurement positions where measurements other than the output state are taken. By dividing the quantum circuit 2 at the intermediate measurement positions, each of the multiple sub-circuits 3a and 3b becomes a reversible circuit.

[0024] The processing unit 12 generates subcircuits 4, 5-1, 5-2, ... for each of the plurality of partial circuits 3a, 3b, by adding an inverse circuit after the partial circuit, which causes the quantum computer 1 to execute an operation that is the inverse of the operation of the partial circuit. For example, for the partial circuit 3a, the processing unit 12 adds an inverse circuit after the partial circuit 4a, which causes the quantum computer 1 to execute the same operation "c1" as the partial circuit 3a, which causes the quantum computer 1 to execute an operation "c1" † An inverse circuit 4b is added to cause the quantum computer 1 to execute "

[0025] The inverse circuit 5b generates multiple subcircuits 5-1, 5-2, ... using different random circuits for the partial circuits 3b that are second or later in the execution order within the quantum circuit 2. In this way, a subcircuit group 5 including multiple subcircuits 5-1, 5-2, ... is generated based on the partial circuits 3b.

[0026] For example, the processing unit 12 adds a random circuit 5c that generates a random initial state of a quantum bit before the partial circuit 5a that causes the quantum computer 1 to execute the same operation "c2" as the partial circuit 3b. Furthermore, the processing unit 12 adds an inverse circuit 5b after the partial circuit 5a. The inverse circuit 5b includes a first inverse circuit that is added after the partial circuit 5a and a second inverse circuit that is added after the first inverse circuit. The first inverse circuit performs an operation "c2" that is the inverse of the operation "c2" of the partial circuit 3b. † The second inverse circuit is a quantum circuit that causes the quantum computer 1 to execute the operation "r 21 The inverse operation of "r 21 † " is a quantum circuit executed by quantum computer 1.

[0027] The processing unit 12 sets the candidate value as a parameter for each of a plurality of candidate values ​​to be set when the quantum computer 1 executes the quantum circuit 2, and causes the quantum computer 1 to execute the sub-circuits 4, 5-1, 5-2, ... a plurality of times. As a result, the quantum computer 1 obtains, for each candidate value, the output state of each of the sub-circuits 4, 5-1, 5-2, ... when that candidate value is set as a parameter.

[0028] Based on the comparison result between the input state and the output state when the sub-circuits 4, 5-1, 5-2, ... are executed, the processing unit 12 determines, from among a plurality of candidate values, a value to be set for the parameter when the quantum circuit 2 is executed. For example, the processing unit 12 determines, for each of a plurality of candidate values, a value to be set for the parameter when the quantum circuit 2 is executed, based on the probability that the input state and the output state when the plurality of sub-circuits 4, 5-1, 5-2, ... match.

[0029] For example, the input state of the subcircuits 4, 5-1, 5-2, ... is assumed to be the state of all quantum bits |0>. In this case, if no error occurs in the quantum calculation of each of the subcircuits 4, 5-1, 5-2, ..., the output state will be |0···0>. Therefore, the processing unit 12 determines, for example, from among the candidate values ​​of the parameter, the candidate value that has the highest probability of the output state being |0···0> (matching the input state), as the value to be set for the parameter when the quantum circuit 2 is executed.

[0030] In this way, each of the partial circuits 3a and 3b obtained by dividing the irreversible quantum circuit 2 can be returned to its initial state by the inverse circuit. Therefore, the correctness of the execution result of the quantum circuit 2 for each candidate value of the parameter can be evaluated using the inverse circuit and the subcircuits 4, 5-1, 5-2, ... added to the partial circuits 3a and 3b. If the correctness can be evaluated, the optimal parameter value can be determined. If the determined value is set for the parameter and the quantum circuit 2 is executed on the quantum computer 1, the correctness of the execution result will be improved.

[0031] For example, by optimizing the value of a parameter that indicates the timing of quantum gate operation, quantum gate operation is performed at the optimal timing, reducing errors and improving the accuracy of the execution results (e.g., average fidelity).

[0032] Note that there are multiple parameters that are set when the quantum circuit 2 is executed. In this case, parameters that affect the execution results of either the partial circuits 3a or 3b can be optimized using the subcircuits of that partial circuit. Therefore, the processing unit 12 determines the values ​​to be set for the parameters used in the execution of either the partial circuits 3a or 3b based on the results of comparing the input state and output state when the subcircuit generated from that partial circuit is executed. For example, the processing unit 12 determines the values ​​to be set for the parameters used in the execution of the partial circuit 3a based on the results of comparing the input state and output state when the subcircuit 4 is executed. Then, the processing unit 12 determines the values ​​to be set for the parameters used in the execution of the partial circuit 3b based on the results of comparing the input state and output state when the subcircuits 5-1 and 5-2 are executed. This allows for efficient optimization of the parameter values.

[0033] Furthermore, for partial circuits 3b that are second or later in the execution order within the quantum circuit 2, the input state when executed within the quantum circuit 2 depends on the execution result of the partial circuit 3a that is executed first. Therefore, the processing unit 12 suppresses the use of random circuits that generate a distribution that deviates from the distribution of output states shown in the execution result of the partial circuit 3a that is executed first when generating the subcircuits 5-1, 5-2, ... of the partial circuit 3b. Note that the distribution of output states is the occurrence probability of each of the possible states "|0···0>, |0···1>, ..., |1···1>" as the output state.

[0034] For example, the processing unit 12 instructs the quantum computer 1 to execute the quantum circuit 2 multiple times up to the third partial circuit, which is the i-th (i is a natural number) partial circuit in the execution order within the quantum circuit 2. The processing unit 12 then obtains the distribution of output states resulting from the multiple executions. When generating the multiple sub-circuits 5-1, 5-2, ... of the fourth partial circuit, which is the i+1th partial circuit in the execution order within the quantum circuit 2, the processing unit 12 performs the following processing.

[0035] The processing unit 12 compares the distribution of occurrence probabilities of the initial states obtained by the generated random circuit with the distribution of occurrence probabilities of the acquired output states, and determines whether or not to adopt the generated random circuit based on the comparison result. For example, the processing unit 12 determines to adopt the generated random circuit if the similarity between the distribution of occurrence probabilities of the initial states and the distribution of occurrence probabilities of the output states is equal to or greater than a predetermined value. If the processing unit 12 determines to adopt the generated random circuit, it generates a sub-circuit by adding the generated random circuit. If the processing unit 12 determines not to adopt the generated random circuit, it discards the generated random circuit.

[0036] As a result, for example, for the subcircuit group 5 of the partial circuit 3b, the subcircuits 5-1, 5-2, ... are generated using a random circuit that generates input states with a distribution close to the occurrence probability distribution of the output states of the partial circuit 3a. As a result, the state of each quantum bit when executing the subcircuits 5-1, 5-2, ... approximates the state when executing the partial circuit 3b during the execution of the quantum circuit 2. As a result, the parameter values ​​can be optimized in a state close to that when the quantum circuit 2 is executed, improving the accuracy of the optimization.

[0037] Furthermore, some parameters, such as the allocation of physical quantum bits, affect the entire quantum circuit 2. For such parameters, the processing unit 12 can evaluate candidate values ​​for the parameters by performing statistical processing that integrates the execution results of each of the subcircuits 5-1, 5-2, ...

[0038] For example, the processing unit 12 generates a plurality of combination patterns (e.g., physical quantum bit allocation patterns) that combine candidate values ​​for each of a plurality of parameters that are set when the quantum circuit 2 is executed. For each of the plurality of combination patterns, the processing unit 12 causes the quantum computer 1 to execute the sub-circuits 4, 5-1, 5-2, ... of each of the plurality of partial circuits 3 a, 3 b a plurality of times using a plurality of parameters to which candidate values ​​indicated in the combination pattern are set. Then, the processing unit 12 determines a combination pattern that indicates values ​​to be set for the parameters when the quantum circuit 2 is executed from among the plurality of combination patterns, based on a comparison result between the input state and the output state when the plurality of sub-circuits for each of the plurality of combination patterns are executed.

[0039] In this way, the values ​​of parameters that affect the entire quantum circuit 2 can also be optimized using the subcircuits 4, 5-1, 5-2, ... for each divided partial circuit. As a result, the quantum circuit 2 can be executed on the quantum computer 1 using the optimized parameter values, improving the accuracy of the execution results of the quantum circuit 2.

[0040] Second Embodiment This is a quantum computing system that optimizes parameters for a quantum circuit with intermediate measurements, with the statistical value of an all-zero sequence as the objective function. Parameter optimization with the statistical value of an all-zero sequence as the objective function involves optimizing parameters by defining the parameter value that maximizes the probability that the output state of all quantum bits will be |0> as the optimal value.

[0041] FIG. 2 is a diagram illustrating an example of the configuration of a quantum computing system. The quantum computing system 300 is a computer system using quantum devices. The quantum computing system 300 includes a classical computer 100 and a quantum computer 200. Terminal devices 401, 402, and so on are connected to the classical computer 100 via a network 20. The terminal devices 401, 402, and so on are computers used by users who request quantum computing by the quantum computing system 300. The classical computer 100 receives computation requests including quantum circuits from the terminal devices 401, 402, and so on. A quantum circuit indicates the order of operations on quantum bits by arranging elements such as quantum gates. A quantum bit is a bit that can represent a superposition of a "0" state and a "1" state.

[0042] The classical computer 100 instructs the quantum computer 200 to execute quantum computation in accordance with the quantum circuits received from the terminal devices 401, 402, . . . The classical computer 100 also obtains the measurement results of each quantum bit from the quantum computer 200.

[0043] The quantum computer 200 has a plurality of quantum bits and devices for manipulating each of the plurality of quantum bits. The plurality of quantum bits of the quantum computer 200 can be realized by, for example, a superconducting system, an ion trap system, a diamond spin system, or the like.

[0044] FIG. 3 is a diagram showing an example of hardware of a device that constitutes a quantum computing system. A classical computer 100 is entirely controlled by a processor 101. A memory 102 and multiple peripheral devices are connected to the processor 101 via a bus 109. The processor 101 may be a multiprocessor. The processor 101 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or a DSP (Digital Signal Processor). At least some of the functions realized by the processor 101 executing a program may be realized by an electronic circuit such as an ASIC (Application Specific Integrated Circuit) or a PLD (Programmable Logic Device).

[0045] The memory 102 is used as a main storage device of the classical computer 100. The memory 102 temporarily stores at least a portion of the OS (Operating System) program and application programs to be executed by the processor 101. The memory 102 also stores various data used in processing by the processor 101. As the memory 102, for example, a volatile semiconductor storage device such as a RAM (Random Access Memory) is used.

[0046] The peripheral devices connected to the bus 109 include a storage device 103, a GPU (Graphics Processing Unit) 104, an input interface 105, an optical drive device 106, a device connection interface 107, and network interfaces 108a and 108b.

[0047] The storage device 103 writes and reads data electrically or magnetically to and from a built-in recording medium. The storage device 103 is used as an auxiliary storage device for the classical computer 100. The storage device 103 stores the OS program, application programs, and various data. Note that the storage device 103 may be, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0048] The GPU 104 is an arithmetic unit that performs image processing. The GPU 104 is an example of a graphics controller. The GPU 104 is connected to a monitor 21. The GPU 104 displays an image on the screen of the monitor 21 in accordance with an instruction from the processor 101. The monitor 21 may be a display device using organic EL (Electro Luminescence) or a liquid crystal display device.

[0049] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals sent from the keyboard 22 and the mouse 23 to the processor 101. The mouse 23 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

[0050] The optical drive device 106 uses a laser beam or the like to read data recorded on an optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded so that it can be read by reflected light. The optical disc 24 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (Rewritable), and the like.

[0051] The device connection interface 107 is a communication interface for connecting peripheral devices to the classical computer 100. For example, a memory device 25 or a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a function for communicating with the device connection interface 107. The memory reader / writer 26 is a device for writing data to the memory card 27 or reading data from the memory card 27. The memory card 27 is a card-type recording medium.

[0052] The network interface 108a is connected to the network 20. The network interface 108a transmits and receives data to and from other computers or communication devices via the network 20. The network interface 108a is a wired communication interface connected by a cable to a wired communication device such as a switch or a router. The network interface 108a may also be a wireless communication interface connected by radio waves to a wireless communication device such as a base station or an access point.

[0053] The network interface 108b is an interface for connecting to the quantum computer 200. The processor 101 transmits a quantum circuit to the quantum computer 200 via the network interface 108b and causes the quantum computer 200 to execute a quantum computation. The processor 101 also obtains the result of the quantum computation via the network interface 108b.

[0054] The classical computer 100 can realize the processing functions of the second embodiment with the hardware described above. The device shown in the first embodiment can also be realized with hardware similar to the classical computer 100 shown in FIG.

[0055] The classical computer 100 realizes the processing functions of the second embodiment by executing a program recorded on, for example, a computer-readable recording medium. The program describing the processing to be executed by the classical computer 100 can be recorded on various recording media. For example, the program to be executed by the classical computer 100 can be stored in a storage device 103. The processor 101 loads at least a portion of the program in the storage device 103 into the memory 102 and executes the program. The program to be executed by the classical computer 100 can also be recorded on a portable recording medium such as an optical disk 24, a memory device 25, or a memory card 27. The program stored on the portable recording medium becomes executable after being installed on the storage device 103, for example, under the control of the processor 101. The processor 101 can also read and execute the program directly from the portable recording medium.

[0056] Quantum computer 200 includes a control device 210 and a quantum device 220. Control device 210 performs gate operations on quantum bits in the quantum device according to a quantum circuit. Quantum device 220 includes multiple quantum bits. Quantum device 220 may be, for example, one or multiple quantum processing units (QPUs).

[0057] Next, we will explain quantum circuits that can be executed by the quantum computer 200. In a quantum circuit, operations to be performed on quantum bits are represented by an array of quantum gates. 4 is a diagram showing an example of a quantum circuit. Unlike classical bits, which can only be in the state "0" or "1," quantum bits 30 can be in a superposition state |ψ> of "0" and "1." The superposition state |ψ> is expressed by the following equation:

[0058]

number

[0059] α is a probability amplitude that indicates the probability that the state of the quantum bit 30 is |0>. |α| 2 is the probability of the state |0>. β is the probability amplitude that indicates the probability that the state of the quantum bit 30 is |1>. |β| 2 is the probability of state |1>.

[0060] Quantum computation proceeds by changing the state of the quantum bit 30. When the state of the quantum bit 30 is measured, a value of |0> or |1> is probabilistically obtained depending on the state. Therefore, the quantum computing system 300 obtains the quantum computation result by statistically processing the measurement results obtained by repeatedly performing quantum computation.

[0061] The procedure of gate operations and measurements in quantum computing can be modeled using a quantum circuit 31. The quantum circuit 31 represents quantum computing using two quantum bits q0 and q1. The states of the two quantum bits can be expressed as a column vector. For example, assume that the initial states of the two quantum bits are both |0>. In that case, the state of the quantum bits is expressed by equation (2).

[0062]

number

[0063] The first element of equation (2) is the probability amplitude that the states of the two quantum bits q0 and q1 are both |0>. The second element is the probability amplitude that the state of the first quantum bit q0 is |0> and the state of the second quantum bit q1 is |1>. The third element is the probability amplitude that the state of the first quantum bit q0 is |1> and the state of the second quantum bit q1 is |0>. The fourth element is the probability amplitude that the states of the two quantum bits q0 and q1 are both |1>.

[0064] First, a Hadamard gate 31a is placed on the first quantum bit q0 in the quantum circuit 31. When the gate operation of this Hadamard gate 31a is performed, the states of the two quantum bits q0 and q1 change as shown in equation (3).

[0065]

number

[0066] Next, a CNOT gate 31b is placed in the quantum circuit 31, with the first quantum bit q0 as the control quantum bit and the second quantum bit q1 as the target quantum bit. When this CNOT gate 31b is operated, the states of the two quantum bits q0 and q1 change as shown in equation (4).

[0067]

number

[0068] In the quantum circuit 31, a T gate 31c is placed at the first quantum bit q0, and a Hadamard gate 31d is placed at the second quantum bit q1. When these gates are operated, the states of the two quantum bits q0 and q1 change as shown in equation (5).

[0069]

number

[0070] Finally, the quantum circuit 31 shows operations 31e and 31f for measuring the states of the two quantum bits q0 and q1. The measurement results of the states of the quantum bits q0 and q1 are probabilistically either |0> or |1>. The measurement results are stored as "0" or "1" in the classical bits c0 and c1. The quantum computer 200 repeats quantum calculations and measurements based on the quantum circuit 31 many times to obtain |α| 2 and |β| 2 Estimate the value of .

[0071] Gate operations and measurements are performed on the quantum bits q0 and q1 according to this quantum circuit 31. Here, there is a correlation between the two quantum bits q0 and q1 in the entangled state.

[0072] 5 is a diagram showing an example of entangled quantum bits. In quantum circuit 32, a Hadamard gate 32a is placed on the first quantum bit. A CNOT gate 32b is placed next, with the first quantum bit as the control quantum bit and the second quantum bit as the target quantum bit. Also shown are measurements 32c and 32d of the states of the two quantum bits. Measurement 32d is assumed to be performed after measurement 32c.

[0073] The input state to this quantum circuit 32 is |00> (both quantum bits are |0>). At this time, the quantum computation executed by the quantum circuit 32 is expressed by the following equation (6).

[0074]

number

[0075] In quantum computer 200, gate operations are performed according to quantum circuit 32. Then, measurement 32c observes that the first quantum bit is either |0> or |1>. When the first quantum bit is |0>, the second quantum bit changes to |0> before measurement 32d. Also, when the first quantum bit is |1>, the second quantum bit changes to |1> before measurement 32d. In this way, when the state of one quantum bit is determined, the state of the other quantum bit is also determined. The state of two quantum bits that have such a correlation is an entangled state.

[0076] Some quantum circuits also have intermediate measurements. In quantum circuits with intermediate measurements, measurements are taken during the execution of the circuit, and subsequent circuits are executed after the measurement. The results of the intermediate measurements may be used in subsequent processing. For example, quantum computation may be reset depending on the state of a specific quantum bit measured in the intermediate measurement. Also, the quantum gate to be executed subsequently may be switched depending on the result of the intermediate measurement.

[0077] A quantum circuit without intermediate measurements is reversible, and it is possible to generate an inverse circuit that performs the reverse gate operations of the quantum circuit. Such a quantum circuit can be said to have reversibility. On the other hand, a quantum circuit with intermediate measurements is not reversible (it is irreversible).

[0078] FIG. 6 is a diagram showing an example of a quantum circuit with intermediate measurements. In addition to the measurement of the output state, measurements at two locations are shown in the quantum circuit 33. In this way, in the quantum circuit 33 with intermediate measurements, when an intermediate measurement is performed on one of two entangled quantum bits, for example, the state of that quantum bit is determined to be |0> or |1>, and at the same time, the state of the other quantum bit is also determined. In such a case, even if an inverse circuit that executes the multiple gate operations of the quantum circuit 33 in the reverse order is executed after the quantum circuit 33 (before the final measurement), it cannot be expected that the quantum bit state will return to the initial state. In other words, the quantum circuit 33 does not have reversibility.

[0079] For irreversible quantum circuits 33, which do not have reversibility, it is not possible to optimize the execution environment using reversibility. One parameter that can be optimized for the execution environment is, for example, a parameter that indicates the allocation relationship between physical qubits and qubits in a quantum circuit. If the allocation of physical qubits is inappropriate, for example, many unnecessary swap gate operations will be performed during execution, increasing the probability of errors occurring.

[0080] The allocation of physical quantum bits is performed, for example, when compiling a quantum circuit in the classical computer 100. When compiling a quantum circuit, first, quantum gates in the quantum circuit are converted into quantum gates (native gates) that can be executed on the quantum computer 200.

[0081] Figure 7 shows an example of the conversion process for native gates. A native gate is a one-qubit gate or a two-qubit gate. For example, a Toffoli gate 34 is a three-qubit gate and is not a native gate. Therefore, during compilation, the Toffoli gate 34 is converted into an equivalent circuit 35 that combines multiple native gates.

[0082] Furthermore, even if a quantum circuit is composed only of native gates, it is not necessarily possible to execute the quantum circuit as is due to hardware constraints (real-world constraints) of the quantum computer 200. That is, some quantum gates can only be executed with specific quantum bits. For example, the gate operation of a two-qubit gate can only be executed with a pair of quantum bits that are connected to each other.

[0083] The constraints for making a quantum circuit executable on quantum computer 200 are that the quantum gates included in the quantum circuit are native gates and that the physical quantum bits in the actual device that are the targets of operation of the quantum gates satisfy the actual device constraints.

[0084] In the case of a simple quantum circuit, the constraints of the actual device can be satisfied by assigning an appropriate physical quantum bit to each input quantum bit as the physical quantum bit that performs the gate operation on the input quantum bit shown in the quantum circuit.

[0085] FIG. 8 is a diagram showing an example of qubit allocation according to a physical machine constraint. For example, the physical machine constraint is represented by a directed graph 36. The nodes of the directed graph 36 correspond to physical qubits, and the arrows connecting the nodes indicate pairs of physical qubits on which a CNOT gate operation can be performed. The source of the arrow is the control qubit, and the tip of the arrow is the target qubit. The directed graph 36 shows that a CNOT gate operation is possible with physical qubit Q1 as the control bit and physical qubit Q0 as the target bit. The directed graph 36 also shows that a CNOT gate operation is possible with physical qubit Q1 as the control bit and physical qubit Q2 as the target bit. CNOT gate operations cannot be performed between any other physical qubits.

[0086] Assume that quantum circuit 37 is executed under such constraints of the actual device. Three quantum bits q0, q1, and q2 are shown in quantum circuit 37. The first quantum gate 37a is a CNOT gate with quantum bit q0 as the control quantum bit and quantum bit q2 as the target quantum bit. The second quantum gate 37b is a CNOT gate with quantum bit q0 as the control quantum bit and quantum bit q1 as the target quantum bit. The third quantum gate 37c is a CNOT gate with quantum bit q1 as the control quantum bit and quantum bit q2 as the target quantum bit.

[0087] Due to limitations of the actual device, the only physical qubit that can be used as a control qubit is physical qubit Q1. Therefore, quantum circuit 37 cannot be executed in its current state, regardless of how physical qubits Q0, Q1, and Q2 are assigned to the three qubits q0, q1, and q2.

[0088] Therefore, at the time of compilation, quantum circuit 37 is converted into quantum circuit 38. The first two quantum gates 38a and 38b of quantum circuit 38 are the same as the first two quantum gates 37a and 37b, respectively, of quantum circuit 37. A swap gate 38c that exchanges the states of quantum bit q0 and quantum bit q1 is placed next to quantum gate 38b. The quantum gate 38d next to swap gate 38c is a CNOT gate that uses quantum bit q0 as the control quantum bit and quantum bit q2 as the target quantum bit.

[0089] Physical qubits are assigned to the qubits of quantum circuit 38. As a result, physical qubit Q1 is assigned to qubit q0, physical qubit Q0 is assigned to qubit q1, and physical qubit Q2 is assigned to qubit q2.

[0090] After execution of swap gate 38c, the state of quantum bit q0 becomes the state of quantum bit q1 before execution of swap gate 38c. Furthermore, after execution of swap gate 38c, the state of quantum bit q1 becomes the state of quantum bit q0 before execution of swap gate 38c. By allocating physical quantum bits in this way, quantum circuit 38 can be executed.

[0091] As such, in many cases, the processing quantum circuit 37 cannot satisfy the actual machine constraints. Therefore, by converting it into an equivalent quantum circuit 38 using a swap gate, a quantum bit allocation that satisfies the execution constraints is performed. In this case, there may be multiple patterns of allocation of the converted quantum circuit and physical quantum bits that can satisfy the actual machine constraints. Which allocation pattern to apply is indicated by, for example, a parameter. Furthermore, the allocation of the physical quantum bits affects the probability of an error occurring.

[0092] When the quantum computer 200 uses a superconducting quantum device 220, operations on quantum bits are performed by irradiating the quantum device with microwave pulses. In the classical computer 100, a schedule for irradiating the pulses is determined according to the quantum circuit.

[0093] 9 is a diagram showing an example of a pulse schedule. Quantum computer 200 is provided with multiple signal lines for irradiating pulse waves to quantum gates in quantum device 220. Some of the signal lines are for gate operation and others are for measurement. Pulse schedule 39a indicates the duration, intensity, etc. of pulse wave irradiation on each signal line.

[0094] In this case, the output timing of the pulse wave for gate operation can be adjusted within a range where the order of gate operation does not deviate from the quantum circuit 39. The output timing of the pulse wave for measurement can also be adjusted. Such differences in the output timing of the pulse wave affect the error occurrence rate. The output timing of the pulse wave is expressed by a parameter in the pulse schedule 39a.

[0095] In this way, the error rate of quantum circuits changes depending on the parameter settings of the execution environment. For example, if we can measure the average fidelity of quantum gates in actual machines according to parameter settings, we can allocate physical qubits to increase fidelity, or schedule pulses to maximize fidelity.

[0096] Since quantum circuit U without intermediate measurements is reversible, we can create an inverse circuit U after quantum circuit U. † It is expected that the measurement result when executing a quantum circuit with intermediate measurements will always return to the initial value. This can be used to evaluate whether a correct execution result is obtained. On the other hand, for quantum circuits with intermediate measurements, it is not easy to determine whether the execution result is correct when executed on the quantum computer 200. Therefore, in the quantum computing system 300, a quantum circuit with intermediate measurements is divided, and parameters are optimized for each sub-circuit obtained by dividing it, with the statistical value of the all-zero sequence as the objective function.

[0097] 10 is a block diagram showing an example of the functions of a classical computer for quantum computing. The classical computer 100 has a storage unit 110, a quantum computing manager 120, a parameter optimizer 130, and a quantum circuit execution instructer 140.

[0098] The storage unit 110 stores information used in quantum computation. For example, the storage unit 110 stores a quantum circuit 111 having intermediate measurements, a parameter set 112 in which initial values ​​are set, and an optimized parameter set 113. The quantum circuit 111 is, for example, a quantum circuit configured with native gates. The parameter sets 112 and 113 include, for example, a parameter indicating an allocation pattern of physical quantum bits and a parameter indicating the output timing of pulse waves in a pulse schedule.

[0099] The quantum computing manager 120 manages the execution of quantum computing in response to a quantum computing request from the terminal device 401. For example, the quantum computing manager 120 converts a quantum circuit sent from the terminal device 401 into an equivalent quantum circuit 111 composed only of native gates. The quantum computing manager 120 then stores the quantum circuit 111 in the storage unit 110. The quantum computing manager 120 also stores in the storage unit 110 a parameter set 112 including a plurality of parameters to be set when the quantum circuit 111 is executed.

[0100] After storing the quantum circuit 111 and the parameter set 112, the quantum computing management unit 120 instructs the parameter optimization unit 130 to optimize the parameters. Upon receiving a response indicating the completion of parameter optimization from the parameter optimization unit 130, the quantum computing management unit 120 instructs the quantum circuit execution instruction unit 140 to execute the quantum circuit 111 using the optimized parameter set 113. The quantum computing management unit 120 obtains the calculation result by the quantum circuit 111 from the quantum circuit execution instruction unit 140 and transmits the calculation result to the terminal device 401.

[0101] The parameter optimization unit 130 optimizes the values ​​of multiple parameters to be applied when executing the quantum circuit 111. For example, the parameter optimization unit 130 optimizes the values ​​of multiple parameters so as to improve the correctness (e.g., average fidelity) of the execution result of quantum computation using the quantum circuit 111. The parameter optimization unit 130 has a quantum circuit division unit 131 and a subcircuit evaluation unit 132 for optimizing the parameter values.

[0102] The quantum circuit dividing unit 131 divides the quantum circuit 111 to generate multiple subcircuits. For example, the quantum circuit dividing unit 131 divides the quantum circuit 111 at the location of an intermediate measurement. The quantum circuit dividing unit 131 adds a random circuit that generates a random initial state to each subcircuit other than the first subcircuit. At this time, multiple random circuits that generate different initial states are added to one subcircuit. Furthermore, the quantum circuit dividing unit 131 adds an inverse circuit of each partial circuit obtained by dividing the subcircuit.

[0103] The sub-circuit evaluation unit 132 performs optimization processing of parameter values ​​for each sub-circuit. For example, the sub-circuit evaluation unit 132 optimizes the parameter values ​​that affect the correctness of the execution result of each sub-circuit, using the statistical value of the all-zero sequence as an objective function for each sub-circuit.

[0104] The quantum circuit execution instruction unit 140 instructs the quantum computer 200 to execute the quantum circuit 111 using the optimized parameter set 113. The quantum circuit execution instruction unit 140 transmits the calculation result by the quantum computer 200 to the quantum calculation management unit 120.

[0105] The function of each element shown in FIG. 10 can be realized by, for example, having the processor 101 execute a program module corresponding to that element. A classical computer 100 with such capabilities can optimize parameters set during the execution of quantum circuits with intermediate measurements.

[0106] FIG. 11 is a diagram showing an example of a quantum circuit to be executed. In the quantum circuit 111 to be executed, intermediate measurements are performed at two locations. Due to the presence of intermediate measurement locations 111a and 111b, the quantum circuit 111 is irreversible. In other words, after a series of gate operations shown in the quantum circuit 111, there is no inverse circuit that returns the state of the quantum bits to the input state. The quantum computation manager 120 designates the quantum circuit 111 to be executed as "C."

[0107] The quantum circuit 111 also includes quantum gates 111c to 111f, whose execution timing can be adjusted with some flexibility. The quantum computation manager 120 sets parameters indicating the execution timing of each of the quantum gates 111c to 111f. For example, the quantum computation manager 120 sets the parameter indicating the execution timing of the quantum gate 111c to "t1." The quantum computation manager 120 sets the parameter indicating the execution timing of the quantum gate 111d to "t2." The quantum computation manager 120 sets the parameter indicating the execution timing of the quantum gate 111e to "t3." The quantum computation manager 120 sets the parameter indicating the execution timing of the quantum gate 111f to "t4." In this case, the parameter set 112 is expressed as "vector θ=(t1, t2, t3, t4)."

[0108] The time required for the execution of each quantum gate is fixed, so it is possible to accurately calculate in advance how many microseconds each of quantum gates 111c to 111f has freedom in adjusting the execution timing (adjustable time width).

[0109] The parameter optimization unit 130 acquires the quantum circuit 111 and the parameter set 112. Then, the quantum circuit division unit 131 in the parameter optimization unit 130 divides the quantum circuit 111 at intermediate measurement points 111a and 111b.

[0110] 12 is a diagram showing an example of the division result of a quantum circuit. When there are multiple measurements taken simultaneously, the quantum circuit division unit 131 divides these measurements together. When the quantum circuit 111 is divided at intermediate measurement points 111a and 111b, it is divided into intermediate measurement points 111a and 111b, partial circuits 111g to 111i, and output measurement point 111j.

[0111] Here, if there are "N-1" intermediate measurement points (N is an integer greater than or equal to 2) in the quantum circuit "C", the equations representing the subcircuits at the time of division are "c1,c2,...,c N ". The equations indicating the N intermediate measurement points are "m1, m2, . . . , m N In this case, the quantum circuit "C" is "C=c1m1c2m2···c N m N "

[0112] The quantum circuit dividing unit 131 generates a parameter group indicating the execution timing of a quantum gate having a degree of freedom in execution timing for each of the partial circuits 111g to 111i. The parameter group of the i-th (i is an integer between 1 and N) sub-circuit is expressed as a vector θ i The parameter indicating the execution timing of a quantum gate having the degree of freedom in the execution timing in the i-th subcircuit is the vector θ i " is an element of

[0113] For example, the parameter set of the partial circuit 111g is "vector θ1=(t1)", the parameter set of the partial circuit 111h is "vector θ2=(t2, t3)", and the parameter set of the partial circuit 111i is "vector θ3=(t4)".

[0114] The quantum circuit dividing unit 131 transmits the partial circuits 111g to 111i obtained by dividing the quantum circuit 111 and parameter sets corresponding to each of the partial circuits 111g to 111i to the subcircuit evaluation unit 132. The subcircuit evaluation unit 132 optimizes the parameters for each of the partial circuits 111g to 111i using the statistical value of the all-zero sequence as an objective function.

[0115] 13 is a diagram showing an example of sub-circuit optimization processing. The sub-circuit evaluation unit 132 adds a random circuit for generating an initial state to each of the partial circuits 111h and 111i that are second or later in the execution order within the quantum circuit 111, among the partial circuits 111g to 111i generated by division.

[0116] When the number of random circuits to be generated is n (n is a natural number), the subcircuit evaluation unit 132 generates n random circuits “r 21 ,r 22 ,···,r 2n Then, the sub-circuit evaluation unit 132 generates n copies of the partial circuit 111h. The sub-circuit evaluation unit 132 adds n random circuits to the input side of each of the n copies of the partial circuit 111h.

[0117] For the partial circuit 111i, the subcircuit evaluation unit 132 also adds n random circuits to the input side of each of the n copies of the partial circuit 111i. Next, the subcircuit evaluation unit 132 adds an inverse circuit to the output side of each of the partial circuits 111g to 111i. When the operation by the original circuit is U, the inverse circuit is the Hermitian conjugate U of U. † For example, the first partial circuit 111g is represented by a copy of the partial circuit 111g (operation "c1") followed by the inverse operation of the partial circuit 111g, "c1 † ” is changed to a subcircuit 41 that performs the inverse circuit of “.”

[0118] The second partial circuit 111h is converted into a plurality of sub-circuits 51, 52, ... for each random circuit. A set of the sub-circuits 51, 52, ... is defined as a sub-circuit group 50. For example, when the operation "r 21 The subcircuit 51 to which the random circuit of " is added is the operation "r 21 ", the subcircuits of operation "c2", and their operations "c2 † r 21 † " is a circuit that executes the inverse circuit of the partial circuit in order. In the inverse circuit, the inverse operation of the partial circuit "c2† " is the inverse operation of the random circuit, "r 21 † " is executed before ".

[0119] The third partial circuit 111i is converted into a plurality of sub-circuits 61, 62, ... for each random circuit. A set of the sub-circuits 61, 62, ... is defined as a sub-circuit group 60. For example, when the operation "r 31 The subcircuit 61 to which the random circuit of " is added is the operation "r 31 ", a partial circuit of operation "c3", and the inverse operation of those operations "c3 † r 31 † This is a quantum circuit that sequentially executes the inverse circuit of

[0120] The subcircuit evaluation unit 132 instructs the quantum computer 200 to execute the first subcircuit 41 a predetermined number of shots (repetitions), for example, with the input states of all quantum bits set to |0>. The subcircuit evaluation unit 132 then tallies the execution results of the subcircuit 41. If no errors occur, the output state of the subcircuit 41 is expected to be |0> for all quantum bits. Therefore, the subcircuit evaluation unit 132 calculates, for example, the probability that all quantum bits have become |0>. Based on the tallied results, the subcircuit evaluation unit 132 updates the parameter values ​​so as to improve the probability that all quantum bits will become |0> in the output state.

[0121] The sub-circuit evaluation unit 132 repeats the process of issuing an execution instruction to the quantum computer 200 for the sub-circuit 41, collecting the execution results, and updating the parameters until a predetermined termination condition for the execution results is satisfied. The sub-circuit evaluation unit 132 stores the parameter values ​​when the termination condition is satisfied as optimal values.

[0122] The subcircuit evaluation unit 132 instructs the quantum computer 200 to execute a predetermined number of shots for each of the subcircuits 51, 52, ... of the subcircuit group 50, for example, with the input states of all quantum bits set to |0>. The subcircuit evaluation unit 132 then aggregates the execution results of the subcircuits 51, 52, .... If no errors occur, the output states of the subcircuits 51, 52, ... are expected to be |0> for all quantum bits. Therefore, the subcircuit evaluation unit 132 calculates, for example, the probability that all quantum bits are |0>. Based on the aggregation results, the subcircuit evaluation unit 132 updates the parameter values ​​so as to improve the probability that all quantum bits are |0> in the output state.

[0123] The sub-circuit evaluation unit 132 repeats the process of issuing an execution instruction to the quantum computer 200 for the sub-circuits 51, 52, ..., collecting the execution results, and updating the parameters until a predetermined termination condition for the execution results is satisfied. The sub-circuit evaluation unit 132 stores the parameter values ​​when the termination condition is satisfied as optimal values.

[0124] The sub-circuit evaluation unit 132 performs the same process for the sub-circuit group 60 as for the sub-circuit group 50 to find optimal parameter values. Then, the sub-circuit evaluation unit 132 stores in the storage unit 110 the parameter group 113 in which the optimal values ​​of all parameters are set.

[0125] Fig. 14 is a diagram showing a first example of a subcircuit to which an inverse circuit is added. Fig. 14 shows an example in which an inverse circuit 41b is added to the first partial circuit 111g of partial circuits 111g to 111i obtained by dividing the quantum circuit 111.

[0126] In subcircuit 41 after the addition of inverse circuit 41b, inverse circuit 41b is added after partial circuit 41a, which performs the same operation as partial circuit 111g, which was the processing target. Partial circuit 41a is arranged with a Hadamard gate 41c acting on quantum bit q0 and an X gate 41d acting on quantum bit q2. Next to these is arranged CNOT gate 41e, with quantum bit q0 as the control quantum bit and quantum bit q1 as the target quantum bit. Next is arranged CNOT gate 41f, with quantum bit q1 as the control quantum bit and quantum bit q2 as the target quantum bit.

[0127] In inverse circuit 41b, quantum bits corresponding to each quantum bit in partial circuit 41a are arranged in reverse order. The quantum bits in partial circuit 41a and the corresponding quantum bits in inverse circuit 41b have inverse gate operations (Hermitian conjugates).

[0128] Specifically, inverse circuit 41b, first, CNOT gate 41g is arranged with qubit q1 as the control qubit and qubit q2 as the target qubit. Next, CNOT gate 41h is arranged with qubit q0 as the control qubit and qubit q1 as the target qubit. Next, quantum gate 41i, which is a Hermitian conjugate of a Hadamard gate acting on qubit q0, and quantum gate 41j, which is a Hermitian conjugate of an X gate acting on qubit q2, are arranged.

[0129] After the inverse circuit 41b, gate operations for measurements 41k to 41m on each quantum bit are shown. When subcircuit 41 is executed with |0> as input to each quantum bit of such subcircuit 41, it is expected that all values ​​measured by measurements 41k to 41m will be |0>, provided that no errors due to noise occur. If an error occurs, |1> will be measured in one of the quantum bits. It can be determined that an error has occurred in the quantum bit for which |1> is measured.

[0130] The probability of an error occurring is affected by, for example, the operation timing of the quantum gate. In the subcircuit 41, the gate operation timings that can be adjusted are the X gate 41d and the quantum gate 41j, which is the Hermitian conjugate of the X gate. The parameter indicating the execution timing of the X gate 41d is t1, and the parameter indicating the execution timing of the quantum gate 41j is t'1.

[0131] The sub-circuit evaluation unit 132 evaluates the sub-circuit 41 ("c1c1 † The parameter set "vector θ1 = (t1)" is optimized so that the number of times that |000> is reached is increased for the measurement results when the calculation ("calculation of |000") is performed multiple times. Then, "vector θ1 = (t1)" is obtained as the optimal parameter set (θ and t1 have dots above them).

[0132] In the subcircuit 41, the parameter "t'1" is increased in association with the addition of the inverse circuit 41b. The subcircuit evaluation unit 132 optimizes the parameter "t1" by setting the value of this parameter to, for example, an appropriate fixed value. The subcircuit evaluation unit 132 may also simultaneously optimize the increased parameter "t'1." When optimizing the parameter "t'1" as well, the subcircuit evaluation unit 132, for example, shifts the parameter "t1" forward or backward, shifts the parameter "t'1" in the opposite direction by the same amount.

[0133] The Hadamard gate and the Hermitian conjugate of the Hadamard gate are the same operation (H † =H). Similarly, the X gate and the Hermitian conjugate of the X gate are the same operation (X † =X). Although not included in the subcircuit 41, the quantum gate operations of the Y gate and the Z gate are the same as the Hermitian conjugate operations (Y † =Y,Z † = Z). Therefore, in the following explanation, H in the reverse circuit † is represented by H, and X in the reverse circuit † is represented by X, and Y in the reverse circuit † is represented by Y, and Z in the reverse circuit † Let Z be used.

[0134] For the partial circuits 111h, 111i, ... other than the first partial circuit 111g, the initial state by a plurality of random circuits becomes the input state. i For the i-th subcircuit represented by (i∈{2, ,N}), multiple random circuits are generated. For example, the random circuit for the i-th subcircuit is expressed by the following formula:

[0135]

number

[0136] The subcircuit evaluation unit 132 adds a random circuit to the input side of each of the n copies of the i-th subcircuit and adds an inverse circuit to the output side. i1 c i c i † r i1 † ,r i2 c i c i † r i2 † ,···,r in c i c i † r in †} is obtained.

[0137] Fig. 15 is a diagram showing a second example of a sub-circuit to which an inverse circuit is added. Fig. 15 shows an example of generating a plurality of sub-circuits 51, 52, ... that perform operations on a random initial state based on a second partial circuit 111h of partial circuits 111g to 111i obtained by dividing the quantum circuit 111.

[0138] For example, the subcircuit 51 has a subcircuit 51a that is a copy of the subcircuit 111h obtained by division, and the subcircuit 51 has a subcircuit 51b that is a copy of the subcircuit 111h obtained by division. 21A random circuit 51b is added to perform the operation "c2". An inverse circuit 51c is added after the partial circuit 51a to perform the inverse operation of the partial circuit 51a and the random circuit 51b. The inverse circuit 51c performs the Hermitian conjugate "c2 † ", and then the operation "r 21 "The Hermitian conjugate of "r 21 † The measurement is performed after the inverse circuit 51c.

[0139] The subcircuit 52 has a subcircuit 52a, which is a copy of the subcircuit 111h obtained by division, and a subcircuit 52b has a subcircuit 52c ...a 22 A random circuit 52b is added to perform the operation "c2". An inverse circuit 52c is added after the partial circuit 52a, performing the inverse operation of the partial circuit 52a and the random circuit 52b. The inverse circuit 52c performs the Hermitian conjugate "c2 † ", and then the operation "r 22 "The Hermitian conjugate of "r 22 † The measurement is performed after the inverse circuit 52c.

[0140] Other random circuits (r i3 ,···,r in ), a subcircuit is generated by adding a random circuit and an inverse circuit to partial circuit 52a, which is a copy of partial circuit 111h. The subcircuit evaluation unit 132 executes each of these subcircuits 51, 52,... multiple times, and evaluates the "vector θ" indicating the values ​​of the parameter groups of each of the subcircuits 51, 52,... in the direction in which the total number of times |0...0> is increased. i " will be updated.

[0141] The sub-circuit evaluation unit 132 calculates the vector θ i Execution of the subcircuits 51, 52, and the vector θ i " and update the "vector θ i" are optimized. For example, subcircuits 51, 52, ... include a parameter group represented by "vector θ2 = (t2, t3)." Therefore, the values ​​of the parameters "t2, t3" are optimized. Then, "vector θ2 = (t2, t3)" (θ, t2, t3 have dots above them) indicating the values ​​of the optimized parameter group is obtained.

[0142] In the subcircuit 51, the parameters "t'2, t'3" are increased in association with the addition of the inverse circuit 52c. The subcircuit evaluation unit 132 optimizes the parameter "t1" by setting the values ​​of these parameters to, for example, appropriate fixed values. The subcircuit evaluation unit 132 may also simultaneously optimize the increased parameters "t2, t3." When optimizing the parameters "t'2, t'3," for example, when the subcircuit evaluation unit 132 shifts the parameter "t2" forward or backward, it shifts the parameter "t'2" in the opposite direction by the same amount. Similarly, when the subcircuit evaluation unit 132 shifts the parameter "t3" forward or backward, it shifts the parameter "t'3" in the opposite direction by the same amount.

[0143] As with the partial circuit 111h, the parameter "t4" is also optimized for the third partial circuit 111i among the partial circuits 111g to 111i obtained by dividing the quantum circuit 111. As a result, an optimized parameter set 113 is obtained.

[0144] 16 is a diagram showing an example of an optimized parameter set. The optimized parameter set 113 is expressed as "vector θ=(t1, t2, t3, t4)" (θ, t1, t2, t3, t4 have dots above them). When the quantum circuit 111 is executed, quantum gates with flexibility in their execution timing are executed at the timing shown in the parameter set 113.

[0145] Next, the procedure of the parameter optimization process will be described in detail with reference to FIGS. 17 is a flowchart showing an example of the procedure for parameter optimization processing. The processing shown in FIG. 17 will be explained below in order of step number.

[0146] [Step S101] The parameter optimization unit 130 acquires a quantum circuit with intermediate measurements. Let the acquired quantum circuit be "C". Also, let the number of measurement locations (intermediate measurements and output state measurements) included in the acquired quantum circuit "C" be "N".

[0147] [Step S102] The quantum circuit splitting unit 131 splits the quantum circuit "C" at a location where there is an intermediate measurement m i (1 ≤ i < N). As a result, the quantum circuit "C" becomes "C = c1m1c2m2 ··· c N m N ".

[0148] [Step S103] The quantum circuit splitting unit 131 divides the parameter group represented by "vector θ" into parameter groups for each of the sub - circuits obtained by splitting. As a result, a "vector θ i " indicating the parameter group for each sub - circuit is obtained.

[0149] [Step S104] The sub - circuit evaluation unit 132 acquires the number "n" of generated random circuits. For example, the sub - circuit evaluation unit 132 reads out the preset number "n" of generations from the memory 102 or the storage device 103.

[0150] [Step S105] The sub - circuit evaluation unit 132 sets "1" to the variable i. [Step S106] The sub - circuit evaluation unit 132 determines whether the value of the variable i is less than or equal to the number "N" of measurement locations. If the value of the variable i is less than or equal to "N", the sub - circuit evaluation unit 132 proceeds to step S107. If the value of the variable i exceeds "N", the sub - circuit evaluation unit 132 proceeds to step S110.

[0151] [Step S107] The sub-circuit evaluation unit 132 executes sub-circuit optimization processing for the i-th sub-circuit. The details of the sub-circuit optimization processing will be described later (see FIG. 18). Through the sub-circuit optimization processing, the values ​​of the parameter group corresponding to the i-th sub-circuit are optimized. The optimized parameter group is represented by a vector θ i " (θ is expressed with a dot above it).

[0152] [Step S108] The subcircuit evaluation unit 132 calculates a vector θ i " (θ i is with a dot above) is stored in memory 102. [Step S109] The sub-circuit evaluation unit 132 adds 1 to the variable i. After that, the sub-circuit evaluation unit 132 proceeds to step S106.

[0153] [Step S110] The sub-circuit evaluation unit 132 outputs an optimized parameter set represented by a "vector θ" (θ with a dot above it). For example, the sub-circuit evaluation unit 132 stores the optimized parameter set in the storage unit 110.

[0154] Next, the sub-circuit optimization process will be described in detail. 18 is a flowchart showing an example of the procedure for the sub-circuit optimization process. The process shown in FIG. 18 will be explained below in order of step number.

[0155] [Step S121] The subcircuit evaluation unit 132 determines whether the value of the variable i is 1. If the value of i is 1, the subcircuit evaluation unit 132 proceeds to step S122. If the value of i is not 1, the subcircuit evaluation unit 132 proceeds to step S123.

[0156] [Step S122] The sub-circuit evaluation unit 132 evaluates all n random circuits by ij =I" (j∈{1,2,···,n}). The operation I indicates that no gate operation is performed on the initial state |0,···,0>. This effectively creates a random circuit "vector r1 = {r11 ,r 12 ,···,r 1n}" is defined. After that, the sub-circuit evaluation unit 132 advances the process to step S124.

[0157] [Step S123] The subcircuit evaluation unit 132 generates n random circuits. The generated random circuits are called "vector r i ={r i1 ,r i2 ,···,r in The subcircuit evaluation unit 132 evaluates the partial circuit "c i " Add a random circuit before each of the n copies of ".

[0158] [Step S124] The subcircuit evaluation unit 132 evaluates the partial circuit “c i "The inverse circuit of "c i † The subcircuit evaluation unit 132 generates the n partial circuits "c i " followed by the generated inverse circuit "c i † " Add.

[0159] [Step S125] The subcircuit evaluation unit 132 generates random circuits “r ij "The inverse circuit of "r ij † The subcircuit evaluation unit 132 generates a subcircuit “c i "The inverse circuit of "c i † " followed by the generated random circuit "r ij "The inverse circuit of "r ij † " is added. This generates n subcircuits.

[0160] [Step S126] The sub-circuit evaluation unit 132 generates a sub-circuit group {r i1 c i c i † r i1 † ,ri2 c i c i † r i2 † ,···,r in c i c i † r in † The sub-circuit evaluation unit 132 obtains the execution results of each sub-circuit from the quantum computer 200.

[0161] [Step S127] The subcircuit evaluation unit 132 tallies the execution results of the subcircuits. For example, the subcircuit evaluation unit 132 counts, for each subcircuit, the number of times that the states of all the quantum bits are measured as |0>(|0···0>).

[0162] [Step S128] The subcircuit evaluation unit 132 calculates a vector θ i For example, the subcircuit evaluation unit 132 updates the vector θ i This process is a parameter optimization process in which the statistical occurrence probability of an all-zero sequence is used as the objective function.

[0163] [Step S129] The subcircuit evaluation unit 132 calculates a vector θ i For example, the sub-circuit evaluation unit 132 determines whether the change in the vector θ i The sub-circuit evaluation unit 132 calculates the amount of change (for example, the inner product) of the vector θ , which indicates the parameter group, and determines that the vector θ has converged when the amount of change is equal to or less than a threshold value. i If the change in the vector θ i If the change in " has not converged, the process proceeds to step S126.

[0164] In this way, for each subcircuit obtained by dividing a quantum circuit with intermediate measurements, the values ​​of the parameter set included in that subcircuit are optimized. That is, optimization is performed for all parameters set during execution of a quantum circuit with intermediate measurements, with the statistical occurrence probability of an all-zero sequence as the objective function. By executing quantum circuit 111 using optimized parameter set 113 on quantum computer 200, quantum computation with high average fidelity becomes possible.

[0165] Since the actual input states to the second and subsequent subcircuits after division are not known in advance, the input states for each divided subcircuit are generated randomly, which makes it possible to obtain parameters with good average values ​​for any input state.

[0166] Third Embodiment The third embodiment is a quantum computing system that can generate, as the initial state of a subcircuit, a state that is closer to the actual initial state than simply generating a circuit randomly.

[0167] In the second embodiment, the sub-circuit evaluation unit 132 performs the following operations: i When optimizing ” (i∈{2, ,N}), the generated random circuit “r i ={r i1 ,r i2 ,···,r in In the third embodiment, the sub-circuit evaluation unit 132 uses "c1m1c2m2···c i-1 m i-1 The distribution of measurement results when " is executed multiple times" and the random circuit "r ij When the distribution of " is far, the random circuit "r ij " is discarded. This allows us to prepare a state that is close to the actual initial state. The approximation of the distributions can be compared using, for example, KL-divergence (Kullback-Leibler divergence).

[0168] In the third embodiment, the sub-circuit optimization process (step S107 in FIG. 17) is different from that in the second embodiment. Fig. 19 is a flowchart showing an example of the procedure for sub-circuit optimization processing in the third embodiment. Of the processing shown in Fig. 19, the processing in steps S201 to S202 and S204 to S209 is the same as the processing in steps S121 to S122 and S124 to S129 in the second embodiment shown in Fig. 18, respectively.

[0169] In the third embodiment, in step S203, instead of the simple random circuit generation process (step S123 in FIG. 18), a random circuit selection process is performed to select a random circuit with an appropriate distribution of output states. The random circuit selection process is a process to select, from the generated random circuits, a random circuit that generates a state close to the actual initial state.

[0170] 20 is a flowchart showing an example of the procedure for random circuit selection processing. The processing shown in FIG. 20 will be explained below in order of step number. [Step S221] The sub-circuit evaluation unit 132 acquires the random circuit execution count “X.” For example, the sub-circuit evaluation unit 132 reads the random circuit execution count “X” preset by the user from the memory 102 or the storage device 103.

[0171] [Step S222] The subcircuit evaluation unit 132 evaluates the operations “c1m1c2m2···c” of the quantum circuit up to the i-th subcircuit. i-1 m i-1 " X times to the quantum computer 200.

[0172] [Step S223] The sub-circuit evaluation unit 132 acquires the measurement result from the quantum computer 200 and substitutes the distribution of the output states into the variable A. [Step S224] The subcircuit evaluation unit 132 generates a vector r i " is generated as an empty set (vector r i :={}).

[0173] [Step S225] The subcircuit evaluation unit 132 sets the variable k to “1”. [Step S226] The sub-circuit evaluation unit 132 determines whether the value of variable k is less than or equal to "n." If the value of variable k is less than or equal to "n," the sub-circuit evaluation unit 132 proceeds to step S227. If the value of variable k exceeds "n," the sub-circuit evaluation unit 132 terminates the random circuit selection process.

[0174] [Step S227] The subcircuit evaluation unit 132 generates a random circuit and calculates the ik " is substituted. [Step S228] The subcircuit evaluation unit 132 generates a random circuit “r ik " is executed X times, and the distribution of the quantum bit states after execution is assigned to variable B.

[0175] [Step S229] The sub-circuit evaluation unit 132 determines whether the difference in distribution between variable A and variable B is equal to or less than a certain value. For example, the sub-circuit evaluation unit 132 calculates the KL-divergence of variable B with respect to variable A. If the value of KL-divergence is equal to or less than a certain value, the sub-circuit evaluation unit 132 determines that the distributions are similar and proceeds to step S230. If the value of KL-divergence exceeds a certain value, the sub-circuit evaluation unit 132 discards the random circuit generated in the immediately preceding step S227 and proceeds to step S227.

[0176] [Step S230] The subcircuit evaluation unit 132 generates a vector r i " to "r ik " (vector r i :=vector r i ∪{r ik}). [Step S231] The subcircuit evaluation unit 132 adds "1" to the value of the variable k (k:=k+1), and proceeds to step S226.

[0177] In this way, n random circuits that generate a state close to the actual initial state are selected. By optimizing the parameter set of the i-th subcircuit using the selected random circuit, the parameter set is optimized to match the state of that subcircuit when the quantum circuit 111 is executed. As a result, appropriate values ​​of the parameters included in the parameter set can be found with high precision, and the average fidelity when the quantum circuit 111 is executed can be improved.

[0178] [Fourth embodiment] The fourth embodiment is a quantum computing system 300 that optimizes parameters indicating the allocation of physical quantum bits to quantum bits in a quantum circuit 111. In the quantum computing system 300 according to the fourth embodiment, an all-zero sequence is evaluated for each element of a set M of initial allocations and routings of physical quantum bits that satisfy the actual machine constraints. Note that routing is a process of using a swap circuit to move the state of a quantum bit that is the target of a two-qubit gate operation to a quantum bit that can perform a two-qubit gate operation under the actual machine constraints, so that the desired quantum computation can be performed.

[0179] 21 is a diagram showing an example of an actual machine constraint for executing a quantum circuit with intermediate measurements. The actual machine constraint depends on the connection relationships between qubits in quantum device 220 of quantum computer 200. The actual machine constraint is represented by directed graph 71. According to directed graph 71, the executable two-qubit gate is a two-qubit gate that uses physical qubit "Q1" as the control qubit and physical qubit "Q0" or physical qubit "Q2" as the target qubit.

[0180] The parameters that indicate the allocation of physical qubits to satisfy the constraints of the actual device cannot be divided into subcircuits, and the parameters of each subcircuit are interrelated. In such cases, it is not possible to optimize each subcircuit individually.

[0181] Therefore, in the fourth embodiment, the quantum circuit dividing unit 131 divides the intermediate measurement “m iThe quantum circuit is divided at a location where there is a ". In this case, if there are multiple intermediate measurements at the same time, they are divided together. The number of intermediate measurement locations is "N-1", and the intermediate measurements and output measurements are divided into "m1,m2,...,m N Then, the operations of the subcircuit obtained by division are defined as "c1,c2,...,c N In this case, the quantum circuit operation C is divided into "C=c1m1c2m2···c N m N "

[0182] For example, assume that the quantum circuit 114 is executed based on the constraints of the actual device. The quantum circuit 114 includes intermediate measurement points. Therefore, the quantum circuit dividing unit 131 divides the quantum circuit 114 at the intermediate measurement points.

[0183] 22 is a diagram showing an example of a method for dividing a quantum circuit including intermediate measurements. The quantum circuit dividing unit 131 divides the quantum circuit 114, for example, at intermediate measurement points 114a and 114b. At this time, if there are multiple intermediate measurements at the same time, the quantum circuit dividing unit 131 divides them all together. As a result, subcircuits 114g to 114i are obtained.

[0184] The operations executed by the subcircuits 114g to 114i are defined as "c1," "c2," and "c3," respectively. The intermediate measurements at the intermediate measurement points 114a and 114b are defined as "m1" and "m2," and the measurement of the output state at the output measurement point 114j is defined as "m3." Then, the operation "C" by the quantum circuit 114 is "C=c1m1c2m2c3m3."

[0185] The subcircuit evaluation unit 132 generates k assignment patterns M of parameters indicating the initial assignment of physical qubits and parameters indicating the intermediate state swapping by the swap circuit. k If all parameter assignment patterns are M, then "M k ∈M".

[0186] The sub-circuit evaluation unit 132 determines the allocation pattern M kFor each of them, the number of times of the all-zero sequence is evaluated. For example, the sub-circuit evaluation unit 132 evaluates the number of times of the all-zero sequence by using the formula "C=c1m1c2m2...c N m N " to allocation pattern M k Applying this, the assigned routed quantum circuit "C'=c'1m'1c'2m'2···c' N m' N " is obtained.

[0187] 23 is a diagram showing an example of an assigned and routed quantum circuit. For example, after the initial assignment, the quantum circuit 114 is modified to satisfy the real machine constraints shown in the directed graph 71 (see FIG. 21), resulting in quantum circuit 114-1.

[0188] In quantum circuit 114-1, physical qubit Q0 is assigned to qubit q0, physical qubit Q1 is assigned to qubit q1 in quantum circuit 114-1, and physical qubit Q3 is assigned to qubit q3 in quantum circuit 114-1.

[0189] Subcircuit 114g has an additional swap gate 111k for swapping qubit q0 and qubit q1. In CNOT gate 111l next to swap gate 111k, the control qubit and target qubit are reversed compared to quantum circuit 114.

[0190] Subcircuit 114h has two additional swap gates 111m and 111n for swapping qubit q0 and qubit q1. In CNOT gate 111o next to swap gate 111n, the control qubit and target qubit are reversed compared to quantum circuit 114.

[0191] Subcircuit 114i has an additional swap gate 111p for swapping qubit q1 and qubit q2. In CNOT gate 111q next to swap gate 111p, physical qubit Q1 becomes the control qubit and physical qubit Q2 becomes the target qubit. X gate 111r and Hadamard gate 111s of partial circuit 111i act on physical qubit Q0. Z gate 111t and Hadamard gate 111u of partial circuit 111i act on physical qubit Q1.

[0192] The sub-circuit evaluation unit 132 generates k patterns of assignment patterns indicated by a parameter group that generates a modified quantum circuit as shown in Fig. 23. The sub-circuit evaluation unit 132 generates k patterns of assignment patterns indicated by a parameter group that generates a modified quantum circuit as shown in Fig. 23. k " (M k ∈M), evaluate the number of all-zero sequences as follows:

[0193] The subcircuit evaluation unit 132 evaluates "c'1c'1 † ” is executed multiple times, the average number of times |0···0> is calculated, and z k1 Let's say. The subcircuit evaluation unit 132 evaluates each "c' i ” (i∈{2, ,N}), execute steps 1 and 2 below. 1. The subcircuit evaluation unit 132 randomly generates a plurality of circuit vectors r i ={r i1 ,r i2 ,···,r in}". 2. The subcircuit evaluation unit 132 i1 c' i c' i † r i1 † ,r i2 c' i c' i † r i2 † ,···,r in c' i c' i † rin †} multiple times, calculate the average number of times |0···0> occurs, and call it "z ki "

[0194] Then, the sub-circuit evaluation unit 132 performs the "Σ i z ki The allocation pattern "M" that minimizes k " is output as the optimal allocation. Next, we will explain in detail the procedure for parameter optimization, which optimizes the initial allocation and routing of physical quantum bits.

[0195] 24 is a flowchart showing an example of the procedure for parameter optimization processing for optimizing the initial allocation and routing of physical quantum bits. The processing shown in FIG. 24 will be described below in order of step number.

[0196] [Step S301] The quantum circuit division unit 131 divides a quantum circuit C having N measurement points and an allocation set “M={M1, M2, . . . , M L For example, the quantum circuit dividing unit 131 reads out from the storage unit 110 the quantum circuit C and the assignment set M that are stored in advance in the storage unit 110.

[0197] [Step S302] The quantum circuit division unit 131 divides the quantum circuit C into intermediate measurements m i ". This divides it at "C=c1m1c2m2···c N m N " is obtained. [Step S303] The subcircuit evaluation unit 132 sets a variable k to “1” (k:=1).

[0198] [Step S304] The sub-circuit evaluation unit 132 determines whether the value of the variable k is less than or equal to the number of allocation patterns L. If the value of k is less than or equal to L, the sub-circuit evaluation unit 132 proceeds to step S305. If the value of k exceeds L, the sub-circuit evaluation unit 132 proceeds to step S312.

[0199] [Step S305] The subcircuit evaluation unit 132 evaluates the obtained quantum circuit “C=c1m1c2m2···c N m N ” for the kth allocation pattern “M k ” to generate the physical qubit assigned and routed quantum circuit “C’=c’1m’1c’2m’2···c’ N m' N " is generated.

[0200] [Step S306] The sub-circuit evaluation unit 132 acquires the number of random circuits to be generated, “n.” For example, the sub-circuit evaluation unit 132 reads the number of random circuits to be generated, “n,” preset by the user, from the memory 102 or the storage device 103.

[0201] [Step S307] The subcircuit evaluation unit 132 sets the variable i to “1”. [Step S308] The subcircuit evaluation unit 132 determines whether the value of the variable i is less than or equal to N. If the value of i is less than or equal to N, the subcircuit evaluation unit 132 proceeds to step S310. If the value of i exceeds N, the subcircuit evaluation unit 132 proceeds to step S309.

[0202] [Step S309] The subcircuit evaluation unit 132 adds "1" to k, and the process proceeds to step S304. [Step S310] The sub-circuit evaluation unit 132 performs a sub-circuit execution process. The details of the sub-circuit execution process will be described later (see FIG. 25). k The average number of times the measurement result was |0···0> in the i-th subcircuit execution process in which ki " is obtained.

[0203] [Step S311] The subcircuit evaluation unit 132 adds "1" to the variable i, and proceeds to step S308. [Step S312] The subcircuit evaluation unit 132 calculates the “z ki " Sum of "Σ i zki " is the smallest "M k " is output.

[0204] The output "M k " is the allocation pattern of physical qubits that has the lowest probability of error. 25 is a flowchart showing an example of the procedure for the sub-circuit execution process. Of the processes shown in FIG. 25, the processes in steps S321 to S327 are the same as the processes in steps S121 to S127 shown in FIG.

[0205] In step S328, the sub-circuit evaluation unit 132 calculates the average number of times that the measurement result after performing multiple times for each sub-circuit becomes |0···0>. The sub-circuit evaluation unit 132 assigns the calculated average number to the variable "z ki " is substituted.

[0206] In this way, even if the parameter set cannot be divided into sub-circuits, it is possible to calculate a parameter set (physical quantum bit allocation pattern / routing) that minimizes the error occurrence rate for each sub-circuit.

[0207] Other Embodiments In the second to fourth embodiments, the quantum circuit dividing unit 131 divides the quantum circuit at intermediate measurement points, but the quantum circuit dividing unit 131 may divide the quantum circuit at points other than intermediate measurement points. For example, when the number of quantum gates in the portion between measurements is large, the quantum circuit dividing unit 131 can divide the circuit more finely to perform optimization. This makes it possible to prevent, for example, some subcircuits from becoming too deep, and to accurately evaluate the subcircuits.

[0208] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents. [Explanation of symbols]

[0209] 1. Quantum computers 2 Quantum circuit 3a,3b,4a,5a partial circuit 4, 5-1, 5-2,... Subcircuit 4b,5b reverse circuit 5c Random Circuit 5 Subcircuits 10. Information processing equipment 11 Storage section 12 Processing section

Claims

1. Divide the quantum circuit to be executed by the quantum computer into multiple subcircuits, generating a subcircuit by adding an inverse circuit after each of the plurality of partial circuits, the inverse circuit causing the quantum computer to execute an operation of the partial circuit; for each of a plurality of candidate values ​​of a parameter that is set to cause the quantum computer to execute the quantum circuit, the candidate value is set to the parameter, and the quantum computer is caused to execute the sub-circuit generated from each of the plurality of partial circuits a plurality of times; determining a value to be set for the parameter in the execution of the quantum circuit from among the plurality of candidate values ​​based on a comparison result between an input state and an output state when the subcircuit is executed; A quantum computing support program that causes a computer to perform processing.

2. In the process of dividing the quantum circuit, the quantum circuit is divided at an intermediate measurement position where a measurement other than an output state is performed. The quantum computing support program according to claim 1.

3. In the process of determining the value to be set for the parameter, a value to be set for the parameter in the execution of the quantum circuit is determined based on a probability that the input state and the output state match when the subcircuit is executed, for each of the plurality of candidate values. The quantum computing support program according to claim 1.

4. In the process of determining the value to be set for the parameter, the value to be set for the parameter used in executing the first partial circuit is determined based on a comparison result between the input state and the output state when the sub-circuit generated from the first partial circuit is executed. The quantum computing support program according to claim 1.

5. In the process of generating the subcircuit, a random circuit that generates a random initial state of a quantum bit based on a second partial circuit that is second or later in the execution order within the quantum circuit is added before the second partial circuit, a first inverse circuit that indicates an operation that is the inverse of the operation of the second partial circuit is added after the second partial circuit, and a second inverse circuit that indicates an operation that is the inverse of the operation of the added random circuit is added after the first inverse circuit to generate a plurality of the subcircuits. The quantum computing support program according to claim 1.

6. In the process of generating the sub-circuit, instructing the quantum computer to execute the quantum circuit multiple times up to a third partial circuit whose execution order is i-th (i is a natural number) within the quantum circuit; Obtain the distribution of output states over multiple runs, When generating the sub-circuit of the fourth partial circuit whose execution order is (i+1) in the quantum circuit, a distribution of initial states obtained by the generated random circuit is compared with a distribution of the acquired output states, and based on the comparison result, it is determined whether or not to adopt the generated random circuit; If it is determined that the random circuit is adopted, the sub-circuit is generated by adding the generated random circuit. The quantum computing support program according to claim 4.

7. In the process of causing the quantum computer to execute the sub-circuit a plurality of times, a plurality of combination patterns are generated by combining candidate values ​​for each of the plurality of parameters that are set when the quantum circuit is executed, and for each of the plurality of combination patterns, the quantum computer is caused to execute the sub-circuit for each of the plurality of partial circuits a plurality of times using the plurality of parameters to which candidate values ​​shown in the combination pattern are set; In the process of determining the value to be set to the parameter, a combination pattern indicating a value to be set to the parameter when the quantum circuit is executed is determined from among the plurality of combination patterns based on a comparison result between an input state and an output state when the sub-circuit is executed for each of the plurality of combination patterns. The quantum computing support program according to claim 1.

8. The value of the parameter is a value indicating the execution timing of a quantum gate having a predetermined range of degrees of freedom in the execution timing. The quantum computing support program according to claim 1.

9. the value of the parameter is a value indicating an allocation pattern of physical quantum bits of the quantum computer to quantum bits included in the quantum circuit; The quantum computing support program according to claim 1.

10. Divide the quantum circuit to be executed by the quantum computer into multiple subcircuits, generating a subcircuit by adding an inverse circuit after each of the plurality of partial circuits, the inverse circuit causing the quantum computer to execute an operation of the partial circuit; for each of a plurality of candidate values ​​of a parameter that is set to cause the quantum computer to execute the quantum circuit, the candidate value is set to the parameter, and the quantum computer is caused to execute the sub-circuit generated from each of the plurality of partial circuits a plurality of times; determining a value to be set for the parameter in the execution of the quantum circuit from among the plurality of candidate values ​​based on a comparison result between an input state and an output state when the subcircuit is executed; A quantum computing-assisted method in which processing is performed by a computer.

11. a processing unit that divides a quantum circuit to be executed by a quantum computer into a plurality of partial circuits, generates a sub-circuit by adding, after each of the plurality of partial circuits, an inverse circuit that causes the quantum computer to execute an operation that is inverse to the operation of the partial circuit, sets a candidate value for each of a plurality of candidate values ​​of a parameter that is set to cause the quantum computer to execute the quantum circuit, causes the quantum computer to execute the sub-circuit generated from each of the plurality of partial circuits a plurality of times, and determines a value to be set for the parameter in the execution of the quantum circuit from among the plurality of candidate values ​​based on a comparison result between an input state and an output state when the sub-circuit is executed; An information processing device having the above.

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