Trimming system and semiconductor module

Abstract

To perform trimming based on a characteristic of a switching element by using a single communication terminal.SOLUTION: A trimming system 1-1 includes a semiconductor module 10 and an external device 20 and the semiconductor module 10 comprises a switching element 1a, a single communication terminal CM, and a control circuit 1b. The external device 20 outputs trimming data td depending on an operational state of the semiconductor module 10. The control circuit 1b includes: a drive control circuit 1b1 that outputs a drive control signal and performs switching control of the switching element 1a; a protection circuit 1b2 that adjusts a protection function of the switching element 1 on the basis of the trimming data td; and a communication circuit 1b3 that receives the trimming data td from the external device 20 by performing both-way communication with the external device 20 via the communication terminal CM and transmits operational state information st based on the protection function adjusted using the trimming data td to the external device 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a trimming system and a semiconductor module. [Background technology]

[0002] In semiconductor modules such as an IPM (Intelligent Power Module) that incorporates a switching element, the circuit functions within the semiconductor module are adjusted before actual operation. As related technologies, for example, a power module has been proposed that transmits data and a clock using two terminals to store a set value in a memory element (Patent Document 1). Also, an inverter device has been proposed that includes a power line modem that communicates with the outside world using the power line as a communication path (Patent Document 2). Furthermore, a technology has been proposed that sets parameters using data based on the states of the data input terminal and address terminal until a clock signal is detected (Patent Document 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-057985 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-204523 [Patent Document 3] Japanese Patent Application Laid-Open No. 2012-175789 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a trimming system and a semiconductor module that enable trimming based on the characteristics of a switching element using a single communication terminal. [Means for solving the problem]

[0005] To solve the above problem, a trimming system is provided. The trimming system includes an external device and a semiconductor module. The external device outputs trimming data according to the operating state of the object to be trimmed. The semiconductor module includes a switching element, a drive control circuit that outputs a drive control signal to control the switching of the switching element, a protection circuit that adjusts the protection function of the switching element based on the trimming data, and a control circuit that includes a communication circuit that receives trimming data from the external device via a single communication terminal and transmits information about the operating state to the external device.

[0006] To solve the above problem, a semiconductor module is provided. The semiconductor module includes a switching element, a single communication terminal, and a control circuit. The control circuit includes a drive control circuit that outputs a drive control signal to control the switching of the switching element, a protection circuit that adjusts a protection function of the switching element based on trimming data output from an external device in accordance with the operating state of the trimming target, and a control circuit including a communication circuit that receives trimming data from the external device via the communication terminal and transmits information about the operating state to the external device. [Effects of the Invention]

[0007] According to one aspect, trimming based on the characteristics of a switching element can be performed using a single communication terminal. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a trimming system. [Figure 2] FIG. 1 is a diagram illustrating an example of the overall configuration of a trimming system. [Figure 3] FIG. 1 is a diagram illustrating an example of the configuration of an HVIC and a high-side semiconductor chip. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of an LVIC and a low-side semiconductor chip. [Figure 5] FIG. 2 is a diagram illustrating an example of the configuration of an overheat detection circuit. [Figure 6] FIG. 10 is a diagram showing a trimming operation flow when variably setting the overheat reference voltage. [Figure 7] 10A and 10B are diagrams for explaining an example of a trimming operation when variably setting an overheat reference voltage. [Figure 8] FIG. 2 is a diagram illustrating an example of the configuration of an overcurrent detection circuit. [Figure 9] FIG. 10 is a diagram showing a trimming operation flow when variably setting an overcurrent reference voltage. [Figure 10] 10A and 10B are diagrams for explaining an example of a trimming operation when variably setting an overcurrent reference voltage. [Figure 11] FIG. 2 is a diagram illustrating an example of a configuration of a logic circuit. [Figure 12] 10 is a diagram showing an example of a timing chart of output data from a counter circuit in a data receiving circuit to a latch circuit; [Figure 13] FIG. 10 is a diagram showing an example of bit allocation of trimming data. [Figure 14] FIG. 1 is a diagram illustrating an example of the configuration of an LVIC having a mechanism for adjusting the driving capacity of a switching element. [Figure 15] FIG. 2 is a diagram illustrating a correspondence relationship between input and output of a drive capability switching circuit. [Figure 16] FIG. 2 is a diagram illustrating an example of the configuration of a drive control circuit. [Figure 17] FIG. 10 is a diagram showing an example of wiring of an HVIC and wiring of an LVIC connected to a communication terminal. [Figure 18] FIG. 10 is a diagram showing the configuration of a first modified example of the trimming system. [Figure 19] FIG. 10 is a diagram showing the configuration of a second modified example of the trimming system. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same configuration are designated by the same reference numerals, and redundant description may be omitted.

[0010] 1 is a diagram illustrating an example of a trimming system. The trimming system 1-1 includes a semiconductor module 10 and an external device 20. The semiconductor module 10 includes a switching element 1a, a single communication terminal CM, and a control circuit 1b, which includes a drive control circuit 1b1, a protection circuit 1b2, and a communication circuit 1b3.

[0011] The external device 20 outputs trimming data td corresponding to the operating state of the semiconductor module 10 to be trimmed. The drive control circuit 1b1 outputs a drive control signal to control the switching of the switching element 1a. The protection circuit 1b2 adjusts the protection function of the switching element 1a based on the trimming data td.

[0012] The communication circuit 1b3 performs bidirectional communication with the external device 20 via the communication terminal CM, receives trimming data td from the external device 20, and transmits information st on the operating status based on the protection function adjusted by the trimming data td to the external device 20.

[0013] Here, in a semiconductor module, it is desirable to have as few additional signal terminals as possible due to constraints on module size and the man-hours required for board wiring. The trimming system 1-1 described above is configured to perform bidirectional communication with an external device 20 via a single communication terminal CM, adjust the protection function of the switching element 1a using trimming data td sent from the external device 20, and send information st on the operating state of the adjustment result to the external device 20. This makes it possible to perform trimming based on the characteristics of the switching element using a single communication terminal that minimizes the number of additional signal terminals.

[0014] Next, the trimming system of this embodiment will be described in detail below. Fig. 2 is a diagram showing an example of the overall configuration of the trimming system. The trimming system 1 has a semiconductor module 10a and a tester 2. The semiconductor module 10a has the functions of the semiconductor module 10 in Fig. 1, and the tester 2 has the functions of the external device 20 in Fig. 1.

[0015] Heat is applied to the semiconductor module 10a from a heating plate (heater) 6. Furthermore, a current detector 7 is connected to the output terminals U, V, and W of the semiconductor module 10a instead of a load. The tester 2 sets the heating temperature of the heating plate 6 to a predetermined temperature via line L11 and monitors the current value detected by the current detector 7 via line L12. The method of using the heating plate 6 and the current detector 7 will be described later.

[0016] The semiconductor module 10a includes a control IC 3, high-side semiconductor chips 4a1, 4a2, and 4a3, and low-side semiconductor chips 4b1, 4b2, and 4b3. The control IC 3 has the functions of the control circuit 1b in FIG. 1. The high-side semiconductor chip 4a1 includes a high-side switching element 4U, a high-side diode 5U, and a temperature-detecting diode 6U. The high-side semiconductor chip 4a2 includes a high-side switching element 4V, a high-side diode 5V, and a temperature-detecting diode 6V. The high-side semiconductor chip 4a3 includes a high-side switching element 4W, a high-side diode 5W, and a temperature-detecting diode 6W.

[0017] The low-side semiconductor chip 4b1 includes a low-side switching element 4X, a low-side diode 5X, and a temperature-detecting diode 6X. The low-side semiconductor chip 4b2 includes a low-side switching element 4Y, a low-side diode 5Y, and a temperature-detecting diode 6Y. The low-side semiconductor chip 4b3 includes a low-side switching element 4Z, a low-side diode 5Z, and a temperature-detecting diode 6Z.

[0018] Here, the high-side switching elements 4U, 4V, and 4W and the low-side switching elements 4X, 4Y, and 4Z are voltage-driven switching elements, such as IGBTs (Insulated Gate Bipolar Transistors). Alternatively, the switching elements may be power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Each of the high-side switching elements 4U, 4V, and 4W is provided with a sense emitter that passes a sense current proportional to the current flowing between the collector and emitter. Similarly, each of the low-side switching elements 4X, 4Y, and 4Z is provided with a sense emitter that passes a sense current proportional to the current flowing between the collector and emitter.

[0019] The high-side switching elements 4U, 4V, and 4W are provided between the positive terminal P and the output terminals U, V, and W of each phase, and the low-side switching elements 4X, 4Y, and 4Z are provided between the output terminals U, V, and W of each phase and the negative terminal N.

[0020] High-side diodes 5U, 5V, and 5W are FWDs (Free Wheel Diodes) for commutating the load current. High-side diodes 5U, 5V, and 5W are connected in anti-parallel to high-side switching elements 4U, 4V, and 4W. High-side diodes 5U, 5V, and 5W may be made of wide-gap semiconductors, or may be realized by parasitic diodes when high-side switching elements 4U, 4V, and 4W are MOSFETs. High-side switching elements 4U, 4V, and 4W and high-side diodes 5U, 5V, and 5W form the upper arm (high-voltage side arm (upper phase)).

[0021] Similarly, low-side diodes 5X, 5Y, and 5Z are connected in anti-parallel to low-side switching elements 4X, 4Y, and 4Z and are FWDs for commutating the load current. Low-side diodes 5X, 5Y, and 5Z may be made of wide-gap semiconductors, or may be realized by parasitic diodes when low-side switching elements 4X, 4Y, and 4Z are MOSFETs. Low-side switching elements 4X, 4Y, and 4Z and low-side diodes 5X, 5Y, and 5Z form the lower arm (low-voltage side arm (lower phase)).

[0022] The node connecting the emitter terminal of the upper arm and the collector terminal of the lower arm is connected to the output terminals U, V, and W of each phase. The collector terminal of the upper arm is connected to the positive terminal P. The emitter terminal of the lower arm is connected to the negative terminal N. The upper and lower arms of each phase form a half-bridge circuit.

[0023] The control IC 3 includes a high voltage IC (HVIC) 30a and a low voltage IC (LVIC) 30b. The HVIC 30a includes a drive circuit 30a1, a storage unit 30a2, and a communication unit 30a3.

[0024] The HVIC 30a is connected to the gates of the high-side switching elements 4U, 4V, and 4W and to the sense emitters of each of the high-side switching elements 4U, 4V, and 4W. Furthermore, the HVIC 30a is connected to the anodes of the temperature detection diodes 6U, 6V, and 6W that detect the temperatures of the high-side switching elements 4U, 4V, and 4W, and the cathodes of the temperature detection diodes 6U, 6V, and 6W are connected to GND.

[0025] The drive circuit 30a1 is a high-side drive control unit that drives the high-side switching elements 4U, 4V, and 4W of the upper arm to switch the high-side switching elements 4U, 4V, and 4W on and off. In this case, the drive circuit 30a1 generates gate voltages according to drive signals InU, InV, and InW transmitted from the tester 2 and supplies them to the gates of the high-side switching elements 4U, 4V, and 4W to control the on and off of the high-side switching elements 4U, 4V, and 4W. The communication unit 30a3 communicates bidirectionally with the tester 2 via the communication terminal CM. The memory unit 30a2 stores trimming data transmitted from the tester 2. The memory unit 30a2 may be, for example, a nonvolatile memory or a latch circuit.

[0026] The LVIC 30b includes a drive circuit 30b1, a memory unit 30b2, and a communication unit 30b3. The LVIC 30b is connected to the gates of the low-side switching elements 4X, 4Y, and 4Z and the sense emitters of each of the low-side switching elements 4X, 4Y, and 4Z. The LVIC 30b is also connected to the anodes of the temperature-sensing diodes 6X, 6Y, and 6Z that detect the temperatures of the low-side switching elements 4X, 4Y, and 4Z, and the cathodes of the temperature-sensing diodes 6X, 6Y, and 6Z are connected to GND.

[0027] The drive circuit 30b1 is a low-side drive control unit that drives the low-side switching elements 4X, 4Y, and 4Z of the lower arm to switch the low-side switching elements 4X, 4Y, and 4Z on and off. In this case, the drive circuit 30b1 generates gate voltages according to drive signals InX, InY, and InZ transmitted from the tester 2, and supplies these voltages to the gates of the low-side switching elements 4X, 4Y, and 4Z to control the on and off of the low-side switching elements 4X, 4Y, and 4Z. The communication unit 30b3 communicates bidirectionally with the tester 2 via the communication terminal CM. The memory unit 30b2 stores trimming data transmitted from the tester 2. The memory unit 30b2 may be, for example, a nonvolatile memory or a latch circuit.

[0028] 3 is a diagram showing an example of the configuration of the HVIC and high-side semiconductor chips, illustrating an equivalent circuit of the HVIC 30a and high-side semiconductor chips 4a1, 4a2, and 4a3 (collectively referred to as high-side semiconductor chip 4a) in the semiconductor module 10a.

[0029] The HVIC 10a includes a power regulator 31a, an input buffer 32a, a logic circuit 33a, a drive control circuit 34a, an overheat detection circuit 35a, an overcurrent detection circuit 36a, and a level shift circuit 37a.

[0030] The high-side semiconductor chip 4a includes a main IGBT 41a, a sense IGBT 42a (corresponding to high-side switching elements 4U, 4V, and 4W), and a temperature detection diode 43a (corresponding to temperature detection diodes 6U, 6V, and 6W). The sense IGBT 42a is a current monitoring power switching element that generates a sense current proportional to the current flowing through the main IGBT 41a. Note that the FWD is not shown in the figure.

[0031] The power supply regulator 31a generates an internal power supply voltage VDD of the HVIC 30a from the power supply voltage VCC and supplies the power supply voltage VDD to a predetermined circuit. The input buffer 32a buffers the drive signals InU, InV, and InW transmitted from the tester 2 and transmits the buffered drive signal g1 to the level shift circuit 37a.

[0032] The level shift circuit 37a shifts the level of the drive signal g1 to the high voltage side and outputs it to the drive control circuit 34a. The logic circuit 33a has the functions of the communication unit 30a3 and the memory unit 30a2, and performs bidirectional communication with the tester 2 via the communication terminal CM and stores the received trimming data values.

[0033] 2, generates a drive control signal for turning on / off the IGBT 41a based on the drive signal output from the level shift circuit 37a, and outputs the drive control signal to the gate of the IGBT 41a to switch the IGBT 41a. The drive control circuit 34a controls the drive of the main IGBT 41a using a drive power supply voltage between a high-potential side drive power supply voltage (voltage VB) and a low-potential side drive power supply voltage (voltage VS).

[0034] Meanwhile, the gate of the main IGBT 41a is connected to the gate of the sense IGBT 42a and the output terminal of the drive control circuit 34a, and the collector of the main IGBT 41a is connected to the collector of the sense IGBT 42a and the positive terminal P. The emitter of the main IGBT 41a is connected to the reference potential terminals (terminals on the voltage VS side) of the drive control circuit 34a, the overheat detection circuit 35a, and the overcurrent detection circuit 36a, and is further connected to the cathode of the temperature detection diode 43a.

[0035] The anode of the temperature detection diode 43a is connected to the input terminal of the overheat detection circuit 35a, and the sense emitter of the sense IGBT 42a is connected to the input terminal of the overcurrent detection circuit 36a. The overheat detection circuit 35a sets an overheat reference voltage for detecting whether the temperature state of the main IGBT 41a is in an overheat state based on setting data SWoh included in the trimming data output from the logic circuit 33a. When the overheat detection circuit 35a detects that the main IGBT 41a is in an overheat state based on the temperature detection voltage at the anode of the temperature detection diode 43a and the set overheat reference voltage, it outputs an H-level overheat detection signal OH to the drive control circuit 34a.

[0036] The overcurrent detection circuit 36a sets an overcurrent reference voltage for detecting whether the current state of the main IGBT 41a is an overcurrent state, based on the setting data SWoc included in the trimming data output from the logic circuit 33a. When the overcurrent detection circuit 36a detects that the main IGBT 41a is in an overcurrent state based on the sense current output from the sense emitter of the sense IGBT 42a and the set overcurrent reference voltage, the overcurrent detection circuit 36a outputs an H-level overcurrent detection signal OC to the drive control circuit 34a.

[0037] When the drive control circuit 34a receives the high-level overheat detection signal OH or the high-level overcurrent detection signal OC, it stops outputting the drive control signal and turns off the main IGBT 41a.

[0038] 4 is a diagram showing an example of the configuration of the LVIC and low-side semiconductor chips, illustrating an equivalent circuit of the LVIC 30b and low-side semiconductor chips 4b1, 4b2, and 4b3 (collectively referred to as low-side semiconductor chip 4b) in the semiconductor module 10a.

[0039] The LVIC 30b includes a power regulator 31b, an input buffer 32b, a logic circuit 33b, a drive control circuit 34b, an overheat detection circuit 35b, and an overcurrent detection circuit 36b. The low-side semiconductor chip 4b includes a main IGBT 41b, a sense IGBT 42b (corresponding to the low-side switching elements 4X, 4Y, and 4Z), and a temperature detection diode 43b (corresponding to the temperature detection diodes 6X, 6Y, and 6Z). The sense IGBT 42b is a current monitoring power switching element that generates a sense current proportional to the current flowing through the main IGBT 41b. Note that the FWD is not shown in the figure.

[0040] The power supply regulator 31b generates a power supply voltage VDD inside the LVIC 30b from the power supply voltage VCC and supplies the power supply voltage VDD to a predetermined circuit. The input buffer 32b buffers the drive signals InX, InY, and InZ transmitted from the tester 2 and transmits the buffered drive signal g2 to the drive control circuit 34b. The logic circuit 33b has the functions of a communication unit 30b3 and a memory unit 30b2, and performs bidirectional communication with the tester 2 via the communication terminal CM and stores the received trimming data values.

[0041] The drive control circuit 34b has the function of the drive circuit 30b1 in Figure 2, and generates a drive control signal for turning on / off the IGBT 41b based on the drive signal g2 output from the input buffer 32b, and outputs the drive control signal to the gate of the IGBT 41b to switch the IGBT 41b.

[0042] Meanwhile, the gate of the main IGBT 41b is connected to the gate of the sense IGBT 42b and the output terminal of the drive control circuit 34b, and the collector of the main IGBT 41b is connected to the collector of the sense IGBT 42b. The emitter of the main IGBT 41b is connected to the reference potential terminal of the drive control circuit 34a and PGND (emitter potential on the switching element side: negative terminal N).

[0043] The anode of the temperature detection diode 43b is connected to an input terminal of the overheat detection circuit 35b, and the sense emitter of the sense IGBT 42b is connected to an input terminal of the overcurrent detection circuit 36b. The overheat detection circuit 35b sets an overheat reference voltage for detecting whether the temperature state of the main IGBT 41b is in an overheat state based on setting data SWoh included in the trimming data output from the logic circuit 33b. When the overheat detection circuit 35b detects that the main IGBT 41b is in an overheat state based on the temperature detection voltage at the anode of the temperature detection diode 43b and the set overheat reference voltage, it outputs an H-level overheat detection signal OH to the drive control circuit 34b.

[0044] The overcurrent detection circuit 36b sets an overcurrent reference voltage for detecting whether the current state of the main IGBT 41b is an overcurrent state, based on the setting data SWoc included in the trimming data output from the logic circuit 33b. When the overcurrent detection circuit 36b detects that the main IGBT 41b is in an overcurrent state based on the sense current output from the sense emitter of the sense IGBT 42b and the set overcurrent reference voltage, the overcurrent detection circuit 36b outputs an H-level overcurrent detection signal OC to the drive control circuit 34b.

[0045] When the drive control circuit 34b receives the high-level overheat detection signal OH or the high-level overcurrent detection signal OC, it stops outputting the drive control signal and turns off the main IGBT 41b.

[0046] 5 is a diagram showing an example of the configuration of an overheat detection circuit. Note that hereinafter, the overheat detection circuits 35a and 35b will be collectively referred to as overheat detection circuit 35, and the temperature detection diodes 43a and 43b will be collectively referred to as temperature detection diode 43. Furthermore, the drive control circuits 34a and 34b will be collectively referred to as drive control circuit 34, and the IGBTs 41a and 41b will be collectively referred to as IGBT 41.

[0047] The overheat detection circuit 35 detects an overheat state of the switching element when the semiconductor module 10a is heated by the heating plate 6, which is set to a predetermined temperature by the tester 2. The overheat detection circuit 35 includes a comparator cmp1 and an overheat reference voltage generation circuit 35-1. The overheat reference voltage generation circuit 35-1 includes a resistor R1 (first resistor), a resistor R2 (second resistor), a resistor R3 (third resistor), a switch SW1 (first switch), and a switch SW2 (second switch).

[0048] One end of resistor R1 is connected to a power supply voltage VDD, the other end of resistor R1 is connected to one end of resistor R2, and a node n1 (first node) between the other end of resistor R1 and one end of resistor R2 is connected to a terminal a1 (first terminal) of switch SW1. The other end of resistor R2 is connected to one end of resistor R3, and a node n2 (second node) between the other end of resistor R2 and one end of resistor R3 is connected to a terminal b1 (third terminal) of switch SW2. The other end of resistor R3 is connected to GND.

[0049] The non-inverting input terminal (+) of the comparator cmp1 is connected to the terminal a2 (second terminal) of the switch SW1 and the terminal b2 (fourth terminal) of the switch SW2. The inverting input terminal (-) of the comparator cmp1 is connected to the anode of the temperature detection diode 43. The output terminal of the comparator cmp1 is connected to the input terminal of the drive control circuit 34. A current output from a constant current source (not shown) flows forward through the temperature detection diode 43, and the potential generated across the temperature detection diode 43 at this time is input to the comparator cmp1 as a temperature detection voltage VOH that indicates the temperature state of the IGBT 41.

[0050] The comparator cmp1 compares the temperature detection voltage VOH at the anode of the temperature detection diode 43 with the overheat reference voltage OH-ref. The temperature detection voltage VOH at the anode of the temperature detection diode 43 has a negative temperature characteristic that decreases as the temperature of the IGBT 41 rises. Therefore, when the level of the temperature detection voltage VOH falls below the overheat reference voltage OH-ref, the comparator cmp1 determines that the temperature state of the IGBT 41 is an overheat state and outputs an H-level overheat detection signal OH to the drive control circuit 34.

[0051] Furthermore, when the level of the temperature detection voltage VOH becomes higher than the overheat reference voltage OH-ref, the comparator cmp1 determines that the temperature state of the IGBT 41 is not overheated, and outputs an L-level overheat detection signal OH to the drive control circuit .

[0052] On the other hand, the overheat reference voltage OH-ref is variably set by the setting data SWoh (hereinafter, sometimes referred to as switch setting data) included in the trimming data. For example, if the switch setting data SWoh sets the switch SW1 to on and the switch SW2 to off ((SW1, SW2)=(ON, OFF)), terminals a1 and a2 are connected and terminals b1 and b2 are disconnected, so the overheat reference voltage OH-ref1 (first overheat reference voltage) is calculated by the following formula (1).

[0053] OH-ref1=((R2+R3) / (R1+R2+R3))×VDD...(1) Furthermore, when the switch SW1 is set to OFF and the switch SW2 is set to ON ((SW1, SW2)=(OFF, ON)) by the switch setting data SWoh included in the trimming data, the terminals a1 and a2 are not connected, and the terminals b1 and b2 are connected, so the overheat reference voltage OH-ref2 (second overheat reference voltage) is calculated by the following formula (2) (OH-ref2 <OH-ref1)。

[0054] OH-ref2=(R3 / (R1+R2+R3))×VDD···(2) In the above, the overheating reference voltage is variably set using three resistors R1, R2, and R3 and two switches SW1 and SW2. However, other configurations may be used in which the number of resistors and the number of switches are increased, in which case the overheating reference voltage can be variably set more precisely using trimming data.

[0055] FIG. 6 is a diagram showing the flow of trimming operations when the overheat reference voltage is variably set. [Step S1] Heat is applied to the semiconductor module 10a using a hot plate 6 (or a thermostatic bath, etc.) (for example, heat is applied to a temperature of 175°C, at which overheat protection is required). The heating setting for the hot plate 6 is set by the tester 2.

[0056] [Step S2] With the temperature maintained at 175° C., information on the temperature detection voltage VOH of the temperature detection diode 43 is sent from the control IC 3 to the tester 2 via the communication terminal CM. [Step S3] When the tester 2 receives information about the temperature detection voltage VOH sent from the control IC 3, it sends trimming data including the switch setting data SWoh to the control IC 3 via the communication terminal CM to set the overheat reference voltage OH-ref.

[0057] [Step S4] The tester 2 receives information on the overheat reference voltage OH-ref (overheat reference voltage information) as information on the operating state transmitted from the control IC 3 via the communication terminal CM. [Step S5] By repeating steps S3 and S4, the tester 2 adjusts the overheat reference voltage OH-ref using the switch setting data SWoh until it reaches a predetermined value.

[0058] 7 is a diagram illustrating an example of a trimming operation when variably setting the overheat reference voltage. With the semiconductor module 10a maintained at a temperature of 175°C, the tester 2 acquires from the control IC 3 a temperature detection voltage VOH at a voltage level requiring overheat protection. It is assumed that the initial value of the overheat reference voltage OH-ref at the start of trimming is the minimum voltage value (OH-ref(1)).

[0059] The tester 2 transmits trimming data (switch setting data) to the control IC 3 to gradually increase the overheat reference voltage OH-ref from the minimum voltage value (OH-ref(1)). In this case, the tester 2 repeatedly receives overheat reference voltage information and transmits switch setting data SWoh until the level of the overheat detection signal OH from the output terminal of the comparator cmp1 changes from L level to H level, and the control IC 3 performs the process of increasing the overheat reference voltage OH-ref (i.e., the process of setting the switch ON / OFF).

[0060] When performing this processing, for example, in the transition from switch setting data SWoh(n-1) to switch setting data SWoh(n), the overheat detection signal OH is at L level when the overheat reference voltage is OH-ref(n-1) set by the switch setting data SWoh(n-1), and the overheat detection signal OH goes to H level when the overheat reference voltage is OH-ref(n) set by the switch setting data SWoh(n). In this case, overheat detection of the temperature detection voltage VOH becomes possible when the overheat reference voltage OH-ref(n) exceeds the overheat reference voltage OH-ref(n-1).

[0061] Therefore, since the overheat reference voltage OH-ref(n) can be said to be the threshold level at which overheat detection is possible and which is located closest to the temperature detection voltage VOH at which overheat protection is required, a switch setting to the overheat reference voltage OH-ref(n) is performed in the overheat detection circuit 35. By performing such adjustment, it is possible to set the optimum overheat reference voltage OH-ref at which overheat protection is activated for the temperature detection voltage VOH.

[0062] 8 is a diagram showing an example of the configuration of the overcurrent detection circuit. Note that, hereinafter, overcurrent detection circuits 36a and 36b will be collectively referred to as overcurrent detection circuit 36, and sense IGBTs 42a and 42b will be collectively referred to as sense IGBT 42.

[0063] The overcurrent detection circuit 36 ​​detects an overcurrent state of the IGBT 41 while the tester 2 is monitoring whether a predetermined current is flowing through the IGBT 41 via the current detector 7 connected to the IGBT 41 .

[0064] The overcurrent detection circuit 36 ​​includes a comparator cmp2 (comparator), a sense resistor Rs, and an overcurrent reference voltage generation circuit 36-1. The overcurrent reference voltage generation circuit 36-1 includes a resistor R11 (first resistor), a resistor R12 (second resistor), a resistor R13 (third resistor), a sense resistor Rs, and a switch SW11 (first switch) and a switch SW12 (second switch). The sense resistor Rs may be disposed outside the overcurrent detection circuit 36.

[0065] One end of resistor R11 is connected to a power supply voltage VDD, the other end of resistor R11 is connected to one end of resistor R12, and a node n1 (first node) between the other end of resistor R11 and one end of resistor R12 is connected to a terminal a11 (first terminal) of switch SW11. The other end of resistor R12 is connected to one end of resistor R13, and a node n2 (second node) between the other end of resistor R12 and one end of resistor R13 is connected to a terminal b11 (third terminal) of switch SW12. The other end of resistor R13 is connected to GND.

[0066] An inverting input terminal (-) of the comparator cmp2 is connected to a terminal a12 (second terminal) of the switch SW11 and a terminal b12 (fourth terminal) of the switch SW12. A non-inverting input terminal (+) of the comparator cmp2 is connected to the sense emitter of the sense IGBT 42 and one end of the sense resistor Rs, and the other end of the sense resistor Rs is connected to GND.

[0067] The sense current Is output from the sense emitter of the sense IGBT 42 flows through the sense resistor Rs and is converted into a current detection voltage VOC, which is input to the non-inverting input terminal (+) of the comparator cmp2.

[0068] The comparator cmp2 compares the current detection voltage VOC with the overcurrent reference voltage OC-ref. When the level of the current detection voltage VOC becomes equal to or greater than the overcurrent reference voltage OC-ref, the comparator cmp2 determines that the current state of the IGBT 41 is an overcurrent state and outputs an H-level overcurrent detection signal OC to the drive control circuit 34.

[0069] Furthermore, when the level of the current detection voltage VOC becomes lower than the overcurrent reference voltage OC-ref, the comparator cmp2 determines that the current state of the IGBT 41 is a non-overcurrent state and outputs an L-level overcurrent detection signal OC to the drive control circuit .

[0070] On the other hand, the overcurrent reference voltage OH-ref is variably set by the switch setting data SWoc included in the trimming data. For example, if the switch setting data SWoc sets the switch SW11 to on and the switch SW12 to off ((SW11, SW12)=(ON, OFF)), the terminals a11 and a12 are connected and the terminals b11 and b12 are disconnected, and the overcurrent reference voltage OC-ref1 (first overcurrent reference voltage) is calculated by the following equation (3).

[0071] OC-ref1=((R12+R13) / (R11+R12+R13))×VDD...(3) Furthermore, when the switch SW11 is set to OFF and the switch SW12 is set to ON by the switch setting data SWoc ((SW11, SW12)=(OFF, ON)), the terminals a11 and a12 are not connected, and the terminals b11 and b12 are connected, so the overcurrent reference voltage OC-ref2 (second overcurrent reference voltage) is calculated from the following equation (4): <OC-ref1)。

[0072] OC-ref2=(R13 / (R11+R12+R13))×VDD...(4) In the above, the overcurrent reference voltage is variably set using three resistors R11, R12, and R13 and two switches SW11 and SW12, but the number of resistors and switches may be increased in addition to this configuration, in which case the overcurrent reference voltage can be variably set more precisely using trimming data.

[0073] FIG. 9 is a diagram showing the flow of trimming operations when the overcurrent reference voltage is variably set. [Step S11] The tester 2 switches on and off the IGBT 41 of the semiconductor module 10a so that the current monitored by the current detector 7 reaches, for example, 200 A, which requires overcurrent protection.

[0074] [Step S12] Information about the current detection voltage VOC, which is obtained by converting the sense current output from the sense IGBT 42 into a voltage using the sense resistor Rs, is sent from the control IC 3 to the tester 2 via the communication terminal CM.

[0075] [Step S13] When the tester 2 receives the information on the current detection voltage VOC sent from the control IC 3, it sends trimming data including the switch setting data SWoc to the control IC 3 via the communication terminal CM to set the overcurrent reference voltage OC-ref.

[0076] [Step S14] The tester 2 receives information on the overcurrent reference voltage OC-ref (overcurrent reference voltage information) as information on the operating state transmitted from the control IC 3 via the communication terminal CM.

[0077] [Step S15] By repeating steps S13 and S14, the tester 2 adjusts the overcurrent reference voltage OC-ref using the switch setting data SWoc until it reaches a predetermined value.

[0078] 10 is a diagram illustrating an example of trimming operation when variably setting the overcurrent reference voltage. While maintaining 200 A detected by the current detector 7, the tester 2 acquires from the control IC 3 the current detection voltage VOC, which is at a voltage level requiring overcurrent protection. The initial value of the overcurrent reference voltage OC-ref at the start of trimming is set to the minimum voltage value (OC-ref(1)).

[0079] The tester 2 transmits trimming data to the control IC 3 to gradually increase the overcurrent reference voltage OC-ref from the minimum voltage value (OC-ref(1)). In this case, the tester 2 repeatedly receives overcurrent reference voltage information and transmits switch setting data SWoc until the level of the overcurrent detection signal OC from the output terminal of the comparator cmp2 changes from H level to L level, and the control IC 3 performs the process of increasing the overcurrent reference voltage OC-ref (i.e., the process of setting the switch ON / OFF).

[0080] When such processing is performed, for example, in the transition from switch setting data SWoc(n-1) to switch setting data SWoc(n), if the overcurrent detection signal OC is at H level when the overcurrent reference voltage OC-ref(n-1) set by the switch setting data SWoc(n-1) is reached, and if the overcurrent detection signal OC becomes L level when the overcurrent reference voltage OC-ref(n) is reached when the switch setting data SWoc(n) is reached, overcurrent detection of the current detection voltage VOC becomes impossible when the overcurrent reference voltage OC-ref(n) exceeds the overcurrent reference voltage OC-ref(n-1).

[0081] Therefore, since the overcurrent reference voltage OC-ref(n-1) can be said to be the threshold level at which overcurrent detection is possible and which is located closest to the current detection voltage VOC at which overcurrent protection is required, a switch setting to obtain the overcurrent reference voltage OC-ref(n-1) is performed in the overcurrent detection circuit 36. By performing such adjustment, it is possible to set the optimal overcurrent reference voltage OC-ref at which overcurrent protection is applied for the current detection voltage VOC.

[0082] 11 is a diagram showing an example of the configuration of a logic circuit. Note that logic circuits 33a and 33b are collectively referred to as logic circuit 33. Logic circuit 33 includes a data receiving circuit 131 and a data transmitting circuit 132. Data receiving circuit 131 includes a counter circuit 131a, a latch circuit 131b (first latch circuit), and a decoder 131c. Data transmitting circuit 132 includes a selection circuit 132a, an AD converter 132b, a latch circuit 132c (second latch circuit), and a transmitting circuit 132d.

[0083] The counter circuit 131a detects the falling edge of the trimming data transmitted from the tester 2 via the communication terminal CM and measures the time t from the falling edge of the trimming data. Then, the counter circuit 131a outputs a pulse signal COUT after the time t has elapsed since the falling edge of the trimming data. The latch circuit 131b latches the trimming data transmitted from the tester 2 via the communication terminal CM with the pulse signal COUT.

[0084] The decoder 131c decodes the multiple output data Ms from the latch circuit 131b, generates switch setting data SW for turning on and off the switches in the element circuits to be trimmed (the overheating detection circuit 35 and the overcurrent detection circuit 36), and transmits the switch setting data SW to the overheating detection circuit 35 and the overcurrent detection circuit 36.

[0085] The decoder 131c decodes the output data Ms from the latch circuit 131b to generate address data Sad of the element circuit to be trimmed. The decoder 131c also generates a mode signal S indicating either the mode of receiving data from the tester 2 or the mode of transmitting data to the tester 2.

[0086] For example, if the mode signal S is "0", it indicates the reception mode, and if the mode signal S is "1", it indicates the transmission mode. When the data reception circuit 131 receives trimming data transmitted from the tester 2, the decoder 131c outputs the mode signal S (=0) and switches to the reception mode. When the data reception by the data reception circuit 131 is completed and the data transmission circuit 132 transmits data to the tester 2, the decoder 131c outputs the mode signal S (=1) and switches to the transmission mode.

[0087] When the data transmission circuit 132 enters the transmission mode, the selection circuit 132a selects the information to be output from among the operating state information of the temperature detection voltage VOH, the overheat reference voltage OH-ref, the current detection voltage VOC, and the overcurrent reference voltage OC-ref, based on the address data Sad output from the decoder 131c.

[0088] The AD converter 132b converts the analog signal information output from the selection circuit 132a into a digital signal by A / D conversion and outputs it. The latch circuit 132c latches the digital signal at a predetermined clock and outputs it. The transmission circuit 132d transmits the output signal from the latch circuit 132c to the tester 2 via the communication terminal CM. After transmitting the data, the transmission circuit 132d generates an END signal and transmits it to the decoder 131c. Upon receiving the END signal, the decoder 131c recognizes the end of data transmission and switches to reception mode.

[0089] FIG. 12 is a diagram showing an example of a timing chart of output data from the counter circuit in the data receiving circuit to the latch circuit. [Period cy1] The counter circuit 131a detects the falling edge e1 of the trimming data and measures the time t from the falling edge e1. After measuring the time t, the counter circuit 131a outputs a pulse signal COUT(1) to the latch circuit 131b. The latch circuit 131b latches the H level of the trimming data at the rising edge of the pulse signal COUT(1), and outputs data d1 that transitions from L level to H level at the rising edge of the pulse signal COUT(1).

[0090] [Period cy2] The counter circuit 131a detects the falling edge e2 of the trimming data and measures the time t from the falling edge e2. After measuring the time t, the counter circuit 131a outputs a pulse signal COUT(2) to the latch circuit 131b. The latch circuit 131b latches the L level of the trimming data at the rising edge of the pulse signal COUT(2) and outputs data d2 that remains at the L level.

[0091] [Period cy3] The counter circuit 131a detects the falling edge e3 of the trimming data and measures the time t from the falling edge e3. After measuring the time t, the counter circuit 131a outputs a pulse signal COUT(3) to the latch circuit 131b. The latch circuit 131b latches the H level of the trimming data at the rising edge of the pulse signal COUT(3), and outputs data d3 that transitions from L level to H level at the rising edge of the pulse signal COUT(3).

[0092] The above operation is repeated for the number of received bits of trimming data. If the falling edge of the trimming data is not detected for a certain period of time, the data receiving circuit 131 determines that communication has ended.

[0093] Fig. 13 is a diagram showing an example of bit allocation of trimming data. The trimming data includes address data and switch setting data, and Fig. 13 shows an example of bit allocation of address data and switch setting data on the low side.

[0094] The number of bits required for the trimming data is 1 bit to identify the high side (upper phase) / low side (lower phase), 2 bits to identify the X / Y / Z phase, and 1 bit to identify the overheat detection circuit 35 and the overcurrent detection circuit 36.

[0095] Furthermore, one bit is required to distinguish between the temperature detection voltage VOH / overheat reference voltage OH-ref for the overheat detection circuit 35 and the current detection voltage VOC / overcurrent reference voltage OC-ref for the overcurrent detection circuit 36, and two bits are required to set the two switches. Therefore, the total number of bits required for trimming data in this configuration is seven bits.

[0096] As an example of the bit allocation setting, the most significant 7th bit is used as the bit to identify high side / low side, with "0" representing low side and "1" representing high side. The sixth and fifth bits are used to identify the X / Y / Z phase, with "00" representing the X phase, "01" representing the Y phase, and "10" representing the Z phase. The fourth bit is used to identify the overheat detection circuit 35 and the overcurrent detection circuit 36, with "0" representing the overheat detection circuit 35 and "1" representing the overcurrent detection circuit 36.

[0097] The third bit is used to distinguish between the temperature detection voltage VOH / overheat reference voltage OH-ref for the overheat detection circuit 35 and the current detection voltage VOC / overcurrent reference voltage OC-ref for the overcurrent detection circuit 36. "0" indicates the temperature detection voltage VOH or the current detection voltage VOC, and "1" indicates the overheat reference voltage OH-ref or the overcurrent reference voltage OC-ref.

[0098] That is, when the fourth bit is "0", it is the overheat detection circuit 35, so if the third bit is "0", the temperature detection voltage VOH for the overheat detection circuit 35 is indicated by "00" for the fourth and third bits. Also, if the third bit is "1", the overheat reference voltage OH-ref for the overheat detection circuit 35 is indicated by "01" for the fourth and third bits.

[0099] Similarly, when the fourth bit is "1", it is the overcurrent detection circuit 36, so if the third bit is "0", the current detection voltage VOC for the overcurrent detection circuit 36 ​​is indicated by the fourth and third bits being "10". Also, if the third bit is "1", the overcurrent reference voltage OC-ref for the overcurrent detection circuit 36 ​​is indicated by the fourth and third bits being "11".

[0100] Meanwhile, the second bit is used to identify the switch setting of switch SW1 or switch SW11, and the first bit is used to identify the switch setting of switch SW2 or switch SW12. In the example of Figure 13, "01" means switch SW1 = OFF (or switch SW11 = OFF) and switch SW2 = ON (or switch SW12 = ON). Note that when the second bit and the first bit are "00", no switch setting is performed.

[0101] As an example, when the trimming data is (0, 0, 0, 1, 1, 0, 1) (the most significant bit is on the left and the least significant bit is on the right), the low side (0), X-phase low-side switching element 4X (00), overcurrent detection circuit (1), overcurrent reference voltage OC-ref (1), switch SW11 = OFF (0), and switch SW12 = ON (1).

[0102] Figure 14 shows an example of the configuration of an LVIC equipped with a mechanism for adjusting the driving capacity of switching elements. The LVIC 30b-1 includes a driving capacity switching circuit 38 in addition to the circuit elements of the LVIC 30b shown in Figure 4. Note that the HVIC 30a can also be equipped with a similar driving capacity switching circuit 38, so the configuration of the LVIC 30b-1 will be described below.

[0103] The drive capability switching circuit 38 receives the temperature detection signals TL / TM / TH output from the overheat detection circuit 35b and the current detection signal ILOW output from the overcurrent detection circuit 36b. Based on the temperature detection signals TL / TM / TH or the current detection signal ILOW, the drive capability switching circuit 38 outputs a drive capability switching signal VREF to the drive control circuit 34b to switch the drive capability of the low-side switching element IGBT 41b. The drive control circuit 34b changes the voltage level of the drive control signal according to the voltage level of the drive capability switching signal VREF, thereby switching the drive capability of the IGBT 41b. The rest of the configuration is the same as in FIG. 4, so a description thereof will be omitted.

[0104] 15 is a diagram showing the correspondence between input and output of the drive capability switching circuit. In item #1, when the temperature T of IGBT 41b is equal to or higher than temperature T2, the overheat detection circuit 35b outputs a temperature detection signal TH. Upon receiving the temperature detection signal TH, the drive capability switching circuit 38 outputs a drive capability switching signal VREF of voltage level V1 to the drive control circuit 34.

[0105] In item #2, when the temperature T of the IGBT 41b is less than the temperature T2 but equal to or greater than the temperature T1, the overheat detection circuit 35b outputs a temperature detection signal TM. Upon receiving the temperature detection signal TM, the drive capability switching circuit 38 outputs a drive capability switching signal VREF of a voltage level V2 to the drive control circuit 34.

[0106] In item #3, when the temperature T of the IGBT41b is less than the temperature T1, a temperature detection signal TL is output from the overheat detection circuit 35b. Also, when a current I2 flows through the IGBT41b, a current detection signal ILOW of L level is output from the overcurrent detection circuit 36b. When receiving the temperature detection signal TL and the current detection signal ILOW of L level, the drive ability switching circuit 38 outputs a drive ability switching signal VREF of voltage level V3 to the drive control circuit 34.

[0107] In item #4, when the temperature T of the IGBT41b is less than the temperature T1, a temperature detection signal TL is output from the overheat detection circuit 35b. Also, when a current I1 (<I2) flows through the IGBT41b, a current detection signal ILOW of H level is output from the overcurrent detection circuit 36b. When receiving the temperature detection signal TL and the current detection signal ILOW of H level, the drive ability switching circuit 38 outputs a drive ability switching signal VREF of voltage level V4 to the drive control circuit 34.

[0108] Note that the protection level (degree of danger) is the highest for item #1 and the lowest for item #4. Also, the relationship of the voltage levels V1, ···, V4 is V1 < V2 < V3 < V4. Therefore, as the protection level is higher, the voltage level of the drive ability switching signal VREF is made lower to reduce the drive current at the turn-on of the IGBT41b, and as the protection level is lower, the voltage level of the drive ability switching signal VREF is made higher to increase the drive current at the turn-on of the IGBT41b, thereby performing the switching of the drive ability.

[0109] FIG. 16 is a diagram showing an example of the configuration of the drive control circuit. The drive control circuit 34 includes PMOS transistors mp1, mp2, NMOS transistors mn1, mn2, mn3, an operational amplifier (differential amplifier) op1, and a resistor R10.

[0110] A power supply voltage VCC is applied to the sources of the PMOS transistors mp1 and mp2. The gate of the PMOS transistor mp1 is connected to the gate of the PMOS transistor mp2, the drain of the PMOS transistor mp1, and the drain of the NMOS transistor mn1. The drain of the PMOS transistor mp2 is connected to the drain of the NMOS transistor mn3 and the gate of the IGBT 41b.

[0111] The drive capacity switching signal VREF is input to the non-inverting input terminal (+) of the operational amplifier op1. The inverting input terminal (-) of the operational amplifier op1 is connected to the source of the NMOS transistor mn1 and one end of the resistor R10. The output terminal of the operational amplifier op1 is connected to the gate of the NMOS transistor mn1 and the drain of the NMOS transistor mn2.

[0112] A drive signal g2 output from the input buffer 32b is input to the gates of the NMOS transistors mn2 and mn3. The source of the NMOS transistor mn2 is connected to the other end of the resistor R10, the source of the NMOS transistor mn3, and GND.

[0113] Here, the PMOS transistor mp1 and the PMOS transistor mp2 function as a current mirror circuit that outputs a current i1×a, which is obtained by amplifying the current i1 supplied to the PMOS transistor mp1 by a factor a, as a drive current (drive control signal) to the gate of the IGBT 41b. The NMOS transistor mn1, the resistor R10, and the operational amplifier op1 form a current control circuit that supplies a current corresponding to the drive capability switching signal VREF to the current mirror circuit formed by the PMOS transistor mp1 and the PMOS transistor mp2.

[0114] When the drive signal g2 output from the input buffer 32b is at L level, the operational amplifier op1 controls the NMOS transistor mn1 so that the potential between the NMOS transistor mn1 and the resistor R10 becomes the potential of the drive capability switching signal VREF. As a result, when the drive signal g2 is at L level, the resistor R10 causes a current i1, whose value is calculated by dividing the drive capability switching signal VREF by the resistance value of the resistor R10, to flow through the path of the PMOS transistor mp1, the NMOS transistor mn1, and the resistor R10.

[0115] The NMOS transistor mn3 is turned off when the drive signal g2 is at L level. At this time, the PMOS transistor mp2 outputs a drive current to the gate of the IGBT 41b to turn on the IGBT 41b. Furthermore, when the drive signal g2 is at H level, the NMOS transistor mn3 is turned on, connecting the gate of the IGBT 41b to GND and turning off the IGBT 41b.

[0116] The NMOS transistor mn2 is turned off when the drive signal g2 is at L level. On the other hand, the NMOS transistor mn2 is turned on when the drive signal g2 is at H level, and at this time, the NMOS transistor mn1 is turned off so that no current flows through the PMOS transistor mp1 (current i1=0).

[0117] The drive capacity switching signal VREF is input to the non-inverting input terminal (+) of the operational amplifier op1, and as the voltage level of the drive capacity switching signal VREF increases, the level of the output signal of the operational amplifier op1 also increases. When the output signal level of the operational amplifier op1 increases, the amount of current drawn by the NMOS transistor mn1 when it turns on also increases, and therefore the current flowing between the source and collector of the PMOS transistor mp1 increases.

[0118] Furthermore, since the PMOS transistors mp1 and mp2 have a differential pair current mirror configuration, when the current flowing between the source and collector of the PMOS transistor mp1 increases, the current flowing between the source and collector of the PMOS transistor mp2 also increases. Therefore, when the voltage level of the drive capability switching signal VREF increases, the drive current when the IGBT 41b is turned on increases.

[0119] On the other hand, when the voltage level of the drive capacity switching signal VREF decreases, the level of the output signal of the operational amplifier op1 also decreases. When the level of the output signal of the operational amplifier op1 decreases, the amount of current drawn by the NMOS transistor mn1 when it turns on also decreases. As a result, the current flowing between the source and collector of the PMOS transistor mp1 decreases, and the current flowing between the source and collector of the PMOS transistor mp2 also decreases.

[0120] Therefore, when the voltage level of the drive capability switching signal VREF decreases, the drive current when the IGBT 41b is turned on decreases. With this configuration, the magnitude of the drive current that charges the gate of the IGBT 41b can be controlled according to the voltage level of the drive capability switching signal VREF.

[0121] 17 is a diagram showing an example of the wiring of an HVIC and the wiring of an LVIC connected to a communication terminal. A connection part 8a (first connection part) is provided on the wiring L1 (first wiring) on ​​the HVIC 30a side connected to the communication terminal CM, and a connection part 8b (second connection part) is provided on the wiring L2 (second wiring) on ​​the LVIC 30b side connected to the communication terminal CM, and the connection parts 8a and 8b are insulated (unconnected). The connection parts 8a and 8b are, for example, lands made of conductive metal foil.

[0122] If the HVIC 30a and the LVIC 30b are always connected to the communication terminal CM by a common wiring, the high voltage on the HVIC 30a side may be applied to the LVIC 30b side during operation of the semiconductor module 10a, potentially destroying the LVIC 30b.

[0123] Therefore, when communication is performed between the tester 2 and the control IC 3 via the communication terminal CM, the probe pr of the tester 2 is used to short-circuit the connection portion 8a and the connection portion 8b, thereby performing trimming.

[0124] By using such a wiring configuration, when communication is performed between the tester 2 and the control IC 3 via the communication terminal CM, the connection parts 8a and 8b can be short-circuited, and when the semiconductor module 10a is in operation and communication is not performed between the tester 2 and the control IC 3, the connection parts 8a and 8b can be insulated.

[0125] Therefore, during operation of the semiconductor module 10a, the high voltage on the HVIC 30a side is not applied to the LVIC 30b side, preventing damage to the LVIC 30b. Furthermore, it is possible to easily switch between short-circuiting and isolation between the wiring L1 on the HVIC 30a side and the wiring L2 on the LVIC 30b side without increasing the number of communication terminals CM. Note that the connections 8a and 8b may be short-circuited using any conductive component other than the probe pr of the tester 2.

[0126] Next, modifications of this embodiment will be described with reference to Figures 18 and 19. Figure 18 shows the configuration of a first modification of the trimming system. The first modification uses the alarm function provided in the HVIC and LVIC to perform trimming of one-way communication at the communication terminal CM.

[0127] The HVIC 30a-1 includes an alarm section (ALM section) 30a4, which transmits an alarm signal HALM to the tester 2 via a terminal other than the communication terminal CM when the temperature state of the high-side switching elements 4U, 4V, and 4W reaches an overheat state or when the current state of the high-side switching elements 4U, 4V, and 4W reaches an overcurrent state. When the tester 2 receives the alarm signal HALM, it transmits trimming data to the trimming element circuits (the overheat detection circuit 35a and the overcurrent detection circuit 36a) of the HVIC 30a-1 via the communication terminal CM, and changes the setting of the overheat reference voltage or the overcurrent reference voltage until the output of the alarm signal HALM stops.

[0128] Similarly, the LVIC 30b-1 includes an alarm unit (ALM unit) 30b4, which transmits an alarm signal LALM to the tester 2 via a terminal other than the communication terminal CM when the temperature of the low-side switching elements 4X, 4Y, and 4Z becomes an overheat state or when the current of the low-side switching elements 4X, 4Y, and 4Z becomes an overcurrent state. When the tester 2 receives the alarm signal LALM, it transmits trimming data to the trimming element circuits (the overheat detection circuit 35b and the overcurrent detection circuit 36b) of the LVIC 30b-1 via the communication terminal CM, and changes the setting of the overheat reference voltage or the overcurrent reference voltage until the output of the alarm signal LALM stops.

[0129] With this configuration, the tester 2 can recognize the state of the control IC 3 from the alarm signals HALM and LALM, allowing trimming to be performed through one-way communication from the tester 2 to the control IC 3. The tester 2 identifies the trimming element circuits based on the pulse width and level of the alarm signals HALM / LALM.

[0130] 19 is a diagram showing the configuration of a second modified example of the trimming system. The second modified example monitors the signal level at the land of the printed circuit board, thereby performing trimming of one-way communication at the communication terminal CM.

[0131] When the semiconductor module 10a is in an open sample state (without a module lid), the signal levels of the temperature detection voltage and overheat reference voltage in the overheat detection circuit 35, the current detection voltage and overcurrent reference voltage in the overcurrent detection circuit 36, and the output level of the alarm signal can be monitored at the lands on the printed circuit board. In this case, the signal levels are monitored by contacting the probe pr of the tester 2 with the lands. In the example of FIG. 19, the probe pr is connected to the land 9, and the sense current flowing through the sense emitter of the high-side switching element 4U is monitored.

[0132] With this configuration, the tester 2 can recognize the state of the control IC 3 through the probe pr, and therefore trimming can be performed by one-way communication from the tester 2 to the control IC 3.

[0133] Although the embodiments have been described above, the configuration of each part shown in the embodiments can be replaced with other parts having similar functions. Also, any other components or processes may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0134] 1-1 Trimming system 10 Semiconductor Module 20 External device 1a Switching element 1b Control circuit 1b1 Drive control circuit 1b2 protection circuit 1b3 Communication circuit CM communication terminal td trimming data st Operation status information

Claims

1. an external device that outputs trimming data according to the operating state of the object to be trimmed; a semiconductor module including: a switching element; a drive control circuit that outputs a drive control signal to control switching of the switching element; a protection circuit that adjusts a protection function of the switching element based on the trimming data; and a control circuit including a communication circuit that receives the trimming data from the external device via a single communication terminal and transmits information on the operating state to the external device; A trimming system having

2. the protection circuit includes an overheat detection circuit and an overcurrent detection circuit included in the trimming target; the overheat detection circuit detects an overheat state of the switching element when the semiconductor module is heated to a predetermined temperature; the overcurrent detection circuit detects an overcurrent state of the switching element while monitoring whether a predetermined current is flowing through the switching element; The trimming data includes address data for specifying the trimming target and setting data for adjusting the protection function. The trimming system of claim 1 .

3. The overheat detection circuit a comparator that compares a temperature detection voltage that indicates the temperature state of the switching element, which is input to an inverting input terminal, with an overheat reference voltage that is input to a non-inverting input terminal, and outputs an overheat detection signal of a high potential level that indicates that the switching element is in an overheat state when the temperature detection voltage is equal to or lower than the overheat reference voltage; an overheat reference voltage generating circuit that generates the overheat reference voltage; The overheat reference voltage generating circuit includes: a plurality of resistors and a plurality of switches, the overheat reference voltage being generated by resistively dividing a power supply voltage by the plurality of resistors based on the switch states of the plurality of switches set to on or off by the setting data, and the overheat reference voltage for protecting the switching element from overheating when the predetermined temperature is given is set; The trimming system of claim 2 .

4. The overheat reference voltage generating circuit includes: a first resistor, a second resistor, a third resistor, a first switch having a first terminal and a second terminal, and a second switch having a third terminal and a fourth terminal; one end of the first resistor is connected to the power supply voltage, the other end of the first resistor and one end of the second resistor are connected to a first node, the other end of the second resistor and one end of the third resistor are connected to a second node, and the other end of the third resistor is grounded; the first terminal is connected to the first node, the third terminal is connected to the second node, and the second terminal and the fourth terminal are connected to the non-inverting input terminal of the comparator; generating a first overheat reference voltage when the first switch is set to ON and the second switch is set to OFF based on the setting data; generating a second overheat reference voltage that is smaller than the first overheat reference voltage when the first switch is set to be off and the second switch is set to be on based on the setting data; The trimming system of claim 3.

5. The overcurrent detection circuit a comparator that compares a current detection voltage that indicates a current state of the switching element and is input to a non-inverting input terminal with an overcurrent reference voltage that is input to an inverting input terminal, and outputs an overcurrent detection signal of a high potential level that indicates that the switching element is in an overcurrent state when the current detection voltage is equal to or greater than the overcurrent reference voltage; an overcurrent reference voltage generating circuit that generates the overcurrent reference voltage; The overcurrent reference voltage generating circuit includes: a plurality of resistors and a plurality of switches, the overcurrent reference voltage being generated by resistively dividing a power supply voltage using the plurality of resistors based on the switch states of the plurality of switches set to on or off by the setting data, and the overcurrent reference voltage for protecting the switching element from overcurrent when the predetermined current is flowing is set; The trimming system of claim 2 .

6. The overcurrent reference voltage generating circuit includes: a first resistor, a second resistor, a third resistor, a first switch having a first terminal and a second terminal, and a second switch having a third terminal and a fourth terminal; one end of the first resistor is connected to the power supply voltage, the other end of the first resistor and one end of the second resistor are connected to a first node, the other end of the second resistor and one end of the third resistor are connected to a second node, and the other end of the third resistor is grounded; the first terminal is connected to the first node, the third terminal is connected to the second node, and the second terminal and the fourth terminal are connected to the inverting input terminal of the comparator; generating a first overcurrent reference voltage when the first switch is set to ON and the second switch is set to OFF based on the setting data; generating a second overcurrent reference voltage that is smaller than the first overcurrent reference voltage when the first switch is set to be off and the second switch is set to be on based on the setting data; The trimming system of claim 5.

7. the control circuit further includes a drive capacity switching circuit that adjusts the drive capacity of the switching element; the overheat detection circuit outputs a temperature detection signal corresponding to the temperature state of the switching element; the overcurrent detection circuit outputs a current detection signal according to a current state of the switching element; the drive capability switching circuit generates drive capability switching signals having different voltage levels based on the temperature detection signal and the current detection signal, and outputs the generated drive capability switching signals to the drive control circuit; the drive control circuit outputs the drive control signal of a drive current that varies depending on the voltage level of the drive capability switching signal to the gate of the switching element; The trimming system of claim 2 .

8. The communication circuit a data receiving circuit including: a counter circuit that detects a falling edge of the trimming data received via the communication terminal and outputs a pulse signal a predetermined time after the falling edge of the trimming data; a first latch circuit that latches the trimming data with the pulse signal; and a decoder that decodes a plurality of output data from the first latch circuit and outputs the address data and the setting data; a data transmission circuit including a selection circuit that selects the information on the operating state based on the address data, an AD converter that converts an analog signal of the information on the operating state selected and output by the selection circuit into a digital signal, a second latch circuit that latches the digital signal, and a transmission circuit that transmits an output signal from the second latch circuit to the external device via the communication terminal, The trimming system of claim 2 .

9. The control circuit a high-side control circuit for controlling the high-side switching element and a low-side control circuit for controlling the low-side switching element, a first connection portion is provided on a first wiring through which the communication terminal is connected to the communication circuit on the high side included in the high side control circuit, and a second connection portion is provided on a second wiring through which the communication terminal is connected to the communication circuit on the low side included in the low side control circuit, the first connection portion and the second connection portion are short-circuited when the two-way communication is performed, and are in an insulated state during operation when the two-way communication is not performed. The trimming system of claim 1 .

10. A switching element; a single communication terminal; a control circuit including: a drive control circuit that outputs a drive control signal to control the switching of the switching element; a protection circuit that adjusts a protection function of the switching element based on trimming data output from an external device in accordance with an operating state of an object to be trimmed; and a communication circuit that receives the trimming data from the external device via the communication terminal and transmits information on the operating state to the external device; A semiconductor module having:

11. the protection circuit includes an overheat detection circuit and an overcurrent detection circuit included in the trimming target, the overheat detection circuit detects an overheat state of the switching element when the semiconductor module is heated to a predetermined temperature; the overcurrent detection circuit detects an overcurrent state of the switching element while monitoring whether a predetermined current is flowing through the switching element; The trimming data includes address data for specifying the trimming target and setting data for adjusting the protection function. The semiconductor module according to claim 10.

12. The overheat detection circuit a comparator that compares a temperature detection voltage that indicates the temperature state of the switching element, which is input to an inverting input terminal, with an overheat reference voltage that is input to a non-inverting input terminal, and outputs an overheat detection signal of a high potential level that indicates that the switching element is in an overheat state when the temperature detection voltage is equal to or lower than the overheat reference voltage; an overheat reference voltage generating circuit that generates the overheat reference voltage; The overheat reference voltage generating circuit includes: a plurality of resistors and a plurality of switches, the overheat reference voltage being generated by resistively dividing a power supply voltage by the plurality of resistors based on the switch states of the plurality of switches set to on or off by the setting data, and the overheat reference voltage for protecting the switching element from overheating when the predetermined temperature is given is set; The semiconductor module according to claim 11.

13. The overheat reference voltage generating circuit includes: a first resistor, a second resistor, a third resistor, a first switch having a first terminal and a second terminal, and a second switch having a third terminal and a fourth terminal; one end of the first resistor is connected to the power supply voltage, the other end of the first resistor and one end of the second resistor are connected to a first node, the other end of the second resistor and one end of the third resistor are connected to a second node, and the other end of the third resistor is grounded; the first terminal is connected to the first node, the third terminal is connected to the second node, and the second terminal and the fourth terminal are connected to the non-inverting input terminal of the comparator; generating a first overheat reference voltage when the first switch is set to ON and the second switch is set to OFF based on the setting data; generating a second overheat reference voltage that is smaller than the first overheat reference voltage when the first switch is set to be off and the second switch is set to be on based on the setting data; The semiconductor module according to claim 12.

14. The overcurrent detection circuit a comparator that compares a current detection voltage that indicates a current state of the switching element and is input to a non-inverting input terminal with an overcurrent reference voltage that is input to an inverting input terminal, and outputs an overcurrent detection signal of a high potential level that indicates that the switching element is in an overcurrent state when the current detection voltage is equal to or greater than the overcurrent reference voltage; an overcurrent reference voltage generating circuit that generates the overcurrent reference voltage; The overcurrent reference voltage generating circuit includes: a plurality of resistors and a plurality of switches, the overcurrent reference voltage being generated by resistively dividing a power supply voltage using the plurality of resistors based on the switch states of the plurality of switches set to on or off by the setting data, and the overcurrent reference voltage for protecting the switching element from overcurrent when the predetermined current is flowing is set; The semiconductor module according to claim 11.

15. The overcurrent reference voltage generating circuit includes: a first resistor, a second resistor, a third resistor, a first switch having a first terminal and a second terminal, and a second switch having a third terminal and a fourth terminal; one end of the first resistor is connected to the power supply voltage, the other end of the first resistor and one end of the second resistor are connected to a first node, the other end of the second resistor and one end of the third resistor are connected to a second node, and the other end of the third resistor is grounded; the first terminal is connected to the first node, the third terminal is connected to the second node, and the second terminal and the fourth terminal are connected to the inverting input terminal of the comparator; generating a first overcurrent reference voltage when the first switch is set to ON and the second switch is set to OFF based on the setting data; generating a second overcurrent reference voltage that is smaller than the first overcurrent reference voltage when the first switch is set to be off and the second switch is set to be on based on the setting data; The semiconductor module according to claim 14.

16. the control circuit further includes a drive capacity switching circuit that adjusts the drive capacity of the switching element; the overheat detection circuit outputs a temperature detection signal corresponding to the temperature state of the switching element; the overcurrent detection circuit outputs a current detection signal according to a current state of the switching element; the drive capability switching circuit generates drive capability switching signals having different voltage levels based on the temperature detection signal and the current detection signal, and outputs the generated drive capability switching signals to the drive control circuit; the drive control circuit outputs the drive control signal of a drive current that varies depending on the voltage level of the drive capability switching signal to the gate of the switching element; The semiconductor module according to claim 11.

17. The communication circuit a data receiving circuit including: a counter circuit that detects a falling edge of the trimming data received via the communication terminal and outputs a pulse signal a predetermined time after the falling edge of the trimming data; a first latch circuit that latches the trimming data with the pulse signal; and a decoder that decodes a plurality of output data from the first latch circuit and outputs the address data and the setting data; a data transmission circuit including a selection circuit that selects the information on the operating state based on the address data, an AD converter that converts an analog signal of the information on the operating state selected and output by the selection circuit into a digital signal, a second latch circuit that latches the digital signal, and a transmission circuit that transmits an output signal from the second latch circuit to the external device via the communication terminal, The semiconductor module according to claim 11.

18. The control circuit a high-side control circuit for controlling the high-side switching element and a low-side control circuit for controlling the low-side switching element, a first connection portion is provided on a first wiring through which the communication terminal is connected to the communication circuit on the high side included in the high side control circuit, and a second connection portion is provided on a second wiring through which the communication terminal is connected to the communication circuit on the low side included in the low side control circuit, the first connection portion and the second connection portion are short-circuited when the two-way communication is performed, and are in an insulated state during actual operation when the two-way communication is not performed. The semiconductor module according to claim 10.

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