Power supply management circuit, memory system, and power supply management method

Abstract

To provide a power supply management circuit capable of appropriately managing control of a plurality of power storage elements.SOLUTION: According to one embodiment, there is provided a power supply management circuit comprising a measuring circuit, a step-up / down circuit, and a plurality of terminals. The measuring circuit is connectable to each of a plurality of power storage elements corresponding to a plurality of switches, via a corresponding switch. The measuring circuit measures a parameter concerning capacity of a power storage element connected via a corresponding switch among the plurality of power storage elements. The step-up / down circuit is connectable to each of the plurality of power storage elements via a corresponding switch. The step-up / down circuit can step up / down a voltage of the power storage element connected via the corresponding switch among the plurality of power storage elements. The terminals are constituted so as to be connected to respective control terminals of the plurality of switches.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a power management circuit, a memory system, and a power management method. [Background technology]

[0002] A power management circuit that controls charging and discharging of a connected power storage device is known. Such a power management circuit can be used in a memory system having a volatile memory. Such a memory system charges the power storage device while an external power source is being supplied. Furthermore, when the external power source is cut off, the memory system can operate using the charge obtained by discharging the power storage device. When using multiple power storage devices, it is desirable to appropriately manage the control of the multiple power storage devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2014 / 0258755 [Patent Document 2] US Patent Application Publication No. 2016 / 0071609 [Patent Document 3] US Patent Application Publication No. 2016 / 0329734 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a power management circuit, a memory system, and a power management method that can appropriately manage the control of a plurality of power storage elements. [Means for solving the problem]

[0005] According to one embodiment, there is provided a power management circuit having a measurement circuit, a step-up / step-down circuit, and a plurality of terminals. The measurement circuit is connectable to each of a plurality of storage elements corresponding to a plurality of switches via the corresponding switch. The measurement circuit measures a parameter related to the capacitance of each of the plurality of storage elements connected via the corresponding switch. The step-up / step-down circuit is connectable to each of the plurality of storage elements via the corresponding switch. The step-up / step-down circuit is capable of boosting or lowering the voltage of each of the plurality of storage elements connected via the corresponding switch. The plurality of terminals are configured to be connected to control terminals of the plurality of switches, respectively. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a configuration of a memory system according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of a switching circuit according to the embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of the configuration of a switching circuit according to the embodiment. [Figure 4] FIG. 4 is a circuit diagram showing the operation of the switching circuit during capacitance measurement according to the embodiment. [Figure 5] 5A and 5B are waveform diagrams illustrating the operation of the switching circuit and the power management circuit according to the embodiment. [Figure 6] FIG. 4 is a circuit diagram showing the operation of the switching circuit during discharge according to the embodiment. [Figure 7] FIG. 10 is a block diagram showing the configuration of a memory system according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] A power management circuit, a memory system, and a power management method according to embodiments will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0008] (Embodiment) A memory system according to an embodiment includes a power management circuit. The memory system uses the power management circuit to charge multiple power storage elements, and can use the charges in the multiple power storage elements when power to the memory system is turned off. In the embodiment described below, a technique is employed to appropriately manage the control of the multiple power storage elements.

[0009] The memory system 1 can be configured as shown in Figure 1. Figure 1 is a block diagram showing the configuration of the memory system 1.

[0010] The memory system 1 is communicatively connected to a host HA via a communication medium and can function as a storage medium for the host HA. The memory system 1 can be configured to include a substrate and multiple electronic components mounted on the substrate. The memory system 1 can be, for example, an SSD (Solid State Drive) or a UFS (Universal Flash Storage) device. The communication medium can be a wired communication path such as a serial cable. The host HA can be, for example, an information processing device such as a personal computer, a server, or a storage box, a mobile phone, an imaging device, a mobile terminal such as a tablet computer or a smartphone, a game device, or an in-vehicle terminal such as a car navigation system.

[0011] The memory system 1 includes a controller 10, a nonvolatile memory 20, a power management circuit 30, a power storage element group 40, an interface connector 50, a switching circuit 60, a volatile memory 70, and a temperature sensor 80.

[0012] The interface connector 50 is a circuit device that can be connected to the host HA. The interface connector 50 can be arranged, for example, at an end of a circuit board. The interface connector 50 has power pins and data pins. The interface connector 50 supplies data received from the host HA via the data pins to the controller 10, and transmits data received from the controller 10 to the host HA via the data pins. The interface connector 50 also supplies the power supply voltage received from the host HA via the power pins to the power management circuit 30.

[0013] The controller 10 is a semiconductor device that comprehensively controls the operation of the memory system 1. For example, the controller 10 controls communication between the host HA and the memory system 1. The controller 10 receives commands from the host HA and executes write operations and read operations on the nonvolatile memory 20. Alternatively, the controller 10 executes an erase operation to erase data stored in the nonvolatile memory 20. The controller 10 controls operations on the nonvolatile memory 20 while using the volatile memory 70. Each function of the controller 10 may be realized by the controller 10 executing firmware. Each function of the controller 10 may be realized by dedicated hardware within the controller 10. The controller 10 may be implemented on a board as an SoC (System-on-a-Chip).

[0014] The nonvolatile memory 20 stores data and / or information in a nonvolatile manner. The nonvolatile memory 20 may be, for example, a NAND flash memory. The nonvolatile memory 20 has a memory cell array in which a plurality of memory cells are arranged in a two-dimensional or three-dimensional matrix. Each memory cell may be capable of multi-value storage using, for example, a plurality of page configurations. In the nonvolatile memory 20, data is erased in block units, and data is written and read in page units. A block is composed of a plurality of pages.

[0015] The volatile memory 70 temporarily stores data and / or information. The volatile memory 70 may be, for example, an SDRAM, a DRAM, or an SRAM. The volatile memory 70 functions as a buffer when transmitting and receiving signals (e.g., commands, data, etc.) between the host HA or the non-volatile memory 20 and the controller 10, and also functions as a working area for the controller 10.

[0016] The temperature sensor 80 measures the ambient temperature of the memory system 1. The temperature sensor 80 supplies the measured temperature to the power management circuit 30. The temperature sensor 80 may supply the measured temperature to the power management circuit 30 under the control of the controller 10. The temperature sensor 80 is, for example, an electronic circuit including a thermistor. In this case, the temperature sensor 80 is, for example, mounted on a substrate near the energy storage element group 40, and is capable of detecting the temperature of the air present near the energy storage element group 40. The temperature sensor 80 may be built into the controller 10 or the non-volatile memory 20.

[0017] The power management circuit 30 controls the supply of power to each part of the memory system 1 (e.g., the controller 10, the nonvolatile memory 20, and the volatile memory 70). The power management circuit 30 can execute part of the PLP (Power Loss Protection) process. The PLP process is a process for protecting data stored in the memory system 1 when power supplied to the memory system 1 from an external source (e.g., the host HA) is lost. In the PLP process, power from the power storage element group 40 is used to urgently save data in the volatile memory 70 to the nonvolatile memory 20 so that the data in the volatile memory 70 is not lost.

[0018] The power management circuit 30 is connected to the energy storage element group 40 via a switching circuit 60. The power management circuit 30 controls the switching circuit 60 in preparation for PLP processing, and also controls charging and discharging of the energy storage element group 40 via the switching circuit 60. The power management circuit 30 can be mounted on a substrate as a PMIC (Power Management IC). The internal configuration of the power management circuit 30 will be described later.

[0019] The power storage element group 40 stores power to be supplied to each component of the memory system 1. The power storage element group 40 includes a plurality of power storage elements 41 to 44. Each of the power storage elements 41 to 44 may be a capacitor or a battery. The capacitor may be an electrolytic capacitor, a multilayer capacitor, a tantalum capacitor, an electric double layer capacitor, a ceramic capacitor, a polymer capacitor, or the like. The battery may be a secondary battery (for example, a lithium ion secondary battery, a nickel-metal hydride battery), or the like.

[0020] The switching circuit 60 is connected between the power supply management circuit 30 and the energy storage element group 40. The switching circuit 60 is capable of connecting at least some of the energy storage elements 41 to 44 in the energy storage element group 40 to the power supply management circuit 30 under the control of the power supply management circuit 30.

[0021] The switching circuit 60 can be configured as shown in Figure 2. Figure 2 is a circuit diagram showing the configuration of the switching circuit 60.

[0022] The switching circuit 60 includes a plurality of switches 61 to 64. The plurality of switches 61 to 64 correspond to a plurality of power storage elements 41 to 44, respectively. Each of the switches 61 to 64 is capable of connecting a corresponding power storage element to the power management circuit 30. FIG. 1 illustrates a configuration in which the power storage element group 40 includes four power storage elements 41 to 44 and the switching circuit 60 includes four switches 61 to 64, but the number of power storage elements included in the power storage element group 40 and the number of switches included in the switching circuit 60 may each be two to three, or five or more.

[0023] A first end of the switch 61 is connected to the energy storage element 41 via a power supply line PL11. A second end of the switch 61 is connected to a power supply terminal 30e of the power management circuit 30 via a power supply line PL1 and a common power supply line PL0. A control terminal of the switch 61 is connected to a control terminal 30a of the power management circuit 30 via a control line CL1. A voltage of a certain potential is output from the power supply terminal 30e of the power management circuit 30, which is treated as a power supply voltage in the power management circuit 30.

[0024] A first end of the switch 62 is connected to the power storage element 42 via a power supply line PL12. A second end of the switch 62 is connected to the power supply terminal 30e of the power management circuit 30 via a power supply line PL2 and a common power supply line PL0. A control terminal of the switch 62 is connected to the control terminal 30b of the power management circuit 30 via a control line CL2.

[0025] The switch 63 has a first end connected to the power storage element 43 via a power supply line PL13. The switch 63 has a second end connected to the power supply terminal 30e of the power management circuit 30 via a power supply line PL3 and a common power supply line PL0. The switch 63 has a control terminal connected to the control terminal 30c of the power management circuit 30 via a control line CL3.

[0026] A first end of the switch 64 is connected to the power storage element 44 via a power supply line PL14. A second end of the switch 64 is connected to the power supply terminal 30e of the power management circuit 30 via a power supply line PL4 and a common power supply line PL0. A control terminal of the switch 64 is connected to the control terminal 30d of the power management circuit 30 via a control line CL4.

[0027] The on / off of the multiple switches 61 to 64 is individually controlled by the power management circuit 30. The on / off control of the multiple switches 61 to 64 may be performed autonomously by the power management circuit 30, or may be performed by the controller 10 via the power management circuit 30. The multiple switches 61 to 64 are not limited to specific elements as long as they can switch the corresponding wiring between the energy storage element group 40 and the switching circuit 60 between a connected state and a disconnected state. The multiple switches 61 to 64 are an example of a switching circuit.

[0028] For example, the switches 61 to 64 in the switching circuit 60 may be transistors TR1 to TR4, respectively, as shown in Fig. 3. The power storage elements 41 to 44 may be capacitors C1 to C4, respectively.

[0029] The source of the transistor TR1 is connected to the power storage element 41 via a power supply line PL11. The drain of the transistor TR1 is connected to the power supply terminal 30e of the power management circuit 30 via a power supply line PL1 and a common power supply line PL0. The gate of the transistor TR1 is connected to the control terminal 30a of the power management circuit 30 via a control line CL1.

[0030] The source of the transistor TR2 is connected to the power storage element 42 via a power supply line PL12. The drain of the transistor TR2 is connected to the power supply terminal 30e of the power management circuit 30 via a power supply line PL2 and a common power supply line PL0. The gate of the transistor TR2 is connected to the control terminal 30b of the power management circuit 30 via a control line CL2.

[0031] The source of the transistor TR3 is connected to the power storage element 43 via a power supply line PL13. The drain of the transistor TR3 is connected to the power supply terminal 30e of the power management circuit 30 via a power supply line PL3 and a common power supply line PL0. The gate of the transistor TR3 is connected to the control terminal 30c of the power management circuit 30 via a control line CL3.

[0032] The source of the transistor TR4 is connected to the power storage element 44 via a power supply line PL14. The drain of the transistor TR4 is connected to the power supply terminal 30e of the power management circuit 30 via a power supply line PL4 and a common power supply line PL0. The gate of the transistor TR4 is connected to the control terminal 30d of the power management circuit 30 via a control line CL4.

[0033] During PLP processing, the power management circuit 30 shown in FIG. 1 acquires the power stored in the power storage element group 40 via the switching circuit 60 and supplies the acquired power to each part of the memory system 1 (e.g., the controller 10, the non-volatile memory 20, and the volatile memory 70).

[0034] The power management circuit 30 includes a constant current circuit 31, a measurement circuit 32, a timer circuit 33, a latch circuit 34, and a voltage step-up / step-down circuit 35. The controller 10 includes a calculation circuit 11. The functions of the calculation circuit 11 may be realized by the controller 10 executing a program.

[0035] The constant current circuit 31 is capable of sinking a constant current Ic to the energy storage element group 40. The constant current circuit 31 extracts charge at the constant current Ic from the energy storage element group 40. Extracting charge at the constant current Ic means, in other words, extracting electrons or reducing the amount of stored charge at a constant current or at a constant amount of charge per unit time.

[0036] The measurement circuit 32 measures the number of charge / discharge cycles N of the energy storage element group 40. The measurement circuit 32 measures parameters related to the capacity of the energy storage element group 40 via a switching circuit 60. The measurement circuit 32 is connectable to each of the energy storage elements 41 to 44 in the energy storage element group 40 via switches 61 to 64 corresponding to each of the energy storage elements 41 to 44. The measurement circuit 32 measures parameters related to the capacity of each of the energy storage elements 41 to 44 connected via a switch. The measurement circuit 32 measures a change dV in the voltage (terminal voltage) across each of the energy storage elements 41 to 44 connected via a switch. The timer circuit 33 measures a time dt during which the measurement circuit 32 measures the change dV in the terminal voltage of the energy storage element. The temperature sensor 80 measures the ambient temperature T while the measurement circuit 32 measures the terminal voltage of the energy storage element group 40. The latch circuit 34 stores the measurement results from the measurement circuit 32, the timer circuit 33, and the temperature sensor 80.

[0037] The step-up / step-down circuit 35 controls the charging and discharging of the energy storage element group 40 via a switching circuit 60. The step-up / step-down circuit 35 is connectable to each of the energy storage elements 41 to 44 via switches 61 to 64 corresponding to the respective energy storage elements 41 to 44. The step-up / step-down circuit 35 is capable of stepping up or stepping down the voltage of the energy storage elements 41 to 44 connected via the switches. The step-up / step-down circuit 35 charges or discharges the energy storage elements 41 to 44 connected via the switches, using power P0 received from the host HA via an interface connector 50. The step-up / step-down circuit 35 may step up a voltage corresponding to the power P0 to charge the energy storage elements. The step-up / step-down circuit 35 may step down a voltage corresponding to the power P0 to discharge the energy storage elements.

[0038] The calculation circuit 11 of the controller 10 may access the latch circuit 34 and obtain the measurement results from the measurement circuit 32, the timer circuit 33, and the temperature sensor 80 from the latch circuit 34. The calculation circuit 11 calculates the fatigue levels ER of each of the storage elements 41 to 44 using the measurement results from the measurement circuit 32, the timer circuit 33, and the temperature sensor 80. As shown in the following formulas 1 to 4, the calculation circuit 11 may calculate the fatigue levels ER1 to ER4 of each of the storage elements 41 to 44 by finding the ratio of the initial capacities C10 to C40 to the current capacities C11 to C41 of each of the storage elements 41 to 44 and adding a correction ΔER according to the number of charge / discharge cycles N and the ambient temperature T. ER1=C11 / (C01)+ΔER(N,T) Equation 1 ER2=C12 / (C02)+ΔER(N,T) Equation 2 ER3 = C13 / (C03) + ΔER(N,T) Equation 3 ER4 = C14 / (C04) + ΔER(N,T) Equation 4

[0039] The effectiveness of the correction ΔER according to the number of charge / discharge cycles N and the ambient temperature T will be described.

[0040] For example, if each of the energy storage elements 41 to 44 in the energy storage element group 40 is a large-capacity capacitor, the lifespan of the large-capacity capacitor will be significantly shortened due to high temperature conditions. Furthermore, Joule heat is generated near the interface during charging and discharging. The higher the temperature, the greater the resistance value, and even if the same current flows, the greater the Joule heat. In other words, charging and discharging a capacitor at high temperatures will cause more wear than simply the effect of temperature. Temperature management is believed to be effective in suppressing such effects.

[0041] The nonvolatile memory 20 may be a NAND flash memory equipped with a temperature sensor. In this case, temperature management can utilize a temperature conversion formula that uses the output of a temperature sensor provided in the NAND flash memory and the output of a temperature sensor provided external to the NAND flash memory. The calculation circuit 11 of the controller 10 may estimate the capacitor temperature by calculating the temperature using the temperature measured by the temperature sensor 80 inside the memory system 1 and the temperature conversion formula. Other methods for estimating the capacitor temperature may also be used. Based on the log results of the temperatures measured by the temperature sensor 80, a correction ΔER corresponding to the number of charge / discharge cycles N and the ambient temperature T is added to each of the formulas 1 to 4 to suppress the number of charge / discharge cycles of capacitors in the energy storage element group 40 whose temperature is expected to become higher in the future and promote the number of charge / discharge cycles of capacitors whose temperature will become lower. By managing the fatigue levels ER1 to ER4 in this manner, the fatigue level can be estimated appropriately, taking into account not only the fatigue level calculated from the current capacity but also the future fatigue level.

[0042] The initial capacitances C01 to C04 of the respective storage elements 41 to 44 can be experimentally obtained and set in the calculation circuit 11 in advance.

[0043] The current capacity of each of the storage elements 41 to 44 can be measured by the power management circuit 30 controlling the switching circuit 60 to extract charge at a constant current Ic from at least some of the storage elements 41 to 44, as shown in Fig. 4. Fig. 4 is a circuit diagram showing the operation of the switching circuit 60 during capacity measurement.

[0044] As shown in Fig. 4(a), the power management circuit 30 maintains all switches 61 to 64 in the switching circuit 60 in an on state. This allows the power management circuit 30 to measure parameters required for calculating the total current capacitances C11 to C14 of all storage elements 41 to 44 in the storage element group 40, as shown in Fig. 5. Fig. 5 is a waveform diagram showing the operation of the switching circuit 60 and the power management circuit 30. In Fig. 5, the state of each switch 61 to 64 is represented as 1 if it is in an on state and 0 if it is in an off state.

[0045] At timing t1, the switching circuit 60 turns on all of the switches 61 to 64 under control of the power management circuit 30. The power management circuit 30 charges all of the power storage elements 41 to 44 in the power storage element group 40 with a voltage V1.

[0046] At timing t2, power management circuit 30 draws in constant current Ic and begins to extract charge at constant current Ic from each of power storage elements 41 to 44. At the same time, power management circuit 30 activates timer circuit 33 to start counting time.

[0047] At timing t3, the power management circuit 30 stops absorbing the constant current Ic, stops counting time, and measures the voltage drop dV1 of each of the storage elements 41-44. The power management circuit 30 obtains the counted time dt1 from the timer circuit 33. The power management circuit 30 charges each of the storage elements 41-44 with the voltage V1, obtains the number of charge / discharge cycles N stored in the latch circuit 33, and increments it. The power management circuit 30 obtains the ambient temperature T from the temperature sensor 80. The power management circuit 30 stores the voltage drop dV1, the time dt1, the number of charge / discharge cycles N, and the ambient temperature T in the latch circuit 33 and supplies them to the controller 10.

[0048] Calculation circuit 11 of controller 10 may calculate the sum of current capacities C11 to C14 of power storage elements 41 to 44 as shown in the following formula 5. C11 + C12 + C13 + C14 = Ic × (dt1) / (dV1) Formula 5

[0049] From timing t1 until just before timing t4, the switching circuit 60 keeps all the switches 61 to 64 in the on state (1 in FIG. 5).

[0050] 4(b), the power management circuit 30 maintains the switch 64 in the switching circuit 60 in an OFF state and the remaining switches 61 to 63 in an ON state. This allows the power management circuit 30 to measure parameters required for calculating the sum of the current capacities C11 to C13 of some of the storage elements 41 to 43 in the storage element group 40, as shown in FIG.

[0051] At timing t4, the switching circuit 60 switches the switch 64 to the OFF state (0 in FIG. 5) and maintains the switches 61 to 63 in the ON state under control of the power management circuit 30. The power management circuit 30 charges some of the power storage elements 41 to 43 in the power storage element group 40 with the voltage V2.

[0052] At timing t5, power management circuit 30 draws in constant current Ic and begins to extract charge at constant current Ic from each of power storage elements 41 to 43. At the same time, power management circuit 30 activates timer circuit 33 to start counting time.

[0053] At timing t6, the power management circuit 30 stops absorbing the constant current Ic, stops counting time, and measures the amount of voltage drop dV2 of each of the storage elements 41-43. The power management circuit 30 obtains the counted time dt2 from the timer circuit 33. The power management circuit 30 charges each of the storage elements 41-43 with voltage V2, obtains the number of charge / discharge cycles N stored in the latch circuit 33, and increments it. The power management circuit 30 obtains the ambient temperature T from the temperature sensor 80. The power management circuit 30 stores the amount of voltage drop dV2, time dt2, the number of charge / discharge cycles N, and the ambient temperature T in the latch circuit 33 and supplies them to the controller 10.

[0054] Calculation circuit 11 of controller 10 may calculate the sum of current capacities C11 to C13 of power storage elements 41 to 43 as shown in the following formula 6. C11 + C12 + C13 = Ic × (dt2) / (dV2) Equation 6

[0055] From timing t4 until just before timing t7, the switching circuit 60 keeps the switch 64 in the OFF state and the remaining switches 61 to 63 in the ON state.

[0056] 4(c), the power management circuit 30 maintains the switch 61 in the switching circuit 60 in an OFF state and the remaining switches 62 to 64 in an ON state. This allows the power management circuit 30 to measure parameters required for calculating the sum of the current capacities C12 to C14 of some of the storage elements 42 to 44 in the storage element group 40, as shown in FIG.

[0057] At timing t7, the switching circuit 60 switches the switch 61 to the OFF state, switches the switch 64 to the ON state, and maintains the switches 62 to 63 in the ON state under the control of the power management circuit 30. The power management circuit 30 charges some of the power storage elements 42 to 44 in the power storage element group 40 with the voltage V3.

[0058] At timing t8, power management circuit 30 draws in constant current Ic and begins to extract charge at constant current Ic from each of power storage elements 42 to 44. At the same time, power management circuit 30 activates timer circuit 33 to start counting time.

[0059] At timing t9, the power management circuit 30 stops absorbing the constant current Ic, stops counting time, and measures the amount of voltage drop dV3 of each of the storage elements 42-44. The power management circuit 30 obtains the counted time dt3 from the timer circuit 33. The power management circuit 30 charges each of the storage elements 42-44 with voltage V3, obtains the number of charge / discharge cycles N stored in the latch circuit 33, and increments it. The power management circuit 30 obtains the ambient temperature T from the temperature sensor 80. The power management circuit 30 stores the amount of voltage drop dV3, time dt3, the number of charge / discharge cycles N, and the ambient temperature T in the latch circuit 33 and supplies them to the controller 10.

[0060] The calculation circuit 11 of the controller 10 may calculate the sum of the current capacities C12 to C14 of the storage elements 42 to 44 as shown in the following formula 7. C12 + C13 + C14 = Ic × (dt3) / (dV3) Equation 7

[0061] From timing t7 to just before timing t10, the switching circuit 60 keeps the switch 61 in the OFF state and the remaining switches 62 to 64 in the ON state.

[0062] 4(d), the power management circuit 30 maintains the switch 62 in the switching circuit 60 in an OFF state, and maintains the remaining switches 61, 63 to 64 in an ON state. This allows the power management circuit 30 to measure parameters required for calculating the sum of the current capacities C11, C13 to C14 of some of the storage elements 41, 43 to 44 in the storage element group 40, as shown in FIG.

[0063] At timing t10, the switching circuit 60 switches the switch 62 to the OFF state, switches the switch 61 to the ON state, and maintains the switches 63 to 64 in the ON state under the control of the power management circuit 30. The power management circuit 30 charges some of the power storage elements 41, 43 to 44 in the power storage element group 40 with a voltage V4.

[0064] At timing t11, power management circuit 30 draws in constant current Ic and begins to extract charge at constant current Ic from each of power storage elements 41, 43 to 44. At the same time, power management circuit 30 activates timer circuit 33 and starts counting time.

[0065] At timing t12, the power management circuit 30 stops absorbing the constant current Ic, stops counting time, and measures the voltage drop dV4 of each of the storage elements 41, 43 to 44. The power management circuit 30 obtains the counted time dt4 from the timer circuit 33. The power management circuit 30 charges each of the storage elements 41, 43 to 44 with a voltage V4, obtains and increments the number of charge / discharge cycles N stored in the latch circuit 33, and obtains the ambient temperature T from the temperature sensor 80. The power management circuit 30 stores the voltage drop dV4, time dt4, the number of charge / discharge cycles N, and the ambient temperature T in the latch circuit 33 and supplies them to the controller 10.

[0066] Calculation circuit 11 of controller 10 may calculate the sum of current capacities C11, C13 to C14 of power storage elements 41, 43 to 44 as shown in the following formula 8. C11 + C13 + C14 = Ic × (dt4) / (dV4) Formula 8

[0067] From timing t10 ​​until just before timing t13, the switching circuit 60 keeps the switch 62 in the OFF state and keeps the remaining switches 61, 63 to 64 in the ON state.

[0068] The calculation circuit 11 can calculate the current capacitance C11 of the storage element 41 using the formulas 5 and 7, as shown in the following formula 9. C11=Ic×(dt1) / (dV1)-Ic×(dt3) / (dV3) Equation 9

[0069] The calculation circuit 11 can calculate the current capacitance C12 of the storage element 42 using the formulas 5 and 8, as shown in the following formula 10. C12=Ic×(dt1) / (dV1)-Ic×(dt4) / (dV4) Equation 10

[0070] The calculation circuit 11 can calculate the current capacitance C13 of the storage element 43 using the formulas 5 to 8, as shown in the following formula 11. C13=Ic×(dt2) / (dV2)+Ic×(dt3) / (dV3)+Ic×(dt4) / (dV4)-2×Ic×(dt1) / (dV1) Equation 11

[0071] The calculation circuit 11 can calculate the current capacitance C14 of the storage element 44 using the formulas 5 and 6, as shown in the following formula 12. C14=Ic×(dt1) / (dV1)-Ic×(dt2) / (dV2) Equation 12

[0072] As shown in Figures 4 and 5, by measuring parameters related to the total capacitance of multiple storage elements, the proportion of error in the measured value can be relatively reduced compared to measuring parameters related to the capacitance of a single storage element, and measurement accuracy can be easily improved.

[0073] Furthermore, measuring a parameter related to the total capacitance of multiple storage elements is advantageous in dealing with power outages during measurement compared to measuring a parameter related to the capacitance of a single storage element. For example, assume that three-quarters of the total number of storage elements in the storage element group 40 are required for PLP processing. In this case, if the power is interrupted while the storage elements are being charged and measured one by one, it becomes impossible to recover the data to be protected. However, in this embodiment, after measuring all storage elements (four in the case of FIG. 4(a)), a method is used in which the capacity of each element is measured one by one (three in the cases of FIGS. 4(b) to 4(d)), and the capacity of each element is estimated by subtraction. Therefore, at least three-quarters of the total number of storage elements are always available in a charged state, making it possible to recover data even if the power is interrupted during measurement.

[0074] The calculation circuit 11 can calculate the current fatigue level ER1 of the storage element 41 using Formula 1 and Formula 9, the initial capacity C01 of the storage element 41, the number of charge / discharge cycles N, and the ambient temperature T. The calculation circuit 11 can calculate the current fatigue level ER2 of the storage element 42 using Formula 2 and Formula 10, the initial capacity C02 of the storage element 42, the number of charge / discharge cycles N, and the ambient temperature T. The calculation circuit 11 can calculate the current fatigue level ER3 of the storage element 43 using Formula 3 and Formula 11, the initial capacity C03 of the storage element 43, the number of charge / discharge cycles N, and the ambient temperature T. The calculation circuit 11 can calculate the current fatigue level ER4 of the storage element 44 using Formula 4 and Formula 12, the initial capacity C04 of the storage element 44, the number of charge / discharge cycles N, and the ambient temperature T. The calculation circuit 11 supplies the current fatigue levels ER1 to ER4 of the storage elements 41 to 44 to the power management circuit 30.

[0075] The power management circuit 30 receives the current fatigue levels ER1 to ER4 of the storage elements 41 to 44 from the calculation circuit 11. The number n of storage elements required for the PLP process may be set in advance in the power management circuit 30. The power management circuit 30 may select n storage elements having relatively small fatigue levels ER from the plurality of storage elements 41 to 44 in the storage element group 40 as the storage elements to be used in the PLP process. The power management circuit 30 selectively maintains n switches in the switching circuit 60 corresponding to the n storage elements in an on state, and maintains the remaining switches in an off state.

[0076] This allows the power management circuit 30 to perform PLP processing by selectively using n storage elements having a relatively low fatigue level ER among the storage elements 41 to 44, and allows the remaining storage elements having a relatively high fatigue level ER to rest. As a result, the fatigue levels of the storage elements 41 to 44 of the storage element group 40 can be leveled out, and the lifespan of the storage elements 41 to 44 of the storage element group 40 can be extended as a whole.

[0077] For example, when n=3 and the fatigue level ER1 is the largest among the current fatigue levels ER1 to ER4 of the storage elements 41 to 44, as shown in FIG. 6(a), the power management circuit 30 selects the storage elements 42 to 44 as the storage elements to be used in the PLP process. The power management circuit 30 maintains the switch 61 in the OFF state and the switches 62 to 64 in the ON state. This maintains the state in which the storage elements 42 to 44 are selectively connected to the power terminal 30e of the power management circuit 30. The power management circuit 30 can perform the PLP process by selectively using the storage elements 42 to 44, which have a relatively small fatigue level ER, among the multiple storage elements 41 to 44, and can rest the storage element 41, which has a relatively large fatigue level ER.

[0078] Alternatively, when n=3 and the fatigue level ER2 is the largest among the current fatigue levels ER1 to ER4 of the storage elements 41 to 44, as shown in FIG. 6(b), the power management circuit 30 selects the storage elements 41, 43 to 44 as the storage elements to be used for the PLP process. The power management circuit 30 maintains the switch 62 in the OFF state and the switches 61, 63 to 64 in the ON state. This maintains the state in which the storage elements 41, 43 to 44 are selectively connected to the power terminal 30e of the power management circuit 30. The power management circuit 30 can perform the PLP process by selectively using the storage elements 41, 43 to 44, which have a relatively small fatigue level ER, among the multiple storage elements 41 to 44, and can rest the storage element 42, which has a relatively large fatigue level ER.

[0079] Alternatively, when n=3 and the fatigue level ER3 is the largest among the current fatigue levels ER1-ER4 of the storage elements 41-44, as shown in FIG. 6(c), the power management circuit 30 selects the storage elements 41-42, 44 as the storage elements to be used in the PLP process. The power management circuit 30 maintains the switch 63 in the OFF state and the switches 61-62, 64 in the ON state. This maintains the state in which the storage elements 41-42, 44 are selectively connected to the power terminal 30e of the power management circuit 30. The power management circuit 30 can perform the PLP process by selectively using the storage elements 41-42, 44 with a relatively small fatigue level ER among the multiple storage elements 41-44, and can rest the storage element 43 with a relatively large fatigue level ER.

[0080] Alternatively, when n=3 and the fatigue level ER4 is the largest among the current fatigue levels ER1 to ER4 of the storage elements 41 to 44, as shown in FIG. 6(d), the power management circuit 30 selects the storage elements 41 to 43 as the storage elements to be used in the PLP process. The power management circuit 30 maintains the switch 64 in the OFF state and the switches 61 to 63 in the ON state. This maintains the state in which the storage elements 41 to 43 are selectively connected to the power terminal 30e of the power management circuit 30. The power management circuit 30 can perform the PLP process by selectively using the storage elements 41 to 43, which have a relatively small fatigue level ER, among the multiple storage elements 41 to 44, and can rest the storage element 44, which has a relatively large fatigue level ER.

[0081] As described above, in the power management circuit 30 of the memory system 1 in this embodiment, the measurement circuit 32 measures parameters related to the capacitance of the storage elements 41-44 that are connected via the switches 61-64. For example, in order to obtain the capacitance of each storage element, the measurement circuit 32 can measure parameters related to the total capacitance of the storage elements while partially changing the storage elements to be measured (see FIGS. 4(a)-4(d) and 5). By measuring parameters related to the total capacitance of the storage elements, the proportion of error in the measured value can be relatively reduced compared to measuring parameters related to the total capacitance of a single storage element, and measurement accuracy can be easily improved. Therefore, control of the storage elements 41-44 can be appropriately managed.

[0082] Furthermore, in this embodiment, in the power management circuit 30 of the memory system 1, the step-up / step-down circuit 35 can boost or step down the voltage of each of the multiple storage elements 41 to 44 connected via the switches 61 to 64. For example, the step-up / step-down circuit 35 can boost or step down the voltage of n storage elements 41 to 44 that have a relatively low fatigue level ER (see FIGS. 6(a) to 6(d)). This allows the power management circuit 30 to selectively use the n storage elements 41 to 44 that have a relatively low fatigue level ER to perform PLP processing, and rest the remaining storage elements that have a relatively high fatigue level ER. As a result, the fatigue levels of the multiple storage elements 41 to 44 in the storage element group 40 can be leveled, and the lifespan of the multiple storage elements 41 to 44 in the storage element group 40 can be extended as a whole. Therefore, from this perspective as well, the control of the multiple storage elements 41 to 44 can be appropriately managed.

[0083] As a modification of the embodiment, in the memory system 101, the switching circuit 160 may be included in the power management circuit 130, as shown in Fig. 7. Fig. 7 is a block diagram showing the configuration of the memory system 101 according to the modification of the embodiment.

[0084] The switching circuit 160 is connected between other components in the power management circuit 130 (for example, the constant current circuit 31, the measurement circuit 32, the timer circuit 33, the latch circuit 34, and the step-up / step-down circuit 35) and the energy storage element group 40. The switching circuit 160 functions as an interface between the other components in the power management circuit 130 and the energy storage element group 40. Under the control of the power management circuit 130, the switching circuit 160 can connect at least some of the energy storage elements of the plurality of energy storage elements 41 to 44 in the energy storage element group 40 to the other components in the power management circuit 130.

[0085] As in the embodiment, the switching circuit 160 includes a plurality of switches 61 to 64 (see FIG. 2). As in the embodiment, the plurality of switches 61 to 64 may be a plurality of transistors TR1 to TR4 (see FIG. 3).

[0086] In the power supply management circuit 130 of this memory system 101, the measurement circuit 32 also measures a parameter related to the capacitance of one of the plurality of storage elements 41-44 that is connected via the switches 61-64. This allows the measurement of a parameter related to the total capacitance of the plurality of storage elements, so that the proportion of error in the measured value can be relatively reduced compared to when measuring a parameter related to the capacitance of a single storage element, and measurement accuracy can be easily improved. Therefore, the control of the plurality of storage elements 41-44 can be appropriately managed.

[0087] Furthermore, in the power management circuit 130 of this memory system 101, the step-up / step-down circuit 35 can also step up or step down the voltage of each of the multiple storage elements 41 to 44 connected via the switches 61 to 64. This allows PLP processing to be performed selectively using n storage elements with relatively low fatigue levels ER among the multiple storage elements 41 to 44, and allows the remaining storage elements with relatively high fatigue levels ER to rest. As a result, the fatigue levels of the multiple storage elements 41 to 44 of the storage element group 40 can be leveled, and the multiple storage elements 41 to 44 of the storage element group 40 can be extended as a whole. Therefore, from this perspective as well, control of the multiple storage elements 41 to 44 can be appropriately managed.

[0088] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0089] 1,101 Memory system, 30,130 Power management circuit, 32 Measurement circuit, 35 Step-up / step-down circuit, 40 Energy storage element group, 41-44 Energy storage element, 60,160 Switching circuit, 61-64 Switch.

Claims

1. a measurement circuit that can be connected to each of a plurality of storage elements corresponding to a plurality of switches via the corresponding switch, and that measures a parameter related to the capacity of each of the storage elements connected via the corresponding switch among the plurality of storage elements; a step-up / step-down circuit that can be connected to each of the plurality of storage elements via the corresponding switch and can boost or lower a voltage of a storage element that is connected to the corresponding switch among the plurality of storage elements; a plurality of terminals configured to be respectively connected to the control terminals of the plurality of switches; Equipped with Power management circuit.

2. The measurement circuit measures a parameter related to the capacitance of one or more storage elements corresponding to one or more switches while one or more switches among the plurality of switches are turned on.

10. The power management circuit of claim 1.

3. The step-up / step-down circuit charges and discharges some of the storage elements corresponding to some of the switches while turning on some of the switches.

10. The power management circuit of claim 1.

4. a plurality of switches configured to be connected to corresponding storage elements among a plurality of connectable storage elements; a measurement circuit to which the plurality of switches are connected and which measures the capacitance of the corresponding storage element connected via a corresponding one of the plurality of switches; a step-up / step-down circuit to which the plurality of switches are connected and which is capable of stepping up or stepping down the voltage of the corresponding storage element connected via the corresponding switch; a plurality of terminals configured to be respectively connected to the control terminals of the plurality of switches; Equipped with Power management circuit.

5. The measurement circuit measures a parameter related to the capacitance of one or more storage elements corresponding to one or more switches while one or more switches among the plurality of switches are turned on.

5. The power management circuit of claim 4.

6. The step-up / step-down circuit charges and discharges some of the storage elements corresponding to some of the switches while turning on some of the switches.

5. The power management circuit of claim 4.

7. A power management circuit according to any one of claims 1 to 6; a memory connected to the power management circuit; A memory system comprising:

8. measuring a parameter related to the capacity of a storage element connected via a corresponding switch among a plurality of connectable storage elements; Increasing or decreasing the voltage of the storage element connected via the corresponding switch among the plurality of storage elements according to the result of the measurement; A power management method including:

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