Magnetic memory device

Abstract

To provide a magnetically stable magnetic memory device.SOLUTION: A magnetic memory device of an embodiment comprises a substrate, a first wiring, a first insulator, a second insulator, a second wiring, and a first magnetoresistive effect element. The first wiring and the first insulator extend in a first direction along the substrate and are arranged in a second direction crossing the first direction. The second insulator extends in the second direction and penetrates the first wiring and the first insulator. The second wiring is provided around the second insulator, extends in the second direction, and penetrates the first wiring and the first insulator. The first magnetoresistive effect element is annularly provided around the second wiring between the first wiring and the second wiring. The first magnetoresistive effect element comprises a first ferromagnetic body between the second wiring and the first wiring, a first nonmagnetic body between the first ferromagnetic body and the first wiring, and a second ferromagnetic body between the first nonmagnetic body and the first wiring.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD Embodiments relate to magnetic memory devices. [Background technology]

[0002] Magnetic memory devices using magnetoresistive elements as memory elements are known. Various methods have been proposed for writing data to magnetoresistive elements. For example, a writing method using spin orbit torque is known. [Prior art documents] [Patent documents]

[0003] X [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0005235 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention aims to provide a magnetically stable magnetic memory device. [Means for solving the problem]

[0005] The magnetic memory device of the embodiment includes a substrate, a first wiring, a first insulator, a second insulator, a second wiring, and a first magnetoresistive element. The first wiring and the first insulator extend in a first direction along the substrate and are aligned in a second direction intersecting the first direction. The second insulator extends in the second direction and penetrates the first wiring and the first insulator. The second wiring is provided around the second insulator and extends in the second direction and penetrates the first wiring and the first insulator. The first magnetoresistive element is provided in a ring shape around the second wiring between the first wiring and the second wiring. The first magnetoresistive element includes a first ferromagnetic body between the second wiring and the first wiring, a first non-magnetic body between the first ferromagnetic body and the first wiring, and a second ferromagnetic body between the first non-magnetic body and the first wiring. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 shows a block diagram illustrating an example of the configuration of a magnetic memory device 1 according to the first embodiment. [Figure 2] FIG. 2 shows a circuit diagram of an example of the circuit configuration of the memory cell array 10 according to the first embodiment. [Figure 3] FIG. 3 shows an example of a planar layout of the memory cell array 10 of the magnetic memory device 1 according to the first embodiment. [Figure 4] FIG. 4 shows a cross-sectional view taken along line IV-IV in FIG. 3, which is an example of the cross-sectional structure of the magnetic memory device 1 according to the first embodiment. [Figure 5] FIG. 5 shows a cross-sectional view taken along line VV in FIG. 3, which is an example of the cross-sectional structure of the magnetic memory device 1 according to the first embodiment. [Figure 6] FIG. 6 shows an enlarged view of region VI in FIG. 4, which is an example of the cross-sectional structure of the memory pillar MP in the magnetic memory device 1 according to the first embodiment. [Figure 7] FIG. 7 shows an example of a curve of the voltage and current characteristics of the memory cell of the magnetic memory device 1 according to the first embodiment. [Figure 8] FIG. 8 shows a cross-sectional view taken along line VIII-VIII in FIG. 3, which is an example of the cross-sectional structure of the memory pillar MP in the magnetic memory device 1 according to the first embodiment. [Figure 9] FIG. 9 shows an example of voltages applied to the memory cell array in a first example of a write operation in the magnetic memory device 1 according to the first embodiment. [Figure 10] FIG. 10 shows an example of the current and magnetization direction applied to the memory cell array in a first example of a write operation in the magnetic memory device 1 according to the first embodiment. [Figure 11] FIG. 11 shows an example of the current and magnetization direction applied to the memory cell array in a second example of the write operation in the magnetic memory device 1 according to the first embodiment. [Figure 12]FIG. 12 shows an example of voltages applied to the memory cell array in a read operation in the magnetic memory device 1 according to the first embodiment. [Figure 13] FIG. 13 shows an example of a current applied to the memory cell array in a read operation in the magnetic memory device 1 according to the first embodiment. [Figure 14] FIG. 14 shows a flowchart as an example of a method for manufacturing the magnetic memory device 1 according to the first embodiment. [Figure 15] FIG. 15 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 16] FIG. 16 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 17] FIG. 17 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 18] FIG. 18 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 19] FIG. 19 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 20] FIG. 20 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 21] FIG. 21 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 22] FIG. 22 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 23] FIG. 23 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 24] FIG. 24 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 25] FIG. 25 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 26]FIG. 26 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 27] FIG. 27 shows an example of a cross-sectional structure of the magnetic memory device 1 according to the first embodiment during manufacturing. [Figure 28] FIG. 28 shows an example of the cross-sectional structure of a memory pillar MPb in a magnetic memory device 1b according to a modification of the first embodiment. [Figure 29] FIG. 29 shows an example of the cross-sectional structure of a memory pillar MPb in a magnetic memory device 1b according to a modification of the first embodiment, and is a cross-sectional view taken along line XXVIIII-XXVIIII in FIG. [Figure 30] FIG. 30 shows an example of the cross-sectional structure of a memory pillar MPc in a magnetic memory device 1c according to the second embodiment. [Figure 31] FIG. 31 shows a flowchart as an example of a method for manufacturing the magnetic memory device 1c according to the second embodiment. [Figure 32] FIG. 32 shows an example of a cross-sectional structure of a magnetic memory device 1c according to the second embodiment during manufacturing. [Figure 33] FIG. 33 shows an example of a cross-sectional structure of a magnetic memory device 1c according to the second embodiment during manufacturing. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference symbol. When multiple components having the same reference symbol are to be distinguished from one another, a subscript will be added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol will be added to the multiple components, and no subscript will be added. Subscripts are not limited to subscripts and superscripts, but also include, for example, lowercase alphabets added to the end of a reference symbol, symbols, and indexes indicating an array.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include portions in which the relationship and ratio of dimensions differ from one another.

[0009] Hereinafter, embodiments will be described using an XYZ Cartesian coordinate system. The positive direction of the vertical axis of a drawing may be referred to as the upper side, and the negative direction as the lower side. The positive direction of the horizontal axis of a drawing may be referred to as the right side, and the negative direction as the left side. That is, in a plan view showing the XY plane (XY plane view (hereinafter the same)), the upper side indicates the +Y direction, the lower side indicates the -Y direction, the right side indicates the +X direction, and the left side indicates the -X direction.

[0010] Hatching has been added to the plan views as appropriate for clarity. The hatching added to the plan views does not necessarily relate to the materials or properties of the components to which the hatching has been added. In cross-sectional views, components such as insulating layers, substrates, wiring, and terminals have been omitted as appropriate for clarity.

[0011] Additionally, any steps in the method flows of the embodiments are not limited to the illustrated order and may occur in an order different from the illustrated order and / or in parallel with other steps unless otherwise indicated.

[0012] In this specification and claims, "connected" refers to being electrically connected, and does not exclude, for example, the presence of another element therebetween. "Electrically connected" may also refer to an insulator being interposed, as long as it is possible for the device to operate in the same manner as an electrically connected device. In this specification, a magnetic memory device is, for example, an MRAM (Magnetoresistive Random Access Memory). The magnetic memory device includes a magnetoresistive effect element as a memory element. The magnetoresistive effect element is a resistance change element that exhibits a tunnel magnetoresistive effect due to a magnetic tunnel junction (MTJ). This magnetoresistive effect element is also called an MTJ element.

[0013] 1. First embodiment A description will be given of a semiconductor device according to the first embodiment. First, the configuration of a magnetic memory device according to the first embodiment will be described.

[0014] 1 is a block diagram showing an example of the configuration of a magnetic memory device according to the first embodiment. The magnetic memory device 1 includes a memory cell array 10, a row decoder 11, a column decoder 12, a read circuit 13, a write circuit 14, a sense amplifier 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0015] The memory cell array 10 is a data storage section in the magnetic memory device 1. The memory cell array 10 includes a plurality of memory cells MC. Each of the plurality of memory cells MC is associated with a pair of a row and a column. Memory cells MC in the same row are associated with the same read word line RWL. Memory cells MC in the same column are associated with the same read bit line RBL and write bit line WBL.

[0016] The row decoder 11 is a circuit that selects a row of the memory cell array 10. The row decoder 11 is connected to the memory cell array 10 via a read word line RWL. An address ADD is supplied to the row decoder 11 from the input / output circuit 17. The row decoder 11 decodes the address ADD and selects a read word line RWL corresponding to a row based on the decoding result. Hereinafter, the selected read word line RWL will be referred to as a selected word line RWL. Furthermore, word lines RWL other than the selected word line RWL will be referred to as unselected word lines RWL.

[0017] The column decoder 12 is a circuit that selects a column of the memory cell array 10. The column decoder 12 is connected to the memory cell array 10 via a read bit line RBL and a write bit line WBL. An address ADD is supplied to the column decoder 12 from the input / output circuit 17. The column decoder 12 decodes the address ADD and selects a write bit line WBL and a read bit line RBL corresponding to a column based on the decoding result. Hereinafter, the selected read bit line RBL will be referred to as a selected read bit line RBL. Hereinafter, the selected write bit line WBL will be referred to as a selected write bit line WBL. Furthermore, read bit lines RBL other than the selected write bit line WBL will be referred to as unselected write bit lines WBL. Furthermore, read bit lines RBL other than the selected read bit line RBL will be referred to as unselected read bit lines RBL.

[0018] The read circuit 13 reads data from the memory cell MC. The read circuit 13 includes, for example, a sense amplifier 15. The sense amplifier 15 is a circuit that outputs data determined to be stored in the memory cell MC from which data is read, using a voltage based on the data stored in the memory cell MC from which data is read.

[0019] The write circuit 14 includes, for example, a write driver (not shown). The write circuit 14 writes data to the memory cells MC.

[0020] The voltage generation circuit 16 generates voltages for various operations of the memory cell array 10 using a power supply voltage provided from outside (not shown) of the magnetic memory device 1. For example, the voltage generation circuit 16 generates various voltages required for a write operation and outputs them to the write circuit 14. Also, for example, the voltage generation circuit 16 generates various voltages required for a read operation and outputs them to the read circuit 13.

[0021] The input / output circuit 17 controls communication with the outside of the magnetic memory device 1. The input / output circuit 17 transfers an address ADD from the outside of the magnetic memory device 1 to the row decoder 11 and the column decoder 12. The input / output circuit 17 transfers a command CMD from the outside of the magnetic memory device 1 to the control circuit 18. The input / output circuit 17 transmits and receives various control signals CNT between the outside of the magnetic memory device 1 and the control circuit 18. The input / output circuit 17 transfers data DAT from the outside of the magnetic memory device 1 to the write circuit 14, and outputs data DAT transferred from the read circuit 13 to the outside of the magnetic memory device 1.

[0022] The control circuit 18 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The control circuit 18 controls the operations of the row decoder 11, the column decoder 12, the read circuit 13, the write circuit 14, the voltage generation circuit 16, and the input / output circuit 17 in the magnetic memory device 1 based on a control signal CNT and a command CMD.

[0023] Next, the configuration of the memory cell array of the magnetic memory device according to the first embodiment will be described.

[0024] 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array according to the first embodiment. In FIG. 2, various components are classified and shown by subscripts including an index (“<>”).

[0025] The memory cell array 10 includes a plurality of read word lines RWL, a write word line WWL, a plurality of read bit lines RBL, a plurality of write bit lines WBL, a plurality of memory strings MS, and a plurality of switching elements TR1.

[0026] The plurality of read word lines RWL are (M+1) word lines WL <0> , …, W.L. <m>, …, and WL <m>M is an integer equal to or greater than 1 (0 <m<M)。

[0027] The plurality of read bit lines RBL are (N+1) read bit lines RBL <0> , …, RBL <n>, …, and RBL <n>N is an integer greater than or equal to 1 (0 <n<N)。

[0028] The plurality of write bit lines WBL include (N+1) write bit lines WBL <0> , …, WBL <n>, …, and WBL <n>Includes:

[0029] The plurality of switching elements TR1 includes (N+1) switching elements TR1 <0> , …, TR1 <n>, …, and TR1 <n>Includes:

[0030] The plurality of memory strings MS are (N+1) memory strings MS <0> , …, MS <n>, …, and MS <n>Includes memory string MS <0> ~MS <n>Each of the memory strings MS <n>This will be explained using an example.

[0031] Memory String MS <n>is wiring SOTL <n>and (M+1) memory cells MC<0,n>, ..., MC<m,n> , …, and MC<M,n> Includes:

[0032] Wiring SOTL <n>is the read bit line RBL <n>a first terminal connected to the switching element TR1; <n>The wiring SOTL has a second end connected to the first end of the wiring SOTL, and a central portion between the two ends. <n>In the center of the<m,n> , …, and MC<M,n> are connected to each other at a distance.<M,n> It also functions as part of the wiring SOTL <n>In the central part of the memory cells MC<0,n> to MC<M,n> The part connected to one of the first ends of the wiring SOTL is also called a "cell part." <n>The central part between two adjacent cell parts is also called the "wiring part."

[0033] Memory cells MC<0,n> to MC<M,n> The second ends of the read word lines RWL <0> ~RWL <m>The memory cells MC<0,n> to MC<M,n> Each of the memory cells MC<m,n> This will be explained using an example.

[0034] Memory cell MC<m,n> is wiring SOTL <n>Among them, memory cells MC<m,n> The cell section connected to the switching element SEL2<m,n> , and magnetoresistive element MTJ<m,n> Includes:

[0035] Switching element SEL2<m,n> is, for example, a two-terminal switching element.<m,n> is a magnetoresistive element (MTJ)<m,n> a first end connected to the read word line RWL; <m>and a second end connected to the first terminal. For example, when the voltage applied between the two terminals is equal to or lower than a threshold, the switching element SEL2 is in a "high resistance" state, e.g., an electrically non-conductive state (off state). When the voltage applied between the two terminals is equal to or higher than a threshold, the switching element SEL2 is in a "low resistance" state, e.g., an electrically conductive state (on state). The switching element SEL2 may have this function regardless of the polarity of the voltage. In other words, the switching element SEL2 may have the above function regardless of the polarity, whether a positive voltage or a negative voltage is applied. By turning the switching element SEL2 on or off, it is possible to control whether a current is supplied to the magnetoresistive element MTJ connected to the switching element SEL2, i.e., whether the magnetoresistive element MTJ is selected or not.

[0036] Magnetoresistive element MTJ<m,n> is the switching element SEL2<m,n> and wiring SOTL <n>Among them, memory cells MC<m,n> The magnetoresistive element MTJ is connected in series between the cell section connected to the<m,n> is a resistance change element. Magnetoresistive effect element MTJ<m,n> functions as a memory element that stores data in a nonvolatile manner by changing its resistance state.

[0037] As described above, each memory string MS includes (M+1) memory cells MC connected to one wiring SOTL. Therefore, the memory cell array 10 has (N+1) memory strings MS, and thus has (M+1)×(N+1) memory cells MC<0,0>, ..., MC<0,n>, ..., MC<0,N>, ..., MC<m,0> , ..., MC<m,n> , ..., MC<m,N> , ..., MC<M,0> , ..., MC<M,n> , …, and MC<M,N> The configuration includes:

[0038] Switching element TR1 <0> ~TR1 <n>Each of the switching elements TR1 and TR2 is a three-terminal switching element such as a MOSFET. <0> ~Switching element TR1 <n>Each of the switching elements TR1 and TR2 has the same configuration. <n>This will be explained using an example.

[0039] Switching element TR1 <n>is wiring SOTL <n>a first end connected to the write bit line WBL <n>and a control terminal connected to the write word line WWL. <n>is the write bit line WBL <n>Wire the voltage applied to SOTL <n>It is possible to control whether or not the data is transferred to the

[0040] FIG. 3 shows an example of a planar layout of the memory cell array 10 of the magnetic memory device 1 according to the first embodiment. FIG. 3 shows an extracted area that functions as one block BLK (or string unit SU). The memory cell array 10 includes a plurality of members SLT, a plurality of memory pillars MP, a plurality of contacts CC, a plurality of read word lines RWL, and a plurality of read bit lines RBL. As shown in FIG. 3, the memory cell array 10 also includes, for example, a memory area MA and a lead-out area (wiring lead-out area) HA. The memory area MA and the lead-out area HA are aligned along the X direction. For example, the lead-out area HA is provided at the end of the memory area MA on the −X direction side. The lead-out area HA may be provided at each of the ends of the memory area MA on the +X direction side and the −X direction side.

[0041] The memory area MA is an area that essentially holds data, and is provided with a plurality of memory pillars MP.

[0042] The lead-out area HA is an area where wirings and contact plugs for connecting various wirings connected to the memory pillars MP provided in the memory area MA and, for example, the row decoder 11 are provided.

[0043] In the lead-out area HA, the read word line RWL <0> ~RWL <m>Each of these has a portion (terrace portion) at its end that does not overlap with the upper wiring layer (conductor layer). This portion that does not overlap with the upper wiring layer has a step shape.

[0044] Specifically, the read word line RWL <0> and the read word line RWL <1> Between the read word line RWL and <1> and the read word line RWL <2> Between , , and the read word line RWL <m-1>and the read word line RWL <m>A step is provided between each of the above.

[0045] The multiple members SLT each extend along the X direction and are aligned in the Y direction. The members SLT have a structure in which an insulating member is embedded inside. The members SLT are provided in the same wiring layer and separate adjacent conductor layers via the members SLT.

[0046] Each of the multiple memory pillars MP functions as, for example, one memory string MS. The multiple memory pillars MP are aligned, for example, in the X direction in the region between adjacent members SLT. However, this is not limiting, and the number and arrangement of memory pillars MP between adjacent slits can be changed as appropriate.

[0047] Furthermore, one read bit line RBL overlaps each memory pillar MP. For example, the multiple read bit lines RBL each extend in the Y direction and are arranged in the X direction. The read bit line RBL overlapping a memory pillar MP is electrically connected to the memory pillar MP.

[0048] The contacts CC are connected to the read word lines RWL in the lead-out area HA. <0> ~RWL <m>The contact plugs CC are formed of, for example, silicon doped with phosphorus or a metal material such as tungsten. The read word line RWL <0> ~RWL <m>are electrically connected to the row decoder 11 via contacts CC connected to each other. That is, the row decoder 11 and the stacked wiring (for example, the read word line RWL) connected to the memory string MS are connected via the contacts CC.

[0049] In the planar layout of the memory cell array 10 of the magnetic memory device 1 described above, an area partitioned by the member SLT functions as one block BLK. In the memory cell array 10, a layout corresponding to one block BLK shown in, for example, FIG. 3 is repeatedly arranged in the Y direction. One memory pillar MP is electrically connected to one read bit line RBL for each space partitioned by the member SLT.

[0050] Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3, showing an example of the cross-sectional structure of the magnetic memory device 1 according to the first embodiment. Fig. 4 and subsequent figures show an example in which the number of read word lines RWL is 10 (M=9). As shown in Fig. 4, the magnetic memory device 1 includes a semiconductor substrate 20, conductor layers 24-27, a plurality of stacked wiring layers LL functioning as read word lines RWL0-RWL9, insulator layers 30-34, a plurality of members SLT, a memory pillar MP, contacts CV and CS, and a switching element TR1.

[0051] An insulator layer 30 is provided on a semiconductor substrate 20. The insulator layer 30 includes, for example, silicon oxide (SiO2). Although not shown in the figure, a circuit region is provided in a part of the semiconductor substrate 20 and in the insulator layer 30, and a memory cell array 10 is provided above the insulator layer 30. In the circuit region, for example, circuits used for a row decoder 11, a sense amplifier 15, etc. are formed. The circuit region includes a switching element TR1, conductive layers 25 to 27, and a contact CS.

[0052] The switching element TR1 includes a gate electrode GC, source / drain regions NN, and an insulator layer OX. The gate electrode GC is provided on the upper surface of the semiconductor substrate 20 via a gate insulator. The source / drain regions NN sandwich an area below the gate electrode GC within the surface area of ​​the semiconductor substrate 20. The insulator layer OX covers the side surfaces of the gate electrode GC.

[0053] One of the source / drain regions NN is connected to the conductor layer 25 via a pillar-shaped contact CS. The other of the source / drain regions NN is connected to the conductor layer 27 via a contact CS. The gate electrode GC is connected to the conductor layer 26 via a contact CS.

[0054] An insulator layer 31 is provided on the insulator layer 30. The insulator layer 31 includes, for example, silicon oxide (SiO2).

[0055] Stacked wiring layers LL and insulator layers 32 are stacked alternately above the insulator layer 31. The stacked wiring layers LL are formed in the shape of a plate extending along the XY plane, for example. The stacked multiple stacked wiring layers LL are used as read word lines RWL0 to RWL9, in order from the semiconductor substrate 20 side. Details of the stacked wiring layers LL will be described later with reference to FIG. 6. The insulator layer 32 includes, for example, silicon oxide.

[0056] An insulating layer 33 is provided above the uppermost stacked wiring layer LL. The insulating layer 33 includes, for example, silicon oxide. A conductive layer 24 is provided on the insulating layer 33. The conductive layer 24 is formed, for example, in a line shape extending in the Y direction. The conductive layer 24 is used as a read bit line RBL. In a region not shown, multiple conductive layers 24 are arranged along the X direction. The conductive layer 24 includes, for example, copper (Cu).

[0057] An insulator layer 34 is provided on the conductor layer 24. The insulator layer 34 includes, for example, silicon oxide. The insulator layer 34 may include wiring and the like for connecting the memory cell array 10 to the row decoder 11 and the sense amplifier 15.

[0058] Each of the multiple memory pillars MP extends along the Z direction and penetrates the insulator layers 31 to 32 and the stacked wiring layer LL. The upper end of each memory pillar MP is included in the insulator layer 33. The lower end of each memory pillar MP is in contact with the conductor layer 25.

[0059] The portion of the memory pillar MP that intersects with the stacked wiring layer LL functions as a cell portion CP (shown in FIG. 6). The shape of the memory pillar MP at the portion where the stacked wiring layer LL and the memory pillar MP intersect is different from the shape of the memory pillar MP in other portions. For example, the diameter of the memory pillar MP at the portion where the stacked wiring layer LL and the memory pillar MP intersect is larger than the diameter of the memory pillar MP in other portions. This will be described in detail later with reference to FIG. 5.

[0060] Each memory pillar MP includes, for example, a core member 40, an SOT layer 41, and a magnetoresistive effect element MTJ. The core member 40 extends along the Z direction and is provided in the center of the memory pillar MP. For example, the upper end of the core member 40 is included in a layer above the layer in which the uppermost laminated wiring layer LL is provided. The lower end of the core member 40 is in contact with the conductor layer 25. The core member 40 includes an insulator such as silicon oxide.

[0061] The SOT layer 41 covers, for example, the periphery of the core member 40. For example, the bottom surface of the SOT layer 41 is in contact with the conductive layer 25. Details of the SOT layer 41 will be described later with reference to FIG.

[0062] The magnetic memory device 1 according to the first embodiment may have a structure in which the SOT layer 41 is buried up to the center without having the core member 40. Such a structure will be described later in a modified example.

[0063] The magnetoresistive element MTJ has a cylindrical shape that covers the periphery of the SOT layer 41 at the intersection of the memory pillar MP and the laminated wiring layer LL. Details of the magnetoresistive element MTJ will be described later with reference to FIG.

[0064] In the structure of the memory pillar MP described above, the portion where the memory pillar MP intersects with one laminated wiring layer LL functions as one memory cell MC.

[0065] A pillar-shaped contact CV is provided on the upper surface of the SOT layer 41. The contact CV is electrically connected to a nonmagnetic layer 412 (described later) in the SOT layer 41.

[0066] One conductive layer 24, i.e., one read bit line RBL, is in contact with the top surface of the contact CV. One conductive layer 24 is connected to one contact CV in each space separated by the members SLT. In other words, each conductive layer 24 is electrically connected to the memory pillar MP provided between adjacent members SLT.

[0067] The member SLT has, for example, a plate-shaped portion provided along the XZ plane, and divides the stacked wiring layer LL and the insulating layers 31 to 32 in the Y direction.

[0068] The circuit configuration and cross-sectional structure of the magnetic memory device 1 according to the first embodiment are not limited to the above-described structure. In the description of FIG. 2 and subsequent figures, for example, an example is shown in which the switching element TR1 is disposed on the semiconductor substrate 20 provided on the lower side (-Z side) of the stacked wiring structure, but the present invention is not limited to this. The switching element TR1 may be provided on the upper side of the stacked wiring structure, for example.

[0069] The switching element TR1 may be configured as a two-terminal switching element.

[0070] 5 is a cross-sectional view taken along line VV in FIG. 3, showing an example of the cross-sectional structure of the magnetic memory device 1 according to the first embodiment. As shown in FIG. 5, the magnetic memory device 1 further includes conductive layers 22 and 37.

[0071] In the lead-out region HA, the ends of the plurality of stacked wiring layers LL are provided in a stepped shape. In the lead-out region HA, the memory cell array 10 further includes a plurality of conductive layers 37.

[0072] One contact CC is provided on each terrace portion of the plurality of stacked wiring layers LL. One conductor layer 37 is provided on each contact CC, and the contact CC and the conductor layer 37 are electrically connected to each other.

[0073] A conductive layer 22 is provided between the semiconductor substrate 20 and the bottom conductive layer 23 of the memory area MA. The conductive layer 22 is formed, for example, in a line shape extending in the Y direction and is used as at least a part of the source line SL. For example, the conductive layer 27 shown in FIG. 4 functions as at least a part of the write bit line WBL and is connected to the conductive layer 22.

[0074] The configuration of the memory cell array 10 in the lead-out region HA is not limited to that described above. For example, the end of the stacked multilayer wiring layer LL may have a step in the Y direction. The end of the stacked multilayer wiring layer LL in the lead-out region HA may have a stepped shape with any number of columns.

[0075] 6 is an enlarged view of region VI in FIG. 4, showing an example of the cross-sectional structure of a memory pillar MP in the magnetic memory device 1 according to the first embodiment. FIG. 6 shows a part of the memory pillar MP, illustrating the structure of the stacked wiring layer LL and the region of the memory pillar MP that intersects with this stacked wiring layer LL. The memory pillar MP extends along the Z direction and has portions that protrude in the XY directions. The portions that protrude in the XY directions are magnetoresistive effect elements MTJ.

[0076] The SOT layer 41 includes, for example, a nonmagnetic layer 411 and a nonmagnetic layer 412. As described above, the core member 40 extends along the Z direction and is provided in the center of the memory pillar MP. The nonmagnetic layer 411 is provided, for example, on a side surface of the core member 40 and has, for example, a cylindrical shape. The nonmagnetic layer 411 is a nonmagnetic, high-resistance conductive film or insulating film. The nonmagnetic layer 411 functions as a protection layer for protecting the nonmagnetic layer 412 from oxidation when the nonmagnetic layer 412 described below is formed. The nonmagnetic layer 411 also functions as a cap layer for the nonmagnetic layer 412 described below. From the viewpoint of improving film adhesion, the nonmagnetic layer 411 includes, for example, tantalum (Ta), tungsten (W), titanium (Ti), or silicon (Si), or a nitride film thereof, such as tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or silicon nitride (SiN).

[0077] The nonmagnetic layer 412 is provided on the side surface of the nonmagnetic layer 411 and has, for example, a cylindrical shape. The nonmagnetic layer 412 functions as a wiring SOTL. A portion of the nonmagnetic layer 412 that intersects with the magnetoresistive element MTJ is used as at least a part of the cell portion CP. A portion of the nonmagnetic layer 412 that does not intersect with the magnetoresistive element MTJ is used as a wiring portion.

[0078] The nonmagnetic layer 412 includes a heavy metal that is nonmagnetic and conductive. The nonmagnetic layer 412 includes at least one element selected from, for example, Ta, α-tungsten (α-W), β-tungsten (β-W), bismuth (Bi), antimony (Sb), iridium (Ir), platinum (Pt), and gold (Au). The nonmagnetic layer 412 includes, for example, BiSb, a Bi alloy, an Sb alloy, or Sb with arsenic (As) added. The nonmagnetic layer 412 may be configured as a single layer including the above-mentioned material, or may be configured as a stack of multiple layers including the above-mentioned material.

[0079] The nonmagnetic layer 412 is a layer that generates a spin orbit torque (SOT) caused mainly by the spin Hall effect due to the current flowing therein. The spin orbit torque acts on a portion of the magnetoresistive element MTJ that is in contact with the nonmagnetic layer 412 (a ferromagnetic layer 421 described later). To obtain a large spin orbit torque, it is necessary to increase the current flowing through the nonmagnetic layer 412, that is, to increase the current density. To ensure the required current density, for example, the radial thickness of the nonmagnetic layer 412 is controlled. The radial direction is the direction that penetrates the cylindrically arranged layers in the memory pillar MP. In other words, the radial direction is the direction perpendicular to the circumferential direction of the cylindrically arranged layers in the memory pillar MP.

[0080] The SOT layer 41 may further include a non-magnetic layer 413 (not shown) between the non-magnetic layer 412 and the magnetoresistive element MTJ at the interface between the non-magnetic layer 412 and the ferromagnetic layer 421. The non-magnetic layer 413 includes, for example, an oxide or a nitride. The non-magnetic layer 413 includes, for example, an oxide having a NaCl structure such as magnesium oxide (MgO) or nickel oxide (NiO), or an oxide with a spinel structure such as magnesium aluminum oxide (MgAlO).

[0081] The magnetoresistive element MTJ includes, for example, a ferromagnetic layer 421, a non-magnetic layer 422, a ferromagnetic layer 423, and a non-magnetic layer 424.

[0082] The ferromagnetic layer 421 is provided on the side surface of the nonmagnetic layer 412 in the layer including the stacked wiring layer LL, and has a cylindrical shape. The ferromagnetic layer 421 is electrically connected to the nonmagnetic layer 412. When the nonmagnetic layer 413 is provided, the nonmagnetic layer 413 has a thickness that allows electrical connection between the nonmagnetic layer 412 and the ferromagnetic layer 421. The ferromagnetic layer 421 is a conductive film having ferromagnetism. The ferromagnetic layer 421 is used as a storage layer. The spin-orbit torque generated in the nonmagnetic layer 412 acts on the ferromagnetic layer 421.

[0083] The ferromagnetic layer 421 is, for example, a ferromagnetic layer containing cobalt (Co), and typical examples include a cobalt-iron alloy (CoFe) and a cobalt-iron-boron alloy (CoFeB). More specifically, the ferromagnetic layer 421 includes, for example, a ferromagnetic material containing Co, CoFe, or CoFeB formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition). The ferromagnetic layer 421 also includes, for example, nickel-iron (NiFe), nickel (Ni), or cobalt-iron (CoFe) formed by a plating method.

[0084] The nonmagnetic layer 422 covers the surface of the ferromagnetic layer 421 except for the portion where the ferromagnetic layer 421 and the nonmagnetic layer 412 contact each other. The nonmagnetic layer 422 is an insulating film having nonmagnetic properties. The nonmagnetic layer 422 is used as a tunnel barrier layer. The nonmagnetic layer 422 is provided between the ferromagnetic layer 421 and the ferromagnetic layer 423, and forms a magnetic tunnel junction together with these two ferromagnetic layers 421 and 423. That is, a magnetoresistance effect occurs in the magnetic tunnel junction portion.

[0085] The non-magnetic layer 422 includes, for example, boron nitride (BN) or aluminum nitride (AlN). The non-magnetic layer 422 includes, for example, hexagonal boron nitride (h-BN) or hexagonal aluminum nitride (h-AlN). More specifically, the non-magnetic layer 422 includes, for example, BN or AlN formed by ALD or CVD. The non-magnetic layer 422 may also include oxides such as magnesium oxide (MgO) or aluminum oxide Al2O3 having a NaCl structure, or magnesium aluminum oxide (Mg2AlO3) having a spinel structure. The non-magnetic layer 422 may be formed by CVD or ALD.

[0086] The ferromagnetic layer 423 is provided on the side surface of the nonmagnetic layer 422 and has, for example, a cylindrical shape. The ferromagnetic layer 423 is a conductive film having ferromagnetic properties. The ferromagnetic layer 423 is used as a reference layer.

[0087] The ferromagnetic layer 423 is a ferromagnetic layer containing, for example, cobalt (Co), and is typically made of a cobalt-iron alloy (CoFe) or a cobalt-iron-boron alloy (CoFeB). More specifically, the ferromagnetic layer 421 contains, for example, a ferromagnetic material containing Co, CoFe, or CoFeB formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition). The ferromagnetic layer 423 also contains, for example, nickel-iron (NiFe), nickel (Ni), or cobalt-iron (CoFe) formed by a plating method.

[0088] The nonmagnetic layer 424 covers the surface of the ferromagnetic layer 423 except for the portion where the ferromagnetic layer 423 and the nonmagnetic layer 422 contact each other. The nonmagnetic layer 424 is a conductive film having nonmagnetic properties. The nonmagnetic layer 424 functions as an underlayer for the ferromagnetic layer 423. The nonmagnetic layer 424 can prevent the ferromagnetic layer 423 from coming into direct contact with the stacked wiring layer LL.

[0089] The nonmagnetic layer 424 contains at least one element selected from the group consisting of tantalum (Ta), tungsten (W), and titanium (Ti). More specifically, the nonmagnetic layer 424 contains, for example, tantalum (Ta), tungsten (W), titanium (Ti), or nitrides thereof formed by ALD or CVD.

[0090] Furthermore, a layer containing silicon (Si) may be further provided between the nonmagnetic layer 424 and the laminated wiring layer LL.

[0091] In this way, the magnetoresistive element MTJ has a structure in which, for example, the ferromagnetic layer 421 and the nonmagnetic layer 422 are in contact with the SOT layer 41, but the ferromagnetic layer 423 and the nonmagnetic layer 424 are not in contact with the SOT layer 41. In other words, for example, the ferromagnetic layer 421 is in contact with the nonmagnetic layer 412. The nonmagnetic layer 422 is provided between the insulator layer 32 and the ferromagnetic layer 421, and has a portion in contact with the nonmagnetic layer 412. The ferromagnetic layer 423 is not in contact with the nonmagnetic layer 412. Other structures will be described later in the second embodiment.

[0092] The laminated wiring layer LL includes a conductor layer 23 and a switching layer 43. The conductor layer 23 is provided, for example, in the shape of a plate extending along the XY plane. The conductor layer 23 includes, for example, tungsten (W) or molybdenum (Mo). The conductor layer 23 mainly functions as a read word line RWL.

[0093] The switching layer 43 covers the surface of the conductor layer 23 except for the portion where the conductor layer 23 contacts the member SLT (not shown). The switching layer 43 has portions provided between the conductor layer 23 and the nonmagnetic layer 424 and between the conductor layer 23 and the insulating layer 32. The switching layer 43 includes a layer that functions as a selector for the memory cell MC. That is, the switching layer 43 functions as a switching element SEL2 in the memory cell MC. The switching layer 43 has an underlayer 431, a variable resistance material layer 432, and a cap layer 433.

[0094] The cap layer 433 covers the surface of the conductor layer 23 except for the portion where the conductor layer 23 contacts the member SLT (not shown). The cap layer 433 contains, for example, Ta, W, Ti, TaN, WN, TiN, or α-carbon (α-C). The cap layer 433 may be composed of a single layer containing the above-mentioned material, or may be composed of a plurality of layers containing the above-mentioned material stacked together. The cap layer 433, for example, improves the adhesion between the conductor layer 23 and the switching layer 43. The cap layer 433 functions, for example, as a barrier metal layer for the conductor layer 23. The cap layer 433 can prevent, for example, W contained in the conductor layer 23 from diffusing into the adjacent insulator layer 32 or the like.

[0095] The variable resistance material layer 432 covers the periphery of the cap layer 433 except for the portion where the cap layer 433 contacts the member SLT (not shown).

[0096] The variable resistance material layer 432 includes at least one chalcogen element selected from the group consisting of tellurium (Te), selenium (Se), and sulfur (S), for example. Alternatively, the variable resistance material layer 432 may include a chalcogenide, which is a compound containing the above chalcogen element. Similarly, the variable resistance material layer 432 may further include at least one element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb).

[0097] The variable resistance material layer 432 can also be a pn junction material using silicon (Si) and germanium (Ge).

[0098] The underlayer 431 covers the periphery of the variable resistance material layer 432, except for the portion where the variable resistance material layer 432 contacts the member SLT (not shown). The underlayer 431 is provided, for example, between the variable resistance material layer 432 and the nonmagnetic layer 424 and between the variable resistance material layer 432 and the insulating layer 32. The underlayer 431 contains, for example, Ta, W, Ti, TaN, WN, TiN, or α-C. The underlayer 431 may be formed as a single layer containing the above-mentioned material, or may be formed by stacking multiple layers containing the above-mentioned material. The underlayer 431 improves, for example, the adhesion between the magnetoresistive effect element MTJ and the switching layer 43. The underlayer 431 can also function, for example, as a barrier metal layer for the conductive layer 23. The underlayer 431 can prevent, for example, W contained in the conductive layer 23 from diffusing into the adjacent insulating layer 32, etc.

[0099] The switching layer 43 is, for example, a two-terminal switching element, with a first terminal corresponding to the surface of the cap layer 433 that contacts the conductive layer 23, and a second terminal corresponding to the surface of the underlayer 431 that contacts the insulator layer 32 and the nonmagnetic layer 424. When the voltage applied between the two terminals is equal to or lower than a threshold, the switching element is in a "high resistance" state, for example, an electrically non-conductive state (off state). When the voltage applied between the two terminals is equal to or higher than the threshold, the switching element changes to a "low resistance" state, for example, an electrically conductive state (on state).

[0100] The above-described structure of the switching layer 43 is an example, and the switching layer 43 may have any other structure as long as it functions as a two-terminal switching element. The switching layer 43 may use, for example, a snapback switching selector, a nonlinear IV selector, a unipolar diode based on a pn junction, or a bipolar diode. In other words, the switching layer 43 may use a selector having a nonlinear current-voltage characteristic, a selector having a snapback characteristic, or a diode. An example of the voltage and current characteristics of the memory cell MC when a selector having a snapback characteristic is used in the switching layer 43 will be described later with reference to FIG. 7.

[0101] The above-described structure of the magnetoresistive element MTJ is merely an example, and the magnetoresistive element MTJ may have other structures. For example, the nonmagnetic layer 422 may further include a portion (hereinafter, sometimes referred to as the nonmagnetic layer 422a) provided on the side of the nonmagnetic layer 412 in the layer including the insulator layer 32. In other words, the nonmagnetic layer 422 may further include the nonmagnetic layer 422a, which is a portion sandwiched between the insulator layer 32 and the nonmagnetic layer 412. The nonmagnetic layer 422a may be provided on the entire side of the nonmagnetic layer 412 in the layer including the insulator layer 32, or may be provided on only a portion of the side of the nonmagnetic layer 412. In other words, the nonmagnetic layer 422 may or may not be provided continuously in the layer including the insulator layer 32 and the layer including the stacked wiring layer LL. The magnetoresistive element MTJ may include additional layers.

[0102] FIG. 7 shows an example of a curve of the voltage and current characteristics of a memory cell of the magnetic memory device 1 according to the first embodiment. The switching element SEL2 (switching layer 43) may have a snapback characteristic as shown in FIG. 7. The horizontal axis of the graph indicates the magnitude of the terminal voltage of the memory cell MC (i.e., the difference in potential between both ends). The vertical axis of the graph indicates the magnitude of the current flowing through the memory cell MC on a logarithmic scale. FIG. 7 shows hypothetical characteristics that do not actually appear using dashed lines. FIG. 7 shows the cases when the memory cell MC is in a low resistance state and a high resistance state.

[0103] When the voltage is increased from 0, the current continues to increase until it reaches the threshold voltage Vth. Until the voltage reaches the threshold voltage Vth, the switching element SEL2 of the memory cell MC is off, that is, non-conductive.

[0104] When the voltage is further increased and reaches the threshold voltage Vth, i.e., point A, the relationship between voltage and current shows a discontinuous change, exhibiting the characteristics shown at points B1 and B2. The magnitude of the current at points B1 and B2 is significantly larger than the magnitude of the current at point A. This sudden change in current is due to the switching element SEL2 of the memory cell MC being turned on. The magnitude of the current at points B1 and B2 depends on the resistance state of the MTJ element MTJ of the memory cell MC.

[0105] When the voltage is reduced from a state in which the switching element SEL2 is on, for example, a state in which the voltage and current show the relationship shown at point B1 or point B2 and points with higher voltages than these, the current continues to decrease.

[0106] When the voltage is further reduced and reaches a certain magnitude, the voltage-current relationship shows a discontinuous change. The voltage at which the voltage-current relationship begins to show a discontinuity depends on the terminal voltage of the MTJ element MTJ of the memory cell MC, i.e., on whether the MTJ element MTJ is in a high-resistance state or a low-resistance state. When the MTJ element MTJ is in a low-resistance state, the voltage-current relationship shows a discontinuity from point C1. When the MTJ element MTJ is in a high-resistance state, the voltage-current relationship shows a discontinuity from point C2. When the voltage-current relationship reaches points C1 and C2, it begins to show the characteristics shown by points D1 and D2, respectively. The magnitudes of the current at points D1 and D2 are significantly smaller than the magnitudes of the current at points C1 and C2, respectively. This sudden change in current is due to the switching element SEL2 of the memory cell MC being turned off.

[0107] The terminal voltage at point D1 of the memory cell MC including the MTJ element MTJ in the low resistance state is referred to as a low hold voltage VhdL, and the terminal voltage at point D2 of the memory cell MC including the MTJ element MTJ in the high resistance state is referred to as a high hold voltage VhdH.

[0108] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6, showing an example of the cross-sectional structure of a memory pillar MP in the magnetic memory device 1 according to the first embodiment. Specifically, FIG. 8 shows the cross-sectional structure of a memory pillar MP in a layer parallel to the surface of the semiconductor substrate 20 and including the conductive layer 23. The upper part (A) of FIG. 8 shows an example in which the magnetoresistive element MTJ is in a low resistance state. The lower part (B) of FIG. 8 shows an example in which the magnetoresistive element MTJ is in a high resistance state.

[0109] In a cross section including the conductive layer 23, the memory pillar MP has a core member 40 in the center. The SOT layer 41 surrounds the side surfaces of the core member 40. The ferromagnetic layer 421 surrounds the side surfaces of the SOT layer 41. The non-magnetic layer 422 surrounds the side surfaces of the ferromagnetic layer 421. The ferromagnetic layer 423 surrounds the side surfaces of the non-magnetic layer 422. The non-magnetic layer 424 surrounds the side surfaces of the ferromagnetic layer 423. The switching layer 43 surrounds the side surfaces of the non-magnetic layer 424. The conductive layer 23 surrounds the side surfaces of the switching layer 43.

[0110] The ferromagnetic layer 423 has an easy axis of magnetization that extends along the shape (or circumference) of the ferromagnetic layer 423 in the XY plane view (top view) seen from the +Z side. The magnetization direction of the ferromagnetic layer 423 is fixed. Note that "the magnetization direction is fixed" means that the magnetization direction does not change due to a torque large enough to reverse the magnetization direction of the ferromagnetic layer 421. In the example of FIG. 8, the magnetization direction of the ferromagnetic layer 423 is clockwise along the easy axis of magnetization in the top view.

[0111] The ferromagnetic layer 421 has an easy axis of magnetization that extends along the shape (or circumference) of the ferromagnetic layer 421 in the XY plane view (top view) seen from the +Z side. A spin-orbit torque generated in the nonmagnetic layer 412 acts on the ferromagnetic layer 421. The ferromagnetic layer 421 is configured to reverse its magnetization direction when a voltage Vw0 or Vw1 (described later in FIG. 9) of a predetermined magnitude is applied and a spin-orbit torque of the predetermined magnitude acts.

[0112] The magnetoresistive element MTJ can be in either a low resistance state or a high resistance state depending on whether the relative relationship between the magnetization directions of the storage layer (ferromagnetic layer 421) and the reference layer (ferromagnetic layer 423) is parallel or antiparallel.

[0113] The upper part (A) of FIG. 8 shows an example in which the magnetoresistive element MTJ is in a low resistance state. At this time, the ferromagnetic layer 421 has a magnetization that is oriented clockwise in the XY plane view (top view) seen from the +Z side. That is, the relative relationship between the magnetization directions of the storage layer (ferromagnetic layer 421) and the reference layer (ferromagnetic layer 423) is parallel. In this parallel state, the resistance value of the magnetoresistive element MTJ is the lowest, and the magnetoresistive element MTJ is set to a low resistance state. This low resistance state is called a "P (Parallel) state" and is defined as, for example, a data "0" state.

[0114] The lower part (B) of FIG. 8 shows an example in which the magnetoresistive element MTJ is in a high-resistance state. At this time, the ferromagnetic layer 421 has a magnetization that is oriented counterclockwise in the XY plane (top view) viewed from the +Z side. That is, the relative relationship between the magnetization directions of the storage layer (ferromagnetic layer 421) and the reference layer (ferromagnetic layer 423) is antiparallel. In this antiparallel state, the resistance value of the magnetoresistive element MTJ is the highest, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called an "AP (Anti-Parallel) state" and is defined as, for example, a data "1" state.

[0115] The way in which data "1" and data "0" are defined is not limited to the above example. For example, the P state may be defined as data "1" and the AP state may be defined as data "0."

[0116] Next, the operation of the magnetic memory device according to the first embodiment will be described.

[0117] First, a first example of a write operation will be described. In the magnetic memory device 1, the magnetization direction of the storage layer relative to the magnetization direction of the reference layer is controlled by utilizing the voltage control magnetic anisotropy (VCMA) effect and spin-orbit torque. Specifically, a write method is adopted that utilizes the VCMA effect generated by applying a voltage to the read word line RWL and the spin-orbit torque generated by passing a current through the wiring SOTL.

[0118] 9 is a diagram showing an example of voltages applied to the memory cell array in a first example of a write operation in the magnetic memory device according to the first embodiment. In FIG. 9, as a first example of a write operation, a write current Ic0 is passed through the wiring SOTL to write data "0". In FIG. 9, the selected memory cell MC to be written (i.e., in a selected state) is the memory cell MC<m,n> is.

[0119] 9 shows a part of the memory cell array 10. That is, first, the selected memory cell MC<m,n> and the connected wiring SOTL <n>, selected read bit line RBL <n>, selected write bit line WBL <n>, and the selected read word line RWL <m>In addition, in FIG. 9, the selected memory cell MC<m,n> The wiring SOTL is representative of the wiring SOTL, the unselected read bit line RBL, the unselected write bit line WBL, and the unselected word line RWL. <n-1>and SOTL<n+1> , unselected read bit lines RBL <n-1>and non-selective RBLs<n+1> , unselected write bit line WBL <n-1>and WBL<n+1> , unselected read word lines RWL <m-1>and RWL<m+1> In the area not shown, the selected memory cell MC<m,n> The states of the wiring SOTL, the unselected read bit lines RBL, the unselected write bit lines WBL, and the unselected read word lines RWL that are not connected to the wiring SOTL are referred to as the wiring SOTL in the following description. <n-1>and SOTL<n+1> , read bit line RBL <n-1>and RBL<n+1> , write bit line WBL <n-1>and WBL<n+1> , read word line RWL <m-1>and RWL<m+1> This is the same as the state of

[0120] In FIG. 9, the switching elements SEL2 and TR1 in the ON state are each marked with a "◯", and the switching elements SEL2 and TR1 in the OFF state are each marked with an "X".

[0121] In addition, the selected memory cell MC<m,n> When performing a first example of a write operation on the read bit line RBL <n>and the write bit line WBL <n>The voltage Vc0 is applied to the wiring SOTL, and the voltage VSS is applied to the wiring SOTL. The voltage VSS is, for example, 0 V. The voltage Vc0 causes a write current Ic0 to flow through the wiring SOTL. <n>(not shown) flows in the wiring SOTL. <n>The read bit line RBL <n>and the write bit line WBL <n>The voltage applied to the read bit line RBL is controlled by the column decoder 12. <n-1>and the write bit line WBL <n-1>The voltage VSS is applied to the read bit line RBL.<n+1> and the write bit line WBL<n+1> The voltage VSS is applied to each of the wiring SOTL <n>The write current Ic0 does not flow through any of the other wirings SOTL.

[0122] In addition, the selected word line RWL <m>A voltage Vw0 is applied to the selected word line RWL. The voltage Vw0 is, for example, greater than the threshold voltage of the switching element TR1 and less than the breakdown voltage of the switching element TR1. Details of the voltage Vw0 will be described later with reference to FIG. 10. <m>The voltage applied to is controlled by a row decoder 11.

[0123] Unselected word line RWL <m-1>and RBL<m+1> A voltage VSS is applied to the

[0124] By applying the voltages as described above, the switching element SEL2<m,n> The switching element TR1 is turned on, and all other switching elements SEL2 are turned off. <n>is turned on, and all other switching elements TR1 are turned off.

[0125] Selected read word line RWL <m>When a voltage Vw0 is applied to the selected write bit line WBL <n>The selected memory cell MC<m,n> For example, current Iw0 <m>(not shown) flows. As described above, the switching element SEL2<m,n> is in the ON state, and all other switching elements SEL2 are in the OFF state, so that the current Iw0 does not flow through each of the other write bit lines WBL.

[0126] 10 is a diagram showing an example of the current and magnetization direction applied to the memory cell array in a first example of a write operation in the magnetic memory device according to the first embodiment.<m,n> Memory string MS including <n>This shows the following.

[0127] As described above, the selected read bit line RBL <n>and the selected write bit line WBL <n>The voltages Vc0 and VSS are applied to the wiring SOTL <n>In the nonmagnetic layer 412 functioning as <n>Write current Ic0 <n>The flow of current through the nonmagnetic layer 412 generates a spin-orbit torque that tries to make the magnetization direction of the ferromagnetic layer 421 parallel to the ferromagnetic layer 423. The spin-orbit torque acts on all of the ferromagnetic layers 421 in contact with the nonmagnetic layer 412.

[0128] As described above, the selected word line RWL <m>A voltage Vw0 is applied to the conductive layer 23, which functions as a magnetic field generating layer. As a result, a current Iw0 flows in the nonmagnetic layer 412 in the −Z direction. <m>Current Iw0 <m>is a magnetoresistive element (MTJ)<m,n> and switching element SEL2<m,n> via the selected read word line RWL <m>The current Iw0 flows from the conductive layer 23, which functions as a <m>The current value of the write current Ic0 <n>is smaller than the current value.

[0129] Here, the voltage Vw0 is applied to the selected memory cell MC<m,n> Magnetoresistive effect element MTJ<m,n> The voltage is for reducing the height of the energy barrier at the time of magnetization reversal of the ferromagnetic layer 421 included in the magnetoresistive effect element MTJ to the energy Ew0 or less, and has a magnitude for reducing the height of the energy barrier to the energy Ew0 or less.<m,n> The height of the energy barrier at the time of magnetization reversal of the ferromagnetic layer 421 included in the<m,n> It is sometimes referred to as.

[0130] When a voltage Vw0 is applied to the conductive layer 23, the energy barrier height ΔE<m,n> becomes equal to or less than the energy Ew0. The VCMA effect acts only on the ferromagnetic layer 421 on the read word line RWL to which the voltage Vw0 is applied.<m-1,n> and magnetoresistive element MTJ<m+1,n> The VCMA effect does not act on the ferromagnetic layer 421. Therefore, the energy barrier height ΔE<m-1,n> and ΔE<m+1,n> is a value greater than the energy Ew0.

[0131] Energy barrier height ΔE<m,n> When the energy is less than Ew0, the wiring SOTL <n>When a write current Ic0 flows through the selected memory cell MC, the magnetization direction of the ferromagnetic layer 421 becomes parallel to the ferromagnetic layer 423 due to the generated spin-orbit torque (the state shown in the upper part (A) of FIG. 8).<m,n> The magnetization direction of the ferromagnetic layer 421 is reversed to a direction parallel to the magnetization direction of the ferromagnetic layer 423. The VCMA effect caused by the voltage Vw0 is, for example, a change in the magnetization direction of the selected memory cell MC due to the spin-orbit torque.<m,n> This increases the speed at which the magnetization direction of the ferromagnetic layer 421 is reversed.

[0132] Also, E in Fig. 10<m-1,n> and ΔE<m+1,n> When the energy barrier height ΔE is greater than the energy Ew0, the wiring SOTL <n>Even if a write current Ic0 flows (even if a spin-orbit torque acts) in the ferromagnetic layer 421, the magnetization direction of the ferromagnetic layer 421 does not reverse.

[0133] By operating in this manner, the selected memory cell MC<m,n> Data "0" is written to

[0134] Next, a second example of the write operation will be described. Fig. 11 is a diagram showing an example of the current and magnetization direction applied to the memory cell array in the second example of the write operation in the magnetic memory device according to the first embodiment. Fig. 11 corresponds to Fig. 10 showing the first example of the write operation. Fig. 11 shows, as the second example of the write operation, a case where a write current Ic1 is passed through the wiring SOTL to write data "1".

[0135] Selected memory cell MC<m,n> When the second example of the write operation is performed on the memory string MS , the on or off state of the switching element SEL2 is the same as that of the first example of the write operation shown in FIG. <n>For the other memory strings MS, the second example of the write operation is similar to the first example of the write operation, and therefore the description will be omitted.

[0136] Selected read bit line RBL <n>and the selected write bit line WBL <n>The voltages VSS and Vc1 are applied to the wiring SOTL <n>In the nonmagnetic layer 412, which functions as a <n>Write current Ic1 <n>The flow of current through the nonmagnetic layer 412 generates a spin-orbit torque that tries to make the magnetization direction of the ferromagnetic layer 421 antiparallel to the ferromagnetic layer 423. The spin-orbit torque acts on all of the ferromagnetic layers 421 in contact with the nonmagnetic layer 412.

[0137] In addition, the selected word line RWL <m>A voltage Vw1 is applied to the conductive layer 23 that functions as a gate electrode. The voltage Vw1 is, for example, greater than the threshold voltage of the switching element TR1 and less than the breakdown voltage of the switching element TR1. As a result, a current Iw1 flows in the nonmagnetic layer 412 in the +Z direction. <m>Current Iw1 flows. <m>is a magnetoresistive element (MTJ)<m,n> and switching element SEL2<m,n> via the selected read word line RWL <m>The current Iw1 flows from the conductive layer 23, which functions as a <m>The current value of the write current Ic1 <n>is smaller than the current value.

[0138] Here, the voltage Vw1 is increased by the energy barrier height ΔE<m,n> is the voltage required to reduce the energy to Ew1 or less, and the energy barrier height ΔE<m,n> to the energy Ew1 or less.

[0139] When a voltage Vw1 is applied to the conductive layer 23, the energy barrier height ΔE<m,n> becomes equal to or less than the energy Ew1. The VCMA effect acts only on the ferromagnetic layer 421 on the read word line RWL to which the voltage Vw1 is applied.<m-1,n> and magnetoresistive element MTJ<m+1,n> The VCMA effect does not act on the ferromagnetic layer 421. Therefore, the energy barrier height ΔE<m-1,n> and ΔE<m+1,n> is a value greater than the energy Ew1.

[0140] Energy barrier height ΔE<m,n> When the energy is less than Ew1, the wiring SOTL <n>When a write current Ic1 flows through the selected memory cell MC, the magnetization direction of the ferromagnetic layer 421 becomes antiparallel to the ferromagnetic layer 423 due to the generated spin-orbit torque (the state shown in the lower part of FIG. 8B).<m,n> The magnetization direction of the ferromagnetic layer 421 is reversed to a direction antiparallel to the magnetization direction of the ferromagnetic layer 423. The VCMA effect caused by the voltage Vw1 is, for example, a spin-orbit torque applied to the selected memory cell MC<m,n> This increases the speed at which the magnetization direction of the ferromagnetic layer 421 is reversed.

[0141] Also, E in Fig. 11<m-1,n> and ΔE<m+1,n> When the energy barrier height ΔE is greater than the energy Ew1, the wiring SOTL <n>Even if the write current Ic1 flows (even if the spin-orbit torque acts), the magnetization direction of the ferromagnetic layer 421 does not reverse.

[0142] By operating in this manner, the selected memory cell MC<m,n> The data "1" is written to

[0143] Next, the read operation will be described. Fig. 12 is a diagram showing an example of voltages applied to the memory cell array in the read operation in the magnetic memory device according to the first embodiment. In the example of Fig. 12, the memory cell MC<m,n> An example in which data is read from a selected memory cell MC<m,n> and the connected wiring SOTL <n>, selected read bit line RBL <n>, selected write bit line WBL <n>, and the selected read word line RWL <m>As in the case of FIG. 9, the wiring SOTL <n-1>and SOTL<n+1> , unselected read bit lines RBL <n-1>and RBL<n+1> , unselected write bit line WBL <n-1>and WBL<n+1> , unselected read word lines RWL <m-1>and RWL<m+1> 9, an example of the voltage applied to each wiring is shown. Also, as in the case of FIG. 9, each of the switching elements SEL2 and TR1 in the ON state is marked with a "○", and each of the switching elements SEL2 and TR1 in the OFF state is marked with an "X".

[0144] Selected memory cell MC<m,n> When a read operation is performed on the selected read bit line RBL <n>A voltage VSS is applied to the unselected read bit lines RBL <n-1>and unselected write bit lines WBL <n-1>are deselected by the column decoder 12 and are in an electrically floating state.<n+1> and unselected write bit lines WBL<n+1> are deselected by the column decoder 12 and are in an electrically floating state.

[0145] In addition, the selected word line RWL <m>A voltage Vr is applied to the selected word line RWL. The voltage Vr is, for example, higher than the threshold voltage of the switching element TR1 and lower than the voltages Vw0 and Vw1. <m>Unselected word lines RWL located on both sides of <m-1>and RBL<m+1> A voltage VSS is applied to the

[0146] By applying the voltages as described above, the switching element SEL2<m,n> The switching element SEL1 is turned on, and all other switching elements SEL2 are turned off. All switching elements TR1 are turned off.

[0147] Selected read word line RWL <m>When a voltage Vr is applied to the selected read bit line RBL <n>The selected memory cell MC<m,n> For example, the read current Ir <m>(not shown) flows. <m>The current value of the write current Ic0 <n>and Ic1 <n>As mentioned above, the current value of the switching element SEL2 is smaller than that of the switching element SEL2.<m,n> is in the ON state, and all other switching elements SEL2 are in the OFF state, so that the read current Ir does not flow through each of the other selected read bit lines RBL.

[0148] 13 is a diagram showing an example of a current applied to the memory cell array in a read operation in the magnetic memory device according to the first embodiment. In FIG. 13, a memory cell MC<m,n> Memory string MS including <n>This shows the following.

[0149] As described above, the selected word line RWL <m>A voltage Vr is applied to the conductive layer 23, which functions as a read current Ir in the +Z direction in the nonmagnetic layer 412. <m>The read current Ir <m>is a magnetoresistive element (MTJ)<m,n> and switching element SEL2<m,n> via the selected read word line RWL <m>The magnetic flux flows from the conductive layer 23 functioning as a magnetic flux into the nonmagnetic layer 412 .

[0150] By flowing the read current Ir through the magnetoresistive element MTJ, the read circuit 13 can determine whether the magnetoresistive element MTJ is in a high-resistance state or a low-resistance state based on the read current Ir. The read current Ir is controlled to be smaller than the write currents Ic0 and Ic1.

[0151] Next, a method for manufacturing the magnetic memory device according to the first embodiment will be described. FIG. 14 is a flowchart showing an example of the method for manufacturing the magnetic memory device according to the first embodiment. Each of FIGS. 15 to 27 shows an example of a cross-sectional structure during the manufacturing process of the magnetic memory device 1 according to the first embodiment. Each of FIGS. 15 to 27 shows an area including a part of the area shown in FIG. 4. Below, an example of a manufacturing process for forming a stacked wiring structure in the memory cell array 10 in the magnetic memory device 1 according to the first embodiment will be described with reference to FIG. 14 as appropriate. As shown in FIG. 14, the method for manufacturing the magnetic memory device 1 according to the first embodiment sequentially performs the processes of steps S101 to S113, for example.

[0152] In the process of step S101, as shown in Fig. 15, sacrificial members and insulator layers are alternately stacked. First, an insulator layer 30 and an insulator layer 31 are formed in this order on a semiconductor substrate 20. A switching element TR1, conductor layers 25 to 27, and a contact CS are formed in a part of the semiconductor substrate 20 and in the insulator layer 30. A sacrificial member 51 and an insulator layer 32 are alternately stacked on the insulator layer 31. An insulator layer 33a is formed on the uppermost sacrificial member 51. Each of the insulator layers 30 to 33a and the sacrificial member 51 is formed by, for example, ALD or CVD.

[0153] The sacrificial members 51 are formed in regions where stacked wiring layers LL functioning as read word lines RWL are to be formed. For example, the number of layers on which the sacrificial members 51 are formed is equal to the number of read word lines RWL. Each of the insulator layers 30 to 33a includes, for example, silicon oxide. The sacrificial members 51 include, for example, silicon nitride.

[0154] In the process of step S102, holes MH are formed as shown in FIG. 16. FIG. 16 shows a region including a part of the region shown in FIG. 15, and in FIG. 16 and subsequent figures, the semiconductor substrate 20, switching element TR1, conductor layers 25-27, and contacts CS are not shown. For example, the holes MH are formed by RIE (Reactive Ion Etching). The holes MH penetrate each of the insulator layers 31-33a and the sacrificial member 51. The bottom of the holes MH reaches the conductor layer 25 in the insulator layer 30.

[0155] In the process of step S103, as shown in FIG. 17, a portion of the sacrificial member 51 is recessed. FIG. 17 shows a cross section of the same region as FIG. 16. Specifically, wet etching is performed through the holes MH to remove a portion of each of the multiple sacrificial members 51 exposed on the side surfaces of the holes MH. The etching solution contains, for example, phosphoric acid (H3PO4). As a result, the side surfaces of the holes MH are processed into a shape in which the sacrificial members 51 have been partially removed. The space created by removing the portion of the sacrificial member 51 in this process may be referred to as space RP1 below. The space RP1 is a region in which, for example, a magnetoresistive element MTJ or the like is to be formed.

[0156] In the process of step S104, a ferromagnetic layer 623 is formed as shown in FIG. 18. FIG. 18 shows a region including a part of the region shown in FIG. 17. FIG. 18 shows a part of the hole MH, and shows the structures of the sacrificial member 51 and the region of the hole MH that intersects with the sacrificial member 51. First, a nonmagnetic layer 424 is formed on the surface and bottom of the hole MH and on the surface exposed in the space RP1. Next, a ferromagnetic layer 623 is formed on the surface of the nonmagnetic layer 424. The ferromagnetic layer 623 fills the space RP1, for example. The nonmagnetic layer 424 and the ferromagnetic layer 623 are formed by, for example, ALD or CVD. By performing the process described below, the ferromagnetic layer 423 is formed from a part of the ferromagnetic layer 623.

[0157] In the process of step S105, the ferromagnetic layer 423 is formed as shown in FIG. 19. FIGS. 19 to 22 each show a cross section of the same region as FIG. 18. Wet etching is performed through the holes MH. The wet etching solution etches the ferromagnetic layer 623 and the nonmagnetic layer 424 formed in the holes MH. That is, the ferromagnetic layer 623 and the nonmagnetic layer 424 formed on the side surfaces of the insulating layer 32 are removed.

[0158] The ferromagnetic layer 623 and the nonmagnetic layer 424 formed on the layer including the sacrificial member 51 are each partially removed. The space created by removing the ferromagnetic layer 623 and the nonmagnetic layer 424 formed on the layer including the sacrificial member 51 in this step may be referred to as a space RP2 below. The space RP2 is a re-exposed portion of the space RP1. As a result, the side surface of the hole MH is processed into a shape in which the ferromagnetic layer 623 and the nonmagnetic layer 424 formed in step S104 have been partially removed. The ferromagnetic layer 623 after the etching process is performed is referred to as a ferromagnetic layer 423. In other words, the ferromagnetic layer 423 is formed by etching the ferromagnetic layer 623.

[0159] In the process of step S106, as shown in FIG. 20, a nonmagnetic layer 422 and a ferromagnetic layer 621 are formed. Specifically, first, an oxide film or the like unintentionally formed on the surface of the ferromagnetic layer 423 by the process of step S105 is removed. Next, a nonmagnetic layer 422 is formed on the surface of the ferromagnetic layer 423. Next, a ferromagnetic layer 621 is formed on the surface of the nonmagnetic layer 422. The nonmagnetic layer 422 and the ferromagnetic layer 621, for example, fill the space RP2. The nonmagnetic layer 422 and the ferromagnetic layer 621 are continuously formed in a vacuum by ALD or CVD. By performing the process described below, the ferromagnetic layer 421 is formed from a part of the ferromagnetic layer 621.

[0160] In the process of step S107, as shown in FIG. 21, a magnetoresistive element MTJ is formed. Specifically, wet etching is performed through the holes MH. The wet etching solution etches the ferromagnetic layer 621 and the nonmagnetic layer 422 formed in the holes MH. That is, the ferromagnetic layer 621 and the nonmagnetic layer 422 formed on the side surfaces of the insulating layer 32 are removed. The ferromagnetic layer 621 after the etching process is performed is referred to as the ferromagnetic layer 421. That is, the ferromagnetic layer 421 is formed by etching the ferromagnetic layer 621.

[0161] Here, ideally, the size of the periphery of the hole MH is substantially the same in the layer including the insulator layer 32 and the layer including the sacrificial member 51. That is, the position of the side surface of the ferromagnetic layer 421 exposed in the hole MH and the position of the side surface of the insulator layer 32 exposed in the hole MH are ideally substantially the same in the Z direction (in the XY plane view). However, the size of the periphery of the hole MH may vary due to, for example, a difference in etching rate between the insulator layer 32 and the ferromagnetic layer 421. For example, the size of the periphery of the hole MH may be larger in the layer including the sacrificial member 51 than in the layer including the insulator layer 32.

[0162] 21 illustrates the case where the nonmagnetic layer 422 formed on the side surface of the insulating layer 32 is removed, but part or all of the nonmagnetic layer 422 may remain. It is sufficient that the ferromagnetic layer 621 is removed from the side surface of the insulating layer 32.

[0163] In the process of step S108, as shown in FIG. 22, the SOT layer 41 and the core member 40 are formed. Specifically, first, a nonmagnetic layer 412 is formed on the exposed surface of the hole MH. The lower end of the nonmagnetic layer 412 is in contact with the conductive layer 25 (not shown) within the insulator layer 30. Next, a nonmagnetic layer 411 is formed on the surface of the nonmagnetic layer 412. Next, the hole MH is filled with the core member 40. The nonmagnetic layer 412, the nonmagnetic layer 411, and the core member 40 are formed by, for example, ALD or CVD. As a result, the memory pillar MP is formed.

[0164] In the process of step S109, slits SH are formed as shown in FIG. 23. FIG. 23 shows a cross section of the same region as FIG. 16. First, an insulator layer 33b is formed on the upper surfaces of the insulator layer 33a and the memory pillar MP. Hereinafter, a layer consisting of the insulator layer 33a and the insulator layer 33b may be referred to as the insulator layer 33. A slit SH is formed in the region where the member SLT is to be formed. Specifically, a mask having an opening in a region corresponding to the slit SH is formed by photolithography or the like, and the slit SH is formed by anisotropic etching using the mask. The slit SH divides, for example, the insulator layers 31 to 33 and the sacrificial member 51, and reaches the insulator layer 30.

[0165] In the process of step S110, the sacrificial member 51 is removed as shown in FIG. 24. FIG. 24 shows a cross section of the same region as FIG. 16. For example, the sacrificial member 51 is selectively removed through the slit SH by wet etching. The etching solution contains, for example, phosphoric acid (H3PO4). This forms a space in the region where the stacked wiring layer LL is to be formed. At this time, the magnetoresistive element MTJ has a nonmagnetic layer 424, which can prevent the etching solution from corroding the ferromagnetic layer 423. The three-dimensional structure of the structure from which the sacrificial member 51 has been removed is maintained by the multiple memory pillars MP.

[0166] In the process of step S111, a switching layer 43 is formed as shown in FIG. 25. FIG. 25 shows a cross section of the same region as FIG. 18. First, a base layer 431 is formed on the surface exposed in the space from which the sacrificial member 51 has been removed, through the slit SH. Next, a variable resistance material layer 432 is formed on the surface of the base layer 431, through the slit SH. Next, a cap layer 433 is formed on the surface of the variable resistance material layer 432, through the slit SH. The base layer 431, the variable resistance material layer 432, and the cap layer 433 are formed by, for example, ALD or CVD. As a result, the switching layer 43 is formed in part of the space from which the sacrificial member 51 has been removed.

[0167] In the process of step S112, the conductor layer 23 is formed as shown in FIG. 26. FIG. 26 shows a cross section of the same region as FIG. 18. The conductor layer 23 is formed on the surface of the cap layer 433 through the slit SH, and the space where the sacrificial member 51 has been removed is filled with the conductor layer 23. The conductor layer 23 is formed by, for example, ALD or CVD. Thereafter, the base layer 431, the variable resistance material layer 432, the cap layer 433, and the conductor layer 23 formed inside the slit SH are removed by an etch-back process. As a result, a plurality of stacked wiring layers LL functioning as read word lines RWL0 to RWL9 are formed.

[0168] In the process of step S113, a member SLT is formed as shown in FIG. 27. FIG. 27 shows a cross section of the same region as FIG. 16. First, the member SLT is embedded in the slit SH. Next, a contact CV is provided on the memory pillar MP. Next, a conductive layer 25 that functions as a read bit line RBL is formed on the contact CV (see FIG. 5).

[0169] The stacked wiring structure in the memory cell array 10 is formed by the manufacturing process of the magnetic memory device 1 according to the first embodiment described above. Note that the manufacturing process described above is merely an example and is not limited to this. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or integrated. Furthermore, the order of the manufacturing processes may be changed as long as no problems arise.

[0170] Furthermore, for example, when forming each layer of the magnetoresistive element MTJ via holes MH, each layer of the magnetoresistive element MTJ may be formed in a microcrystalline state such as amorphous to improve embedding properties. In this case, each layer of the magnetoresistive element MTJ may be formed by ALD.

[0171] Furthermore, for example, when forming each layer of the magnetoresistive element MTJ via holes MH, if selective formation is desired, such as forming the layer included in the magnetoresistive element MTJ thicker in the space RP1 or RP2 than on the side of the insulator layer 32, ALD may be used, for example.

[0172] Furthermore, for example, when forming each layer of the switching layer 43 through the slit SH, each layer of the switching layer 43 may be formed in a microcrystalline state such as amorphous to improve embedding properties. In this case, each layer of the switching layer 43 may be formed by ALD.

[0173] Furthermore, for example, in the above-described manufacturing method, an example in which the sacrificial member 51 is removed after the magnetoresistive effect element MTJ is formed has been described, but this is not limiting. The magnetoresistive effect element MTJ or a portion of the magnetoresistive effect element MTJ may be formed, for example, after the sacrificial member 51 is removed. That is, the magnetoresistive effect element MTJ or a portion of the magnetoresistive effect element MTJ may be formed through the slit SH. For example, when the ferromagnetic layer 423 is formed through the slit SH, it is no longer necessary to protect the ferromagnetic layer 423 from the etching solution in step S110, and therefore the formation of the nonmagnetic layer 424 may be omitted.

[0174] The effects of the magnetic memory device 1 according to the first embodiment will be described below.

[0175] According to the magnetic memory device 1 of the first embodiment, the magnetoresistive element MTJ has a circulating magnetization structure (closed magnetic circuit, closed magnetic path). That is, the ferromagnetic layer 421 and the ferromagnetic layer 423 are formed in a cylindrical shape, and magnetization circulates along the circumference. Therefore, no magnetic charge is generated at the ends of the ferromagnetic layer 421 and the ferromagnetic layer 423 in a static environment. Since no magnetic charge is generated at the ends of the ferromagnetic layer 421 and the ferromagnetic layer 423, the magnetoresistive element MTJ can have a structure that is stable against both heat and an external magnetic field.

[0176] Furthermore, in the magnetic memory device 1 according to the first embodiment, the ends of the ferromagnetic layers 421 and 423 have no magnetic charges, and therefore no leakage magnetic field is generated to the outside. Therefore, the magnetoresistive element MTJ does not cause magnetic field disturbance to adjacent bits. In other words, the structure of the magnetoresistive element MTJ in the magnetic memory device 1 can suppress disturbance from the ferromagnetic layers 421 and 423 to adjacent bits.

[0177] Furthermore, according to the magnetic memory device 1 of the first embodiment, the magnetoresistive element MTJ does not have an SAF (Synthetic Anti-Ferromagnetic) structure. That is, the magnetoresistive element MTJ does not have a shift canceling layer or a spacer layer on the outer periphery of the reference layer. In other words, the magnetoresistive element MTJ does not have a structure antiferromagnetically coupled to the ferromagnetic layer 423 between the ferromagnetic layer 423 and the stacked wiring layer LL. This is because, as described above, the ferromagnetic layer 421 and the ferromagnetic layer 423 do not generate a leakage magnetic field to the outside, and therefore an SAF structure for suppressing a leakage magnetic field from the ferromagnetic layer 423 to the ferromagnetic layer 421 is not necessary. As such, since the magnetoresistive element MTJ does not have an SAF structure, the structure can be simplified, the design can be facilitated, and the manufacturing cost can be reduced.

[0178] Furthermore, according to the magnetic memory device 1 of the first embodiment, the nonmagnetic layer 422 can be made thicker than the plate-shaped tunnel barrier layer in, for example, a magnetoresistive element having a rectangular parallelepiped shape (sometimes referred to as a magnetoresistive element MTJr). The insulating tunnel barrier layer is required to be designed to have low electrical resistance so as not to inhibit the read current, etc. For example, the tunnel barrier layer of the magnetoresistive element MTJr is designed to have low resistance by being made thin.

[0179] In contrast, the nonmagnetic layer 422 has a cylindrical shape, and therefore can be designed to have a larger current-carrying area than a plate-shaped tunnel barrier layer. That is, the nonmagnetic layer 422 has a large current-carrying area, and therefore has a structure that makes it easy to pass a current through the magnetoresistive element MTJ without thinning it. Compared to a plate-shaped tunnel barrier layer, the nonmagnetic layer 422 is less subject to restrictions on thinning, and can be made thicker. That is, the magnetic memory device 1 according to the first embodiment can facilitate the design of the resistance of the magnetoresistive element MTJ.

[0180] Furthermore, according to the magnetic memory device 1 of the first embodiment, in the cylindrical magnetoresistive element MTJ, the ferromagnetic layer 423 serving as the reference layer is provided on the outer periphery of the ferromagnetic layer 421 serving as the memory layer. In such a structure, it is easy to form the volume of the ferromagnetic layer 423 to be larger than the volume of the ferromagnetic layer 421. For example, if the layer thicknesses of the ferromagnetic layer 423 and the ferromagnetic layer 421 are the same, the volume of the ferromagnetic layer 423 will inevitably be larger than the volume of the ferromagnetic layer 421. In this case, the retention energy of the reference layer will be larger than the retention energy of the memory layer. That is, by making the volume of the reference layer and the volume of the memory layer different, the magnetoresistive element MTJ can easily make the retention energy of the reference layer and the retention energy of the memory layer different.

[0181] For example, in a magnetoresistive element, the retention energy of the reference layer needs to be designed to be larger than that of the storage layer. In the case of a structure such as a magnetoresistive element MTJr, it may be difficult to differentiate the retention energies of the reference layer and the storage layer due to the difference in volume between the reference layer and the storage layer. In such cases, the difference in retention energy between the reference layer and the storage layer is controlled by the difference in magnetic anisotropy of the materials. In other words, different materials may be used for the reference layer and the storage layer.

[0182] In contrast, the magnetoresistive element MTJ can use the same material for the reference layer and the memory layer, which makes it easier to control the retention energy of the magnetic material than when controlling the magnetic anisotropy by the material, and as a result, it becomes easier to design the magnetoresistive element MTJ.

[0183] Furthermore, according to the magnetic memory device 1 of the first embodiment, the magnetic memory device 1 has a switching layer in the stacked wiring layer LL. Therefore, the magnetic memory device 1 can, for example, prevent the read current Ir from flowing into memory cells MC on the same read word line RWL, thereby improving the selectivity of the memory cells MC. Also, it can prevent disturbance to adjacent bits caused by application of the voltage Vw0 or Vw1.

[0184] Furthermore, according to the magnetic memory device 1 of the first embodiment, when writing data, it is necessary to pass the write current Ic0 or Ic1, which can prevent erroneous writing during a read operation (when the read current Ir is passed).

[0185] Furthermore, according to the magnetic memory device 1 of the first embodiment, the magnitude of the current (write current Ic0 or Ic1) flowing through the magnetoresistive element MTJ during writing can sometimes be reduced compared to a magnetic memory device such as an STT-MRAM.

[0186] Furthermore, according to the magnetic memory device 1 of the first embodiment, film formation can be performed without using sputtering throughout the entire manufacturing process. For example, the magnetic memory device 1 can use ALD or CVD in film formation throughout the entire manufacturing process. Furthermore, the magnetic memory device 1 can be etched without using IBE (Ion Beam Etching) throughout the entire manufacturing process. For example, the magnetic memory device 1 can use chemical etching (wet etching or RIE) in etching throughout the entire manufacturing process. In this way, the magnetic memory device 1 can be manufactured using equipment that can reduce manufacturing costs throughout the entire manufacturing process.

[0187] In the magnetic memory device 1 according to the first embodiment described above, an example has been shown in which the core member 40 is provided in the center of the memory pillar MP. However, the memory pillar MP of the magnetic memory device 1 does not have to have the core member 40. Hereinafter, the magnetic memory device 1, memory pillar MP, and nonmagnetic layer 412 according to the modified example of the first embodiment may be referred to as magnetic memory device 1b, memory pillar MPb, and nonmagnetic layer 412b, respectively, to distinguish them from the magnetic memory device 1, memory pillar MP, and nonmagnetic layer 412 of the first embodiment.

[0188] Fig. 28 shows an example of the cross-sectional structure of a memory pillar MPb in a magnetic memory device 1b according to a modified example of the first embodiment. Fig. 28 shows a part of the memory pillar MPb, and illustrates the structures of the stacked wiring layer LL and the region of the memory pillar MPb that intersects with this stacked wiring layer LL. Fig. 28 shows a cross section of the same region in the magnetic memory device 1 as in Fig. 6.

[0189] 28, the memory pillar MPb does not have a core member 40 or a nonmagnetic layer 411. In the memory pillar MPb, a nonmagnetic layer 412b is embedded in the region where the core member 40 and the nonmagnetic layer 411 are provided in the memory pillar MP. In other words, the nonmagnetic layer 412b extends along the Z direction and is provided in the center of the memory pillar MP.

[0190] The structures of the magnetoresistive element MTJ and the laminated wiring layer LL are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0191] Fig. 29 is a cross-sectional view taken along line XXVIIII-XXVIIII in Fig. 28, showing an example of the cross-sectional structure of a memory pillar MPb in a magnetic memory device 1b according to a modified example of the first embodiment. Specifically, Fig. 29 shows the cross-sectional structure of a memory pillar MP in a layer that is parallel to the surface of the semiconductor substrate 20 and includes a conductive layer 23. Fig. 29 shows a cross-section of the same region as Fig. 8 in the magnetic memory device 1. The upper part (A) of Fig. 29 shows an example where the magnetoresistive effect element MTJ is in a low resistance state. The lower part (B) of Fig. 29 shows an example where the magnetoresistive effect element MTJ is in a high resistance state.

[0192] The nonmagnetic layer 412b is provided in the center of the memory pillar MPb in the cross section including the conductive layer 23. The other structures are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0193] In the magnetic memory device 1b according to the modification of the first embodiment, the radial thickness of the nonmagnetic layer 412b can be adjusted by adjusting the presence or absence of the core member 40 and the radial thickness of the core member 40. That is, the current density in the nonmagnetic layer 412b (the wiring SOTL) can be adjusted, and the generated spin-orbit torque can be adjusted.

[0194] 2. Second embodiment The magnetic memory device 1 according to the second embodiment will be described below. The magnetic memory device 1 according to the second embodiment is different from the magnetic memory device 1 according to the first embodiment. Hereinafter, the magnetic memory device 1 according to the second embodiment may be referred to as a magnetic memory device 1c to distinguish it from the magnetic memory device 1 according to the first embodiment.

[0195] Furthermore, the memory pillar MP, magnetoresistive element MTJ, ferromagnetic layer 421, non-magnetic layer 422, ferromagnetic layer 423, and non-magnetic layer 424 in the second embodiment may be referred to as memory pillar MPc, magnetoresistive element MTJc, ferromagnetic layer 421c, non-magnetic layer 422c, ferromagnetic layer 423c, and non-magnetic layer 424c, respectively, to distinguish them from the memory pillar MP, magnetoresistive element MTJ, ferromagnetic layer 421, non-magnetic layer 422, ferromagnetic layer 423, and non-magnetic layer 424 in the first embodiment.

[0196] The magnetic memory device 1c differs from the magnetic memory device 1 according to the first embodiment mainly in the structure and manufacturing method of the magnetoresistive element MTJc. The other structures and manufacturing methods of the second embodiment are almost the same as those of the first embodiment. The following mainly describes the magnetic memory device 1c according to the second embodiment, focusing on the differences from the first embodiment.

[0197] The structure of the magnetoresistive effect element MTJc of the magnetic memory device 1c will be described in detail with reference to FIG. 30. FIG. 30 shows an example of the cross-sectional structure of a memory pillar MPc in the magnetic memory device 1c according to the second embodiment. FIG. 30 shows a part of the memory pillar MPc, illustrating the structures of the stacked wiring layer LL and the region of the memory pillar MP that intersects with this stacked wiring layer LL. FIG. 30 shows a cross section of the same region as FIG. 6 in the first embodiment.

[0198] As in the first embodiment, the memory pillar MPc extends along the Z direction and has a portion protruding in the XY directions. The portion protruding in the XY directions is the magnetoresistive element MTJc.

[0199] The structures of the core member 40 and the SOT layer 41 are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0200] The magnetoresistive element MTJc includes, for example, a ferromagnetic layer 421c, a non-magnetic layer 422c, a ferromagnetic layer 423c, and a non-magnetic layer 424c. The magnetoresistive element MTJc has, for example, a structure in which the ferromagnetic layer 421c, the non-magnetic layer 422c, the ferromagnetic layer 423c, and the non-magnetic layer 424c are in contact with the SOT layer 41. That is, the magnetoresistive element MTJc differs from the magnetoresistive element MTJ mainly in that not only the ferromagnetic layer 421c and the non-magnetic layer 422c, but also the ferromagnetic layer 423c and the non-magnetic layer 424c are in contact with the SOT layer 41.

[0201] Specifically, the ferromagnetic layer 421c is provided on a side surface of the nonmagnetic layer 412 in a layer including the stacked wiring layer LL. The nonmagnetic layer 422c covers the surface of the ferromagnetic layer 421c except for the portion where the ferromagnetic layer 421c and the nonmagnetic layer 412c contact each other. The ferromagnetic layer 423c covers the surface of the ferromagnetic layer 421c except for the portion where the nonmagnetic layer 422c and the ferromagnetic layer 421c contact each other. The nonmagnetic layer 424c covers the surface of the ferromagnetic layer 423c except for the portion where the ferromagnetic layer 423c and the nonmagnetic layer 422c contact each other.

[0202] In other words, for example, the ferromagnetic layer 421c is in contact with the nonmagnetic layer 412. The nonmagnetic layer 422c is provided between the insulator layer 32 and the ferromagnetic layer 421c, and has a first portion in contact with the nonmagnetic layer 412. The ferromagnetic layer 423c is provided between the insulator layer 32 and the first portion, and has a second portion in contact with the nonmagnetic layer 412.

[0203] The materials and functions of the ferromagnetic layer 421c, nonmagnetic layer 422c, ferromagnetic layer 423c, and nonmagnetic layer 424c are similar to those of the ferromagnetic layer 421, nonmagnetic layer 422, ferromagnetic layer 423, and nonmagnetic layer 424, respectively, and therefore will not be described further.

[0204] The structure of the laminated wiring layer LL is the same as that of the first embodiment, and therefore a description thereof will be omitted.

[0205] Next, a method for manufacturing the magnetic memory device 1c according to the second embodiment will be described. The method for manufacturing the magnetic memory device 1c according to the second embodiment differs from the method for manufacturing the magnetic memory device 1 according to the first embodiment mainly in the formation of the magnetoresistive effect element MTJc.

[0206] FIG. 31 is a flowchart showing an example of a method for manufacturing the magnetic memory device 1c according to the second embodiment. FIGS. 32 and 33 show an example of a cross-sectional structure of the magnetic memory device 1c according to the second embodiment during manufacturing. FIGS. 32 and 33 each show a cross section of the same region as FIG. 20. An example of a series of manufacturing steps for forming a stacked wiring structure in the memory cell array 10 of the magnetic memory device 1c according to the second embodiment will be described below with reference to FIG. 31 as appropriate. As shown in FIG. 31, in the method for manufacturing the magnetic memory device 1c according to the second embodiment, for example, steps S101 to S103, S201, S202, and S108 to S113 are executed in order.

[0207] First, similarly to the first embodiment, the processes of steps S101 to S103 are executed in order.

[0208] In the process of step S201, as shown in FIG. 32, a nonmagnetic layer 424c, a ferromagnetic layer 623c, a nonmagnetic layer 422c, and a ferromagnetic layer 621c are formed. Specifically, first, the nonmagnetic layer 424c is formed on the surface and bottom of the hole MH and on the surface exposed in the space RP1. Next, the ferromagnetic layer 623c is formed on the surface of the nonmagnetic layer 424c. Next, the nonmagnetic layer 422c is formed on the surface of the ferromagnetic layer 623c. Next, the ferromagnetic layer 621c is formed on the surface of the nonmagnetic layer 422c. The nonmagnetic layer 424c, the ferromagnetic layer 623c, the nonmagnetic layer 422c, and the ferromagnetic layer 621c fill, for example, the space RP1.

[0209] The nonmagnetic layer 424c, the ferromagnetic layer 623c, the nonmagnetic layer 422c, and the ferromagnetic layer 621c are successively formed in a vacuum by ALD or CVD. By performing a process described later, the ferromagnetic layer 423c is formed from a part of the ferromagnetic layer 623c. By performing a process described later, the ferromagnetic layer 421c is formed from a part of the ferromagnetic layer 621c.

[0210] In the process of step S202, as shown in FIG. 33, the magnetoresistive element MTJc is formed. Specifically, wet etching is performed through the holes MH. The wet etching solution etches the nonmagnetic layer 424c, the ferromagnetic layer 623c, the nonmagnetic layer 422c, and the ferromagnetic layer 621c formed in the holes MH. That is, the nonmagnetic layer 424c, the ferromagnetic layer 623c, the nonmagnetic layer 422c, and the ferromagnetic layer 621c formed on the side surfaces of the insulating layer 32 are removed. The ferromagnetic layer 623c and the ferromagnetic layer 621c after the etching process are referred to as the ferromagnetic layer 423c and the ferromagnetic layer 421c, respectively. That is, the ferromagnetic layer 623c and the ferromagnetic layer 621c are etched to form the ferromagnetic layer 423c and the ferromagnetic layer 421c, respectively.

[0211] Then, similarly to the first embodiment, the processes of steps S108 to S113 are executed in order. As a result, a stacked wiring structure in the memory cell array is formed in the second embodiment. Note that the manufacturing process described above is merely an example, and other processes may be inserted between each manufacturing process.

[0212] The effects of the magnetic memory device 1c according to the second embodiment will be described below.

[0213] According to the magnetic memory device 1c of the second embodiment, the ferromagnetic layer 421c, the nonmagnetic layer 422c, the ferromagnetic layer 423c, and the nonmagnetic layer 424c in the magnetoresistive element MTJc are continuously formed in a vacuum. This can prevent the magnetoresistive element MTJc from being exposed to air during film formation. This can prevent the magnetoresistive element MTJc from containing impurities such as oxide films. By preventing the presence of impurities, the magnetoresistive element MTJc can prevent deterioration of its characteristics.

[0214] 3. Other modifications Note that part or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0215] (Appendix 1) forming a stack in which the sacrificial member and the first insulator are alternately stacked along the second direction; forming memory holes extending in the second direction and each penetrating the stack; removing a portion of the sacrificial member through the memory hole; forming a second ferromagnetic body in the first space from which the sacrificial member has been removed; removing a portion of the second ferromagnetic body through the memory hole; forming a first non-magnetic body and a first ferromagnetic body in this order in the first space and a part of the memory hole; removing a portion of the first non-magnetic body and the first ferromagnetic body through the memory hole; forming a second wiring extending in the second direction in a part of the memory hole; forming a slit to divide the laminate; selectively removing the sacrificial member through the slit; forming a variable resistance material in a portion of the space from which the sacrificial member was removed; forming a first wiring in the space from which the sacrificial member has been removed; forming a fourth insulator in the slit; Equipped with the first ferromagnetic body and the second ferromagnetic body are formed in an annular shape between the first wiring and the second wiring, the first ferromagnetic body and the second ferromagnetic body have an easy axis of magnetization along the circumferential direction; A method for manufacturing a magnetic memory device.

[0216] (Appendix 2) The method further includes forming a second insulator in the memory hole after forming the second wiring in a part of the memory hole. A method for manufacturing a magnetic memory device according to claim 1.

[0217] (Appendix 3) the second ferromagnetic body, the first non-magnetic body, the first ferromagnetic body, the second wiring, the first wiring, and the variable resistance material are formed by ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition). A method for manufacturing a magnetic memory device according to claim 1.

[0218] (Appendix 4) forming a stack in which the sacrificial member and the first insulator are alternately stacked along the second direction; forming memory holes extending in the second direction and each penetrating the stack; removing a portion of the sacrificial member through the memory hole; forming a second ferromagnetic body, a first non-magnetic body, and a first ferromagnetic body in this order in the first space from which the sacrificial member has been removed and in a part of the memory hole; removing a portion of the second ferromagnetic body, the first non-magnetic body, and the first ferromagnetic body through the memory hole; forming a second wiring extending in the second direction in a part of the memory hole; forming a slit to divide the laminate; selectively removing the sacrificial member through the slit; forming a variable resistance material in a portion of the space from which the sacrificial member was removed; forming a first wiring in the space from which the sacrificial member has been removed; forming a fourth insulator in the slit; Equipped with the first ferromagnetic body and the second ferromagnetic body are formed in an annular shape between the first wiring and the second wiring, the first ferromagnetic body and the second ferromagnetic body have an easy axis of magnetization along the circumferential direction; A method for manufacturing a magnetic memory device.

[0219] (Appendix 5) The method further includes forming a second insulator in the memory hole after forming the second wiring in a part of the memory hole. A method for manufacturing a magnetic memory device according to claim 5.

[0220] In the first and second embodiments, the magnetic memory devices 1 to 1c may have other structures. The magnetic memory devices 1, 1b, and 1c may have other structures.

[0221] The embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions described in the claims and their equivalents. [Explanation of symbols]

[0222] 1, 1b, 1c, ... magnetic memory device, 10... memory cell array, 11... row decoder, 12... column decoder, 13... read circuit, 14... write circuit, 15... sense amplifier, 16... voltage generation circuit, 17... input / output circuit, 18... control circuit, 20... semiconductor substrate, 22 to 27... conductive layer, 30 to 34, 37... insulating layer, 40... core member, 41... SOT layer, 43... switching layer, 411... non-magnetic layer, 412... non-magnetic layer, 413... non-magnetic layer, 421... ferromagnetic layer, 422... non-magnetic layer, 423... ferromagnetic layer, 424... non-magnetic layer, 431... underlayer, 432... variable resistance material layer, 433... cap layer, TR1, SEL2... switching element< / m> < / m> < / m> < / m> < / n> < / n> < / n> < / m> < / m> < / n> < / m> < / m> < / m> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m>

Claims

1. A substrate; a first wiring and a first insulator extending in a first direction along the substrate and aligned in a second direction intersecting the first direction; a second insulator extending in the second direction and penetrating the first wiring and the first insulator; a second wiring provided around the second insulator, extending in the second direction, and penetrating the first wiring and the first insulator; a first magnetoresistive element provided in a circular shape around the second wiring between the first wiring and the second wiring; Equipped with The first magnetoresistive element is a first ferromagnetic body between the second wiring and the first wiring; a first non-magnetic body between the first ferromagnetic body and the first wiring; a second ferromagnetic body between the first non-magnetic body and the first wiring; having Magnetic memory device.

2. a first switching element provided between the first wiring and the first magnetoresistive element and connected in series to the first magnetoresistive element; Further comprising:

10. The magnetic memory device of claim 1.

3. a plurality of third wirings and a plurality of third insulators extending in the first direction, arranged alternately in the second direction, and penetrated by the second wirings and the second insulators; a plurality of second magnetoresistance effect elements provided in a circular shape around the second wiring between the plurality of third wirings and the second wiring; Further provided with Each of the plurality of second magnetoresistance effect elements a third ferromagnetic body between the second wiring and the third wiring; a second non-magnetic body between the third ferromagnetic body and the third wiring; a fourth ferromagnetic body between the second non-magnetic body and the third wiring; having 10. The magnetic memory device of claim 1.

4. In a write operation of writing data to the first magnetoresistive element, A first voltage is applied to the first wiring, a second voltage lower than the first voltage is applied to a first end of the second wiring, and a third voltage higher than the second voltage is applied to a second end of the second wiring; the third voltage has a magnitude that causes a first current to flow from the second terminal to the first terminal; 10. The magnetic memory device of claim 1.

5. the second voltage is a ground voltage; 5. The magnetic memory device of claim 4.

6. the first ferromagnetic body is in contact with the second wiring; the first non-magnetic body is provided between the first insulator and the first ferromagnetic body, and further has a portion in contact with the second wiring; the second ferromagnetic body is not in contact with the second wiring; 10. The magnetic memory device of claim 1.

7. the first ferromagnetic body is in contact with the second wiring; the first non-magnetic body is provided between the first insulator and the first ferromagnetic body and further has a first portion in contact with the second wiring; the second ferromagnetic body further has a second portion that is provided between the first insulator and the first portion and that is in contact with the second wiring; 10. The magnetic memory device of claim 1.

8. The first magnetoresistive element is a third non-magnetic body between the second ferromagnetic body and the first wiring, The first switching element is a first conductor on the first wiring; a variable resistance material on the first conductor; a second conductor on the variable resistance material; Further comprising:

3. The magnetic memory device of claim 2.

9. the first non-magnetic body contains at least one element selected from boron (B), magnesium (Mg), and aluminum (Al); The first ferromagnetic body and the second ferromagnetic body contain at least one element selected from cobalt (Co), iron (Fe), and nickel (Ni).

10. The magnetic memory device of claim 1.

10. the first non-magnetic material contains hexagonal boron nitride (h-BN) or hexagonal aluminum nitride (h-AlN); 10. The magnetic memory device of claim 1.

11. the third non-magnetic body contains at least one element selected from tantalum (Ta), tungsten (W), and titanium (Ti); 9. The magnetic memory device of claim 8.

12. the variable resistance material includes at least one element selected from sulfur (S), selenium (Se), tellurium (Te), boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb); 9. The magnetic memory device of claim 8.

13. the first switching element is a selector having a nonlinear current-voltage characteristic, a selector having a snapback characteristic, or a diode; 3. The magnetic memory device of claim 2.

14. A substrate; a first wiring and a first insulator extending in a first direction along the substrate and aligned in a second direction intersecting the first direction; a second wiring extending in the second direction and penetrating the first wiring and the first insulator; a first magnetoresistive element provided in a circular shape around the second wiring between the first wiring and the second wiring; a first switching element provided between the first wiring and the first magnetoresistive element and connected in series to the first magnetoresistive element; Equipped with The first magnetoresistive element is a first ferromagnetic body between the second wiring and the first wiring; a first non-magnetic body between the first ferromagnetic body and the first wiring; a second ferromagnetic body between the first non-magnetic body and the first wiring; having Magnetic memory device.

15. a plurality of third wirings and a plurality of third insulators extending in the first direction, arranged alternately in the second direction, and penetrated by the second wirings; a plurality of second magnetoresistance effect elements provided in a circular shape around the second wiring between the plurality of third wirings and the second wiring; Further provided with Each of the plurality of second magnetoresistance effect elements a third ferromagnetic body between the second wiring and the third wiring; a second non-magnetic body between the third ferromagnetic body and the third wiring; a fourth ferromagnetic body between the second non-magnetic body and the third wiring; having 15. The magnetic memory device of claim 14.

16. In a write operation of writing data to the first magnetoresistive element, A first voltage is applied to the first wiring, a second voltage lower than the first voltage is applied to a first end of the second wiring, and a third voltage higher than the second voltage is applied to a second end of the second wiring; the third voltage has a magnitude that causes a first current to flow from the second terminal to the first terminal; 15. The magnetic memory device of claim 14.

17. the first non-magnetic material contains boron (B), magnesium (Mg), or aluminum (Al); the first ferromagnetic body and the second ferromagnetic body contain cobalt (Co), iron (Fe), or nickel (Ni); 15. The magnetic memory device of claim 14.

18. the first ferromagnetic body is in contact with the second wiring; the first non-magnetic body is provided between the first insulator and the first ferromagnetic body, and further has a portion in contact with the second wiring; 15. The magnetic memory device of claim 14.

19. The first magnetoresistive element is a third non-magnetic body between the second ferromagnetic body and the first wiring, The first switching element is a first conductor on the first wiring; a variable resistance material on the first conductor; a second conductor on the variable resistance material; Further comprising:

15. The magnetic memory device of claim 14.

20. the variable resistance material includes at least one element selected from sulfur (S), selenium (Se), tellurium (Te), boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb); 20. The magnetic memory device of claim 19.

Images