Offset cancellation amplifier, display driver, and display device

Abstract

To provide an offset cancel amplifier, a display driver, and a display device capable of generating a highly accurate output voltage corresponding to an input voltage.SOLUTION: An offset cancellation amplifier according to the present invention includes: a first differential pair that receives an input voltage at one end, receives an input voltage or an output voltage at the other end, and outputs a first current pair corresponding to a difference between voltages at both ends; first and second capacitive elements; a switch circuit that supplies a reference voltage or the input voltage to one end of the first capacitive element and supplies the output voltage to one end of the second capacitive element in an on state; a second differential pair having one end of the first capacitive element connected to one end thereof and one end of the second capacitive element connected to the other end thereof and outputting a second current pair corresponding to the difference between voltages at both ends thereof; an output amplification stage for generating the output voltage by sending a current corresponding to a magnitude of a current obtained by current-coupling the first and second current pairs to an output node; and a third capacitive element having one end and the other end thereof connected to one end of each of the first and second capacitive elements.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an offset cancellation amplifier including an offset cancellation circuit, and a display driver and a display device including the offset cancellation amplifier. [Background technology]

[0002] Currently, operational amplifier circuits are known as such offset cancellation amplifiers (see, for example, FIG. 3 of Patent Document 1).

[0003] FIG. 1 is a circuit diagram showing the configuration of such an operational amplifier circuit.

[0004] The operational amplifier circuit shown in FIG. 1 includes an operational amplifier configured with a first differential pair consisting of transistors M1 and M2, a transistor M3 as a current source, a current mirror circuit consisting of transistors M4 and M5, and an output buffer circuit consisting of transistors M6 and M7, as well as the following offset cancellation circuit.

[0005] That is, the offset cancellation circuit includes a second differential pair consisting of transistors M8 and M9, a transistor M10 as a current source, capacitors C1 and C2, and switches SW1 to SW3 and SW5.

[0006] Next, the operation of the operational amplifier circuit shown in FIG. 1 will be described.

[0007] In this operational amplifier circuit, an offset cancellation preparation step and an output step are carried out in this order.

[0008] First, in the offset cancellation preparation step, the switches SW1, SW3, and SW5 are turned on, and the switch SW2 is turned off. Therefore, an equal input voltage V is applied to the gates of the transistors M1 and M2, and the input voltage V is supplied to the gate of the transistor M9 and the capacitor C2, and the output voltage V is supplied to the gate of the transistor M8 and the capacitor C1.

[0009] As a result, a voltage VC1 obtained by superimposing the offset voltage on the input voltage VIN is stored in the capacitor C1, and the input voltage VIN is stored in the capacitor C2.

[0010] Next, in the output step, the switches SW1, SW3, and SW5 are turned off, and the switch SW2 is turned on. Therefore, when the switch SW3 transitions from on to off, the supply of the output voltage VOUT to the capacitor C1 is cut off. Furthermore, when the switch SW5 transitions from on to off, the supply of the input voltage VIN to the capacitor C2 is cut off. Therefore, the second differential pair (M8, M9) constituting the offset cancellation circuit causes a current pair corresponding to the difference between the input voltage VIN and a voltage VC1, in which an offset voltage is superimposed on the input voltage VIN, i.e., the offset voltage, to flow through the current pair output by the first differential pair (M1, M2) constituting the operational amplifier. This removes the offset voltage. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-300683 Summary of the Invention [Problem to be solved by the invention]

[0012] Incidentally, during the output phase of the operational amplifier circuit described in the above-mentioned technical document 1, switches SW1, SW3, and SW5 are turned off. However, because these switches are composed of transistors, if the output phase period is long, off-leak currents will flow through each of them. For example, when used as a gamma buffer for a display driver, it is necessary to maintain a stable voltage for the frame period required to rewrite one screen (approximately 16.7 ms for 60 Hz drive). Note that the current values ​​of the off-leak currents that flow through each switch when it is off are not necessarily the same due to manufacturing variations and other factors.

[0013] Therefore, particularly when the off-leak currents of the switches SW3 and SW5 are different, a difference occurs between the amount of fluctuation in the voltage (VIN) at one end of the capacitor C1 due to the off-leak current and the amount of fluctuation in the voltage (VIN+offset voltage) at one end of the capacitor C2.

[0014] This causes a problem in that the accuracy of the offset cancellation decreases, and accordingly the accuracy of the output voltage VOUT also decreases.

[0015] Therefore, an object of the present invention is to provide an offset cancellation amplifier, a display driver, and a display device that can generate and maintain a highly accurate output voltage corresponding to an input voltage even when the output process period is long. Although it is possible to increase the capacitance value of a capacitive element to suppress the effects of off-leakage current, this method results in a problem of a significant increase in area. Therefore, the present invention realizes an offset cancellation amplifier that sets the capacitance value of a capacitive element to a relatively small value and is still able to generate and maintain a highly accurate output voltage. [Means for solving the problem]

[0016] The offset cancellation amplifier according to the present invention is an offset cancellation amplifier that receives an input voltage, and outputs an output voltage corresponding to the input voltage from an output node while removing an offset voltage occurring in the output voltage, and includes: a first differential pair that receives the input voltage at one end and the input voltage or the output voltage at the other end, and outputs a first current pair corresponding to a voltage difference between the voltage at the one end and the voltage at the other end; first and second capacitance elements; a switch circuit that, in an on state, supplies a predetermined reference voltage or the input voltage to one end of the first capacitance element and supplies the output voltage to one end of the second capacitance element; a second differential pair, the second differential pair having one end of the first capacitance element connected to one end thereof and the one end of the second capacitance element connected to the other end thereof, outputting a second current pair corresponding to a voltage difference between the voltage at one end of the second capacitance element and the voltage at the other end thereof; an output amplification stage that receives the first current pair and the second current pair and generates the output voltage by sending to the output node a current corresponding to the magnitude of a current obtained by current-combining the first current pair and the second current pair; and a third capacitance element having one end connected to the one end of the first capacitance element and the other end connected to the one end of the second capacitance element.

[0017] a reference voltage generating unit configured to generate m (m is an integer equal to or greater than 1) reference voltages in accordance with desired gamma characteristics; and first to m-th gamma buffers configured to receive the m reference voltages individually and amplify the received reference voltages individually to generate m gamma voltages and apply the m gamma voltages to the taps of the resistor string; wherein each of the first to m-th gamma buffers is the offset cancellation amplifier according to claim 1, and receives the reference voltage received by itself as the input voltage, and outputs the output voltage output from the offset cancellation amplifier as the gamma voltage.

[0018] A display device according to the present invention includes a display panel, and a display driver including a gray scale voltage generation circuit that generates a plurality of gray scale voltages, that selects a gray scale voltage from the plurality of gray scale voltages corresponding to a brightness level indicated by a video signal, and that sends a drive signal having the selected gray scale voltage to the display panel, wherein the gray scale voltage generation circuit includes a resistor string including a plurality of resistors connected in series to each other via a plurality of taps, and that outputs the plurality of gray scale voltages having different voltage levels from each of the taps, a reference voltage generation unit that generates m (m is an integer of 2 or more) reference voltages in accordance with desired gamma characteristics, and first to m-th gamma buffers that individually receive the m reference voltages and individually amplify the received reference voltages to generate m gamma voltages and apply them to the taps of the resistor string, each of the first to m-th gamma buffers being the offset cancellation amplifier that receives the reference voltage it receives as the input voltage, and outputs the output voltage output from the offset cancellation amplifier as the gamma voltage. [Effects of the Invention]

[0019] In the offset cancellation amplifier according to the present invention, when the difference between the output voltage on which the offset voltage is superimposed and the reference voltage (input voltage) is detected as the offset voltage, the switch circuit, when in the on state, supplies the reference voltage (input voltage) to one end of the first capacitance element and the output voltage to one end of the second capacitance element, whereby the reference voltage (input voltage) is held in the first capacitance element and the output voltage is held in the second capacitance element.

[0020] At this time, when the switch circuit transitions from the on state to the off state, an off-leak current flows. However, in the offset cancellation amplifier, a third capacitive element is provided, one end of which is connected to one end of each of the first and second capacitive elements, and the other end of each third capacitive element is connected to one end of each of the first and second capacitive elements, thereby suppressing voltage fluctuations associated with the off-leak current.

[0021] This allows the voltage at one end of each of the first and second capacitance elements that is held when the switch circuit is in the on state to be maintained for a long period of time, such as one frame period, even after the switch circuit transitions from the on state to the off state.

[0022] Therefore, according to the present invention, even in an offset cancellation operation using a capacitive element with a relatively small capacitance, it is possible to generate a highly accurate output voltage corresponding to the input voltage and maintain it for a long period of time. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of an operational amplifier circuit as a conventional offset cancellation amplifier. [Figure 2] FIG. 1 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_1 according to a first embodiment of the present invention. [Figure 3] 1 is a time chart showing the transition of the on / off states of each of switch elements 21, 22, 31, and 32. [Figure 4A]FIG. 1 is a schematic circuit diagram in which the on / off states of switch elements 21, 22, 31, and 32 and current paths are indicated by thick solid lines in a first step. [Figure 4B] FIG. 1 is a schematic circuit diagram in which the on / off states of switch elements 21, 22, 31, and 32 and current paths are indicated by thick solid lines in a first step. [Figure 5] FIG. 10 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_2 according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_3 according to a third embodiment of the present invention. [Figure 7] FIG. 10 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_4 according to a fourth embodiment of the present invention. [Figure 8] FIG. 10 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_5 according to a fifth embodiment. [Figure 9] FIG. 10 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_6 according to a sixth embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_6. [Figure 11] 1 is a time chart showing the transition of the on / off states of each of switch elements 21, 22, 31a to 31c, and 32a to 32c. [Figure 12A] 3 is a cross-sectional view that schematically shows the cross-sectional structure, connection configuration, and state of each transistor of transistors 32a to 32c in a first step. [Figure 12B] 3 is a cross-sectional view that schematically shows the cross-sectional structure, connection configuration, and state of each of the transistors 32a to 32c during a transition from a first process to a second process. FIG. [Figure 13] FIG. 2 is a block diagram showing a schematic configuration of a display device 400. [Figure 14] FIG. 2 is a block diagram showing the internal configuration of a data driver 103. [Figure 15] 2 is a circuit diagram showing the internal configuration of a grayscale voltage generating circuit 122. FIG. [Figure 16]1 is a time chart showing the transition of the on / off states and voltage levels of each of switch elements 21, 22, 31a to 31c, and 32a to 32c each made up of an Nch transistor. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be described in detail below with reference to the drawings. [Example]

[0025] FIG. 2 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_1 as a first embodiment of the offset cancellation amplifier according to the present invention.

[0026] The offset cancellation amplifier 100_1 is a voltage follower made up of an operational amplifier with an offset cancellation circuit, which amplifies an input voltage VI and outputs an output voltage VO. The offset cancellation amplifier 100_1 has a differential amplification stage 10_1, an output amplification stage 90_1, and a control circuit CNT.

[0027] The differential amplification stage 10_1 includes a first differential stage B1 which serves as the core of the above-mentioned operational amplifier, and a second differential stage B2 which serves as an offset cancellation circuit.

[0028] The differential stage B1 includes N-channel transistors 11 and 12 and a current source Id1.

[0029] The transistor 11 receives the input voltage VI at its gate via a node nd1. The source of the transistor 11 is connected to a current source Id1, and its drain is connected to the output amplifier stage 90_1 via a node nd11. The transistor 12 receives the input voltage VI or the output voltage VO at its gate via a node nd2. The source of the transistor 12 is connected to the current source Id1, and its drain is connected to the output amplifier stage 90_1 via a node nd12. The current source Id1 receives a power supply voltage VE1 (e.g., zero volts) having a low potential as a power supply voltage, and draws a predetermined constant current from the sources of the transistors 11 and 12.

[0030] With this configuration, the differential pair (11, 12) consisting of transistors 11 and 12 passes a pair of currents I11 and I12, which are obtained by dividing the above constant current by two, to nodes nd11 and nd12, respectively, at a ratio corresponding to the difference between the input voltage VI and the voltage at node nd2.

[0031] The differential stage B2 includes N-channel transistors 13 and 14, capacitors Ca, Cb, and Cf as capacitive elements, switch elements 21, 22, 31, and 32, and a current source Is1.

[0032] The switch element 21 receives a switch signal S1 and is in an off state while the switch signal S1 is at, for example, logic level 0, and is in an on state while the switch signal S1 is at logic level 1. When the switch element 21 is in an on state, it supplies an input voltage VI to the gate of the transistor 12 via a node nd2. The switch element 22 receives a switch signal S2 and is in an off state while the switch signal S2 is at, for example, logic level 0, and is in an on state while the switch signal S2 is at logic level 1. When the switch element 22 is in an on state, it supplies an output voltage VO to the gate of the transistor 12 via a node nd2.

[0033] Both switch elements 31 and 32 receive a switch signal S1, and are in an off state while the switch signal S1 is at logic level 0, for example, and are in an on state while the switch signal S1 is at logic level 1. When the switch element 31 is in an on state, it supplies a predetermined reference voltage Vref or an input voltage VI to the gate of the transistor 13 and one end of each of the capacitors Ca and Cf via a node nd3. When the switch element 32 is in an on state, it supplies an output voltage VO to the gate of the transistor 14, the other end of the capacitor Cf, and one end of the capacitor Cb via a node nd4. Note that the relationship between the logic levels of the switch signals S1 and S2 and the on / off states of each switch element applies when each switch element is configured as an N-channel transistor switch.

[0034] Here, as shown in FIG. 2, a power supply voltage VE1 is applied to the other end of each of the capacitors Ca and Cb, one end of the capacitor Ca is connected to one end of the capacitor Cf, and one end of the capacitor Cb is connected to the other end of the capacitor Cf.

[0035] The capacitance of each of the capacitors Ca, Cb, and Cf is Cf>Ca Cf>Cb Let's say.

[0036] The transistor 13 has its source connected to the current source Is1 and its drain connected to the output amplification stage 90_1 via a node nd13. The transistor 14 has its source connected to the current source Is1 and its drain connected to the output amplification stage 90_1 via a node nd14.

[0037] The current source Is1 receives the power supply voltage VE1 and draws a predetermined constant current from the sources of the transistors 13 and 14.

[0038] With this configuration, the differential pair (13, 14) consisting of transistors 13 and 14 passes a pair of currents I13 and I13, which are obtained by dividing the above constant current in half at a ratio corresponding to the difference between the voltage at node nd3 and the voltage at node nd4, to nodes nd13 and nd14, respectively.

[0039] The output amplifier stage 90_1 receives the above-mentioned current pairs (I11, I12) and (I13, I14) and sends out to the output node nd0 a current corresponding to the difference between the current I13 superimposed on the current I11 and the current I14 superimposed on the current I12. As a result, the output amplifier stage 90_1 generates, on the output node nd0, a voltage having a voltage value corresponding to the input voltage VI as an output voltage VO.

[0040] In performing the offset cancellation operation, the control circuit CNT generates switch signals S1 and S2 that control the voltages supplied to the input pairs of the differential stage B1 and the differential stage B2, and supplies these signals to the switch elements 21, 22, 31 and 32 described above.

[0041] FIG. 3 is a time chart showing the transition of the on / off states of the switch elements 21, 22, 31, and 32 in accordance with the switch signals S1 and S2 generated by the control circuit CNT.

[0042] The control circuit CNT first sets the switch elements 21, 31, and 32 to the ON state and the switch element 22 to the OFF state using the switch signals S1 and S2 (first step), as shown in Fig. 3. After executing the first step, the control circuit CNT then uses the switch signals S1 and S2 to switch the switch elements 21, 31, and 32 to the OFF state and the switch element 22 to the ON state, as shown in Fig. 3 (second step).

[0043] Next, the offset cancel operation performed by executing the first and second steps shown in FIG. 3 will be described. [1st step] FIG. 4A is a schematic circuit diagram in which the on / off states of switch elements 21, 22, 31, and 32 and current paths are indicated by thick solid lines in the first step.

[0044] As shown in FIG. 4A, in the first step, the switch elements 21, 31, and 32 are in the ON state, and the switch element 22 is in the OFF state.

[0045] At this time, with switch element 21 turned on and switch element 22 turned off, the gates of transistors 11 and 12 are shorted together, as shown by the thick solid line in Fig. 4A. Furthermore, with switch element 31 turned on, reference voltage Vref is applied to the gate of transistor 13 and one end of capacitor Ca, and capacitor Ca is charged by reference voltage Vref.

[0046] As a result, the voltage at one end of the capacitor Ca becomes equal to the reference voltage Vref, and this voltage is stored in the capacitor Ca. The reference voltage Vref may be the input voltage VI.

[0047] 4A, when the switch element 32 is turned on, the output voltage VOUT is applied as a feedback voltage to one end of the capacitor Cb as well as to the gate of the transistor 14. As a result, the capacitor Cb is charged by the output voltage VOUT, and the voltage at one end of the capacitor Cb becomes equal to the output voltage VOUT.

[0048] In the state shown in FIG. 4A, the gates of the transistors 11 and 12 that form a differential pair of the operational amplifier are short-circuited, so the difference in the differential pair is zero.

[0049] Therefore, in the first step, an operation is performed to equalize the voltage values ​​of the reference voltage Vref applied to the gate of transistor 13 belonging to the offset cancellation circuit and the output voltage VO applied to the gate of transistor 14. At this time, if an offset occurs in the output voltage VO due to manufacturing variations in the pair transistors of the differential pair (11, 12) or the differential pair (13, 14), for example, the output voltage VO will be the reference voltage Vref plus the offset voltage. Therefore, the voltage at one end of capacitor Cb will be the reference voltage Vref plus the offset voltage Voff, and this voltage (Vref + Voff) will be held in capacitor Cb.

[0050] In this way, in the first step, the reference voltage Vref and the voltage (Vref+Voff) obtained by adding the offset voltage occurring in the output voltage VO to the reference voltage Vref are held in the capacitors Ca and Cb, respectively.

[0051] In the differential stage B2 serving as an offset cancellation circuit, a capacitor Cf is connected between one end of the capacitor Ca and one end of the capacitor Cb, so that in the first step, the capacitor Cf holds the voltage difference between the reference voltage Vref and the output voltage VO on which the offset voltage Voff is superimposed, i.e., the offset voltage Voff. [Second process] FIG. 4B is a schematic circuit diagram in which the on / off states of the switch elements 21, 22, 31, and 32 and the current paths are indicated by thick solid lines in the second step.

[0052] As shown in FIG. 4B, in the second step, the switch elements 21, 31, and 32 are turned off, and the switch element 22 is turned on.

[0053] At this time, the switch element 22 is turned on and the switch elements 21, 31, and 32 are turned off, so that the output voltage VO is supplied to the gate of the transistor 12 forming the differential pair via the switch element 22, as shown by the thick solid line in FIG. 4B.

[0054] As a result, a pair of currents (I11, I12) corresponding to the difference between the input voltage VI and the output voltage VO flows through a pair of nodes (nd11, nd12).

[0055] Furthermore, by switching the switch elements 31 and 32 to the off state, the voltage (Vref) held in the capacitor Ca is applied to the gate of the transistor 13, and the voltage (Vref+Voff) held in the capacitor Cb is applied to the gate of the transistor 14, as shown by the thick solid lines in Fig. 4B. As a result, the differential pair (13, 14) detects the difference between the voltage (Vref) and the voltage (Vref+Voff), i.e., the offset voltage Voff, and passes a pair of currents (I13, I14) corresponding to the offset voltage Voff through a pair of nodes (nd13, nd14).

[0056] As a result, the output amplification stage 90_1 sends to the output node nd0 a current obtained by current-combining a pair of currents (I11, I12) corresponding to the difference between the input voltage VI and the output voltage VO with a pair of currents (I13, I14) corresponding to the offset voltage Voff. In other words, the output amplification stage 90_1 sends to the output node nd0 a current corresponding to a voltage obtained by removing the offset voltage Voff from the difference between the input voltage VI and the output voltage VO. Therefore, the output voltage VO from which the offset voltage Voff has been removed is generated at the output node nd0.

[0057] In the second step, if the step period is long, off-leak currents flow through the switch elements 31 and 32 in the off state. Due to manufacturing variations and other factors, the off-leak currents of the two elements are not necessarily the same. Therefore, if the off-leak currents of the switch elements 31 and 32 differ in magnitude, a difference will occur between the amount of fluctuation in the voltage at one end of the capacitor Ca and the amount of fluctuation in the voltage at one end of the capacitor Cb. This may result in a decrease in the accuracy of offset cancellation during the second step, which may also decrease the accuracy of the output voltage VOUT.

[0058] However, in the configuration shown in FIG. 2, the offset voltage Voff occurring in the output voltage VO is stored in the capacitor Cf in the first step, and is held together with the capacitors Ca and Cb in the second step.

[0059] 2, even if the off-leak currents of switch elements 31 and 32 are different in magnitude, the configuration includes capacitor Cf, which has a capacitance value greater than capacitors Ca and Cb, and therefore fluctuations in the voltage difference held in capacitor Cf are suppressed. Furthermore, as long as the voltage difference held in capacitor Cf connected to the input pair of differential pair (13, 14) is maintained, the output currents I13 and I14 of differential pair (13, 14) will not fluctuate even if the voltage of the input pair of differential pair (13, 14) fluctuates. Therefore, the configuration shown in FIG. 2 can maintain high-precision offset cancellation even when the second step period is long, and as a result, can generate a high-precision output voltage VO.

[0060] In the configuration shown in FIG. 2, N-channel transistors are used as the transistors (11 to 14) that constitute the first and second differential pairs, but the conductivity types of the transistors that constitute the first differential pair and the conductivity types of the transistors that constitute the second differential pair may be different from each other. [Example]

[0061] FIG. 5 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_2 according to a second embodiment of the present invention, which has been made in view of the above points.

[0062] The configuration shown in FIG. 5 is the same as that shown in FIG. 2 except that a differential amplifier stage 10_2 is adopted instead of the differential amplifier stage 10_1 shown in FIG. 2 and an output amplifier stage 90_2 is adopted instead of the output amplifier stage 90_1.

[0063] 2. Moreover, in the differential amplification stage 10_2 shown in FIG. 5, a differential stage B1a is employed in place of the differential stage B1, and the differential stage B1 is the same as that shown in FIG.

[0064] In the differential stage B1a, a differential pair consisting of P-channel transistors 15 and 16 is used instead of the differential pair (11, 12) shown in FIG. 2, and along with this change, a current source Id2 is used instead of the current source Id1 shown in FIG. 2.

[0065] The current source Id2 receives a power supply voltage VE2 (VE2>VE1) having a high potential as a power supply voltage, and supplies a predetermined constant current to the sources of the transistors 15 and 16.

[0066] The transistor 15 receives the input voltage VI at its gate via the node nd1, and supplies a current I15 having a magnitude corresponding to the input voltage VI from its drain to the output amplifier stage 90_2 via the node nd15. The transistor 16 receives the voltage of the node nd2, i.e., the output voltage VO or the input voltage VI, at its gate, and supplies a current I15 having a magnitude corresponding to this voltage from its drain to the output amplifier stage 90_2 via the node nd15.

[0067] The output amplifier stage 90_2 receives the above-mentioned current pairs (I15, I16) and (I13, I14) and sends currents corresponding to the difference between the mutually current-coupled currents I15 and I13 and the difference between the currents I16 and I14 to the output node nd0. As a result, the output amplifier stage 90_2 generates, on the output node nd0, a voltage having a voltage value corresponding to the input voltage VI as an output voltage VO.

[0068] The offset cancellation amplifier 100_2 also performs offset cancellation by sequentially executing the above-described first and second steps, similarly to the offset cancellation amplifier 100_1 shown in Fig. 2. At this time, similarly to the offset cancellation amplifier 100_1, the offset cancellation amplifier 100_2 also connects one end of the capacitor Ca to one end of the capacitor Cb via the capacitor Cf, thereby enabling the generation of a highly accurate output voltage VO even if the period of the second step is long. [Example]

[0069] FIG. 6 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_3 according to the third embodiment.

[0070] The configuration shown in FIG. 6 employs an output amplification stage 90_1A, which represents an example of a specific internal configuration, as the output amplification stage 90_1 shown in FIG. 2, and the other configurations are the same as those shown in FIG.

[0071] As shown in FIG. 6, the output amplification stage 90_1A includes a Pch current mirror circuit 70_1, floating current sources 91 and 92, an Nch current mirror circuit 80, a P-channel output transistor 93, and an N-channel output transistor 94.

[0072] The Pch current mirror circuit 70_1 includes P-channel transistors 71 to 74. A power supply voltage VE4 is applied to the source of each of the transistors 71 and 72, and the gate of each is connected to the drain of the transistor 73. The transistor 71 generates a current I71 having a magnitude corresponding to the voltage applied to its gate and supplies this current from its drain to the source of the transistor 73. The transistor 72 generates a current I72 having a magnitude corresponding to the voltage applied to its gate and supplies this current from its drain to the source of the transistor 74.

[0073] Transistors 73 and 74 receive a predetermined bias voltage BP at their respective gates. Transistor 73 generates a current I91 having a magnitude corresponding to the bias voltage BP and supplies it from its drain via node nd75 to floating current source 91. Transistor 74 generates a current I92 having a magnitude corresponding to the bias voltage BP and supplies it from its drain via node nd76 to floating current source 92.

[0074] In this way, the Pch current mirror circuit 70_1 has a cascode current mirror configuration in which the first-stage transistor pair (71, 72) and the second-stage transistor pair (73, 74) are cascode-connected.

[0075] The floating current source 91 receives a current I91 via a node nd75 on the input side of the Pch current mirror circuit 70_1 and supplies it via a node nd85 to the input side of the Nch current mirror circuit 80. The floating current source 92 receives a current I92 via a node nd76 on the output side of the Pch current mirror circuit 70_1 and supplies it to the output side of the Nch current mirror circuit 80 via a node nd86.

[0076] The Nch current mirror circuit 80 receives a power supply voltage VE3 that is lower than the above-mentioned power supply voltage VE4, and flows a current I91 from a node nd85 on its input side toward the power supply voltage VE3, and also turns this current back to flow to a node nd86 on its output side. At this time, the floating current source 92 extracts the current flowing to the node nd86 from the node nd76 on the output side of the Pch current mirror circuit 70_1.

[0077] Here, the drain of the transistor 71 and the source of the transistor 73 are connected to nodes nd12 and nd14, respectively, and the drain of the transistor 72 and the source of the transistor 74 are connected to nodes nd11 and nd13.

[0078] In this way, by connecting the output pair nd11 (nd13) and nd12 (nd14) to the connection node pair between the cascode-connected first-stage transistor pair and the second-stage transistor pair, the Pch current mirror circuit 70_1 current-couples the current pairs (I11, I12) and (I13, I14) in accordance with the following relational expression: In addition, currents I91 and I92 of the floating current sources 91 and 92 act as the input current and output current of the Nch current mirror circuit 80.

[0079] I91=I71-(I12+I14) I92=I72-(I11+I13) I71=I72 I91=I92 With the above-described configuration, the Pch current mirror circuit 70_1 causes a current I91 corresponding to the magnitude of one current I12 of the first current pair (I11, I12) to flow to the input node nd75 based on the power supply voltage VE4. Furthermore, the Pch current mirror circuit 70_1 causes a current I92, which is obtained by superimposing the other current I11 of the first current pair (I11, I12) on a current obtained by folding back the current I71 flowing through the transistor 71, to flow to the output node nd76.

[0080] Here, the voltage generated at the node nd76 is supplied to the gate of the output transistor 93 as a Pch drive signal, and the voltage generated at the node nd86 is supplied to the gate of the output transistor 94 as an Nch drive signal.

[0081] In this way, the Pch current mirror circuit 70_1, the Nch current mirror circuit 80, and the floating current sources 91 and 92 function as a load circuit that outputs, as a Pch drive signal and an Nch drive signal, the voltages generated at the nodes nd76 and nd86 when current is drawn from the nodes nd11 and nd12 by the differential pairs (11, 12) and (13, 14). Note that the Pch drive signal and the Nch drive signal are current-coupled via the floating current source 92, so the respective drive signals operate in approximately the same phase.

[0082] The output transistor 93 has a power supply voltage VE6 applied to its source. The output transistor 93 receives the voltage of node nd76 on the output side of the Pch current mirror circuit 70_1 at its gate as a Pch drive signal, and outputs a current based on the Pch drive signal from its source to the output node nd0. The output transistor 94 has a power supply voltage VE5, which is lower than the power supply voltage VE6, applied to its source. The output transistor 94 receives the voltage of node nd86 on the output side of the Nch current mirror circuit 80 at its gate as an Nch drive signal, and draws a current based on this Nch drive signal from the output node nd0 via its source. [Example]

[0083] FIG. 7 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_4 according to the fourth embodiment.

[0084] The configuration shown in FIG. 7 is the same as that shown in FIG. 6 except that an output amplification stage 90_1B is employed instead of the output amplification stage 90_1A shown in FIG.

[0085] 6. In addition, the output amplification stage 90_1B employs a Pch current mirror circuit 70_2 instead of the Pch current mirror circuit 70_1 shown in FIG. 6, and other configurations are the same as those shown in FIG.

[0086] The Pch current mirror circuit 70_2 is a one-stage current mirror obtained by removing the second-stage transistor pair (73, 74) from a cascode current mirror circuit such as the Pch current mirror circuit 70_1 shown in FIG.

[0087] Even when such a configuration is adopted, the current pairs (I11, I12) and (I13, I14) are current-coupled in accordance with the following relational expressions.

[0088] I91=I71-(I12+I14) I92=I72-(I11+I13) I71=I72 I91=I92 [Example]

[0089] FIG. 8 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_5 according to the fifth embodiment.

[0090] The configuration shown in FIG. 8 employs an output amplification stage 90_2A, which represents an example of a specific internal configuration, as the output amplification stage 90_2 shown in FIG. 5, and the other configurations are the same as those shown in FIG.

[0091] Moreover, output amplification stage 90_2A employs an Nch current mirror circuit 80_1 instead of the Nch current mirror circuit 80 in output amplification stage 90_1A shown in FIG. 6, and other configurations are the same as those shown in output amplification stage 90_1A.

[0092] However, in the output amplification stage 90_2A, the drain of the transistor 71 and the source of the transistor 73 of the Pch current mirror circuit 70_1 are connected to the differential stage B2 via a node nd14, and the drain of the transistor 72 and the source of the transistor 74 of the Pch current mirror circuit 70_1 are connected to the differential stage B2 via a node nd13.

[0093] The Nch current mirror circuit 80_1 includes N-channel transistors 81 to 84. A power supply voltage VE3 is applied to the sources of the transistors 81 and 82, and the gates of the transistors 81 and 82 are connected to the drain of the transistor 83. The transistor 81 generates a current I81 having a magnitude corresponding to the voltage applied to its gate and outputs this current from its source to the power supply voltage VE3. The transistor 82 generates a current I82 having a magnitude corresponding to the voltage applied to its gate and outputs this current from its source to the power supply voltage VE3.

[0094] The transistor 83 receives the current I91 sent from the floating current source 91 at its drain via the node nd85. The drain of the transistor 83 is connected to the gates of the transistors 81 and 82. The transistor 83 receives a predetermined bias voltage BN at its gate, generates a current having a magnitude corresponding to the bias voltage BN, and outputs this current from its source to the drain of the transistor 81.

[0095] The transistor 84 receives at its drain the current I92 sent from the floating current source 92 via the node nd86. The transistor 84 receives at its gate the bias voltage BN, generates a current having a magnitude corresponding to the bias voltage BN, and outputs this current from its source to the drain of the transistor 82.

[0096] In this way, the Nch current mirror circuit 80_1 has a cascode current mirror configuration in which the first-stage transistor pair (81, 82) and the second-stage transistor pair (83, 84) are cascode-connected.

[0097] Here, the drain of the transistor 81 and the source of the transistor 83 are connected to a node nd16, and the drain of the transistor 82 and the source of the transistor 84 are connected to a node nd15.

[0098] Therefore, with the above-described configuration, the current pairs (I15, I16) and (I13, I14) generated in the differential stage B1a and the differential stage B2 shown in FIG. 8 are current-coupled by the output amplification stage 90_2A shown in FIG. 8 in accordance with the following relational expressions:

[0099] I91=I71-I14=I81-I16 I92=I72-I13=I82-I15 I71=I72 I81=I82 With the above-described configuration, the Pch current mirror circuit 70_1 causes a current I91 corresponding to one current I14 of the current pair (I13, I14) to flow to an input node nd75 based on the power supply voltage VE4. Furthermore, the Pch current mirror circuit 70_1 causes a current I92, which is obtained by superimposing the other current I13 of the current pair (I13, I14) on a current I72 obtained by folding back the current I71 flowing through the transistor 71, to flow to an output node nd76.

[0100] Furthermore, the Nch current mirror circuit 80_1 flows a current corresponding to one current I16 of the current pair (I15, I16) to an input node nd85 based on the power supply voltage VE3 and couples it with the current I91 of the floating current source 91. Furthermore, the Nch current mirror circuit 80_1 flows a current obtained by superimposing the other current I13 of the current pair (I13, I14) on a current I82 obtained by folding back the current I81 flowing through the transistor 81 to an output node nd86 and couples it with the current I92 of the floating current source 92.

[0101] Here, the voltage generated at the node nd76 is supplied to the gate of the output transistor 93 as a Pch drive signal, and the voltage generated at the node nd86 is supplied to the gate of the output transistor 94 as an Nch drive signal.

[0102] In this way, the Pch current mirror circuit 70_1, the Nch current mirror circuit 80_1, and the floating current sources 91 and 92 function as a load circuit that outputs, as a Pch drive signal and an Nch drive signal, voltages generated at nodes nd76 and nd86 when current is drawn from nodes nd11 and nd12 by the differential pair (13, 14) and current is supplied from nodes nd15 and nd16 by the differential pair (15, 16). Note that the Pch drive signal and the Nch drive signal are current-coupled via the floating current source 92, so the respective drive signals operate in approximately the same phase.

[0103] 6, the output transistor 93 receives the voltage at the node nd76 at its gate as a Pch drive signal, and the output transistor 94 receives the voltage at the node nd86 at its gate as an Nch drive signal. The output transistors 93 and 94 supply currents acting on the Pch drive signal and the Nch drive signal, respectively, from the power supply voltages connected to their sources to the output node nd0. [Example]

[0104] FIG. 9 is a circuit diagram showing a configuration of an offset cancellation amplifier 100_6 according to the sixth embodiment.

[0105] The configuration shown in FIG. 9 is the same as that shown in FIG. 2 except that a differential amplifier stage 10_3 is employed instead of the differential amplifier stage 10_1.

[0106] 2. Moreover, in the differential amplification stage 10_3 shown in FIG. 9, a differential stage B2a is employed in place of the differential stage B2, and the differential stage B1 is the same as that shown in FIG.

[0107] In addition, in the differential stage B2a, a switch circuit 31A is used instead of the switch element 31 shown in FIG. 2, and a switch circuit 32A is used instead of the switch element 32 shown in FIG. 2; other configurations except for these points are the same as those of the differential stage B1 shown in FIG. 2.

[0108] The switch circuit 31A includes switch elements 31a, 31b, and 31c.

[0109] Both switch elements 31a and 31b receive a switch signal S1 and are in an off state while the switch signal S1 is at, for example, logic level 0, and are in an on state while the switch signal S1 is at logic level 1. When the switch element 31a is in an on state, it supplies a predetermined reference voltage Vref or input voltage VI to the gate of the transistor 13 and the switch element 31c via a node nd3a. When the switch element 31b is in an on state, it supplies the reference voltage Vref or input voltage VI to one ends of capacitors Ca and Cf via a node nd3b. The switch element 31c receives a switch signal S2 and is in an off state while the switch signal S2 is at, for example, logic level 0, and is in an on state while the switch signal S2 is at logic level 1. When the switch element 31c is in an on state, it supplies the voltages at one ends of capacitors Ca and Cf to the gate of the transistor 13 via the node nd3a.

[0110] The switch circuit 32A includes switch elements 32a, 32b, and 32c.

[0111] Both switch elements 32a and 32b receive a switch signal S1 and are in an off state while the switch signal S1 is at, for example, logic level 0, and are in an on state while the switch signal S1 is at, for example, logic level 1. When the switch element 32a is in an on state, it supplies an output voltage VO to the gate of the transistor 14 and the switch element 32c via a node nd4a. When the switch element 32b is in an on state, it supplies the output voltage VO to one end of the capacitor Cb and the other end of the capacitor Cf via a node nd4b. When the switch signal S2 is in an off state while the switch signal S2 is at, for example, logic level 0, and is in an on state while the switch signal S2 is at, for example, logic level 1. When the switch element 32c is in an on state, it supplies the voltages at one end of the capacitor Cb and the other end of the capacitor Cf to the gate of the transistor 14 via the node nd4a.

[0112] 9 may be realized by P-channel transistor switches, as shown in Fig. 10. In this case, the relationship between the on and off states of each switch in Fig. 10 and the logic levels is such that the on state is at logic level 0 and the off state is at logic level 1. In addition, when each of the switch elements 21, 22, 32a to 32c and 31a to 31c is realized by P-channel transistor switches, a control circuit CNT_1 is adopted instead of the control circuit CNT.

[0113] As shown in FIG. 11, the control circuit CNT_1 generates a switch signal S1X in a first step, which represents, for example, a logic level 0 to be set to an ON state, and in a second step, which represents, for example, a logic level 1 to be set to an OFF state, and supplies this to the gates of each of the switch elements 21, 31a, 31b, 32a, and 32b as transistor switches, as shown in FIG.

[0114] In addition, the control circuit CNT_1 generates a switch signal S2X as a binary signal that sets the switch elements 22, 31c, and 32c as transistor switches, as shown in FIG. 11, and that sets the switch elements 22, 31c, and 32c as transistor switches, as shown in FIG. 10.

[0115] The following describes the effects obtained by employing the switch circuits 31A and 32A shown in FIG. 9 or 10 instead of the switch elements 31 and 32 shown in FIG.

[0116] As described above, in the configuration shown in Figure 2, capacitor Cf is provided to prevent a decrease in offset cancellation accuracy due to differences in the magnitude of off-leakage currents that occur when switch elements 31 and 32 are in the off state. However, in addition to off-leakage current, another factor that can decrease offset cancellation accuracy is switching noise that occurs when switch elements 31 and 32 change from the on state to the off state. When each switch element is configured as a transistor switch as shown in Figure 10, the transistor switch switches from the on state to the off state by changing the gate voltage of the transistor switch. However, switching noise can occur due to coupling effects of parasitic capacitance between the terminals of the transistor and between surrounding elements as a result of the change in gate voltage, and due to the movement of charge within the channel of the transistor switch, which can decrease offset cancellation accuracy.

[0117] As described above, if the effects of the switching noise of switch elements 31 and 32 are approximately equal and the voltage difference held in capacitor Cf connected to the input pair of differential pair (13, 14) is maintained, the output currents I13 and I14 of differential pair (13, 14) will not fluctuate even if the voltage of the input pair of differential pair (13, 14) fluctuates, making it possible to generate a highly accurate output voltage VO. However, since the effects of the switching noise of switch elements 31 and 32 are not necessarily approximately equal, it is desirable to minimize the generation of switching noise of switch elements 31 and 32.

[0118] Therefore, in the offset cancellation amplifier 100_6 shown in FIG. 9 or FIG. 10, in order to suppress a decrease in offset cancellation accuracy caused by switching noise, switch circuits 31A and 32A having the same functions as the switch elements 31 and 32 are employed instead of the switch elements 31 and 32, respectively.

[0119] The following describes the operation of the transistors 32a to 32c included in the switch circuit 32A, with reference to Figures 12A and 12B. Figures 12A and 12B are cross-sectional views that schematically show the cross-sectional structure of each of the transistors 32a to 32c and their connection to one another. Figure 12A shows the state of each transistor in the first step shown in Figure 11, and Figure 12B shows the state of each transistor during the transition from the first step to the second step. [1st step] First, in the first step, as shown in FIG. 12A, the transistor 32a receives a switch signal S1X of logic level 0 at its gate Ga, turning it on and forming a channel CH between its source region Sa and drain region Da. Furthermore, the transistor 32b receives a switch signal S1X of logic level 0 at its gate Gb, turning it on and forming a channel CH between its source region Sb and drain region Db. Note that in the first step, the transistor 32c receives a switch signal S2X of logic level 1 at its gate Gc, turning it off. Therefore, no channel is formed between the source region Sc and drain region Dc of the transistor 32c.

[0120] In the first step, the output voltage VO is supplied to one end of the capacitor Cb via the transistor 32b and the node nd4b, and the output voltage VO is supplied to the gate of the transistor 14 via the transistor 32a and the node nd4a. [Second process] 12B, when the process moves from the first step to the second step, the switch signal S1X supplied to the gate Ga of the transistor 32a and the gate Gb of the transistor 32b transitions from logic level 0 to logic level 1. As a result, both the transistors 32a and 32b transition from an on state to an off state. Furthermore, the switch signal S2X supplied to the gate Gc of the transistor 32c transitions from logic level 1 to logic level 0, causing the transistor 32c to transition from an off state to an on state.

[0121] Therefore, when the voltage at the gate of each of the transistors 32a, 32b, and 32c transitions, charge moves in the direction shown by the thick solid line in FIG. 12B via the parasitic capacitance Cpc that is parasitic between each gate and source, and between the gate and drain.

[0122] That is, due to parasitic capacitance coupling of the transistors during switching, charges move from the drain region Da of the transistor 32a to the gate Ga. Charges also move from the drain region Db of the transistor 32b to the gate Gb. Furthermore, charges move from the gate Gc of the transistor 32c to the source region Sc and the drain region Dc.

[0123] Therefore, the voltage fluctuation at node nd4a caused by charge transfer from the drain region Da to the gate Ga of transistor 32a is offset by the voltage fluctuation at node nd4a caused by charge transfer from the gate Gc to the source region Sc of transistor 32c. Furthermore, the voltage fluctuation at node nd4b caused by charge transfer from the drain region Db to the gate Gb of transistor 32b is offset by the voltage fluctuation at node nd4b caused by charge transfer from the gate Gc to the source region Sc of transistor 32c. As a result, charge transfer due to parasitic capacitance coupling of transistors during switching has almost no effect on the charge stored in capacitor Cb, and potential fluctuation at node nd4b can be suppressed. Furthermore, the transition between the on and off states of the transistors during switching causes the creation and disappearance of channels CH, which in turn causes charge migration. In Figures 12A and 12B, the charges accumulated in the channels CH of transistors 32a and 32b in the on state in step 1 disperse and migrate to the drain and source regions of each transistor when they change to the off state in step 2 and the channels CH disappear. Approximately half of the charges in the channel CH of transistor 32a migrate toward the drain region Da, as shown by the bold solid line in Figure 12B, and then migrate into the channel CH of transistor 32c, which is in the on state in step 2. Similarly, approximately half of the charges in the channel CH of transistor 32b migrate toward the drain region Db, as shown by the bold solid line in Figure 12B, and then migrate to the channel CH of transistor 32b, which is in the on state in step 2.

[0124] That is, about half of the charge in the channel CH of the transistor 32a in the first step moves directly to the channel CH of the transistor 32c in the second step via the node nd4a, and about half of the charge in the channel CH of the transistor 32b in the first step moves directly to the channel CH of the transistor 32c in the second step via the node nd4b. Therefore, the charge movement in the channel CH of the transistor during switching has almost no effect on the charge stored in the capacitor Cb, and fluctuations in the potential of the node nd4b can be suppressed.

[0125] The charge transfer between the transistors 32a to 32c in the first step and the second step as shown in FIGS. 12A and 12B also occurs in the transistors 31a to 31c included in the switch circuit 31A.

[0126] This makes it possible to suppress voltage fluctuations in the voltage at one end of capacitor Ca (voltage at node nd3b) and the voltage at one end of capacitor Cb (voltage at node nd4b) caused by the switching operations of each of transistors 31a, 31b, 32a, and 32b during the transition from the first step to the second step.

[0127] Therefore, it is possible to perform highly accurate offset cancellation without increasing the capacitance of the capacitors Ca, Cb, and Cf.

[0128] In the offset cancellation amplifiers 100_1 to 100_6 shown in FIGS. 2 and 5 to 10, N-channel transistors are used as the transistors (11 to 14) that form the first and second differential pairs, but P-channel transistors may also be used.

[0129] 9 or 10 have the same switching function as the switch elements 31 and 32 shown in FIGS. 2, 5 to 8, and therefore the switch circuits 31A and 32A are also expressed as being in an on state or an off state. However, the on state of the switch circuit 31A means that the switch elements 31a and 31b are in an on state and the switch element 31c is in an off state, and the off state of the switch circuit 31A means that the switch elements 31a and 31b are in an off state and the switch element 31c is in an on state. The same applies to the switch circuit 32A.

[0130] In short, the offset cancellation amplifier according to the present invention may include the following first to third differential pairs, first and second capacitive elements, a switch circuit, and an output amplification stage.

[0131] That is, the first differential pair (11, 12) receives an input voltage (VI) at one end and an input or output voltage (VO) at the other end, and outputs a first current pair (I11, I12) corresponding to the voltage difference between the voltage at one end and the voltage at the other end. When the switch circuits (31 and 32, 31A and 32A) are in the on state, they supply a predetermined reference voltage (Vref) or input voltage (VI) to one end of a first capacitance element (Ca) and supply the output voltage (VO) to one end of a second capacitance element (Cb). The second differential pair (13, 14) has one end of the first capacitance element (Ca) connected to one end of itself and one end of the second capacitance element (Cb) connected to the other end of itself, and outputs a second current pair (I13, I14) corresponding to the voltage difference between the voltage at one end and the voltage at the other end of itself. The output amplifier stages (90_1, 90_2) receive the first and second current pairs and generate an output voltage (VO) by sending a current corresponding to the magnitude of the current obtained by current-coupled the first and second current pairs to an output node (nd0). One end of the third capacitance element (Cf) is connected to one end of the first capacitance element (Ca) and the other end is connected to one end of the second capacitance element (Cb).

[0132] In this offset cancellation amplifier, a reference voltage (input voltage) is first commonly input to the input pair of the first differential pair (11, 12), and an output voltage on which the reference voltage (input voltage) and an offset voltage are superimposed is input to the input pair of the second differential pair (13, 14). That is, by turning on the switch circuit described above, the reference voltage (input voltage) is supplied to one end of the first capacitance element (Ca) and the output voltage is supplied to one end of the second capacitance element (Cb). As a result, the reference voltage (input voltage) is stored in the first capacitance element (Ca), the output voltage is stored in the second capacitance element (Cb), and the offset voltage, which is the difference between the output voltage and the reference voltage (input voltage), is stored in the third capacitance element (Cf) (first step).

[0133] Then, a reference voltage (input voltage) and an output voltage are input to the input pair of the first differential pair (11, 12), and the input pair of the second differential pair (13, 14) holds the voltage accumulated in the first capacitance element (Ca), the voltage accumulated in the second capacitance element (Cb), and the offset voltage accumulated in the third capacitance element (Cf) by turning off the switch circuit. At this time, the first differential pair (11, 12) outputs a first current pair (I11, I12) corresponding to the voltage difference between the reference voltage (input voltage) and the output voltage, and the second differential pair (13, 14) outputs a second current pair (I13, I14) that is the same as in the first step and corresponds to the offset voltage, and the first current pair and the second current pair are current-coupled in the output amplification stages (90_1, 90_2). Since the same current as in the first step flows through the second current pair (I13, I14), the same current also flows through the first current pair (I11, I12). That is, the output amplifier stages (90_1, 90_2) output an output voltage from which the offset voltage has been removed, and act to make the voltage difference between the reference voltage (input voltage) input to the input pair of the first differential pair (11, 12) and the output voltage zero (second step).

[0134] However, when the switch circuit transitions from the on state to the off state in the second step, an off-leak current flows, which may cause different fluctuations in the voltages held in the first and second capacitance elements.

[0135] Therefore, in the offset cancellation amplifier according to the present invention, a third capacitance element is provided to one end of each of the first and second capacitance elements, with one end and the other end of the third capacitance element being connected to the other end of the third capacitance element, thereby preventing the voltage difference (offset voltage) between the input pair of the second differential pair (13, 14) from fluctuating due to the off-leak current and maintaining the voltage difference (offset voltage).

[0136] Furthermore, by configuring the switch circuit in a way that can suppress the effects of switching noise (parasitic capacitance coupling and movement of charge within the channel) that occurs when the switch circuit (31A and 32A) transitions from the on state to the off state, it is possible to suppress fluctuations in the voltage at one end of each of the first and second capacitance elements (Ca and Cb) that are accumulated when the switch circuit (31A and 32A) is in the on state.

[0137] Therefore, according to the present invention, it is possible to generate a highly accurate output voltage corresponding to an input voltage by highly accurate offset cancellation. [Example]

[0138] FIG. 13 is a block diagram showing a schematic configuration of a display device 400 incorporating any one of the offset cancellation amplifiers 100_1 to 100_6 shown in FIGS.

[0139] The display device 400 includes a display controller 101 , a gate driver 102 , a data driver 103 , and a display panel 200 .

[0140] The display panel 200 is made of, for example, a liquid crystal or organic EL display panel, and has gate lines GL1 to GLr (r is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, and data lines DL1 to DLw (w is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen. At each intersection of the gate lines GL1 to GLr and the data lines DL1 to DLw, a display cell (area surrounded by a dashed line) that displays red, green, or blue is formed.

[0141] The display controller 101 receives a video signal VD and supplies, to the gate driver 102, a gate timing signal that indicates the timing at which to apply a gate selection signal to each of the gate lines GL1 to GLr, based on the video signal VD.

[0142] In addition, based on the video signal VD, the display controller 101 generates a video data signal DVS that includes various control signals including a clock signal, a load signal, etc., and a series of pixel data pieces that represent the brightness level of each pixel as a digital value, and supplies this to the data driver 103.

[0143] The gate driver 102 sequentially generates gate selection signals including at least one pulse for selecting a gate line in response to the gate timing signal supplied from the display controller 101, and supplies the gate selection signals to each of the gate lines GL1 to GLr of the display panel 200.

[0144] The data driver 103 receives each of the pixel data pieces included in the video data signal DVS for one horizontal scanning line (w pieces), converts each pixel data piece into a drive signal having a voltage value corresponding to the brightness level represented by the pixel data piece, and supplies the generated w drive signals as drive signals G1 to Gw to the data lines DL1 to DLw of the display panel 200, respectively.

[0145] FIG. 14 is a block diagram showing a schematic internal configuration of the data driver 103. As shown in FIG.

[0146] As shown in FIG. 14, the data driver 103 includes a control circuit 120, a data latch section 121, a grayscale voltage generating circuit 122 as a level voltage generating circuit according to the present invention, a decoder section 123, and an amplifier section .

[0147] The control circuit 120 receives the video data signal DVS and extracts from the video data signal DVS various control signals including a horizontal synchronization signal, a vertical synchronization signal, a clock signal, a load signal, etc., and a series of pixel data fragments. The control circuit 120 supplies the extracted clock signal, load signal, and series of pixel data fragments to a data latch unit 121, and also supplies a control signal Sgma that handles gamma setting and timing control corresponding to the display device to a grayscale voltage generation circuit 122. The grayscale voltage generation circuit 122 may also receive voltages VGMA0 and VGMA1 from the outside as reference gamma voltages.

[0148] The data latch unit 121 sequentially captures each pixel data piece in the sequence of pixel data pieces at the timing of the clock signal in response to the load signal. Every time the data latch unit 121 captures w pixel data pieces, it outputs the w pixel data pieces to the decoder unit 123 as pixel data P1 to Pw.

[0149] The grayscale voltage generation circuit 122 generates grayscale voltages VR0 to VR(n-1) (n is an integer of 2 or more), each having a voltage value according to a specified gamma characteristic, and supplies the generated grayscale voltages VR0 to VR(n-1) to the decoder unit 123. In generating the grayscale voltages VR0 to VR(n-1), the grayscale voltage generation circuit 122 cancels the offset of an operational amplifier (described later) included in itself for each frame period in accordance with a timing control signal included in the control signal Sgma.

[0150] The decoder unit 123 includes w decoders DEC that individually receive the pixel data P1 to Pw output from the data latch unit 121. Each of the decoders DEC receives the above-mentioned gradation voltages VR0 to VR(n-1) and selects, from the gradation voltages VR0 to VR(n-1), a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece that it received. The decoder unit 123 receives the w gradation voltages selected by each decoder DEC and supplies gradation signals V1 to Vw having the respective voltage values ​​to the amplifier unit 124.

[0151] The amplifier section 124 amplifies the grayscale signals V1 to Vw individually and outputs the amplified signals to the data lines DL1 to DLw of the display panel 200 as the drive signals G1 to Gw.

[0152] The grayscale voltage generating circuit 122 will be described in detail below.

[0153] FIG. 15 is a circuit diagram showing an example of the internal configuration of the grayscale voltage generating circuit 122. As shown in FIG.

[0154] 15, the grayscale voltage generation circuit 122 includes amplifiers GA0 and GA1, a gamma selector GSL, a first resistor string LD1, a second resistor string LD2, and a gamma control circuit GCNT. The grayscale voltage generation circuit 122 further includes gamma buffers GB0 to GB(m-1) (m is an integer equal to or greater than 2 and less than n).

[0155] The amplifiers GA0 and GA1 are input gamma amplifiers, each consisting of, for example, a voltage follower operational amplifier whose inverting input terminal and output terminal are connected. The amplifier GA0 receives a first DC voltage VGMA0 at its non-inverting input terminal and applies a voltage having the same voltage value as the voltage VGMA0 to the node nda0. The amplifier GA1 receives a second DC voltage VGMA1, which has a voltage value lower than the voltage VGMA0, at its non-inverting input terminal and applies a voltage having the same voltage value as the voltage VGMA1 to the node nda1.

[0156] The resistor string LD1 consists of first to xth (x is an integer greater than or equal to 2) resistors connected in series between nodes nda0 and nda1, and supplies the voltages at each of the (x+1) connection points (called taps) of the first to xth resistors to the gamma selector GSL as reference voltages Rf0 to Rfx.

[0157] The gamma control circuit GCNT supplies a gamma characteristic designation signal de that designates a desired gamma characteristic to the gamma selector GSL. Furthermore, the gamma control circuit GCNT generates binary (logical level 0 or 1) switch signals S1 and S2 (or S1X and S2X) that control the offset cancel operation in accordance with a timing control signal included in the control signal Sgma, and supplies them to the gamma buffers GB0 to GB(m-1), respectively.

[0158] That is, the gamma control circuit GCNT includes a configuration equivalent to the control circuit CNT or CNT_1 included in the offset cancellation amplifiers 100_1 to 100_6 shown in FIGS. 2, 5 to 10 as a circuit unit that generates the switch signals S1 and S2 (or S1X and S2X). That is, as shown in FIG. 16, the gamma control circuit GCNT executes a first process within a range from time ts to time th within a vertical blanking period (from time t0 to time t1) for each frame period, and then executes a second process. Note that, when each switch element is configured with an Nch transistor, the gamma control circuit GCNT supplies a switch signal S1 of logic level 1 (VE2) that sets each switch element to an on state to the switch elements 21, 31, and 32, or the switch elements 21, 31a, 31b, 32a, and 32b in the first process. Furthermore, in the first step, the gamma control circuit GCNT supplies a switch signal S2 of logic level 0 (VE1) to the switch element 22, or the switch elements 22, 31c, and 32c, which sets each switch element to the OFF state.

[0159] 16, in a second step following the first step, the gamma control circuit GCNT supplies a switch signal S1 of logic level 0 (VE1) that sets each switch element to an OFF state to the switch elements 21, 31, and 32, or the switch elements 21, 31a, 31b, 32a, and 32b. Furthermore, in the second step, the gamma control circuit GCNT supplies a switch signal S2 of logic level 1 (VE2) that sets each switch element to an ON state to the switch element 22, or the switch elements 22, 31c, and 32c.

[0160] In the gamma control circuit GCNT, when each switch element is configured with a Pch transistor, the switch signals that control each switch element to an on or off state are switch signals S1X and S2X that are in phase opposite to the switch signals S1 and S2 shown in FIG.

[0161] Furthermore, when the gamma buffers GB0 to GB(m-1) of the grayscale voltage generation circuit 122 are configured with the offset cancellation amplifiers 100_1 to 100_6 shown in FIGS. 2, 5 to 10, the second step period is much longer than the first step period, at about one frame period (at 60 Hz drive, one frame period is about 16.7 ms). Therefore, the off-leak currents of the switch elements 31 and 32 and the switch elements 31a, 31b, 32a, and 32b, which are connected to one end of the capacitors Ca and Cb, respectively, and which are controlled to the off state in the second step, cannot be ignored. However, even if different off-leak currents occur for each switch element in the second step, the provision of capacitor Cf (>Ca, Cb) suppresses fluctuations in the voltage difference between the input pairs of the second differential pair (13, 14). As a result, the output voltage of the offset cancellation amplifier is maintained stable for a long period of time.

[0162] Therefore, even if offset cancellation amplifiers using capacitive elements with relatively small capacitance values ​​are used as the gamma buffers GB0 to GB(m-1), it is possible to generate and hold a highly accurate output voltage corresponding to the input voltage for a long period of time.

[0163] In this way, in the grayscale voltage generation circuit 122 included in the data driver 103, a reference voltage generation unit consisting of amplifiers GA0, GA1, resistor string LD1, and gamma selector GSL generates m (m is an integer greater than or equal to 2) reference voltages in accordance with the desired gamma characteristics.

[0164] Furthermore, the grayscale voltage generating circuit 122 includes a resistor string LD2 and first to m-th gamma buffers GB0 to GB(m-1). The resistor string LD2 includes a plurality of resistors connected in series to each other via a plurality of taps, and outputs grayscale voltages VR0 to VR(n-1) having different voltage levels from each of the taps.

[0165] The first to m-th gamma buffers GB0 to GB(m-1) individually receive the m reference voltages and amplify them to generate gamma voltages VG0 to VG(m-1), which are applied to the taps of the resistor string LD2. Each of the first to m-th gamma buffers GB0 to GB(m-1) is configured with one of the offset cancellation amplifiers 100_1 to 100_6 shown in Figures 2 and 5 to 10, receives the reference voltage it receives as an input voltage, amplifies the input voltage, and outputs the resulting output voltage as the gamma voltage.

[0166] With this configuration, it is possible to generate highly accurate grayscale voltages VR0 to VR(n-1) having voltage values ​​that conform to the desired gamma characteristics through highly accurate offset cancellation without increasing the size of each transistor included in each of the gamma buffers GB0 to GB(m-1). [Explanation of symbols]

[0167] 10_1 Differential amplifier stage 11~16 Transistors 21, 22, 31, 32 Switch elements 90_1 Output amplifier stage 100_1 Offset Cancellation Amplifier 122 Gradation voltage generation circuit Ca, Cb, Cf capacitors CNT control circuit GB0~GB(m-1) Gamma buffer

Claims

1. An offset cancellation amplifier receives an input voltage, outputs an output voltage corresponding to the input voltage from an output node, and removes an offset voltage occurring in the output voltage, a first differential pair that receives the input voltage at one end and the input voltage or the output voltage at the other end, and outputs a first current pair corresponding to a voltage difference between the voltage at the one end and the voltage at the other end; first and second capacitive elements; a switch circuit that, when in an on state, supplies a predetermined reference voltage or the input voltage to one end of the first capacitance element and supplies the output voltage to one end of the second capacitance element; a second differential pair, the one end of which is connected to one end of the first capacitance element and the one end of which is connected to the other end of the second capacitance element, and which outputs a second current pair corresponding to a voltage difference between a voltage at one end of the first capacitance element and a voltage at the other end of the second capacitance element; an output amplifier stage that receives the first current pair and the second current pair and generates the output voltage by sending a current corresponding to a magnitude of a current obtained by current-combining the first current pair and the second current pair to the output node; a third capacitance element having one end connected to the one end of the first capacitance element and the other end connected to the one end of the second capacitance element.

2. 2. The offset cancellation amplifier according to claim 1, wherein the capacitance of the third capacitance element is larger than the capacitances of the first and second capacitance elements.

3. a first step of supplying the input voltage to the other end of the first differential pair and turning on the switch circuit to store the reference voltage or the input voltage in the first capacitance element and store the output voltage on which the offset voltage is superimposed in the second capacitance element; and a second step of supplying the output voltage to the other end of the first differential pair and holding the voltages stored in the first and second capacitive elements in the first step as the voltages at the one end and the other end of the second differential pair, respectively, by switching the switch circuit to an off state.

4. 2. The offset cancellation amplifier according to claim 1, wherein the conductivity type of the pair of transistors that constitute the first differential pair is different from the conductivity type of the pair of transistors that constitute the second differential pair.

5. The switch circuit a first switch element that receives the reference voltage or the input voltage and supplies the reference voltage or the input voltage to the one end of the second differential pair when in the on state; a second switch element that receives the reference voltage or the input voltage and supplies the reference voltage or the input voltage to the one end of the first capacitance element when in the on state; a third switch element that cuts off the connection between the one end of the second differential pair and the one end of the first capacitive element when in the on state; a fourth switch element that receives the output voltage and supplies the output voltage to the other end of the second differential pair when in the on state; a fifth switch element that receives the output voltage and supplies the output voltage to the one end of the second capacitance element when in the on state; and a sixth switch element that cuts off the connection between the other end of the second differential pair and the one end of the second capacitance element when in the on state. The offset cancellation amplifier according to any one of claims 1 to 4.

6. The output amplifier stage comprises: a first current mirror circuit that causes a current corresponding to the magnitude of a current obtained by combining one current of the first current pair and one current of the second current pair to flow to a first node, and causes a current obtained by superimposing a current obtained by combining the other current of the first current pair and the other current of the second current pair on a current obtained by folding back the current flowing to the first node, and causes a current to flow to a second node; a second current mirror circuit that mirrors the current flowing through the third node and causes the resulting current to flow through a fourth node; a first floating current source disposed between a first node and a third node, the first floating current source coupling a current flowing in the first node and a current flowing in the third node; a second floating current source disposed between the second and fourth nodes and coupling a current flowing in the second node and a current flowing in the fourth node; a first output transistor having a gate connected to the second node and transmitting a current corresponding to the magnitude of the voltage of the second node to the output node; 2. The offset cancellation amplifier according to claim 1, further comprising: a second output transistor having its gate connected to the fourth node and extracting from the output node a current corresponding to the magnitude of the voltage of the fourth node.

7. a display driver including a grayscale voltage generating circuit that generates a plurality of grayscale voltages, selecting a grayscale voltage corresponding to a luminance level indicated by a video signal from the plurality of grayscale voltages, and sending a drive signal having the selected grayscale voltage to a display panel, The gradation voltage generating circuit a resistor string including a plurality of resistors connected in series to each other via a plurality of taps, and outputting the plurality of grayscale voltages having different voltage levels from each of the taps; a reference voltage generating unit that generates m (m is an integer of 2 or more) reference voltages according to a desired gamma characteristic; first to m-th gamma buffers that individually receive the m reference voltages, individually amplify the received reference voltages, thereby generating m gamma voltages and applying the m gamma voltages to the taps of the resistor string, respectively; A display driver characterized in that each of the first to mth gamma buffers is an offset cancellation amplifier as described in claim 1, which receives the reference voltage that it receives as the input voltage, and outputs the output voltage output from the offset cancellation amplifier as the gamma voltage.

8. a control circuit for controlling the first to mth gamma buffers; The control circuit, for each of the first to m-th gamma buffers, a first step of supplying the input voltage to the other end of the first differential pair and turning on the switch circuit to store the reference voltage or the input voltage in the first capacitance element and store the output voltage on which the offset voltage is superimposed in the second capacitance element; a second step of supplying the output voltage to the other end of the first differential pair and switching the switch circuit to an off state, thereby holding the voltages stored in the first and second capacitance elements in the first step as the voltages at the one end and the other end of the second differential pair, respectively.

9. 9. The display driver according to claim 8, wherein the control circuit performs the first step within a vertical blanking period of a frame period of the video signal.

10. A display panel; a display driver that includes a grayscale voltage generation circuit that generates a plurality of grayscale voltages, selects a grayscale voltage corresponding to a luminance level indicated by a video signal from the plurality of grayscale voltages, and sends a drive signal having the selected grayscale voltage to the display panel, The gradation voltage generating circuit a resistor string including a plurality of resistors connected in series to each other via a plurality of taps, and outputting the plurality of grayscale voltages having different voltage levels from each of the taps; a reference voltage generating unit that generates m (m is an integer of 2 or more) reference voltages according to a desired gamma characteristic; first to m-th gamma buffers that individually receive the m reference voltages, individually amplify the received reference voltages, thereby generating m gamma voltages and applying the m gamma voltages to the taps of the resistor string, respectively; A display device characterized in that each of the first to mth gamma buffers is an offset cancellation amplifier as described in claim 1, which receives the reference voltage that it receives as the input voltage, and outputs the output voltage output from the offset cancellation amplifier as the gamma voltage.

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