Non-volatile memory device

Abstract

To provide a nonvolatile memory device that can be miniaturized.SOLUTION: A decoder (20, 30) is configured such that each of switching elements (221a to 221b, 222a to 222d) in a k-th (k is an integer satisfying k<n) selection group (221, 222) is connected to a plurality of different switching elements (222a to 222d, 223a to 223h) among the plurality of switching elements (222a to 222d, 223a to 223h) included in a (k+1)-th selection group (222, 223), and each of switching elements (221a, 221b) of a first selection group (221) is connected to a voltage terminal (VSS) to which a predetermined voltage is applied, and each of switching elements (223a to 223h) of an n-th selection group (223) is connected to a driver circuit (23).SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The invention disclosed herein relates to non-volatile memory devices. [Background technology]

[0002] The semiconductor nonvolatile memory circuit proposed in Patent Document 1 selects a memory cell for performing an information read or write operation by selecting a word line with an X decoder and a bit line with a Y decoder. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-212061

[0004] [overview] In recent years, with the increase in memory capacity, there has been an increasing demand for miniaturization of each circuit in a semiconductor nonvolatile memory circuit.

[0005] The nonvolatile memory device disclosed in this specification is configured to have a first memory element configured to output a first current, a second memory element arranged in parallel with the first memory element and configured to output a second current, a current supply circuit configured to supply a reference current that fluctuates within a certain range, a sense amplifier configured to compare the magnitudes of the first current and the reference current and the second current and the reference current, and a current difference acquisition circuit connected to the sense amplifier and configured to acquire the difference between the current value of the first current and the current value of the second current based on a first comparison result that is a comparison result of the first current and the reference current and a second comparison result that is a comparison result of the second current and the reference current. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the overall configuration of a nonvolatile memory device. [Figure 2]FIG. 2 is a circuit diagram of a conventional X decoder. [Figure 3] FIG. 3 is a diagram showing a transistor cell. [Figure 4] FIG. 4 is a layout diagram of a conventional X decoder. [Figure 5] FIG. 5 is a diagram showing the relationship between addressing signals and selected word lines. [Figure 6] FIG. 6 is a circuit diagram of an X decoder used in the nonvolatile memory device according to this embodiment. [Figure 7] FIG. 7 is a layout diagram of the X decoder. [Figure 8] FIG. 8 is a circuit diagram of an X decoder used in the nonvolatile memory device of the second embodiment. [Figure 9] FIG. 9 is a schematic circuit diagram showing the operation state of the X decoder. [Figure 10] FIG. 10 is a layout diagram of an X decoder used in the nonvolatile memory device of the third embodiment. [Figure 11] FIG. 11 is a layout diagram of an X decoder used in the nonvolatile memory device of the fourth embodiment.

[0007] [Detailed explanation] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure consists of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, an N-channel MOS field effect transistor will be referred to as an NMOS transistor, and a P-channel MOS field effect transistor will be referred to as a PMOS transistor.

[0008] First Embodiment Fig. 1 is a block diagram showing an example of the overall configuration of a nonvolatile memory device 1. The nonvolatile memory device 1 shown in Fig. 1 has a memory array 10, an X-decoder 20, a Y-decoder 30, and a control circuit 40. Note that the nonvolatile memory device 1 may be configured as an IC (Integrated Circuit) in which the memory array 10, the X-decoder 20, the Y-decoder 30, and the control circuit 40 are integrated into a single package.

[0009] The memory array 10 has m word lines WL1 to WLm laid in the X-axis direction, 2n bit lines BL1 to BL2n laid in the Y-axis direction, and a plurality of (m×n) memory cells CELL arranged in a matrix along the word lines WL1 to WLm and the bit lines BL1 to BL2n. The configuration and operation of the memory array 10 will be described in detail later.

[0010] The X decoder (row decoder) 20 drives the word lines WL1 to WLm in response to instructions from the control circuit 40. The Y decoder (column decoder) 30 drives the bit lines BL1 to BL2n in response to instructions from the control circuit 40. The control circuit 40 controls each part of the device in response to commands input from outside the device.

[0011] The memory array 10 has m word lines WL1 to WLm laid in the X-axis direction (second direction), 2n bit lines BL1 to BL2n laid in the Y-axis direction, and a plurality of (m×n) memory cells CELL arranged in a matrix along the word lines WL1 to WLm and the bit lines BL1 to BL2n. A control circuit 40 controls an X-decoder 20 to select a word line and a Y-decoder 30 to select a bit line, thereby selecting a memory cell CELL from which information is to be read or written.

[0012] <Xデコーダ20、Yデコーダ30> To easily understand the features of the X decoder 20 and Y decoder 30 of the nonvolatile memory device 1 according to the present disclosure, a conventional X decoder 9 will first be described. FIG. 2 is a circuit diagram of the conventional X decoder 9. FIG. 3 is a diagram showing a transistor cell. FIG. 4 is a layout diagram of the conventional X decoder 9. For ease of explanation, the X decoder 9 shown in FIGS. 2 and 4 is configured to control eight word lines WL1 to WL8. In the X decoder 9 shown in FIG. 4, the pre-decoder 91 is omitted from the illustration.

[0013] As shown in Fig. 2, the X decoder 9 has a predecoder 91, a selection circuit 92, and a driver circuit 93. As shown in Fig. 2, the predecoder 91 has three predecode circuits 911, 912, and 913. The predecoder 91 outputs selection signals ST1, ST2, ST3, ST4, ST5, and ST6 for determining the word line to be selected based on an address designation signal Ax sent from a control circuit. The selection signals ST1, ST2, ST3, ST4, ST5, and ST6 are each signals that are either high level or low level, which has a voltage lower than that of the corresponding signal.

[0014] The addressing signal Ax is 3-bit data, and the data for each digit is either "0" or "1." The pre-decoder 91 extracts information for each digit using a separator such as a multiplexer (not shown). The first digit information Ax1 is sent to the pre-decoding circuit 911, the second digit information Ax2 is sent to the pre-decoding circuit 912, and the third digit information Ax3 is sent to the pre-decoding circuit 913. The first digit of the addressing signal Ax is the most significant bit. For example, if the addressing signal Ax is (110), the first digit information is "1," the second digit information is "1," and the third digit information is "0."

[0015] The pre-decoding circuit 911 outputs a first selection signal ST1 and a second selection signal ST2. When the first digit information Ax1 is "0", the pre-decoding circuit 911 outputs a high-level second selection signal ST2. At this time, the first selection signal ST1 is at a low level. Furthermore, when the first digit information Ax1 is "1", the pre-decoding circuit 911 outputs a high-level first selection signal ST1. At this time, the second selection signal ST2 is at a low level.

[0016] Similarly, in the pre-decoding circuit 912, when the second digit information Ax2 is "0", the fourth selection signal ST4 is at a high level and the third selection signal ST3 is at a low level. Also, when the second digit information Ax2 is "1", the third selection signal ST3 is at a high level and the fourth selection signal ST4 is at a low level.

[0017] Furthermore, in the pre-decoding circuit 913, when the third digit information Ax3 is "0", the sixth selection signal ST6 is at a high level and the fifth selection signal ST5 is at a low level. Also, when the third digit information Ax3 is "1", the fifth selection signal ST5 is at a high level and the sixth selection signal ST6 is at a low level.

[0018] The selection signals ST1, ST2, ST3, ST4, ST5, and ST6 output from the pre-decoder 91 are supplied to a selection circuit 92. The selection circuit 92 has a first selection group 921, a second selection group 922, and a third selection group 923. The first selection group 921 has eight switching elements 921a to 921h connected in parallel. Similarly, the second selection group 922 has eight switching elements 922a to 922h connected in parallel. The third selection group 923 has eight switching elements 923a to 923h connected in parallel. The switching elements included in the first selection group 921 are referred to as the first-stage switching element 921a, the second-stage switching element 921b, ..., the eighth-stage switching element 921h. The same applies to the selection groups 922 and 923.

[0019] The configuration of the switching elements will be described with reference to the drawings. All of the switching elements in the selection circuit 92 have the same configuration. The switching elements shown in FIGS. 2 and 3 are NMOS transistor cells 70. FIG. 3 shows an example of an NMOS transistor cell incorporated in the nonvolatile memory device 1. As shown in FIG. 3, the NMOS transistor cell 70 has a source region 70S, a drain region 70D, and a gate 70G.

[0020] In the NMOS transistor cell 70, the source region 70S and the drain region 70D are n-type semiconductor layers formed on the upper surface of a p-type semiconductor substrate. The source region 70S and the drain region 70D are spaced apart, and a gate electrode 70G is disposed in the region between the source region 70S and the drain region 70D. In the following description, the source region 70S, the drain region 70D, and the gate electrode 70G will be simply referred to as the source 70S, the drain 70D, and the gate 70G. The NMOS transistor used as a switching element in the selection circuit 92 of the X-decoder 9 has a rectangular shape in a plan view, but is not limited to this.

[0021] In the selection circuit 92, switching elements of the same stage in each of the selection groups 921, 922, and 923 are connected in series. For example, the drain of the first-stage switching element 921a in the first selection group 921 is connected to the source of the first-stage switching element 922a in the second selection group 922. Furthermore, the drain of the first-stage switching element 922a in the second selection group 922 is connected to the source of the first-stage switching element 923a in the third selection group 923.

[0022] The source of the first-stage switching element 921a in the first selection group 921 is connected to a VSS terminal to which a reference voltage is supplied. The VSS terminal may be, for example, a ground voltage terminal, but is not limited to this. The reference voltage may be any voltage that serves as a reference for the operation of the nonvolatile memory device. The drain of the first-stage switching element 923a in the third selection group 923 is connected to a first-stage inverter element 93a (described later) of the driver circuit 93. Other stages in each selection group of the selection circuit 92 are connected in a similar manner.

[0023] Any one of the selection signals ST1, ST2, ST3, ST4, ST5, and ST6 output from the pre-decoder 91 is input to the gate 70G of each switching element of the selection circuit 92.

[0024] The first-stage switching element 923a to the eighth-stage switching element 923h of the third selection group 923 of the selection circuit 92 all output decision signals DECOUT1 to DECOUT8. The decision signals DECOUT1 to DECOUT8 are supplied to the driver circuit 93.

[0025] The driver circuit 93 has first-stage inverter elements 93a to eighth-stage inverter elements 93h, which correspond to the number of stages in the selection circuit 92, i.e., eight stages in the X decoder 9. The first-stage inverter elements 93a to eighth-stage inverter elements 93h are arranged in parallel. The drains 70D of the switching elements 923a to 923h of each stage in the third selection group 923 of the selection circuit 92 are connected to the inputs of the first-stage inverter elements 93a to eighth-stage inverter elements 93h, respectively (see FIG. 4). The decision signals DECOUT1 to DECOUT8 output from the first-stage switching elements 923a to eighth-stage switching elements 923h of the third selection group 923 are input to the inputs of the first-stage inverter elements 93a to eighth-stage inverter elements 93h, respectively.

[0026] The decision signals DECOUT1 to DECOUT8 are signals whose states switch to a high level or a low level whose voltage level is lower than the high level. When the decision signals DECOUT1 to DECOUT8 switch to a low level, the outputs of the first-stage inverter element 93a to the eighth-stage inverter element 93h to which the decision signals DECOUT1 to DECOUT8 are input switch to a high level.

[0027] The decision signals DECOUT1 to DECOUT8 are signals that switch to low level only when all of the switching elements connected in series, in other words, all of the switching elements in the same stage of each selection group, are on.

[0028] The outputs of the inverter elements 93a to 93h in each stage are connected to word lines of the memory array, here word lines WL1 to WL8. That is, the word line that drives the memory cell CELL is selected by the outputs of the first-stage inverter element 93a to the eighth-stage inverter element 93h. When the outputs of the first-stage inverter element 93a to the eighth-stage inverter element 93h go high, the word line connected to the inverter element that is outputting high is selected.

[0029] 2 and 4, the first selection signal ST1 and the second selection signal ST2 are input to the gates 70G of the switching elements 921a to 921h of each stage of the first selection group 921 of the selection circuit 92. More specifically, the second selection signal ST2 is input to the gates 70G of the first-stage switching element 921a to the fourth-stage switching element 921d. Furthermore, the first selection signal ST1 is input to the gates 70G of the fifth-stage switching element 921e to the eighth-stage switching element 921h.

[0030] When the first-digit information Ax1 of the addressing signal Ax is "0," the second selection signal ST2 goes high. At this time, the drains 70D and sources 70S of the first-stage switching elements 921a to the fourth-stage switching elements 921d of the first selection group 921 of the selection circuit 92 are conductive. That is, the first-stage switching elements 921a to the fourth-stage switching elements 921d are turned on. Also, when the first-digit information Ax1 of the addressing signal Ax is "0," the first selection signal ST1 goes low. At this time, the drains 70D and sources 70S of the fifth-stage switching elements 921e to the eighth-stage switching elements 921h of the first selection group 921 of the selection circuit 92 are non-conductive. That is, the fifth-stage switching elements 921e to the eighth-stage switching elements 921d are turned off.

[0031] Conversely, when the first-digit information Ax1 of the addressing signal Ax is "1," the second selection signal ST2 goes low. At this time, the drains 70D and sources 70S of the first-stage switching elements 921a to the fourth-stage switching elements 921d of the first selection group 921 of the selection circuit 92 are conductive. That is, the first-stage switching elements 921a to the fourth-stage switching elements 921d are turned off. Also, when the first-digit information Ax1 of the addressing signal Ax is "1," the first selection signal ST1 goes high. At this time, the drains 70D and sources 70S of the fifth-stage switching elements 921e to the eighth-stage switching elements 921h of the first selection group 921 of the selection circuit 92 are conductive. That is, the fifth-stage switching elements 921e to the eighth-stage switching elements 921d are turned on.

[0032] 2 and 4, the third selection signal ST3 and the fourth selection signal ST4 are input to the gates 70G of the switching elements 922a to 922h of each stage of the second selection group 922 of the selection circuit 92. More specifically, the fourth selection signal ST4 is input to the gates 70G of the first-stage switching element 922a, the second-stage switching element 922b, the fifth-stage switching element 922e, and the sixth-stage switching element 922f. The third selection signal ST3 is input to the gates 70G of the third-stage switching element 922c, the fourth-stage switching element 922d, the seventh-stage switching element 922g, and the eighth-stage switching element 922h.

[0033] When the second-digit data Ax2 of the addressing signal Ax is "0," the fourth selection signal ST4 goes high. At this time, the drains 70D and sources 70S of the first-stage switching element 922a, the second-stage switching element 922b, the fifth-stage switching element 922e, and the sixth-stage switching element 922f of the second selection group 922 of the selection circuit 92 are conductive. That is, the first-stage switching element 922a, the second-stage switching element 922b, the fifth-stage switching element 922e, and the sixth-stage switching element 922f are turned on. Furthermore, when the second-digit data Ax2 of the addressing signal Ax is "0," the third selection signal ST3 goes low. At this time, the drains 70D and sources 70S of the third-stage switching element 922c, the fourth-stage switching element 922d, the seventh-stage switching element 922g, and the eighth-stage switching element 922h of the second selection group 922 of the selection circuit 92 are in a non-conductive state. In other words, the third-stage switching element 922c, the fourth-stage switching element 922d, the seventh-stage switching element 922g, and the eighth-stage switching element 922h are turned off.

[0034] Conversely, when the second-digit information Ax2 of the addressing signal Ax is "1," the fourth selection signal ST4 goes low. At this time, the drains 70D and sources 70S of the first-stage switching element 922a, the second-stage switching element 922b, the fifth-stage switching element 922e, and the sixth-stage switching element 922f of the second selection group 922 of the selection circuit 92 are in a non-conductive state. In other words, the first-stage switching element 922a, the second-stage switching element 922b, the fifth-stage switching element 922e, and the sixth-stage switching element 922f are turned off. Furthermore, when the second-digit information Ax2 of the addressing signal Ax is "1," the third selection signal ST3 goes high. At this time, the drains 70D and sources 70S of the third-stage switching element 922c, the fourth-stage switching element 922d, the seventh-stage switching element 922g, and the eighth-stage switching element 922h of the second selection group 922 of the selection circuit 92 are brought into a conductive state. That is, the third-stage switching element 922c, the fourth-stage switching element 922d, the seventh-stage switching element 922g, and the eighth-stage switching element 922h are turned on.

[0035] 2 and 4, the fifth selection signal ST5 and the sixth selection signal ST6 are input to the gates 70G of the switching elements 923a to 923h of each stage of the third selection group 923 of the selection circuit 92. More specifically, the sixth selection signal ST6 is input to the gates 70G of the first-stage switching element 923a, the third-stage switching element 923c, the fifth-stage switching element 923e, and the seventh-stage switching element 923g. The fifth selection signal ST5 is input to the gates 70G of the second-stage switching element 923b, the fourth-stage switching element 923d, the sixth-stage switching element 923f, and the eighth-stage switching element 923h.

[0036] When the third-digit information Ax3 of the addressing signal Ax is "0," the sixth selection signal ST6 goes high. At this time, the drains 70D and sources 70S of the first-stage switching element 923a, the third-stage switching element 923c, the fifth-stage switching element 923e, and the seventh-stage switching element 923g of the third selection group 923 of the selection circuit 92 are conductive. That is, the first-stage switching element 923a, the third-stage switching element 923c, the fifth-stage switching element 922e, and the seventh-stage switching element 923g are turned on. Furthermore, when the third-digit information Ax3 of the addressing signal Ax is "0," the fifth selection signal ST5 goes low. At this time, the drains 70D and sources 70S of the second-stage switching element 923b, the fourth-stage switching element 922d, the sixth-stage switching element 923f, and the eighth-stage switching element 922h of the third selection group 923 of the selection circuit 92 are in a non-conductive state. In other words, the second-stage switching element 923b, the fourth-stage switching element 923d, the sixth-stage switching element 923f, and the eighth-stage switching element 923h are turned off.

[0037] Conversely, when the third-digit information Ax3 of the addressing signal Ax is "1," the sixth selection signal ST6 goes low. At this time, the drains 70D and sources 70S of the first-stage switching element 923a, the third-stage switching element 923c, the fifth-stage switching element 923e, and the seventh-stage switching element 923g of the third selection group 923 of the selection circuit 92 are in a non-conductive state. In other words, the first-stage switching element 923a, the third-stage switching element 923c, the fifth-stage switching element 923e, and the seventh-stage switching element 923g are turned off. Furthermore, when the third-digit information Ax3 of the addressing signal Ax is "1," the fifth selection signal ST5 goes high. At this time, the drains 70D and sources 70S of the second-stage switching element 923b, the fourth-stage switching element 923d, the sixth-stage switching element 923f, and the eighth-stage switching element 923h of the third selection group 923 of the selection circuit 92 are brought into a conductive state. That is, the second-stage switching element 923b, the fourth-stage switching element 923d, the sixth-stage switching element 923f, and the eighth-stage switching element 923h are turned on.

[0038] In the selection circuit 92, a word line is selected by a combination of on-states of the switching elements in the first selection group 921, the second selection group 922, and the third selection group 923. That is, in the X decoder 9, the word line to be selected from the eight word lines is determined by the 3-bit addressing signal Ax. FIG. 5 is a diagram showing the relationship between the addressing signal Ax and the selected word line. FIG. 5 is a table that associates the information of each digit of the addressing signal Ax with the word line that is selected when the addressing signal Ax is input.

[0039] For example, as shown in Figure 5, the case where the addressing signal Ax is (110) will be described. In this case, the first digit information Ax1 is "1", the second digit information Ax2 is "1", and the third digit information Ax3 is "0". Therefore, the first selection signal ST1, the third selection signal ST3, and the sixth selection signal ST6 are at high levels, and the second selection signal ST2, the fourth selection signal ST4, and the fifth selection signal ST5 are at low levels.

[0040] Therefore, in the first selection group 921 of the selection circuit 92, the fifth-stage switching element 921e to the eighth-stage switching element 921h are turned on. Also, in the second selection group 922, the third-stage switching element 922c, the fourth-stage switching element 922d, the seventh-stage switching element 922g, and the eighth-stage switching element 922h are turned on. Furthermore, in the third selection group 923, the first-stage switching element 923a, the third-stage switching element 923c, the fifth-stage switching element 923e, and the seventh-stage switching element 923g are turned on.

[0041] That is, the seventh-stage switching element 921g of the first selection group 921, the seventh-stage switching element 922g of the second selection group 922, and the seventh-stage switching element 923g of the third selection group 923 are turned on. As a result, the Hi-Z decision signal DECOUT7 output from the seventh-stage switching element 923g of the third selection group 923 is switched to low level. As a result, the output of the seventh-stage inverter element 93g is switched to high level, that is, the word line WL7 is selected.

[0042] In this way, the X decoder 9 determines which of the eight word lines to select by the 3-bit address specification signal Ax. The Y decoder also has a similar configuration.

[0043] The X decoder 9 configured as shown in FIGS. 2 and 4 requires 24 switching elements to control eight word lines. In addition, in an actual nonvolatile memory device, the number of word lines and bit lines is far greater than eight. Therefore, when the selection circuit 92 is configured as shown in FIGS. 2 and 4, the number of switching elements in the nonvolatile memory device increases, making it difficult to reduce the area of ​​the selection circuit 92, that is, to reduce the size of the nonvolatile memory device. Furthermore, the increased number of switching elements increases power consumption.

[0044] Therefore, in the nonvolatile memory device 1 according to this embodiment, a device is implemented to reduce the number of switching elements in the X-decoder 20 and the Y-decoder 30. The configurations of the X-decoder 20 and the Y-decoder 30 of the nonvolatile memory device 1 according to this embodiment will be described below with reference to the drawings. FIG. 6 is a circuit diagram of the X-decoder 20 used in the nonvolatile memory device 1 according to this embodiment. FIG. 7 is a layout diagram of the X-decoder 20. The X-decoder 20 and the Y-decoder 30 have the same configuration. The X-decoder 20 will be described as a representative of the X-decoder 20 and the Y-decoder 30. The pre-decoder 21 is not shown in FIG. 7.

[0045] As shown in Figures 6 and 7, the X decoder 20 has a predecoder 21, a selection circuit 22, and a driver circuit 23. As shown in Figure 6, the X decoder 20 has three predecode circuits 211, 212, and 213. The predecoder 21 outputs selection signals ST1, ST2, ST3, ST4, ST5, and ST6 based on an address specification signal Ax. The predecoder 21 has a configuration similar to that of the conventional predecoder 91. Therefore, detailed description of the predecoder 21 and the selection signals ST1, ST2, ST3, ST4, ST5, and ST6 will be omitted.

[0046] 6 and 7, the driver circuit 23 includes eight inverter elements, namely, a first-stage inverter element 23a to an eighth-stage inverter element 23h. The driver circuit 23 has the same configuration as the conventional driver circuit 93. That is, the first-stage inverter element 23a to the eighth-stage inverter element 23h have the same configuration as the first-stage inverter element 93a to the eighth-stage inverter element 93h used in the driver circuit 93.

[0047] As shown in FIGS. 7 and 8, the selection circuit 22 has a first selection group 221, a second selection group 222, and a third selection group 223. The selection circuit 22 is supplied with selection signals ST1, ST2, ST3, ST4, ST5, and ST6 output from the pre-decoder 21. The first selection group 221 has two switching elements 221a and 221b. The second selection group 222 has four switching elements 222a to 222d. Furthermore, the third selection group 223 has eight switching elements 223a to 223h. In the selection circuit 22, each switching element is an NMOS transistor.

[0048] The first selection group 221 has a first-stage switching element 221a and a second-stage switching element 221b. The first-stage switching element 221a and the second-stage switching element 221b are arranged in parallel. The sources of both switching elements 221a and 221b are connected to the VSS terminal. The drain of the first-stage switching element 221a in the first selection group 221 is connected to the sources of the first-stage switching element 222a and the second-stage switching element 222b in the second selection group 222. In addition, the drain of the second-stage switching element 221b in the first selection group 221 is connected to the sources of the third-stage switching element 222c and the fourth-stage switching element 222d in the second selection group 222.

[0049] A first selection signal ST1 and a second selection signal ST2 are input to the first selection group 221. The second selection signal ST2 is input to the gate of the first-stage switching element 221a. The first selection signal ST1 is input to the gate of the second-stage switching element 221b.

[0050] In the first selection group 221, the first-stage switching element 221a is conductive between its source and drain, i.e., is turned on, when the second selection signal ST2 is at a high level. Furthermore, the second-stage switching element 221b is conductive between its source and drain, i.e., is turned on, when the first selection signal ST1 is at a high level. As described above, when the addressing signal Ax is input, the pre-decoding circuit 211 of the pre-decoder 21 outputs one of the first selection signal ST1 and the second selection signal ST2 at a high level and the other at a low level. Therefore, in the first selection group 221, the first-stage switching element 221a and the second-stage switching element 221b are controlled so that one is turned on and the other is turned off.

[0051] The second selection group 222 has a first-stage switching element 222a, a second-stage switching element 222b, a third-stage switching element 222c, and a fourth-stage switching element 222d. The first-stage switching element 222a to the fourth-stage switching element 222d are arranged in parallel.

[0052] The sources of the first-stage switching element 222a and the second-stage switching element 222b in the second selection group 222 are connected to the drain of the first-stage switching element 221a in the first selection group 221. In addition, the drain of the first-stage switching element 222a is connected to the sources of the first-stage switching element 223a and the second-stage switching element 223b in the third selection group 223. In addition, the drain of the second-stage switching element 222b is connected to the sources of the third-stage switching element 223c and the fourth-stage switching element 223d in the third selection group 223.

[0053] The sources of the third-stage switching element 222c and the fourth-stage switching element 222d in the second selection group 222 are connected to the drain of the second-stage switching element 221b in the first selection group 221. The drain of the third-stage switching element 222c is connected to the sources of the fifth-stage switching element 223e and the sixth-stage switching element 223f in the third selection group 223. The drain of the fourth-stage switching element 222d is connected to the sources of the seventh-stage switching element 223g and the eighth-stage switching element 223h in the third selection group 223.

[0054] A third selection signal ST3 and a fourth selection signal ST4 are input to the second selection group 222. The fourth selection signal ST4 is input to the gates of the first-stage switching element 222a and the third-stage switching element 222c. The third selection signal ST3 is input to the gates of the second-stage switching element 222b and the fourth-stage switching element 222d.

[0055] In the second selection group 222, the first-stage switching element 222a and the third-stage switching element 222c are electrically connected between their source and drain, i.e., turned on, when the fourth selection signal ST4 is at a high level. Similarly, the second-stage switching element 222b and the fourth-stage switching element 222d are electrically connected between their source and drain, i.e., turned on, when the third selection signal ST3 is at a high level. As described above, when the address signal Ax is input to the pre-decode circuit 212 of the pre-decoder 21, one of the third selection signal ST3 and the fourth selection signal ST4 is at a high level and the other is at a low level. Therefore, in the second selection group 222, one of the first-stage switching element 222a and the third-stage switching element 222c and the second-stage switching element 222b and the fourth-stage switching element 222d is controlled to be on and the other is off.

[0056] The third selection group 223 has a first-stage switching element 223a, a second-stage switching element 223b, a third-stage switching element 223c, a fourth-stage switching element 223d, a fifth-stage switching element 223e, a sixth-stage switching element 223f, a seventh-stage switching element 223g, and an eighth-stage switching element 223h. The first-stage switching element 223a to the eighth-stage switching element 223d are arranged in parallel.

[0057] The sources of the first-stage switching element 223a to the eighth-stage switching element 223h of the third selection group 223 are connected to the first-stage inverter element 23a to the eighth-stage inverter element 23h of the driver circuit 23, respectively. Decision signals DECOUT1 to DECOUT8 output from the first-stage switching element 223a to the eighth-stage switching element 223h of the third selection group 223 are input to the first-stage inverter element 23a to the eighth-stage inverter element 23h, respectively.

[0058] A fifth selection signal ST5 and a sixth selection signal ST6 are input to the third selection group 223. The sixth selection signal ST6 is input to the gates of the first-stage switching element 223a, the third-stage switching element 223c, the fifth-stage switching element 223e, and the seventh-stage switching element 223g. The fifth selection signal ST5 is input to the gates of the second-stage switching element 223b, the fourth-stage switching element 223d, the sixth-stage switching element 223f, and the eighth-stage switching element 223h.

[0059] In the third selection group 223, the first-stage switching element 223a, the third-stage switching element 223c, the fifth-stage switching element 223e, and the seventh-stage switching element 223g are conductive between their source and drain, i.e., are turned on, when the sixth selection signal ST6 is at a high level. Also, the second-stage switching element 223b, the fourth-stage switching element 223d, the sixth-stage switching element 223f, and the eighth-stage switching element 223h are conductive between their source and drain, i.e., are turned on, when the fifth selection signal ST5 is at a high level. As described above, when the address specification signal Ax is input to the pre-decode circuit 213 of the pre-decoder 21, one of the fifth selection signal ST5 and the sixth selection signal ST6 is at a high level and the other is at a low level. Therefore, in the third selection group 223, the first stage switching element 223a, the third stage switching element 223c, the fifth stage switching element 223e, and the seventh stage switching element 223g, and the second stage switching element 223b, the fourth stage switching element 223d, the sixth stage switching element 223f, and the eighth stage switching element 223h are controlled so that one is on and the other is off.

[0060] 6 and 7, in the selection circuit 22, the number of switching elements in the second selection group 222 is greater than the number of first switching elements, and the number of switching elements in the third selection group 223 is greater than the number of second switching elements. Two switching elements in the second selection group 222 are connected to each of the switching elements in the first selection group 221. Two switching elements in the third selection group 223 are connected to each of the switching elements in the second selection group 222. That is, in the selection circuit 22, multiple switching elements are connected in a so-called tournament configuration.

[0061] Even when using a selection circuit 22 configured in this manner, it is possible to select one of eight word lines with a 3-bit address signal Ax by switching on or off the switching elements 221a, 221b of the first selection group 221, the switching elements 222a to 222d of the second selection group 222, and the switching elements 223a to 223h of the third selection group 223.

[0062] For example, a case will be described in which (110) is input as the addressing signal Ax, as in the conventional case. The predecoder 21 has the same configuration as the conventional predecoder 91. Therefore, the selection signals output from the predecoder 21 are such that the first selection signal ST1, the third selection signal ST3, and the sixth selection signal ST6 are at high level, and the second selection signal ST2, the fourth selection signal ST4, and the fifth selection signal ST5 are at low level.

[0063] Therefore, in the first selection group 221 of the selection circuit 22, the second-stage switching element 221b is turned on. Also, in the second selection group 222, the third-stage switching element 222c and the fourth-stage switching element 222d are turned on. Furthermore, in the third selection group 223, the first-stage switching element 223a, the third-stage switching element 223c, the fifth-stage switching element 223e, and the seventh-stage switching element 223g are turned on.

[0064] The second-stage switching element 221b of the first selection group 221, the fourth-stage switching element 222d of the second selection group 222, and the seventh-stage switching element 223g of the third selection group 223 are turned on. As a result, the source of the seventh-stage switching element 223g of the third selection group 223 is electrically connected to the VSS line via the second-stage switching element 221b of the first selection group 221 and the fourth-stage switching element 222d of the second selection group 222. As a result, the Hi-Z decision signal DECOUT7 output from the seventh-stage switching element 223g of the third selection group 223 is switched to low level. As a result, the output of the seventh-stage inverter element 23g is switched to high level, that is, the word line WL7 is selected.

[0065] The Y decoder 30 can also select a bit line with a configuration similar to that of the X decoder 20 described above.

[0066] 7, by arranging the multiple switching elements of the selection circuit 22 in a tournament pattern, the number of switching elements can be reduced compared to a conventional selection circuit 92. This allows the area of ​​the selection circuit 22 to be smaller than that of the conventional selection circuit 92. Furthermore, in the area of ​​the selection circuit 22 where switching elements are no longer arranged compared to the conventional selection circuit 92, elements other than those constituting the selection circuit 22 of the nonvolatile memory device 1 can also be arranged. As a result, it is possible to reduce the size of the nonvolatile memory device 1.

[0067] Second Embodiment An X decoder 20A used in another example of the nonvolatile memory device 1 will be described with reference to the drawings. FIG. 8 is a circuit diagram of the X decoder 20A used in the nonvolatile memory device of the second embodiment. FIG. 9 is a timing chart showing the operation of the X decoder 20A. The X decoder 20A according to the second embodiment differs from the X decoder 20 in that it has a pre-decoder 21A. Other than this, the X decoder 20A has the same configuration as the X decoder 20, and parts of the X decoder 20A that are substantially the same as those of the X decoder 20 are assigned the same reference numerals and detailed description of the same parts will be omitted.

[0068] The nonvolatile memory device 1 is configured to send a high-level signal to a word line selected by the addressing signal Ax when an enable signal EN is received from the control circuit 40. As shown in Fig. 8, the enable signal EN is input to a predecoding circuit 211 that outputs a drive signal for driving a switching element connected to the VSS terminal of the selection circuit 22 of the predecoder 21A.

[0069] Here, the operation when the addressing signal Ax is (110) will be described. The control circuit 40 transmits the addressing signal Ax to the X-decoder 20A. At time T1, the pre-decoding circuits 211, 212, and 213 of the pre-decoder 21 acquire the first-digit information Ax1, the second-digit information Ax2, and the third-digit information Ax3 of the addressing signal Ax. Then, the pre-decoding circuits 212 and 213 switch the third selection signal ST3 and the sixth selection signal ST6 to high level based on the second-digit information Ax2 and the third-digit information Ax3 (see FIG. 9).

[0070] 9, at time T1, the fourth-stage switching element 222d of the second selection group 222 and the seventh-stage switching element 223g of the third selection group 223 of the selection circuit 22 are switched on. At time T1, the second-stage switching element 222b of the second selection group 222, the first-stage switching element 223a, the third-stage switching element 223c, and the fifth-stage switching element 223e of the third selection group 223 are also switched on.

[0071] 6, the wiring connecting the switching elements of the first selection group 221 and the switching elements of the second selection group 222 is longer than in the conventional configuration. The longer wiring causes parasitic capacitance to be formed between the wirings.

[0072] In the selection circuit 22 configured as above, at time T1, the second-stage switching element 222b of the second selection group 222 and the third-stage switching element 223c of the third selection group 223 are both on. As a result, electric charge is charged in the parasitic capacitance formed by the wiring connected to the drain of the first-stage switching element 221a of the first selection group 221.

[0073] Then, at time T2, the control circuit 40 outputs an enable signal EN. The enable signal EN is a signal synchronized with a read operation or a write operation of the nonvolatile memory device 1, and is output as a reference for starting each operation.

[0074] In the X-decoder 20A, the enable signal EN is input to the pre-decode circuit 211 of the pre-decoder 21A. At time T2, the pre-decode circuit 211 switches the first select signal ST1 to high level. This turns on the second-stage switching element 221b of the first select group 221. That is, the second-stage switching element 221b of the first select group 221, the fourth-stage switching element 222d of the second select group 222, and the seventh-stage switching element 223g of the third select group 223 are turned on, and the Hi-Z decision signal DECOUT7 output from the seventh-stage switching element 223g switches to low level. This switches the output of the seventh-stage inverter element 23g of the driver circuit 23 to high level, and the word line WL7 is selected.

[0075] As described above, in the X decoder 20A, before the enable signal EN is input to the pre-decoder 21, the switching elements of the selection groups other than the first selection group 221 connected to the reference voltage VSS are controlled first. With this configuration, electric charge is pre-charged to the parasitic capacitance formed by the wiring connecting the switching elements of the first selection group 221 and the switching elements of the second selection group. In this state, even if the enable signal EN is input at time T2 and the switching elements of the first selection group 221 are controlled, neither charging nor discharging occurs in the parasitic capacitance formed by the wiring connected to the drain of the first-stage switching element 221a in the first selection group 221 that is not switched on.

[0076] For example, suppose the same addressing signal Ax(110) as described above is input. In a configuration in which the select signal from the predecoding circuit 213 of the predecoder 21A is switched by the enable signal EN, the switching elements of the first selection group 221 and the second selection group 222 are both controlled at a stage before the predecoder 21A receives the enable signal EN. The first-stage switching element 221a of the first selection group 221 is off, and the second-stage switching element 222b of the second selection group 222 is on. In this state, no charge is stored in the parasitic capacitance of the wiring connected to the drain of the first-stage switching element 221a of the first selection group 221.

[0077] In this state, when the sixth select signal ST6 from the pre-decode circuit 213 switches to high level, each switching element in the third selection group is turned on. This causes parasitic capacitance due to the wiring connected to the drain of the first-stage switching element 221a to charge, lowering the drain voltage, which is the output of the third-stage switching element 223c. If the parasitic capacitance exceeds a certain level, the charging of the parasitic capacitance may cause the output signal DECOUT3 of the third-stage switching element 223c in the third selection group 223 to switch from Hi-Z to low level, potentially selecting a word line other than the one specified by the addressing signal Ax. The same applies when the enable signal EN controls the switching elements in the second selection group 222 to operate.

[0078] As described above, in the X decoder 20A, the enable signal EN controls the switching elements of the first selection group 221 connected to the reference voltage VSS, so no charge is generated in the regulating capacitance when the enable signal EN is received. Therefore, when the enable signal EN is received, it is possible to accurately select the word line specified by the addressing signal Ax.

[0079] <Third embodiment> An X-decoder 20B used in another example of the nonvolatile memory device 1 will be described with reference to the drawings. FIG. 10 is a layout diagram of the X-decoder 20B used in the nonvolatile memory device of the third embodiment. The X-decoder 20B according to the third embodiment differs from the selection circuit 22 of the X-decoder 20 in the positions of the switching elements that make up the first selection group 221 of the selection circuit 22B. Other than this, the X-decoder 20B has the same configuration as the X-decoder 20. Therefore, parts of the X-decoder 20B that are substantially the same as those of the X-decoder 20 are assigned the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0080] The circuit configuration of the X decoder 20B is the same as that of the X decoder 20. Therefore, detailed explanation of the circuit configuration and its operation will be omitted.

[0081] 7 and other figures, in a selection circuit 22 in which switching elements are arranged in a tournament pattern, gaps where no elements are arranged are formed between adjacent switching elements in the first selection group 221 and between adjacent switching elements in the second selection group 222. As shown in FIG. 10, in the selection circuit 22 of the X decoder 20B, the transistor cell 70 of the first-stage switching element 221a in the first selection group 221 is arranged between the transistor cell 70 of the first-stage switching element 222a in the second selection group 222 and the transistor cell 70 of the second-stage switching element 222b. In addition, the transistor cell 70 of the second-stage switching element 221b in the first selection group 221 is arranged between the transistor cell 70 of the second-stage switching element 222c in the second selection group 222 and the transistor cell 70 of the fourth-stage switching element 222d.

[0082] With this configuration, the selection circuit 22 is configured with the horizontal width of the second selection group 222 and the third selection group 223, which makes it possible to further reduce the area of ​​the selection circuit 22. In other words, it is possible to further miniaturize the nonvolatile memory device 1. Also, since the transistor cells 70 that make up the selection circuit 22 are configured to be arranged together, manufacturing and design are easier.

[0083] <Fourth embodiment> An X-decoder 20C used in yet another example of the nonvolatile memory device 1 will be described with reference to the drawings. FIG. 11 is a layout diagram of the X-decoder 20C used in the nonvolatile memory device of the fourth embodiment. The X-decoder 20C according to the fourth embodiment differs from the selection circuit 22 of the X-decoder 20 in that a selection circuit 22C uses a T-shaped composite transistor cell 81 and an I-shaped composite transistor cell 82. Other than this, the X-decoder 20C has the same configuration as the X-decoder 20. Therefore, parts of the X-decoder 20C that are substantially the same as those of the X-decoder 20 are assigned the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0084] The circuit configuration of the X decoder 20C is the same as that of the X decoder 20. As shown in Fig. 11, the X decoder 20C has two T-shaped composite transistor cells 81 and four I-shaped composite transistor cells 82.

[0085] As shown in FIG. 11, the T-shaped composite transistor cell 81 has a common active area 81M, first individual active areas 81S and 81T, and a second individual active area 81U.

[0086] 11, the first individual active areas 81S and 81T are arranged on opposite sides of the common active area 81M. A gate line 81G is arranged in the middle of the first individual active areas 81S and 81T. The second individual active area 81U is arranged to face a part of the common active area 81M that differs from the first individual active areas 81S and 81T. A gate line 81G is arranged in the middle of the second individual active area 81U and the common active area. As a result, the common active area 81M, the first individual active areas 81S and 81T, and the second individual active area 81U are arranged in a T-shape.

[0087] In the T-shaped composite transistor cell 81, the common active area 81M, the first individual active area 81S, and the gate line 81G, the common active area 81M, the first individual active area 81T, and the gate line 81G, and the common active area 81M, the second individual active area 81U, and the gate line 81G each constitute a different transistor cell.

[0088] 11, two T-shaped composite transistor cells 81 are designated as a first T-shaped composite transistor cell 81A and a second T-shaped composite transistor cell 81B. The second individual active area 81U and the common active area 81M of the first T-shaped composite transistor cell 81A form a first stage switching element 221a of the first selection group 221. The first individual active area 81S and the common active area 81M of the first T-shaped composite transistor cell 81A form a first stage switching element 222a of the second selection group 222. The first individual active area 81T and the common active area 81M of the first T-shaped composite transistor cell 81A form a second stage switching element 221b of the second selection group 222.

[0089] Similarly, in the second T-shaped composite transistor cell 81B, the second stage switching element 221b of the first selection group 221, the third stage switching element 222c of the second selection group 222 and the fourth stage switching element 222d are configured.

[0090] In the selection circuit 22C shown in FIG. 11 , the vertical direction is defined as the first direction, and the horizontal direction is defined as the second direction. In each of the first T-shaped composite transistor cell 81A and the second T-shaped composite transistor cell 81B, two first individual active areas 81S and 81T are arranged side by side in the first direction. Furthermore, the second individual active areas 81U of the first T-shaped composite transistor cell 81A and the second T-shaped composite transistor cell 81B are arranged on different sides of the respective common active areas 81M in the second direction. As a result, at least a portion of the first T-shaped composite transistor cell 81A and the second T-shaped composite transistor cell 81B overlap in the first direction. This configuration allows the areas of the first selection group 221 and the second selection group 222 to be reduced.

[0091] The I-shaped composite transistor cell 82 will be described with reference to the drawings. As shown in Fig. 11, the I-shaped composite transistor cell 82 has a common active area 82M and individual active areas 82S and 82T. The individual active areas 82S and 82T are arranged on opposite sides of the common active area 81M. A gate line 82G is arranged in the middle of the individual active areas 82S and 82T.

[0092] In the layout shown in FIG. 11, the four I-shaped composite transistor cells 82 are a first I-shaped composite transistor cell 82A, a second I-shaped composite transistor cell 82B, a third I-shaped composite transistor cell 82C, and a fourth I-shaped composite transistor cell 82D.

[0093] The individual active area 82S and the common active area 82M of the first I-shaped composite transistor cell 82A form the first stage switching element 223a of the third select group 223. The individual active area 82T and the common active area 81M of the first I-shaped composite transistor cell 82A form the second stage switching element 223b of the third select group 223.

[0094] Similarly, the individual active area 82S and the common active area 82M of the second I-shaped composite transistor cell 82B form the third stage switching element 223c of the third select group 223. The individual active area 82T and the common active area 81M of the second I-shaped composite transistor cell 82B form the fourth stage switching element 223d of the third select group 223.

[0095] Additionally, the individual active area 82S and the common active area 82M of the third I-shaped composite transistor cell 82C form a fifth-stage switching element 223e of the third selection group 223. The individual active area 82T and the common active area 81M of the third I-shaped composite transistor cell 82C form a sixth-stage switching element 223f of the third selection group 223.

[0096] Furthermore, the individual active area 82S and the common active area 82M of the fourth I-shaped composite transistor cell 82D constitute a seventh-stage switching element 223g of the third selection group 223. The individual active area 82T and the common active area 81M of the fourth I-shaped composite transistor cell 82D constitute an eighth-stage switching element 223h of the third selection group 223.

[0097] By using a common active region 81M in the T-shaped composite transistor cells 81A and 81B, it is possible to omit wiring that connects switching elements of different selection groups. Also, by using a common active region 82M in the I-shaped composite transistor cells 82A, 82B, 82C, and 82D, terminals connected to the switching elements of the second selection group 222 are shared. This also makes it possible to omit wiring.

[0098] In this way, by using T-shaped composite transistor cells 81A, 81B and I-shaped composite transistor cells 82A, 82B, 82C, and 82D in the selection circuit 22C, wiring can be omitted and the area of ​​the selection circuit 22C can be reduced, making it possible to miniaturize the nonvolatile memory device 1.

[0099] In the above-described configuration, an arbitrary word line is selected from eight word lines, but this is not limited to this. An arbitrary word line may also be selected from a larger number of word lines. In this case, the number of bits of the addressing signal Ax increases, and the number of predecode circuits in the predecoder increases. This can be addressed by increasing the number of selection groups in the selection circuit. Furthermore, while two switching elements in a selection group arranged on the word line side are connected to switching elements in one selection group, this is not limited to this, and three or more switching elements may be connected. In this case, similar operation can be achieved by connecting the same number of control lines from the predecoder to each group as the number of switching elements connected to one switching element.

[0100] In the X decoder exemplified above, NMOS transistors are used as switching elements in the selection circuits 22 and 22C, but PMOS transistors may also be used.

[0101] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0102] <Additional Notes> The various embodiments described above will be generally described below.

[0103] The nonvolatile memory device (1) described above has a decoder (20, 30) configured to drive a plurality of wirings connected to a memory array (10), The decoder (20, 30) A pre-decoding circuit (21, 21A) configured to output a selection signal (ST1) in response to an address designation signal (Ax, Ay) for designating a wiring; a selection circuit (22, 22C) configured to be driven based on selection signals (ST1, ST2, ST3, ST4, ST5, ST6) supplied from the pre-decoding circuit (21, 21A) and select designated wirings (WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8); a driver circuit (23) connected to the selection circuit (22, 22C) and configured to drive selected wirings (WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8); The selection circuit (22, 22C) The switching element includes n selection groups (221, 222, 223) (n is an integer of 2 or more) each configured with a plurality of switching elements (221a to 221b, 222a to 222d, 223a to 223h) connected in parallel, Each of the switching elements (221a to 221b, 222a to 222d) of the k-th selection group (221, 222) (where k is an integer satisfying k < n) is configured to be connected to a plurality of different switching elements (222a to 222d, 223a to 223h) included in the (k + 1)-th selection group (222, 223). In a first configuration, each switching element (221a, 221b) of the first selection group (221) is connected to a voltage terminal (VSS) to which a predetermined voltage is applied, and each switching element (223a to 223h) of the n-th selection group (223) is connected to a driver circuit (23).

[0104] In the non-volatile memory device (1) having the first configuration, when the selection circuit (22) has three or more (n ≥ 3) selection groups (221, 222, 223), the switching elements (221a to 221b, 222a to 222d, 223a to 223h) of each selection group (221, 222, 223) are each constituted by a transistor cell (70) including an active region (70S, 70D). In a second configuration, the transistor cell (70) of the m-th selection group (221) is disposed between the transistor cells (70) of the r-th selection group (222) (where m and r are integers satisfying 1 ≤ m < r ≤ n).

[0105] In the non-volatile memory device (1) having the first configuration, the switching elements (221a to 221b, 222a to 222d, 223a to 223h) of each selection group (221, 222, 223) are each constituted by a transistor cell (81, 82) including an active region (81S, 81T, 81U, 81M, 82S, 82T, 82M). At least some of the plurality of transistor cells (81, 82) have composite transistor cells (81, 82) having a configuration having a common active area (81M, 82M) and a plurality of individual active areas (81S, 81T, 81U, 82S, 82T), and the composite transistor cells (81, 82) are configured to form a plurality of switching elements (third configuration).

[0106] In the nonvolatile memory device (1) of the third configuration, at least one of the plurality of composite transistor cells (81) Two first individual active areas (81S, 81T) configured to face each other on opposite sides of one common active area (81M), with the common active area (81M) interposed therebetween; a second individual active area (81U) disposed opposite to the two first individual active areas (81S, 81T) of the common active area (81M) at a different position to form a T-shape, The switching element formed by the first individual active area (81S, 81T) and the common active area (81M) of the T-shaped composite transistor cell (81) and the switching element formed by the second individual active area (81U) and the common active area (81M) are configured to be switching elements of different selection groups (221, 222) (fourth configuration).

[0107] In the nonvolatile memory device (1) of the fourth configuration, a plurality of T-shaped composite transistor cells (81A, 81B) are arranged side by side in a first direction, which is a direction in which two first individual active areas (81S, 81T) are arranged side by side, The second individual active areas (81U, 81U) of adjacent T-shaped composite transistor cells (81A, 81B) are connected to different sides of the respective common active areas (82M, 82M) in a second direction intersecting the first direction, and Adjacent T-shaped composite transistor cells (81A, 81B) are configured to at least partially overlap in the first direction (fifth configuration).

[0108] In the nonvolatile memory device (1) of any of the first to fifth configurations, the decoder circuit (22, 22C) is configured (sixth configuration) to drive the switching elements (221a, 221b) of the first selection group (221) using an enable signal (EN) that instructs the start of operation. [Explanation of symbols]

[0109] 1. Non-volatile memory device 10 Memory Array 20, 20A, 20B, 20C X decoder 21, 21A Predecoder 211, 212, 213 Pre-decoding circuit 22, 22C selection circuit 221 First Selection Group 221a, 221b: first stage switching element, second stage switching element 222 Second Selection Group 222a to 222d First stage switching element to fourth stage switching element 223 Third Selection Group 223a to 223h 1st stage switching element to 8th stage switching element 23 Driver circuit 23a to 23h 1st stage inverter element to 8th stage inverter element 30 Y decoder 40 Control circuit 70 transistor cells 70D drain region 70G gate electrode 70S Source Area 81 T-shaped composite transistor cell 81A, 81B T-shaped composite transistor cell 81G gate line 81M common active area 81S, 81T First individual active area 81U Second Individual Active Area 82 second transistor cell 82A, 82B, 82C, 82D I-shaped composite transistor cells 82G gate line 82M common active area 82S, 82T individual active areas 9X Decoder 91 Predecoder 911, 912, 913 Pre-decoding circuit 92 Selection circuit 921 First Selection Group 921a to 921h 1st stage switching element to 8th stage inverter element 922 Second Selection Group 922a to 922h 1st stage switching element to 8th stage inverter element 923 Third Selection Group 923a to 923h 1st stage switching element to 8th stage inverter element 93 Driver Circuit 93a to 93h 1st stage inverter element to 8th stage inverter element Ax Addressing Signal BL1~BL2n bit lines CELL memory cell DECOUT1~DECOUT8 decision signal EN Enable signal ST1 First selection signal ST2 Second selection signal ST3 Third selection signal ST4 4th selection signal ST5 5th selection signal ST6 6th selection signal VSS reference voltage WL1~WLm word lines

Claims

1. 1. A non-volatile memory device having a decoder configured to drive a plurality of interconnects connected to a memory array, comprising: The decoder a pre-decode circuit configured to output a selection signal in response to an address designation signal for designating the wiring; a selection circuit configured to be driven based on the selection signal supplied from the pre-decode circuit to select the designated wiring; a driver circuit connected to the selection circuit and configured to drive the selected wiring; The selection circuit n selection groups (n is an integer of 2 or more) each configured with a plurality of switching elements connected in parallel; each of the switching elements in the k-th selection group (k is an integer satisfying k<n) is configured to be connected to a plurality of different switching elements among the plurality of switching elements included in the k+1-th selection group; A nonvolatile memory device configured such that each switching element of the first selection group is connected to a voltage terminal to which a predetermined voltage is applied, and each switching element of the nth selection group is connected to the driver circuit.

2. When the selection circuit has three or more (n≧3) selection groups, each of the switching elements in each selection group is configured by a transistor cell including an active region, 2. The nonvolatile memory device of claim 1, wherein the transistor cells of the mth selection group are arranged between the transistor cells of the rth selection group (m and r are integers satisfying 1≦m<r≦n).

3. Each of the switching elements in each of the selection groups is composed of a transistor cell including an active region, 2. The nonvolatile memory device of claim 1, wherein at least some of the plurality of transistor cells are configured to have a composite transistor cell having a configuration having a common active area and a plurality of individual active areas, and the composite transistor cell is configured to form a plurality of switching elements.

4. At least one of the plurality of composite transistor cells two first individual active areas configured to face one of the common active areas at positions opposite to the common active area; a second individual active area disposed in a different position from the two first individual active areas of the common active area to face each other and form a T-shape; 4. The nonvolatile memory device of claim 3, wherein the switching element formed by the first individual active area and the common active area of ​​the T-shaped composite transistor cell and the switching element formed by the second individual active area and the common active area are configured to be switching elements of different selection groups.

5. a plurality of the T-shaped composite transistor cells are arranged side by side in a first direction in which two of the first individual active areas are arranged side by side; the second individual active areas of the adjacent T-shaped composite transistor cells are connected to different sides of the respective common active areas in a second direction intersecting the first direction; The nonvolatile memory device of claim 4 , wherein adjacent T-shaped composite transistor cells are configured to at least partially overlap in the first direction.

6. 6. The nonvolatile memory device according to claim 1, wherein the pre-decoding circuit is configured to drive the switching elements of the first selected group in response to an enable signal that instructs the start of operation.

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