Gate driver circuit, semiconductor device, and power source apparatus

Abstract

To further consider generation of a drive signal at a startup in a gate driver circuit.SOLUTION: A gate driver circuit 55 includes a power source control circuit 15. The power source control circuit 15 includes a first voltage generation circuit 1 that is configured to adjust an input voltage Vreg to a voltage value having a first accuracy with respect to a target voltage Vta during a first period, and a second voltage generation circuit 10 that is configured to adjust the input voltage Vreg to a voltage value having a second accuracy with respect to the target voltage Vta during a second period T2 which is shorter than the first period T1. The second voltage generation circuit 10 generates the input voltage Vreg from a first timing t11 to a second timing t13, and the first voltage generation circuit 1 generates the input voltage Vreg from the second timing t13. The first accuracy is higher than the second accuracy.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a gate driver circuit, a semiconductor device, and a power supply device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there are semiconductor devices that generate a switch voltage by a switching operation using a switch element, and such semiconductor devices include a gate driver circuit that generates a drive signal for driving the switch element.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-171290

[0005] [overview] The gate driver circuit disclosed in Patent Document 1 leaves room for further consideration regarding generation of drive signals at startup.

[0006] The gate driver circuit disclosed in this specification includes a drive control circuit and a power supply control circuit. The drive control circuit is configured to receive an input voltage and drive a switch element at a period based on a pulse signal. The power supply control circuit is configured to generate the input voltage. The power supply control circuit includes a first voltage generation circuit configured to adjust the input voltage to a voltage value with a first accuracy relative to a target voltage during a first period, and a second voltage generation circuit configured to adjust the input voltage to a voltage value with a second accuracy relative to the target voltage during a second period shorter than the first period. The second voltage generation circuit generates the input voltage from a predetermined first timing and generates the input voltage from the first timing until a second timing that is after a second period has elapsed but before the first period has elapsed. The first voltage generation circuit generates the input voltage from the second timing.

[0007] The semiconductor device disclosed in this specification includes the gate driver circuit configured as described above and a switch element.

[0008] The power supply device disclosed in this specification includes the semiconductor device having the above-described configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a power supply device 200Y. [Figure 2] FIG. 2 is a graph showing the drain-source current Ids and the drain-source voltage Vds of the switch element SW1. [Figure 3] FIG. 3 is a timing chart showing the voltage levels of the power supply device 200Y. [Figure 4] FIG. 4 is a diagram showing the power supply device 200X. [Figure 5] FIG. 5 is a timing chart showing the voltage levels of the power supply device 200X.

[0010] [Detailed explanation] <Regarding the power supply device 200Y of the comparative example> First, power supply device 200Y will be described as a comparative example of power supply device 200X of the present disclosure. Next, the problems with the comparative example will be described, followed by a description of power supply device 200X of the present disclosure.

[0011] The power supply device 200Y is a DC / DC converter that generates an output voltage Vout and supplies it to a load (not shown).

[0012] Fig. 1 is a diagram showing a power supply device 200Y. As shown in Fig. 1, the power supply device 200Y includes a semiconductor device 100 and various discrete components (for example, an inductor L1 and a capacitor Co).

[0013] The semiconductor device 100 is configured to receive a high-side power supply voltage HVcc and generate a switch voltage Vsw. The semiconductor device 100 changes the logic level of the switch voltage Vsw between a high level (based on the power supply voltage Vdd) and a low level (based on the ground voltage GND). The detailed configuration of the semiconductor device 100 will be described later.

[0014] The power supply device 200Y generates a DC output voltage Vout by smoothing the switch voltage Vsw using a capacitor C1 and an inductor L1.

[0015] <Regarding the semiconductor device 100> 1, the semiconductor device 100 includes a switch element SW1 and a gate driver circuit 50. The semiconductor device 100 also includes a plurality of external terminals (in this figure, a high-side power supply terminal HVcc, an input power supply terminal Vdd, a ground terminal GND, and a switch output terminal Vsw) as means for establishing electrical connection with the outside of the device.

[0016] In this description, the voltages generated at each terminal will be assigned the same reference numerals as those of the corresponding terminals. Specifically, the voltage generated at the high-side power supply terminal HVcc will be referred to as the high-side power supply voltage HVcc. ​​Similarly, the voltage generated at the input power supply terminal Vdd will be referred to as the power supply voltage Vdd, the voltage generated at the ground terminal GND will be referred to as the ground voltage GND, and the voltage generated at the switch output terminal Vsw will be referred to as the switch voltage Vsw.

[0017] The gate driver circuit 50 is configured to generate a drive signal G1. The gate driver circuit 50 includes a high-precision regulator 1, a pulse signal generation circuit 2, and a drive control circuit 3.

[0018] The high-precision regulator 1 receives the high-side power supply voltage HVcc as an input and generates the input voltage Vreg. The high-precision regulator 1 will be described in detail later.

[0019] The pulse signal generating circuit 2 generates a pulse signal PWM that drives the device with a predetermined frequency.

[0020] The high-side power supply terminal of the drive control circuit 3 is connected to the output terminal of the input voltage Vreg. The low-side power supply terminal of the drive control circuit 3 is connected to the ground terminal GND. The input terminal of the drive control circuit 3 is connected to the output terminal of the pulse signal PWM.

[0021] The drive control circuit 3 operates when the input voltage Vreg input to the high-side power supply terminal is equal to or greater than the operating voltage Vth. Specifically, at this time, the drive control circuit 3 generates a drive signal G1 in response to the pulse signal PWM. The drive signal G1 is a pulse-driven signal with the same pulse period as the pulse period of the pulse signal PWM. The voltage value of the high-level drive signal G1 is the input voltage Vreg. The voltage value of the low-level drive signal G1 is the ground voltage GND.

[0022] On the other hand, when the input voltage Vreg is lower than the operating voltage Vth, the drive control circuit 3 cannot operate, and the drive signal G1 is maintained at a low level.

[0023] The switching element SW1 is an enhancement-mode Gan-HEMT [High Electron Mobility Transistor]. The gate terminal of the switching element SW1 is connected to the output terminal of the drive control circuit 3. The drain terminal of the switching element SW1 is connected to the applied terminal of the input power supply terminal Vdd. The source terminal of the switching element SW1 is connected to the switch output terminal Vsw.

[0024] The switching element SW1 is controlled to be turned on / off by the drive signal G1. Specifically, when the drive signal G1 is at a high level, the switching element SW1 is turned on. Also, when the drive signal G1 is at a low level, the switching element SW1 is turned off.

[0025] When the switching element SW1 is on, the switch voltage Vsw becomes a high level (with reference to the power supply voltage Vdd). When the switching element SW1 is off, the switch voltage Vsw becomes a low level (with reference to the ground voltage GND).

[0026] The gate driver circuit 50 is configured to be able to operate the switching element SW1 in an intermittent operation (burst operation). Specifically, the on / off control of the switching element SW1 is performed such that a switching period in which the switching element SW1 performs a switching operation and a stop period in which the switching element SW1 maintains an off state are alternately repeated. The detailed configuration of the gate driver circuit 50 will be described later.

[0027] <Consideration on the gate voltage of Gan-HEMT> Here, as general characteristics of Gan-HEMT, there are the following. In order to suitably exhibit the current capacity of Gan-HEMT, the voltage value of the high-level drive voltage input to the gate of Gan-HEMT must be set within a predetermined voltage range (hereinafter, also referred to as the "high-efficiency range"). The current capacity means the magnitude of the drain-source current at a predetermined drain-source voltage. For example, when the current capacity is high, the magnitude of the drain-source current at a predetermined drain-source voltage becomes larger.

[0028] Let us explain this with a specific example. For example, suppose the high efficiency range of switch element SW1 is 5.5V or higher and less than 6.0V. The upper limit of the high efficiency range is the rated voltage (=gate breakdown voltage) of switch element SW1. In this case, if the voltage value of high-level drive signal G1 falls below 5.5V, the current capability of switch element SW1 will drop significantly. Furthermore, if drive signal G1 exceeds 6.0V, the rated voltage of switch element SW1 will be exceeded, and there is a risk that switch element SW1 will be destroyed. More details are as follows.

[0029] Figure 2 is a graph showing the drain-source current Ids and drain-source voltage Vds of the switch element SW1. In Figure 2, the dashed line indicates the state where the gate-source voltage Vgs of the switch element SW1 is 5.0V (= the state where the drive voltage G1 is outside the high-efficiency range). In Figure 2, the solid line indicates the state where the gate-source voltage Vgs of the switch element SW1 is 5.7V (= the state where the drive voltage G1 is within the high-efficiency range). Note that in this case, the on-threshold voltage of the switch element SW1 is less than 5.0V.

[0030] 2, for example, when the drain-source voltage Vds is a predetermined voltage Va, the drain-source current Ids is larger when the gate-source voltage Vgs is 5.7 V than when the gate-source voltage Vgs is 5.0 V. In this way, when the gate-source voltage Vgs of the switch element SW1 is set to a value within the high-efficiency range (in this example, 5.5 V or more and less than 6.0 V), the current capability of the switch element SW1 is optimally exhibited.

[0031] Therefore, the gate driver circuit 50 sets the voltage value of the high-level drive signal G1 to a value within the high-efficiency range. Here, the high-efficiency range is a relatively narrow range, as in the example above (5.5 V or more and less than 6.0 V). Therefore, the gate driver circuit 50 (more specifically, the drive control circuit 3) generates the drive signal G1 with relatively high accuracy.

[0032] Here, the voltage value of the high-level drive signal G1 is determined based on the voltage value of the input voltage Vreg input to the drive control circuit 3. Therefore, the high-precision regulator 1 generates the input voltage Vreg with high precision, targeting a target voltage Vta within a relatively narrow range. When the voltage value of the input voltage Vreg is within the target voltage Vta, the current capability of the switch element SW1 becomes high. The high-precision regulator 1, which has such high-precision voltage generation capability, will be described in detail below.

[0033] <About High-Precision Regulator 1> As shown in FIG. 1, the high-precision regulator 1 includes a reference voltage generating circuit 4, an operational amplifier OP1, transistors Q1 and Q2, variable resistors VR1 and VR2, a resistor R1, and capacitors C1 and C2.

[0034] The reference voltage generating circuit 4 is a bandgap power supply circuit configured to generate a reference voltage Vref. The reference voltage generating circuit 4 is connected to an output terminal of a high-side power supply voltage HVcc and a ground terminal GND. The output terminal of the reference voltage generating circuit 4, which generates the reference voltage Vref, is connected to the non-inverting input terminal (+) of an operational amplifier OP1.

[0035] The output terminal of the operational amplifier OP1 is fed back to the inverting input terminal (-) via a variable resistor VR1. Specifically, the output terminal of the operational amplifier OP1 is connected to a first terminal of the variable resistor VR1. The second terminal of the variable resistor VR1 is connected to a first terminal of the variable resistor VR2. The second terminal of the variable resistor VR2 is connected to the ground terminal GND.

[0036] The variable resistors VR1 and VR2 are connected in series to form a voltage divider circuit. A feedback voltage Vf corresponding to the voltage division ratio of the variable resistors VR1 and VR2 is generated at the connection node between the variable resistors VR1 and VR2.

[0037] The operational amplifier OP1 controls the output so that the reference voltage Vref and the feedback voltage Vf coincide (so that the non-inverting input terminal (+) and the inverting input terminal (-) are imaginarily shorted).

[0038] Transistors Q1 and Q2 are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate terminal of transistor Q1 is connected to the drain terminal, i.e., diode-connected. The drain terminal of transistor Q1 is connected to the gate terminal of transistor Q2 as well as to the first terminal of resistor R1. The source terminal of transistor Q1 is connected to the output terminal of operational amplifier OP1 as well as to the first terminal of capacitor C1.

[0039] The drain terminal of the transistor Q2 is connected to the output terminal of the high-side power supply voltage HVcc together with the first terminal of the resistor R1, and the source terminal of the transistor Q2 forms the output terminal of the input voltage Vreg and is connected to the high-side power supply terminal of the drive control circuit 3.

[0040] The second terminal of the capacitor C1 is connected to the ground terminal GND, the first terminal of the capacitor C2 is connected to the gate terminal of the transistor Q2, and the second terminal of the capacitor C2 is connected to the ground terminal GND.

[0041] Capacitor C2 is charged by the high-side power supply voltage HVcc. ​​A first charging voltage Vc1 corresponding to the charge amount (= charge amount) of capacitor C2 is generated at the connection node between the first end of capacitor C2 and the gate end of transistor Q2. When the first charging voltage Vc1 exceeds the on-threshold voltage of transistor Q2, transistor Q2 turns on.

[0042] The high-precision regulator 1 increases the input voltage Vreg to a first voltage V1 with a first accuracy during a first period T1 (details of which will be described later). The first accuracy is an accuracy with which the first voltage V1 becomes a voltage value within the range of the target voltage Vta.

[0043] Figure 3 is a timing chart showing the voltage levels of the power supply device 200Y. From top to bottom, Figure 3 shows the logic levels of the high-side power supply voltage HVcc, pulse signal PWM, drive signal G1, input voltage Vreg, and output voltage Vout. Figure 3 also shows the operation of switch element SW1 intermittently.

[0044] As shown in FIG. 3, at a predetermined time t1, the switching operation of the switch element SW1 stops. Specifically, the high-side power supply voltage HVcc falls to low level, and the pulse signal PWM stops pulse driving and remains at low level. The drive signal G1 is maintained at low level (based on the ground voltage GND) in response to the pulse signal PWM. The input voltage Vreg also begins to decrease. As the drive signal G1 remains at low level, the switch element SW1 remains off and stops switching operation. As a result, the switch voltage Vsw is maintained at low level (not shown), and the output voltage Vout gradually decreases.

[0045] After that, at time t2, the switching operation of the switch element SW1 is resumed. Specifically, the high-side power supply voltage HVcc rises to a high level again, and the pulse signal PWM resumes pulse driving.

[0046] At time t2, the input voltage Vreg is at a low level (based on the ground voltage GND). From this state, the capacitor C2 is charged, and the first charging voltage Vc1 gradually increases. As the first charging voltage Vc1 increases, the conductivity of the transistor Q2 increases, and the voltage at the source terminal of the transistor Q2 (= the input voltage Vreg) gradually increases.

[0047] At time t3, the input voltage Vreg exceeds the operating voltage Vth. In other words, from time t2 to time t3, the input voltage Vreg does not reach the operating voltage Vth. Therefore, from time t2 to time t3, the drive control circuit 3 cannot raise the drive signal G1 from low level to high level. In other words, from time t2 to time t3, the drive signal G1 is maintained at low level. Therefore, the switching operation of the switch element SW1 stops during this period. Then, the switch voltage Vsw continues to be maintained at low level (not shown), and the output voltage Vout continues to decrease.

[0048] At time t3, the input voltage Vreg exceeds the operating voltage Vth. This causes the drive control circuit 3 to resume operation, and after a predetermined time has elapsed from time t3, pulse driving of the drive signal G1 resumes. After time t3, when the drive signal G1 first rises to a high level (based on the input voltage Vreg), charging of the capacitor Co begins. This causes the output voltage Vout to start rising again.

[0049] When time t4 arrives after the first period T1 has elapsed since time t2, the input voltage Vreg reaches the first voltage V1.

[0050] <Considerations about input voltage Vreg> As described above, the high-precision regulator 1 has a high-precision voltage generation capability. Specifically, the high-precision regulator 1 increases the input voltage Vreg to the first voltage V1 with a relatively high first precision through operations such as generation of the reference voltage Vref by the bandgap reference voltage generation circuit 4, feedback control by the operational amplifier OP1, and generation of the gate voltage by charging and discharging the capacitors C1 and C2.

[0051] On the other hand, the period until the input voltage Vreg reaches the first voltage V1 from the ground voltage GND level, i.e., the first period T1, takes a relatively long time. Therefore, if the switch element SW1 is operated intermittently as shown in Figure 3, it takes a relatively long time until the switching operation resumes. If the switching stop period is long, the drop time of the output voltage Vout (the period from time t1 to time t4 in Figure 3) becomes long, and the output ripple Vrpy of the output voltage Vout becomes relatively large.

[0052] Furthermore, it takes time for the switch element SW1 to start switching operation not only during the intermittent operation of the switch element SW1 but also during normal startup of the semiconductor device 100. It takes a relatively long time from startup of the semiconductor device 100 until the output voltage Vout reaches the target voltage.

[0053] To address this problem, the semiconductor device 150 of the present disclosure is capable of suppressing the time until the start of the switching operation of the switch element SW1 from being prolonged. The semiconductor device 150 according to each embodiment of the present disclosure will be described in detail below. Note that the semiconductor device 150 according to each embodiment of the present disclosure includes components in common with the semiconductor device 100 described above. For this reason, the same reference numerals are used to designate the common components, and descriptions thereof will be omitted.

[0054] <Embodiment of power supply device 200X of the present disclosure> 4 is a diagram showing a power supply device 200X. The semiconductor device 150 of the present disclosure is mounted on the power supply device 200X. The power supply device 200X is a DC / DC converter that generates an output voltage Vout and supplies it to a load (not shown).

[0055] As shown in FIG. 4, the power supply device 200X includes a semiconductor device 150 and various discrete components (for example, an inductor L1 and a capacitor Co).

[0056] The semiconductor device 150 is configured to receive a high-side power supply voltage HVcc and generate a switch voltage Vsw. The semiconductor device 150 changes the logic level of the switch voltage Vsw between a high level (based on the power supply voltage Vdd) and a low level (based on the ground voltage GND). The detailed configuration of the semiconductor device 150 will be described later.

[0057] The power supply device 200X generates a DC output voltage Vout by smoothing the switch voltage Vsw using a capacitor C1 and an inductor L1.

[0058] <Regarding the semiconductor device 150> 4, the semiconductor device 150 includes a switch element SW1 similar to that described above. In addition, the semiconductor device 150 includes a gate driver circuit 55.

[0059] The semiconductor device 150 also has multiple external terminals (in this figure, a high-side power supply terminal HVcc, an input power supply terminal Vdd, a ground terminal GND, and a switch output terminal Vsw) as means for establishing electrical connection with the outside of the device.

[0060] The gate driver circuit 55 is configured to generate a drive signal G1. The gate driver circuit 55 includes a pulse signal generation circuit 2 and a drive control circuit 3 similar to those described above. In addition, the gate driver circuit 55 includes a power supply control circuit 15.

[0061] The power supply control circuit 15 is configured to receive the high-side power supply voltage HVcc as an input and generate the input voltage Vreg. Specifically, this is as follows.

[0062] The power supply control circuit 15 includes the high-precision regulator 1 similar to that described above. In addition, the power supply control circuit 15 includes a high-speed regulator 10.

[0063] The high-speed regulator 10 can increase the input voltage Vreg to a second voltage V2 with second accuracy during a second period T2. The second period T2 is shorter than the first period T1. The second accuracy is an accuracy such that the voltage value of the second voltage V2 is outside the range of the target voltage Vta (more specifically, a value below the lower limit of the target voltage Vta and higher than the operating voltage Vth).

[0064] The range from the lower limit to the upper limit of the target voltage Vta is smaller than the range from the operating voltage Vth to the lower limit of the target voltage Vta. For this reason, it can be said that the high-precision regulator 1 setting the input voltage Vreg to the first voltage V1 is more accurate than the high-speed regulator 10 setting the input voltage Vreg to the second voltage V2.

[0065] The high-speed regulator 10 generates the input voltage Vreg from a first timing, which is the start-up time of the semiconductor device 150, to a predetermined second timing. The second timing is when a third period T3 has elapsed since the first timing. The third period T3 is a period longer than the first period T1 and shorter than the second period T2. The change in the input voltage Vreg at each timing will be described in detail later.

[0066] <About the High-Speed ​​Regulator 10> The high-speed regulator 10 includes a resistor R2, transistors Q3 and Q4, a Zener diode D1, and a capacitor C3. The transistors Q3 and Q4 are N-channel MOSFETs. The transistor Q3 is diode-connected. The drain terminal of the transistor Q3 is connected to the gate terminal of the transistor Q4, as well as to the first terminal of the resistor R2 and the first terminal of the capacitor C3. The source terminal of the transistor Q3 is connected to the cathode of the Zener diode D1.

[0067] The drain terminal of transistor Q4, together with the second terminal of resistor R1, the second terminal of resistor R2, and the drain terminal of transistor Q2, is connected to the high-side power supply terminal HVcc. ​​The source terminal of transistor Q4, together with the source terminal of transistor Q2, is connected to the high-side power supply terminal of drive control circuit 3. That is, the source terminals of transistors Q2 and Q4 are electrically connected to each other and have the same potential.

[0068] The second end of the capacitor C3 is connected to the ground terminal GND together with the Zener diode D1.

[0069] The capacitance of capacitor C3 is smaller than that of capacitor C2. Specifically, the capacitance of capacitor C3 is 1 / 60 to 1 / 40 times the capacitance of capacitor C2. Therefore, the charging speed (= the rate at which the charge amount increases) of capacitor C3 is faster than that of capacitor C2.

[0070] Capacitor C3 is charged by the high-side power supply voltage HVcc. ​​A second charging voltage Vc2 corresponding to the charge amount of capacitor C3 is generated at the connection node between the first end of capacitor C3 and the gate end of transistor Q4. When the second charging voltage Vc2 exceeds the on-threshold voltage of transistor Q4, transistor Q4 turns on.

[0071] Figure 5 is a timing chart showing the voltage levels of the power supply device 200X. From top to bottom, Figure 5 shows the logic levels of the high-side power supply voltage HVcc, pulse signal PWM, drive signal G1, input voltage Vreg, and output voltage Vout. Figure 5 also shows the operation of switch element SW1 intermittently.

[0072] As shown in Figure 5, at a predetermined time t10, the switching operation of the switch element SW1 stops. Specifically, the high-side power supply voltage HVcc falls to low level, and the pulse signal PWM stops pulse driving and remains at low level. The drive signal G1 is also maintained at low level in response to the pulse signal PWM. The input voltage Vreg also begins to decrease. With the drive signal G1 maintained at low level, the switch element SW1 remains off and stops switching operation. As a result, the switch voltage Vsw is maintained at low level, and the output voltage Vout gradually decreases.

[0073] After that, at time t11 (the first timing described above), the switching operation of the switch element SW1 is resumed. Specifically, the high-side power supply voltage HVcc rises to a high level again, and the pulse signal PWM resumes pulse driving.

[0074] At time t11, the input voltage Vreg drops to low level (ground voltage GND). From this state, the high-side power supply voltage HVcc charges the capacitors C2 and C3. This gradually increases the gate voltages of the transistors Q2 and Q4.

[0075] As described above, capacitor C3 charges faster than capacitor C2. Furthermore, as described above, the high-precision regulator 1 generates the reference voltage Vref, performs feedback control using the operational amplifier OP1, and charges capacitor C1. Therefore, the second charging voltage Vc2 rises faster than the first charging voltage Vc1. That is, the second charging voltage Vc2 reaches the on-threshold voltage of transistor Q4 before the first charging voltage Vc1 reaches the on-threshold voltage of transistor Q2. In other words, after time 11, transistor Q4 turns on before transistor Q2.

[0076] Immediately after time t11, the second charging voltage Vc2 exceeds the on-threshold voltage of transistor Q4, turning transistor Q4 on. At this time, the first charging voltage Vc1 is below the on-threshold voltage of transistor Q2, so transistor Q2 is off. Then, as the second charging voltage Vc2 rises, the drain-source voltage of transistor Q4 (= input voltage Vreg) begins to rise.

[0077] When a predetermined time has elapsed from time t11 and the input voltage Vreg exceeds the operating voltage Vth, the drive control circuit 3 resumes operation, and the drive signal G1 resumes pulse driving. Then, when the drive signal G1 first rises to high level, the capacitor Co begins to charge, and the output voltage Vout begins to rise.

[0078] When the second period T2 elapses from time t11 and time t12 arrives, the input voltage Vreg reaches the second voltage V2. After time t12 (more specifically, between time t12 and time t13), the voltage value of the high-level drive signal G1 becomes the second voltage V2.

[0079] At time t13 (the second timing described above), a predetermined time (third period T3) has elapsed since time t12, the second charging voltage Vc2 exceeds the on-threshold voltage of transistor Q2. As a result, transistor Q2 turns on at time t13. After time t13, the second charging voltage Vc2 rises, causing the drain-source voltage of transistor Q2 (= input voltage Vreg) to rise. Furthermore, the rise in input voltage Vreg causes the gate-source voltage of transistor Q4 to fall below the on-threshold voltage of transistor Q4. When the gate-source voltage of transistor Q4 falls below the on-threshold voltage of transistor Q4, transistor Q4 turns off.

[0080] At time t14, which is the first period after time t11, the input voltage Vreg reaches the first voltage V1. After time t14, the voltage value of the high-level drive signal G1 becomes the first voltage V1.

[0081] As described above, the input voltage Vreg reaches the second voltage V2 after the second period T2 has elapsed since the switching operation of the switching element SW1 resumes (=time t11, first timing). More specifically, the input voltage Vreg exceeds the operating voltage Vth before the second period T2. Therefore, the period from the resumption of the switching operation of the switching element SW1 to the resumption of operation of the drive control circuit 3 is shorter than the first period T1. In other words, the fall time of the output voltage Vout of the power supply device 200X is shorter than the fall time of the output voltage Vout of the power supply device 200Y described above. Therefore, the output ripple Vrpx of the output voltage Vout of the power supply device 200X is smaller than the output ripple Vrpy of the power supply device 200Y described above.

[0082] Then, after the first period T1 has elapsed (=time t14), the input voltage Vreg becomes the first voltage V1. Then, the voltage value of the high-level drive signal G1 becomes the first voltage V1. As described above, the first voltage V1 is within the range of the high-efficiency region of the switch element SW1. Therefore, after the first period T1 has elapsed since the switching operation of the switch element SW1 resumed, the current capability of the switch element SW1 can be optimally exhibited.

[0083] Therefore, the configurations of the present disclosure can provide a gate driver circuit 50, a semiconductor device 150, and a power supply device 200X that can optimally utilize the current capability of the switch element SW1 while making the output ripple Vrpx of the output voltage Vout relatively small.

[0084] <Modification> The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure. For example, the power supply device 200X is a DC / DC converter, but it can be used in other applications such as a power terminalless driver.

[0085] <Additional Notes> The gate driver circuit (55) disclosed in the specification includes a drive control circuit (3) configured to receive an input of an input voltage (Vreg) and drive a switch element (SW1) at a period based on a pulse signal (PWM), and a power supply control circuit (15) configured to generate the input voltage (Vreg), and the power supply control circuit (15) includes a first voltage generation circuit (1) configured to set the input voltage (Vreg) to a voltage value with a first precision with respect to a target voltage (Vta) in a first period (T1), and a second voltage generation circuit (1) configured to set the input voltage (Vreg) to a voltage value with a first precision with respect to a target voltage (Vta) in a second period (T2) shorter than the first period (T1). and a second voltage generating circuit (10) configured to set a voltage value with a second accuracy relative to the reference voltage (Vta), wherein the second voltage generating circuit (10) generates an input voltage (Vreg) from a predetermined first timing (t11) and generates the input voltage (Vreg) from the first timing (t11) until a second timing (t13) that is after the second period (T2) has elapsed but before the first period (T1) has elapsed, and the first voltage generating circuit (1) generates the input voltage (Vreg) from the second timing (t13), and the first accuracy is preferably configured to be higher than the second accuracy (first configuration).

[0086] In the gate driver circuit (55) according to the first configuration, the switch element (SW1) may be a GaN-HEMT (second configuration).

[0087] In the gate driver circuit (55) according to the second configuration, the drive control circuit (3) generates a drive signal (G1) that pulses between high and low levels according to the voltage value of the input voltage (Vreg) and inputs the drive signal to the switch element (SW1), thereby driving the switch element (SW1), and the switch element (SW1) is preferably configured such that when the voltage value of the high-level drive signal (G1) is within a high efficiency range that is higher than its own on-threshold voltage and lower than its own gate withstand voltage, the switch element (SW1) has a higher current capability and a target voltage (Vta) that is within the high efficiency range, compared to when the voltage value of the high-level drive signal (G1) is lower than the lower limit of the high efficiency range and equal to or higher than the on-threshold voltage (third configuration).

[0088] The gate driver circuit (55) according to any one of the first to third configurations may be configured so that the first timing (t11) is the timing at which driving of the switch element (SW1) starts (fourth configuration).

[0089] In a gate driver circuit (55) according to any one of the first to fourth configurations, the first voltage generating circuit (1) includes a first charge / discharge circuit (C2) configured to receive an input of a power supply voltage (HVcc) and be charged to generate a first charging voltage (Vc1), and a first transistor (Q2) configured to be driven and controlled by receiving the first charging voltage (Vc1) at its gate; the second voltage generating circuit (10) includes a second charge / discharge circuit (C3) configured to receive an input of the power supply voltage (HVcc) and be charged to generate a second charging voltage (Vc2), and a first transistor (Q2) configured to receive the second charging voltage (Vc2) at its gate. and a second transistor (Q4) configured to be driven and controlled, wherein the rate of increase of the second charging voltage (Vc2) during charging is faster than the rate of increase of the first charging voltage (Vc1) during charging, and the output terminal of the input voltage (Vreg) is electrically connected so that the source of the first transistor (Q2) and the source of the second transistor (Q4) are at the same potential, and when the first transistor (Q2) is on, the gate-source voltage of the second transistor (Q4) falls below the on-threshold voltage of the second transistor (Q4), so that the second transistor (Q4) is turned off (fifth configuration).

[0090] A semiconductor device (150) disclosed in the specification includes a gate driver circuit (55) according to any one of the first to fifth configurations and a switch element (SW1) (sixth configuration).

[0091] The power supply device (200X) disclosed in the specification includes a semiconductor device (150) according to the sixth configuration (seventh configuration). [Explanation of symbols]

[0092] 1 High-precision regulator (first voltage generation circuit) 2 Pulse signal generation circuit 3. Drive control circuit 4. Reference voltage generation circuit 10 High-speed regulator (second voltage generation circuit) 15 Power supply control circuit 50 Gate driver circuit 55 Gate driver circuit 100 Semiconductor device 150 Semiconductor devices 200X power supply 200Y power supply C1 capacitor C2 Capacitor (1st charge / discharge circuit) C3 Capacitor (second charge / discharge circuit) D1 Zener diode G1 drive signal GND Ground voltage, ground terminal HVcc High side power supply terminal, high side power supply voltage Ids Drain-source current L1 inductor OP1 operational amplifier PWM pulse signal Q1 transistor Q2 transistor (first transistor) Q3 transistor Q4 transistor (second transistor) R1, R2 resistance SW1 Switch element T1 1st period T2 2nd period T3 Third Period V1 First voltage V2 Second voltage VR1, VR2 variable resistors Va voltage Vc1 First charging voltage Vc2 Second charging voltage Vdd Input power supply terminal, power supply voltage Vds Drain-source voltage Vf Feedback voltage Vgs Gate-source voltage Vout Output voltage Vref Reference voltage Vreg input voltage Vrpx output ripple Vrpy output ripple Vsw Switch output terminal, switch voltage Vta target voltage Vth operating voltage

Claims

1. a drive control circuit configured to receive an input voltage and drive a switch element at a period based on the pulse signal; a power supply control circuit configured to generate the input voltage; Equipped with The power supply control circuit a first voltage generating circuit configured to set the input voltage to a voltage value with a first accuracy relative to a target voltage during a first period; a second voltage generating circuit configured to set the input voltage to a voltage value with the second accuracy relative to the target voltage in a second period shorter than the first period; Including, the second voltage generating circuit generates the input voltage from a predetermined first timing, and generates the input voltage from the first timing until a second timing that is after the second period has elapsed but before the first period has elapsed; the first voltage generating circuit generates the input voltage from the second timing; The gate driver circuit, wherein the first precision is higher than the second precision.

2. 2. The gate driver circuit according to claim 1, wherein the switching element is a GaN-HEMT.

3. the drive control circuit generates a drive signal that pulses between high and low levels according to a voltage value of the input voltage, and inputs the drive signal to the switch element to drive the switch element; when the voltage value of the drive signal at a high level is within a high efficiency range that is higher than its own on threshold voltage and lower than its own gate withstand voltage, the switch element has a higher current capability than when the voltage value of the drive signal at a high level is lower than the lower limit value of the high efficiency range and equal to or higher than the on threshold voltage, The gate driver circuit according to claim 2 , wherein the target voltage is a voltage within the high efficiency range.

4. The gate driver circuit according to claim 1 , wherein the first timing is a timing at which the driving of the switch element starts.

5. The first voltage generating circuit a first charge / discharge circuit configured to receive an input of a power supply voltage, be charged, and generate a first charging voltage; a first transistor configured to be driven and controlled by inputting the first charging voltage to its gate; Including, The second voltage generating circuit a second charging / discharging circuit configured to receive the power supply voltage, be charged, and generate a second charging voltage; a second transistor configured to be driven and controlled by receiving the second charging voltage at its gate; Including, The rate of increase of the second charging voltage during charging is faster than the rate of increase of the first charging voltage during charging, an output terminal of the input voltage is configured such that a source of the first transistor and a source of the second transistor are electrically connected to each other so as to have the same potential; 2. The gate driver circuit according to claim 1, wherein when the first transistor is on, the gate-source voltage of the second transistor falls below an on-threshold voltage of the second transistor, and the second transistor is turned off.

6. a gate driver circuit according to claim 1; The switch element; A semiconductor device comprising:

7. A power supply device comprising the semiconductor device according to claim 6.

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