Image sensor and operating method thereof

Abstract

To provide an image sensor that can operate in either a global shutter (GS) method or a rolling shutter (RS) method.SOLUTION: An image sensor includes: a floating diffusion region FD which accumulates photo charges generated from a photodiode PD through a transfer transistor TX; a reset transistor RX; a source follower transistor SF which amplifies a voltage of the FD and outputs an amplified voltage to a first node N1; a selection transistor SX which connects the first node N1 and an output line CLi; a second node N2 which is connected to the reset transistor; and first and second capacitors CP1, CP2 disposed to a path connecting the first node and the second node. In a signal-dump operation of a GS mode, a pixel voltage is stored in the first capacitor through the first node and a reset voltage is stored in the second capacitor through the first node. In a RS mode, a charge overflowed from the PD is stored in one of the first capacitor and the second capacitor.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to a CMOS image sensor (Complementary Metal Oxide Semiconductor Image Sensor), and more particularly to an image sensor that can operate in a global shutter mode and a rolling shutter mode. [Background technology]

[0002] An image sensor is a device that converts optical signals into electrical signals. In a rolling shutter type image sensor, each row of a pixel array is exposed to different time intervals. In contrast, a global shutter type image sensor operates such that the exposure time interval for each row of a pixel array is the same.

[0003] As image sensors continue to improve day by day, there is always the challenge of improving their performance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 11,317,042 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor that can selectively operate in either a global shutter mode or a rolling shutter mode. [Means for solving the problem]

[0006] In order to achieve the above object, an image sensor according to the present invention includes a row driver, at least one photodiode, a floating diffusion region that accumulates photocharges generated in the at least one photodiode through a transfer transistor, a reset transistor that provides a voltage of a pixel power terminal to the floating diffusion region based on a reset control signal, a source follower transistor that amplifies the voltage of the floating diffusion region and outputs the amplified voltage to a first node, a selection transistor that connects the first node to an output line, a second node connected to the reset transistor, first and second capacitors that are disposed in a path connecting the first and second nodes, and a plurality of transistors that are disposed between the first and second nodes and connected to the first and second capacitors, respectively, and In a rolling shutter mode, the row driver controls the plurality of transistors to store a pixel voltage in the first capacitor through the first node and to store a reset voltage in the second capacitor through the first node, and in a rolling shutter mode, at least one of the first capacitor and the second capacitor is a lateral overflow integration capacitor (LOFIC) configured to store charge overflowed from the at least one photodiode.

[0007] and a plurality of capacitors connected to the first node through a plurality of transistors, wherein in a signal dump operation in a global shutter mode, the row driver controls at least some of the plurality of transistors to store a pixel voltage or a reset voltage from the floating diffusion region in the plurality of capacitors through the source follower transistor and the first node, and at least one of the plurality of capacitors is a lateral overflow integration capacitor (LOFIC) configured to store charge overflowing from the at least one photodiode in a rolling shutter mode.

[0008] In order to achieve the above object, a method for operating an image sensor according to the present invention includes an image sensor including a plurality of pixels, each including a photodiode and a plurality of transistors, a row driver that supplies a control signal to each of the plurality of pixels, a timing controller that controls driving of the row driver, and a readout circuit that outputs image signals of the plurality of pixels, the image sensor storing a first pixel voltage output by a source follower transistor in a first capacitor and a first reset voltage of a floating diffusion region output by the source follower transistor in a second capacitor in response to a photocharge generated in a photodiode included in each of the plurality of pixels exposed to light during the same time period in response to a global shutter mode control signal; the image sensor outputs, to a column line, outputs of the source follower transistors corresponding to the first pixel voltage stored in the first capacitor and the first reset voltage stored in the second capacitor as rolling readouts from the pixels in response to the global shutter mode control signal; and the image sensor outputs, to the column line, second pixel voltages output by the source follower transistors and second reset voltages of the floating diffusion regions output by the source follower transistors in response to photocharges generated in photodiodes included in each of the pixels exposed to light, at least some of which are different from each other in time intervals in response to the rolling shutter mode control signal; The image sensor selectively provides the capacitance of the first capacitor or the second capacitor, in which charge overflowing from the photodiode is stored, to the floating diffusion region by a lateral overflow integration method in response to the rolling shutter mode control signal. [Effects of the Invention]

[0009] The image sensor according to the present invention can selectively operate in either a global shutter mode or a rolling shutter mode. The image sensor of the present invention has a simple structure using a small number of transistors and can operate in either a global shutter method or a rolling shutter method, and can generate images with little degradation in both the global shutter method and the rolling shutter method. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention; [Figure 2A] FIG. 2 is a diagram for explaining the operation of the image sensor of FIG. 1 in a global shutter mode. [Figure 2B] 2 is a diagram for explaining the operation of the image sensor of FIG. 1 in a rolling shutter mode. [Figure 3A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 3B] FIG. 3B is a diagram conceptually illustrating a signal dump operation in global shutter mode of the pixel of FIG. 3A. [Figure 3C] FIG. 3B is a diagram for conceptually explaining a readout operation in the global shutter mode of the pixel of FIG. 3A. [Figure 3D] FIG. 3B is a timing diagram illustrating the operation of the pixel of FIG. 3A in global shutter mode. [Figure 3E] FIG. 3B is a diagram for conceptually explaining the operation of the pixel of FIG. 3A in rolling shutter mode. [Figure 3F] FIG. 3B is a timing diagram illustrating the operation of the pixel of FIG. 3A in rolling shutter mode. [Figure 4A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 4B]FIG. 4B is a timing diagram illustrating the operation of the pixel of FIG. 4A in global shutter mode. [Figure 4C] FIG. 4B is a timing diagram illustrating the operation of the pixel of FIG. 4A in rolling shutter mode. [Figure 4D] FIG. 4B is a timing diagram illustrating the operation of the pixel of FIG. 4A in rolling shutter mode. [Figure 5A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 5B] FIG. 5B is a timing diagram illustrating the operation of the pixel of FIG. 5A in a global shutter mode. [Figure 5C] FIG. 5B is a timing diagram illustrating the operation of the pixel of FIG. 5A in rolling shutter mode. [Figure 5D] FIG. 5B is a timing diagram illustrating operation in rolling shutter mode according to one embodiment of the pixel of FIG. 5A. [Figure 6A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 6B] FIG. 6B is a timing diagram illustrating the operation of the pixel of FIG. 6A in global shutter mode. [Figure 6C] FIG. 6B is a timing diagram illustrating the operation of the pixel of FIG. 6A in rolling shutter mode. [Figure 6D] 6B is a timing diagram illustrating operation in rolling shutter mode according to one embodiment of the pixel of FIG. 6A. [Figure 7A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 7B] FIG. 7B is a timing diagram illustrating the operation of the pixel of FIG. 7A in a global shutter mode. [Figure 7C] FIG. 7B is a timing diagram illustrating the operation of the pixel of FIG. 7A in rolling shutter mode. [Figure 8A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 8B] FIG. 8B is a timing diagram illustrating the operation of the pixel of FIG. 8A in global shutter mode. [Figure 8C] FIG. 8B is a timing diagram illustrating the operation of the pixel of FIG. 8A in rolling shutter mode. [Figure 9A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 9B] FIG. 9B is a timing diagram illustrating the operation of the pixel of FIG. 9A in global shutter mode. [Figure 9C] FIG. 9B is a timing diagram illustrating the operation of the pixel of FIG. 9A in rolling shutter mode. [Figure 10A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 10B] FIG. 10B is a timing diagram illustrating the operation of the pixel of FIG. 10A in a global shutter mode. [Figure 10C] FIG. 10B is a timing diagram illustrating the operation of the pixel of FIG. 10A in rolling shutter mode. [Figure 11A] 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention. [Figure 11B] FIG. 11B is a timing diagram illustrating the operation of the pixel of FIG. 11A in a global shutter mode. [Figure 11C] FIG. 11B is a timing diagram illustrating the operation of the pixel of FIG. 11A in rolling shutter mode. [Figure 11D] FIG. 11B is a timing diagram illustrating the operation of the pixel of FIG. 11A in rolling shutter mode. [Figure 12] 2 is a diagram illustrating a pixel group of a pixel array according to an embodiment of the present invention; [Figure 13] 1 is a perspective view showing a schematic configuration of an image sensor according to an embodiment of the present invention; [Figure 14] 1 is a perspective view showing a schematic configuration of an image sensor according to an embodiment of the present invention; [Figure 15] 1 is a perspective view showing a schematic configuration of an image sensor according to an embodiment of the present invention; [Figure 16A] 1 is a perspective view showing a schematic configuration of an image sensor according to an embodiment of the present invention; [Figure 16B] FIG. 16B is a cross-sectional view showing a schematic configuration of the image sensor of FIG. 16A according to one embodiment. [Figure 16C] FIG. 16B is a cross-sectional view showing a schematic configuration of the image sensor of FIG. 16A according to one embodiment. [Figure 17] 1 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention; [Figure 18] 1 is a block diagram showing a schematic configuration of an application processor according to an embodiment of the present invention; [Figure 19] 1 is a flowchart illustrating an operation method of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, specific examples of embodiments for carrying out an image sensor and an operating method thereof according to the present invention will be described with reference to the drawings.

[0012] FIG. 1 is a block diagram showing a schematic configuration of an image sensor 100 according to an embodiment of the present invention. The image sensor 100 according to the embodiment of the present invention operates in either a global shutter mode or a rolling shutter mode based on a mode control signal MC. The image sensor 100 performs both the signal dump operation and the rolling readout operation using one source follower transistor based on a feedback structure in a global shutter mode. In addition, the image sensor 100 uses a lateral overflow integration capacitor (LOFIC) as a capacitor for storing a pixel voltage or a reset voltage in the global shutter mode. In one embodiment, image sensor 100 selectively provides capacitance of a capacitor to a floating diffusion region during rolling shutter mode readout operation. In this specification, the pixel voltage refers to a voltage output to a column line in response to photocharges generated in a photodiode.

[0013] The image sensor 100 will now be described in detail with reference to FIG. FIG. 1 illustrates an image sensor 100 that outputs pixel signals PXS in parallel for each column line, but the present invention is not limited thereto and may be implemented as an image sensor that outputs pixel signals in parallel for each pixel. The image sensor 100 generates image data, which is visual information of an object captured through a lens, and an image signal processor (not shown) processes the image data generated by the image sensor 100 and outputs it to a display device or stores it in a storage device. The image sensor 100 includes a pixel array 110, a row driver 120, a timing controller 130, a ramp signal generator 140, an ADC (analog-to-digital converter) 150, and an output buffer 160.

[0014] The pixel array 110 includes a plurality of pixels PXs. The pixel array 110 receives a plurality of pixel driving signals CSn from the row driver 120, such as a select signal for controlling a select transistor, a reset signal for controlling a reset transistor, and a transfer transistor control signal for controlling a transfer transistor. Each of the plurality of pixels PXs of the pixel array 110 operates under the control of a received pixel drive signal CSn. The plurality of pixels PXs are arranged, for example, in the form of a matrix. Each pixel PX is electrically connected to one of a plurality of row lines and one of a plurality of column lines. In one embodiment, each pixel PX includes multiple transistors controlled by a row driver 120 . In one embodiment, two or more adjacent pixels PXs form a pixel group, and the two or more pixels PXs included in the pixel group share at least some of the transmission transistors, drive transistors, selection transistors, and reset transistors with each other.

[0015] Each of the plurality of pixels PXs includes a photoelectric conversion element that converts an incident optical signal into an electrical signal. Each pixel PX includes at least one photoelectric conversion element. The photoelectric conversion element may be a photodiode (PD). The photoelectric conversion element may be any one of a photodiode (PD), a photocapacitor, a photogate, a pinned photodiode (PPD), a partially pinned photodiode, an organic photodiode (OPD), and a quantum dot (QD), or a combination thereof. The embodiments of this specification will be described on the assumption that the photoelectric conversion element is a photodiode PD, but other photoelectric conversion elements as described above can also be used, and the photoelectric conversion element is not limited to a photodiode PD.

[0016] The row driver 120 drives one or more rows of the pixel array 110 under the control of the timing controller 130 . That is, the row driver 120 drives at least one of the rows. The row driver 120 generates a selection signal for driving at least one of the rows. The row driver 120 activates the pixels corresponding to the selected row. The pixel signals PXS of the pixels in the selected row are transmitted to the ADC 150 via a plurality of column lines CLm.

[0017] The pixel signal PXS includes a reset voltage signal and a pixel voltage signal. The pixel voltage signal is a voltage of a floating diffusion region that reflects the charge generated in the photodiode PD included in each of the plurality of pixels. The reset voltage signal is the voltage of the floating diffusion region that is used as a reference voltage for performing correlated double sampling (CDS) with the pixel voltage signal. The timing controller 130 controls the pixel array 110 , the row driver 120 , the ramp signal generator 140 , and the ADC 150 . The timing controller 130 provides a timing control signal (TC) to the row driver 120 .

[0018] The timing control signal TC according to the embodiment of the present invention is set differently based on the mode control signal MC. For example, the mode control signal MC is a signal based on a shooting mode selected by a user, and the shooting mode includes a still image mode, a video mode, and the like. The mode control signal MC is a signal that controls the image sensor 100 to operate in the global shutter mode or the rolling shutter mode. In one embodiment, the mode control signal MC is provided from an image signal processor. The row driver 120 drives each of the plurality of pixels PXs in a global shutter mode or a rolling shutter mode based on the timing control signal TC. The row driver 120 uses a signal that controls a source follower transistor to output a pixel signal PXS for each of the plurality of pixels PXs in either a global shutter mode or a rolling shutter mode. Each of the plurality of pixels PXs includes one source follower transistor. That is, one and the same source follower transistor is used as the output of the pixel signal PXS in both the global shutter method and the rolling shutter method.

[0019] In one embodiment, the row driver 120 operates the pixels PX to provide multiple conversion gain modes when driving each of the pixels PXs in a rolling shutter manner. In this case, the row driver 120 selectively electrically connects the lateral overflow storage capacitor LOFIC to the floating diffusion region so that the pixel PX applies a high conversion gain (HCG) to the pixel voltage to generate a pixel voltage signal, or applies a low conversion gain (LCG) to the pixel voltage to generate a pixel voltage signal. In the rolling shutter mode, the lateral overflow storage capacitor LOFIC used in the multiple conversion gain modes is a capacitor that stores a pixel voltage in the signal dump operation in the global shutter mode or a capacitor that stores a reset voltage. The timing controller 130 controls the ramp signal generator 140 through a ramp control signal (CS_RP) and controls the ADC 150 through an ADC control signal (CS_ADC). The lamp control signal (CS_RP) includes a lamp enable signal, a mode signal, and the like.

[0020] The ramp signal generator 140 generates a ramp signal RAMP in response to the ramp control signal (CS_RP). The ramp signal generator 140 generates a ramp signal RAMP having a preset slope. The ramp signal generator 140 provides the generated ramp signal RAMP to the ADC 150 . The ADC 150 converts the reset voltage signal and pixel voltage signal of the pixel signal PXS into a digital signal, pixel data PXD, based on the ramp signal RAMP, and outputs the digital signal. For example, the ADC 150 converts the reset voltage signal and the pixel voltage signal into digital signals using a correlated double sampling method based on the ramp signal RAMP, and outputs the difference between the reset voltage signal and the pixel voltage signal as pixel data PXD, which is a digital signal. The ADC 150 includes a comparator 151 and a counter circuit 152 .

[0021] The pixel signal PXS and the ramp signal RAMP are provided to a comparator 151 . The counter circuit 152 counts the clock signal corresponding to the level of the reset voltage signal and the level of the pixel voltage signal. The counter circuit 152 generates the difference between the level of the reset voltage signal and the level of the pixel voltage signal as pixel data PXD, which is a digital signal. The output buffer 160 includes a plurality of column memory blocks 161 corresponding to each column for storing pixel signals PXD. The output buffer 160 includes a sense amplifier 162 for amplifying the pixel signal PXD stored in the column memory block 161 . The sense amplifier SA outputs the amplified pixel signal PXD to the image data IDT.

[0022] FIG. 2A is a diagram for explaining the operation of the image sensor 100 in FIG. 1 in the global shutter mode, and FIG. 2B is a diagram for explaining the operation of the image sensor 100 in FIG. 1 in the rolling shutter mode. 1 and 2A, when the image sensor 100 operates in a global shutter mode, it controls each pixel PX so that the photodiode photocharge integration time P1 for all pixels in the pixel array 110 is located in the same time interval. The integration time refers to the time it takes for the photodiode to substantially integrate photocharges. The image sensor 100 performs a signal dump operation during the photocharge accumulation time P1.

[0023] In the global shutter mode, the image sensor 100 performs a rolling readout operation. That is, the image sensor 100 controls each pixel PX so that the time period during which the readout is performed after the accumulation time differs for each row of the pixel array. Alternatively, the time period during which the lead-out is performed may be different for each row of a certain group. In this case, pixels in the same group are read out in the same time interval. The time required to read out all the pixels PXs of the pixel array 110 corresponding to any one frame of the image signal is a frame readout time P2.

[0024] 1 and 2B, when the image sensor 100 operates in a rolling shutter mode, it controls each pixel PX so that the time interval during which the photodiode photocharge accumulation time P3 occurs varies from row to row in the pixel array. Depending on the embodiment, the time interval over which accumulation is performed may be different for every row. Or, the time interval over which accumulation is performed may vary for each row in a given group. In this case, pixels in the same group undergo photocharge accumulation in the same time interval. In the rolling shutter mode, the image sensor 100 performs a rolling readout operation. That is, the image sensor 100 controls each pixel PX so that the time period P4 during which the readout is performed after the accumulation time differs for each row of the pixel array. Alternatively, the time period during which the lead-out is performed may be different for each row of a certain group. In this case, pixels in the same group are read out in the same time interval.

[0025] FIG. 3A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PX in FIG. 3A corresponds to pixel PX in image sensor 100 in FIG. Figure 3B is a diagram conceptually explaining the signal dump operation of pixel PX in global shutter mode of Figure 3A, Figure 3C is a diagram conceptually explaining the readout operation of pixel PX in global shutter mode of pixel PX in Figure 3A, Figure 3D is a timing diagram explaining the operation of pixel PX in global shutter mode of pixel PX in Figure 3A, Figure 3E is a diagram conceptually explaining the operation of pixel PX in rolling shutter mode of pixel PX in Figure 3A, and Figure 3F is a timing diagram explaining the operation of pixel PX in rolling shutter mode of pixel PX in Figure 3A.

[0026] Referring to FIG. 3A, a pixel PX according to an embodiment of the present invention includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a source follower transistor SF, a selection transistor SX, a precharge transistor PX, a precharge selection transistor PSX, a feedback transistor FBT, a first transistor T1, a second transistor T2, a first capacitor CP1, and a second capacitor CP2. The transfer transistor TX connects the photodiode PD and the floating diffusion region FD, and is controlled by a transfer control signal TG. The reset transistor RX connects the first pixel voltage power supply VDD1 and the floating diffusion region FD, and is controlled by a reset control signal RS. One terminal of the reset transistor RX is connected to the first pixel voltage power supply VDD1, and the other terminal is connected to the second node N2. The second node N2 is included in the floating diffusion region FD. Therefore, the potential of the second node N2 is the same as the potential of the floating diffusion region FD.

[0027] The pixel PX according to the embodiment of the present invention precharges the floating diffusion region FD using the reset transistor RX in a rolling readout operation in global shutter mode. That is, it is not necessary to include a separate transistor for precharging the floating diffusion region FD. The source follower transistor SF is called the drive transistor and is controlled by the voltage on the floating diffusion region FD. The source follower transistor SF connects the first node N1 to the second pixel voltage power supply VDD2. The second pixel voltage power supply VDD2 may provide the same voltage as or a different voltage from the first pixel voltage power supply VDD1.

[0028] A feedback transistor FBT, a first transistor T1, and a second transistor T2 are connected in series between a first node N1 and a second node N2. When the feedback transistor FBT, the first transistor T1, and the second transistor T2 are arranged in series with each other, one terminal of the feedback transistor FBT is connected to the first node N1, and the other terminal is connected to one terminal of the first transistor T1 and one terminal of the first capacitor CP1. One terminal of the first transistor T1 is connected to the other terminal of the feedback transistor FBT, and the other terminal of the first transistor T1 is connected to one terminal of the second transistor T2 and one terminal of the second capacitor CP2. One terminal of the second transistor T2 is connected to the other terminal of the first transistor T1, and the other terminal of the second transistor T2 is connected to a second node N2.

[0029] A precharge transistor PX and a precharge selection transistor PSX are connected in series between the first node N1 and the ground. The precharge transistor PX connects the first node N1 and the precharge selection transistor PSX, and is controlled by a precharge signal PC. The precharge selection transistor PSX connects the precharge transistor PX to the ground, and is controlled by a precharge selection signal PSEL. The selection transistor SX connects the first node N1 and the column line CLi and is controlled by a selection signal SEL.

[0030] The pixel PX according to the embodiment of the present invention performs the signal dump operation and the rolling readout operation in the global shutter mode using one source follower transistor SF. The second capacitor CP2 is also formed by a lateral overflow storage capacitor LOFIC. That is, when the image sensor 100 operates in the rolling shutter mode, the charge that overflows from the photodiode PD during the accumulation time is stored in the second capacitor CP2. When the image sensor 100 operates in a global shutter mode, the reset control signal RS has a high level during the accumulation time, and the charge overflowing in the photodiode PD may not be stored in the second capacitor CP2.

[0031] Referring to FIG. 3B, pixel PX performs a signal dump operation in global shutter mode. The pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and stored in the first capacitor CP1, and the reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and stored in the second capacitor CP2. Alternatively, the reset voltage is stored in the first capacitor CP1 and the pixel voltage is stored in the second capacitor CP2. At this time, the selection transistor SX is turned off.

[0032] In the global shutter mode, the precharge transistor PX is controlled by the precharge signal PS so that a constant, small current flows through it, and the precharge selection transistor PSX is turned on by the precharge selection signal PSEL at a high level. In this case, the precharge transistor PX operates in the saturation region, and the precharge selection transistor PSX operates in the linear region. When the pixel of other embodiments described below operates in global shutter mode, the precharge transistor PX and the precharge select transistor PSX operate in a similar manner.

[0033] Referring to FIG. 3C, the pixel PX performs a rolling readout operation in a global shutter mode. The charge corresponding to the pixel voltage stored in the first capacitor CP1 is transferred to the floating diffusion region FD. The pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX. The charge corresponding to the reset voltage stored in the second capacitor CP2 moves to the floating diffusion region FD. The reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0034] The source follower transistor SF that amplifies the pixel voltage and the reset voltage in the rolling readout operation is the same as the source follower transistor SF that amplifies the pixel voltage and the reset voltage in the signal dump operation. That is, the pixel voltage and reset voltage in the signal dump operation are fed back to the floating diffusion region FD in the rolling readout operation. Therefore, the pixel PX does not require a separate sample and hold circuit dedicated to the global shutter mode, and the pixel PX operates in the global shutter mode using a reduced number of transistors.

[0035] FIG. 3D is a timing diagram illustrating the operation of the pixel PX in the global shutter mode. For a signal dump operation, at time T1, the reset control signal RS transitions high and the floating diffusion region FD is reset. At time T2, the source follower transistor SF outputs a reset voltage to the first node N1 in response to the voltage of the floating diffusion region FD. At time T3, the feedback control signal FB transitions to a high level and remains at a high level while storing the pixel voltage and the reset voltage in the first capacitor CP1 and the second capacitor CP2, respectively.

[0036] At time T3, the first control signal LOF1 transitions to a high level to turn on the first transistor T1, and at time TA, the reset voltage is stored in the second capacitor CP2. At time T4, the first control signal LOF1 transitions to a low level, and the first transistor T1 is turned off. At time T5, the transmission control signal TG transitions to a high level, and the charge in the photodiode PD moves to the floating diffusion region FD. In response to the voltage of the floating diffusion region FD, the source follower transistor SF outputs a pixel voltage to the first node N1. At time TB, the pixel voltage at the first node N1 is stored in the first capacitor CP1. For the rolling readout operation, at time T8, the reset control signal RS transitions to a high level, and the floating diffusion region FD is reset (precharged). The select control signal SEL remains high during the rolling readout operation of the pixel voltage and the reset voltage, and the select transistor SX is turned on.

[0037] At time T10, the second control signal LOF2 transitions to a high level, turning on the second transistor T2, and the charge stored in the second capacitor CP2 is transferred to the floating diffusion region FD. At time TC, the reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX. At time T12, the reset control signal RS transitions to high level again, and the floating diffusion region FD is reset (precharged). At time T14, the first control signal LOF1 and the second control signal LOF2 transition to a high level, turning on the first transistor T1 and the second transistor T2, and the charge stored in the first capacitor CP1 moves to the floating diffusion region FD. At time TD, the pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0038] FIG. 3E is a diagram for conceptually explaining the operation of the pixel PX in the rolling shutter mode. In the rolling shutter mode, the precharge selection signal PSEL, the feedback control signal FB, and the first control signal LOF1 are maintained at a low level, and the precharge selection transistor PSX, the feedback transistor FBT, and the first transistor T1 are turned off. Photocharges are accumulated in the photodiode PD during the accumulation time. When the illumination is high, the photocharges overflowing from the photodiode PD are transferred to the second capacitor CP2, which is made up of a lateral overflow storage capacitor LOFIC. In one embodiment, a separate path for transferring overflowed photocharges between the second capacitor CP2 and the photodiode PD is formed, or the potential barrier of the second transistor T2 is adjusted so that the photocharges overflowed in the photodiode PD are transferred to the second capacitor CP2.

[0039] Depending on the embodiment, the first capacitor CP1 may also be configured as a lateral overflow storage capacitor LOFIC. In this case, the capacitance of the first capacitor CP1 and the capacitance of the second capacitor CP2 can be configured to be different. Therefore, the first capacitor CP1 and the second capacitor CP2 act as a two-stage lateral overflow storage capacitor LOFICs. That is, the photo-generated charges overflowing from the second capacitor CP2 are transferred back to the first capacitor CP1. The embodiments described with reference to Figures 3E and 3F are described assuming that the first transistor T1 is turned off and the second capacitor CP2 is only configured as a lateral overflow storage capacitor LOFIC, but the present invention is not limited thereto.

[0040] FIG. 3F is a timing diagram illustrating the operation of pixel PX in rolling shutter mode. Referring to FIG. 3F, a pixel PX according to an embodiment of the present invention provides a high conversion gain HCG mode and a low conversion gain LCG mode. At time T1, the reset control signal RS transitions to a high level, turning on the reset transistor RX and resetting the floating diffusion region FD. At this time, the second transistor T2 is turned off. At time T3, the selection transistor SX is turned on by the selection control signal SEL at a high level, and at time TA, the reset voltage of the HCG mode corresponding to the voltage of the floating diffusion region FD is sampled. At time T4, the transfer transistor TX is turned on by the high level transfer control signal TG, and the photocharges from the photodiode PD are transferred to the floating diffusion region FD.

[0041] At time TB, the pixel voltage of HCG mode corresponding to the voltage of the floating diffusion region FD is The pressure is sampled. At time T6, the second transistor T2, which connects the second node N2 and the second capacitor CP2 consisting of the lateral overflow storage capacitor LOFIC, is turned on by the high-level second control signal LOF2, and the second capacitor CP2 is electrically coupled to the floating diffusion region FD. At time TC, the pixel voltage in LCG mode is sampled at the floating diffusion region FD to which the second capacitor CP2 is electrically coupled. At time T7, the reset control signal RS is at a high level, turning on the reset transistor RX to reset the floating diffusion region FD electrically coupled to the second capacitor CP2. At time TD, the reset voltage of the LCG mode is sampled at the floating diffusion region FD to which the second capacitor CP2 is electrically coupled.

[0042] In the pixel PX according to the embodiment of the present invention, at least one capacitor (CP1, CP2) that stores the pixel voltage and / or the reset voltage in the global shutter mode is configured as a lateral overflow storage capacitor LOFIC, which stores the overflowed photocharge of the photodiode PD in the rolling shutter mode. Furthermore, in the rolling shutter mode, at least one capacitor (CP1, CP2) selectively provides capacitance to the floating diffusion region FD, thereby enabling the pixel PX to provide a plurality of conversion gain modes. Therefore, a high quality image can be produced.

[0043] FIG. 4A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXa in FIG. 4A corresponds to pixel PX in image sensor 100 in FIG. 3A to 3F, detailed descriptions of overlapping or similar parts will be omitted. Referring to FIG. 4A, the pixel PXa according to the embodiment of the present invention differs from the pixel PX described with reference to FIG. 3A in that it includes a conversion gain transistor CGT connecting the second node N2 and the floating diffusion region FD.

[0044] The second node N2 is selectively electrically coupled to the floating diffusion region FD by turning on or off the conversion gain transistor CGT. The second capacitor CP2 is electrically coupled to the floating diffusion region FD by turning on or off the second transistor T2 and the conversion gain transistor CGT. In one embodiment, the second capacitor CP2 comprises a lateral overflow storage capacitor LOFIC. Depending on the embodiment, the first capacitor CP1 may also be configured as a lateral overflow storage capacitor LOFIC. The pixel PXa precharges the floating diffusion region FD using the reset transistor RX and the conversion gain transistor CGT in a rolling readout operation in global shutter mode. That is, it is not necessary to include a separate transistor for precharging the floating diffusion region FD.

[0045] FIG. 4B is a timing diagram illustrating the operation of pixel PXa in the global shutter mode of the pixel of FIG. 4A. For a signal dump operation, at time T1, the reset control signal RS and the conversion gain control signal DCG transition to a high level, turning on the reset transistor RX and the conversion gain transistor CGT, and resetting the floating diffusion region FD. At time T2, the source follower transistor SF outputs a reset voltage to the first node N1 in response to the voltage of the floating diffusion region FD. At time T3, the feedback control signal FB transitions to a high level and remains at a high level while storing the pixel voltage and the reset voltage in the first capacitor CP1 and the second capacitor CP2, respectively.

[0046] At time T3, the first control signal LOF1 transitions to a high level, turning on the first transistor T1. At time TA, the reset voltage at the first node N1 is stored in the second capacitor CP2. At time T4, the first control signal LOF1 transitions to a low level, turning off the first transistor T1. At time T5, the transmission control signal TG transitions to a high level, and the charge in the photodiode PD moves to the floating diffusion region FD. The source follower transistor SF outputs a pixel voltage to the first node N1 in response to the voltage of the floating diffusion region FD. At time TB, the pixel voltage at the first node N1 is stored in the first capacitor CP1.

[0047] For the rolling readout operation, at time T8, the reset control signal RS and the conversion gain control signal DCG transition to a high level, the reset transistor RX and the conversion gain transistor CGT are turned on, and the floating diffusion region FD is precharged. The selection control signal SEL and the conversion gain control signal DCG remain at a high level during the rolling readout operation of the pixel voltage and the reset voltage, and the selection transistor SX and the conversion gain transistor CGT remain turned on. At time T10, the second control signal LOF2 transitions to a high level, turning on the second transistor T2, and the charge stored in the second capacitor CP2 is transferred to the floating diffusion region FD. At time TC, the reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0048] At time T12, the reset control signal RS transitions to high level again, and the floating diffusion region FD is precharged. At time T13, the reset transistor RX is turned off. At time T14, the first control signal LOF1 and the second control signal LOF2 transition to a high level, turning on the first transistor T1 and the second transistor T2, and the charge stored in the first capacitor CP1 moves to the floating diffusion region FD. At time TD, the pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0049] FIG. 4C is a timing diagram illustrating the operation of pixel PXa in the rolling shutter mode of the pixel of FIG. 4A. Referring to FIG. 4C, a pixel PXa according to an embodiment of the present invention provides a high conversion gain HCG mode and a low conversion gain LCG mode. The pixel PXa according to the embodiment of the present invention differs from the pixel PX described with reference to FIG. 3F in that the conversion gain transistor CGT remains turned off in the HCG mode and remains turned on in the LCG mode. Therefore, in the HCG mode, the second node N2 is isolated from the floating diffusion region FD, thereby improving the quality of the image generated by the image sensor 100.

[0050] At time T1, the reset control signal RS transitions to a high level, turning on the reset transistor RX and resetting the floating diffusion region FD. At this time, the second transistor T2 is turned off. At time T3, the selection transistor SX is turned on by the selection control signal SEL at a high level, and at time TA, the reset voltage of the HCG mode corresponding to the voltage of the floating diffusion region FD is sampled. At time T4, the transfer transistor TX is turned on by the high level transfer control signal TG, and the photocharges from the photodiode PD are transferred to the floating diffusion region FD. At time TB, the pixel voltage in HCG mode, which corresponds to the voltage of the floating diffusion region FD, is sampled. At time T6, the second transistor T2, which connects the second node N2 and the second capacitor CP2 formed of the lateral overflow storage capacitor LOFIC, is turned on by the second control signal LOF2 at a high level.

[0051] The conversion gain transistor CGT connecting the second node N2 and the floating diffusion region FD is turned on by the conversion gain control signal DCG at a high level. The second transistor T2 and the conversion gain transistor CGT remain turned on in the LCG mode. The second capacitor CP2 is electrically coupled to the floating diffusion region FD. At time TC, the pixel voltage in LCG mode is sampled at the floating diffusion region FD to which the second capacitor CP2 is electrically coupled. At time T7, the reset control signal RS is at a high level, turning on the reset transistor RX to reset the floating diffusion region FD electrically coupled to the second capacitor CP2. At time TD, the reset voltage of the LCG mode is sampled at the floating diffusion region FD to which the second capacitor CP2 is electrically coupled.

[0052] FIG. 4D is a timing diagram illustrating the operation of pixel PXa in the rolling shutter mode of the pixel of FIG. 4A. Referring to FIG. 4D, a pixel PXa according to an embodiment of the present invention provides a high conversion gain HCG mode, a middle conversion gain (MCG) mode, and a low conversion gain LCG mode. That is, the pixel PXa according to an embodiment of the present invention, unlike the operation of the pixel PXa described with reference to FIG. 4C, can reduce the large conversion gain drop when converting from HCG mode to LCG mode by providing a medium conversion gain mode. Furthermore, since the second node N2 is isolated from the floating diffusion region FD in the HCG mode, the quality of the image generated by the image sensor 100 can be improved.

[0053] The following mainly describes the differences from the operation of pixel PXa described with reference to FIG. 4C. Referring to FIG. 4D, pixel PXa performs a readout operation in the MCG / LCG mode in the rolling shutter mode. At time T6, the conversion gain transistor CGT connecting the second node N2 and the floating diffusion region FD is turned on by the conversion gain control signal DCG at a high level. The conversion gain transistor CGT remains turned on in MCG / LCG mode. The second node N2 is electrically coupled to the floating diffusion region FD. That is, a parasitic capacitance due to the junction of the second node N2 is provided to the floating diffusion region FD. At time TC, the pixel voltage in the MCG mode is sampled at the floating diffusion region FD to which the second node N2 is electrically coupled.

[0054] At time T7, the second transistor T2, which connects the second node N2 and the second capacitor CP2 formed of the lateral overflow storage capacitor LOFIC, is turned on by the second control signal LOF2 at a high level. The capacitance of a second capacitor CP2 is additionally provided across the floating diffusion region FD. At time TD, the pixel voltage in the LCG mode is sampled at the floating diffusion region FD to which the second node N2 and the second capacitor CP2 are electrically coupled. At time T8, the reset transistor RX is turned on by the reset control signal RS at a high level, resetting the floating diffusion region FD electrically coupled to the second capacitor CP2 and the second node N2. At time TE, the reset voltage of the LCG mode is sampled at the floating diffusion region FD to which the second capacitor CP2 and the second node N2 are electrically coupled. At time T10, the second transistor T2 is turned off by the second control signal LOF2 at a low level. At time TF, the reset voltage of the MCG mode is sampled at the floating diffusion region FD to which the second node N2 is electrically coupled.

[0055] At time T1, the reset control signal RS transitions to a high level, turning on the reset transistor RX and resetting the floating diffusion region FD. At this time, the second transistor T2 is turned off. At time T3, the selection control signal SEL is at a high level to turn on the selection transistor SX, and the reset voltage of the HCG mode corresponding to the voltage of the floating diffusion region FD is sampled at time TA. At time T4, the transfer transistor TX is turned on by the high level transfer control signal TG, and the photocharges in the photodiode PD are transferred to the floating diffusion region FD. At time TB, the pixel voltage in HCG mode, which corresponds to the voltage of the floating diffusion region FD, is sampled. At time T6, the second transistor T2, which connects the second node N2 and the second capacitor CP2 formed of the lateral overflow storage capacitor LOFIC, is turned on by the second control signal LOF2 at a high level.

[0056] The conversion gain transistor CGT connecting the second node N2 and the floating diffusion region FD is turned on by the conversion gain control signal DCG at a high level. The second transistor T2 and the conversion gain transistor CGT remain turned on in the LCG mode. The second capacitor CP2 is electrically coupled to the floating diffusion region FD. At time TC, the pixel voltage in LCG mode is sampled at the floating diffusion region FD to which the second capacitor CP2 is electrically coupled. At time T7, the reset transistor RX is turned on by the reset control signal RS at a high level, resetting the floating diffusion region FD electrically coupled to the second capacitor CP2. At time TD, the reset voltage of the LCG mode is sampled at the floating diffusion region FD to which the second capacitor CP2 is electrically coupled.

[0057] In the pixel PXa according to an embodiment of the present invention, at least one capacitor (CP1, CP2) that stores the pixel voltage and / or the reset voltage in the global shutter mode is configured as a lateral overflow storage capacitor LOFIC, which stores the overflowed photocharges of the photodiode PD in the rolling shutter mode. Also, in the rolling shutter mode, at least one capacitor (CP1, CP2) selectively provides capacitance to the floating diffusion region FD, thereby allowing the pixel PX to provide multiple conversion gain modes. Furthermore, the second node N2 and the floating diffusion region FD are separated by the conversion gain transistor CGT, so that a greater number of conversion gain modes can be provided. Therefore, a high quality image can be produced.

[0058] FIG. 5A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXb in FIG. 5A corresponds to pixel PX in image sensor 100 in FIG. Detailed description of overlapping or similar parts will be omitted with reference to FIGS. 3A to 4D. Referring to FIG. 5A, the pixel PXb according to the embodiment of the present invention differs from the pixel PXa described with reference to FIG. 4A in that it includes a read transistor RT connecting one terminal of the first capacitor CP1 to the floating diffusion region FD.

[0059] The read transistor RT is controlled by a read control signal RD. During readout operation in global shutter mode, pixel PXb can reduce degradation of image quality by transferring the charge corresponding to the pixel voltage stored in first capacitor CP1 to floating diffusion region FD through read transistor RT. That is, the charge corresponding to the pixel voltage is transferred to the floating diffusion region FD through a reduced number of transistors, thereby improving image quality. In addition, in the pixel PXb, the second node N2 is isolated from the floating diffusion region FD in the HCG mode of the rolling shutter mode, thereby improving the quality of the image generated by the image sensor 100. In one embodiment, the second capacitor CP2 comprises a lateral overflow storage capacitor LOFIC. Depending on the embodiment, the first capacitor CP1 may also be configured as a lateral overflow storage capacitor LOFIC.

[0060] FIG. 5B is a timing diagram illustrating the operation of pixel PXb in the global shutter mode of the pixel of FIG. 5A. The following mainly describes the differences from the operation of pixel PXa described with reference to FIG. 4B. In the signal dump operation, the read transistor RT remains turned off by the low level read control signal RD.

[0061] For the rolling readout operation, at time T8, the reset control signal RS and the conversion gain control signal DCG transition to a high level, the reset transistor RX and the conversion gain transistor CGT are turned on, and the floating diffusion region FD is precharged. The selection control signal SEL remains at a high level during the rolling readout operation of the pixel voltage and the reset voltage, and the selection transistor SX remains turned on. At time T10, the second control signal LOF2 transitions to a high level, turning on the second transistor T2. The conversion gain transistor CGT is turned on. The charge stored in the second capacitor CP2 is transferred to the floating diffusion region FD through the second transistor T2 and the conversion gain transistor CGT. At time TC, the reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0062] In another embodiment, the second transistor T2 and the conversion gain transistor CGT are turned off, the read transistor RT is turned on, and the charge stored in the second capacitor CP2 may be transferred to the floating diffusion region FD through the read transistor RT. At time T12, the reset control signal RS transitions to high level again, and the floating diffusion region FD is precharged. At time T13, the conversion gain control signal DCG transitions to a low level, and the conversion gain transistor CGT is turned off. Therefore, the second node N2 is electrically isolated by the floating diffusion region FD. At time T14, the read control signal RD transitions to a high level, turning on the read transistor RT. The first transistor T1 and the second transistor T2 are turned off. The charge stored in the first capacitor CP1 is transferred to the floating diffusion region FD through the read transistor RT. At time TD, the pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0063] FIG. 5C is a timing diagram illustrating the operation of pixel PXb in the rolling shutter mode of the pixel of FIG. 5A. The following mainly describes the differences from the operation of pixel PXa described with reference to FIG. 4C. In pixel PXb, the read control signal RD maintains a low level during all readout operations in the HCG mode and the LCG mode, and the read transistor RT maintains a turned-off state.

[0064] FIG. 5D is a timing diagram illustrating operation of pixel PXb in rolling shutter mode according to one embodiment of the pixel of FIG. 5A. The following mainly describes the differences from the operation of pixel PXa described with reference to FIG. 4D. In pixel PXb, the read control signal RD maintains a low level during all readout operations in the HCG mode, MCG mode, and LCG mode, and the read transistor RT maintains a turned-off state.

[0065] FIG. 6A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXc in FIG. 6A corresponds to pixel PX in image sensor 100 in FIG. Detailed description of overlapping or similar parts will be omitted with reference to FIGS. 3A to 5D. Referring to FIG. 6A, pixel PXc according to an embodiment of the present invention differs from pixel PXb described with reference to FIG. 5A in that it includes multiple photodiodes (PD1, PD2), multiple transfer transistors (TX1, TX2), a third capacitor CP3, a second transistor T2, and a second read transistor RT2. The first read transistor RT1 corresponds to the read transistor RT in FIG. 5A, and the third transistor T3 corresponds to the second transistor T2 in FIG. 5A.

[0066] Pixel PXc according to an embodiment of the present invention is a dual photodiode pixel. That is, one pixel PXc includes multiple photodiodes (PD1, PD2), and the multiple photodiodes (PD1, PD2) share the same microlens. The pixel PXc may correspond to some or all of the pixels PXs included in the pixel array 110 of the image sensor 100 in FIG.

[0067] The embodiments described with reference to Figures 6A to 6D are described assuming that pixel PXc is a dual-photodiode pixel, but apply equally to super-photodiode pixels in which multiple pixels each have a separate photodiode but share one and the same microlens. The pixel PXc according to the embodiment of the present invention stores voltages corresponding to photocharges generated in the multiple photodiodes PD1 and PD2 in different capacitors CP1 and CP2, respectively, during a signal dump operation in a global shutter mode. Alternatively, the second capacitor CP2 stores a voltage corresponding to the photocharges generated in the first photodiode PD1, and the first capacitor CP1 stores both voltages corresponding to the photocharges generated in the first photodiode PD1 and the second photodiode PD2.

[0068] The image sensor 100 performs autofocusing in global shutter mode using a pixel voltage corresponding to the photocharge generated in the first photodiode PD1 of the pixel PXc and a pixel voltage corresponding to the photocharge generated in the second photodiode PD2. In one embodiment, if the pixel PXc that generates the phase data used for autofocusing is configured as a superphotodiode pixel, in rolling shutter mode of the pixel PXc, the output is not used for image generation and a bad pixel correction process is performed.

[0069] In addition, during readout operation in global shutter mode, pixel PXc can reduce degradation of image quality by transferring charge corresponding to the pixel voltage stored in first capacitor CP1 and / or second capacitor CP2 to floating diffusion region FD through one of the read transistors (RT1, RT2). In addition, in the pixel PXc, the second node N2 is isolated from the floating diffusion region FD in the HCG mode of the rolling shutter mode, thereby improving the quality of the image generated by the image sensor 100. In one embodiment, the third capacitor CP3 comprises a lateral overflow storage capacitor LOFIC. Depending on the embodiment, the first capacitor CP1 and / or the second capacitor CP2 may also be configured as a lateral overflow storage capacitor LOFIC.

[0070] FIG. 6B is a timing diagram illustrating the operation of pixel PXc in the global shutter mode of the pixel of FIG. 6A. The operation of pixel PXc described with reference to FIG. 6B will be described assuming that the second capacitor CP2 stores a voltage corresponding to the photocharges generated in the first photodiode PD1, and the first capacitor CP1 stores both voltages corresponding to the photocharges generated in the first photodiode PD1 and the second photodiode PD2. The third capacitor CP3 stores a reset voltage. The following mainly describes the differences from the operation of pixel PXb described with reference to FIG. 5B.

[0071] In the signal dump operation, the read transistors RT1 and RT2 and the third transistor T3 are maintained in a turned-off state by the low level read control signals RD1 and RD2 and the third control signal LOF3. At time T1, the reset control signal RS and the conversion gain control signal DCG are at high levels, turning on the reset transistor RX and the conversion gain transistor CGT, and resetting the floating diffusion region FD. At time T2, the source follower transistor SF outputs a reset voltage to the first node N1 in response to the voltage of the floating diffusion region FD. The feedback transistor FBT, the first transistor T1, and the second transistor T2 are turned on by the feedback control signal FB, the first control signal LOF1, and the second control signal LOF2 at a high level. At time TA, the reset voltage of the first node N1 is stored in the third capacitor CP3.

[0072] At time T3, the second transistor T2 is turned off by the second control signal LOF2, and at time T4, the first transfer transistor TX1 is turned on, and a pixel voltage corresponding to the photocharges generated in the first photodiode PD1 is output to the first node N1. At time TB, the pixel voltage of the first node N1 corresponding to the photocharges generated in the first photodiode PD1 is stored in the second capacitor. At time T7, the first transfer transistor TX1 and the second transfer transistor TX2 are turned on, and a pixel voltage corresponding to the photocharges generated in both the first photodiode PD1 and the second photodiode PD2 is output to the first node N1. At time TC, a pixel voltage corresponding to the photocharges generated in the first photodiode PD1 and the second photodiode PD2 is stored in the first capacitor CP1. For the rolling readout operation, at time T8, the reset control signal RS and the conversion gain control signal DCG transition to a high level, the reset transistor RX and the conversion gain transistor CGT are turned on, and the floating diffusion region FD is precharged. The selection control signal SEL remains at a high level during the rolling-out operation of the pixel voltage and the reset voltage, and the selection transistor SX remains turned on.

[0073] At time T10, the third control signal LOF3 transitions to a high level, turning on the third transistor T3. The conversion gain transistor CGT is turned on. The charge stored in the third capacitor CP3 is transferred to the floating diffusion region FD through the third transistor T3 and the conversion gain transistor CGT. At time TD, the reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX. At time T12, the reset control signal RS transitions to high level again, and the floating diffusion region FD is precharged. At time T13, the conversion gain control signal DCG transitions to a low level, and the conversion gain transistor CGT is turned off. Therefore, the second node N2 is electrically isolated by the floating diffusion region FD.

[0074] At time T14, the second read control signal RD2 transitions to a high level, turning on the second read transistor RT2. The second transistor T2 and the third transistor T3 are turned off. The charge stored in the second capacitor CP2 is transferred to the floating diffusion region FD through the second read transistor RT2. At time TE, the pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX. At time T16, the floating diffusion region FD is precharged again, and at time T18, the first read transistor RT1 is turned on by the high-level first read control signal RD1, and the charge stored in the first capacitor CP1 is transferred to the floating diffusion region FD through the first read transistor RT1. At time TF, the pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0075] FIG. 6C is a timing diagram illustrating the operation of pixel PXc in the rolling shutter mode of the pixel of FIG. 6A. The operation of pixel PXc described with reference to FIG. 6C will be described assuming that pixel PXc is a dual photodiode pixel. The following mainly describes the differences from the operation of pixel PXa described with reference to FIG. 4C. The operation of pixel PXc, as described with reference to FIG. 6C, provides multiple conversion gain modes. In one embodiment, the plurality of conversion gain modes includes an HCG mode and an LCG mode.

[0076] In pixel PXc, the first and second read control signals (RD1, RD2) maintain a low level during all readout operations in the HCG mode and LCG mode, and the first and second read transistors (RT1, RT2) maintain a turned-off state. In the HCG mode, at time TA, after the reset voltage is sampled, the first and second transmission transistors (TX1, TX2) are simultaneously turned on by the first and second transmission control signals (TG1, TG2). Therefore, the photocharges generated by the first and second photodiodes (PD1, PD2) are simultaneously transferred to the floating diffusion region FD, and the pixel voltage is sampled at time TB. In the LCG mode, the conversion gain transistor CGT is turned on to electrically connect the third capacitor CP3 to the floating diffusion region FD. With the third capacitor CP3 electrically connected to the floating diffusion region FD, the pixel voltage in the LCG mode is sampled at time TC. At time T7, the reset transistor RX is turned on, and at time TD, the reset voltage of the LCG mode is sampled.

[0077] FIG. 6D is a timing diagram illustrating the operation of pixel PXc in the rolling shutter mode of the pixel of FIG. 6A. The operation of pixel PXc described with reference to FIG. 6D will be described assuming that pixel PXc is a dual photodiode pixel. The following mainly describes the differences from the operation of pixel PXa described with reference to FIG. 4D. The operation of pixel PXd, as described with reference to FIG. 6D, provides multiple conversion gain modes. In one embodiment, the multiple conversion gain modes include an HCG mode, an MCG mode, and an LCG mode.

[0078] In pixel PXc, the first and second read control signals (RD1, RD2) maintain a low level during all readout operations in the HCG mode and LCG mode, and the first and second read transistors (RT1, RT2) maintain a turned-off state. Also, in the HCG mode, after the reset voltage is sampled at time TA, the first and second transmission transistors TX1 and TX2 are simultaneously turned on by the first and second transmission control signals TG1 and TG2. Therefore, the photocharges generated by the first and second photodiodes (PD1, PD2) simultaneously move to the floating diffusion region FD and are sampled at time TB. In the MCG and LCG modes, the conversion gain transistor CGT remains turned on.

[0079] At time TC, the pixel voltage of the floating diffusion region FD in MCG mode is sampled with the third transistor T3 turned off. At time T7, the third transistor T3 is turned on, electrically connecting the third capacitor CP3 to the floating diffusion region FD. At time TD, the LCG mode pixel voltage of the floating diffusion region FD is sampled. At time T8, the floating diffusion region FD is reset, and at time TE, the reset voltage in the LCG mode is sampled with the third capacitor CP3 electrically connected to the floating diffusion region FD. At time T10, the third capacitor CP3 is electrically isolated from the floating diffusion region FD, and at time TF, the reset voltage of the MCG mode of the floating diffusion region FD is sampled.

[0080] FIG. 7A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXd in FIG. 7A corresponds to pixel PX of image sensor 100 in FIG. Detailed description of overlapping or similar parts will be omitted with reference to FIGS. 3A to 6B. Referring to FIG. 7A, pixel PXd according to an embodiment of the present invention differs from pixel PX described with reference to FIG. 3A in that a first feedback transistor FBT1 and a second feedback transistor FBT2 are connected in parallel between a first node N1 and a second node N2. The first transistor T1 and the second transistor T2 are connected in series with the first feedback transistor FBT1 and the second feedback transistor FBT2, respectively.

[0081] One terminal of the first capacitor CP1 is connected to one terminal of each of the first feedback transistor FBT1 and the first transistor T1, and one terminal of the second capacitor CP2 is connected to one terminal of each of the second feedback transistor FBT2 and the second transistor T2. Therefore, the first capacitor CP1 and the second capacitor CP2 are connected in parallel between the first node N1 and the second node N2. In one embodiment, the second capacitor CP2 comprises a lateral overflow storage capacitor LOFIC. Depending on the embodiment, the first capacitor CP1 may also be configured as a lateral overflow storage capacitor LOFIC. That is, at least one of the first capacitor CP1 and the second capacitor CP2 is configured as a lateral overflow storage capacitor LOFIC. Pixels PXd according to embodiments of the present invention can operate in a global shutter mode using a reduced number of transistors. In addition, the paths between the first capacitor CP1 and the floating diffusion region FD and the second capacitor CP2 are symmetrical to each other. Therefore, correlated double sampling (CDS) can be performed accurately even in global shutter mode.

[0082] FIG. 7B is a timing diagram illustrating the operation of pixel PXd in the global shutter mode of the pixel of FIG. 7A. The operation of pixel PXd, which will be described with reference to FIG. 7B, stores a reset voltage and a pixel voltage in the first capacitor CP1 and the second capacitor CP2, respectively. The following mainly describes the differences from the operation of the pixel PX described with reference to FIG. 3B.

[0083] In the signal dump operation, the first and second transistors T1 and T2 are maintained in a turned-off state by the first and second control signals LOF1 and LOF2 being at a low level. At time T1, the reset control signal RS transitions to a high level, and the floating diffusion region FD is reset. At time T2, the source follower transistor SF outputs a reset voltage to the first node N1 in response to the voltage of the floating diffusion region FD. At time T3, the first feedback control signal FB1 transitions to a high level, turning on the first feedback transistor FBT1. At time TA, the reset voltage at the first node N1 is stored in the first capacitor CP1. At time T5, the transmission control signal TG transitions to a high level, and the charge in the photodiode PD moves to the floating diffusion region FD. The second feedback control signal FB2 transitions to a high level, and the second feedback transistor FBT2 is turned on. The source follower transistor SF outputs a pixel voltage to the first node N1 in response to the voltage of the floating diffusion region FD.

[0084] At time TB, the pixel voltage at the first node N1 is stored in the second capacitor CP2. For the rolling readout operation, at time T8, the reset control signal RS transitions to a high level, and the floating diffusion region FD is reset (precharged). The select control signal SEL remains high during the rolling readout operation of the pixel voltage and the reset voltage, and the select transistor SX is turned on. At time T10, the first control signal LOF1 transitions to a high level, turning on the first transistor T1, and the charge stored in the first capacitor CP1 is transferred to the floating diffusion region FD. At time TC, the reset voltage of the floating diffusion region FD is output to the column line CLi. Unlike the operation of the pixel PX in FIG. 3B, the first transistor T1 is turned off at time T11. At time T12, the reset control signal RS transitions to high level again, and the floating diffusion region FD is reset (precharged). At time T14, the second control signal LOF2 transitions to a high level, turning on the second transistor T1, and the charge stored in the second capacitor CP2 is transferred to the floating diffusion region FD. At time TD, the pixel voltage of the floating diffusion region FD is output to the column line CLi.

[0085] FIG. 7C is a timing diagram illustrating the operation of pixel PXd in the rolling shutter mode of the pixel of FIG. 7A. The operation of pixel PXd, as described with reference to FIG. 7C, provides multiple conversion gain modes. The following mainly describes the differences from the operation of the pixel PX described with reference to FIG. 3F.

[0086] In one embodiment, the plurality of conversion gain modes includes an HCG mode and an LCG mode. In the LCG mode, the capacitance of the first capacitor CP1 or the second capacitor CP2 is provided to the floating diffusion region FD. Alternatively, in the LCG mode, the entire capacitance of the first capacitor CP1 and the second capacitor CP2 is provided to the floating diffusion region FD. In another embodiment, the multiple conversion gain modes include an HCG mode, an MCG mode, and an LCG mode, similar to the embodiment described with reference to FIG. 4D. In this case, the capacitance of the first capacitor CP1 is configured to be different from the capacitance of the second capacitor CP2. Alternatively, in the MCG mode, the capacitance of the first capacitor CP1 or the second capacitor CP2 is provided to the floating diffusion region FD, and in the LCG mode, the capacitance of both the first capacitor CP1 and the second capacitor CP2 is provided to the floating diffusion region FD.

[0087] The operation of pixel PXd will be described with reference to FIG. 7C on the assumption that the multiple conversion gain modes include an HCG mode and an LCG mode. Also, in the LCG mode, it is assumed that the capacitance of the first capacitor CP1 is provided to the floating diffusion region FD. In the HCG mode and the LCG mode, the first feedback control signal FB1 and the second feedback control signal FB2 are maintained at a low level. In the HCG mode, at time T1, the floating diffusion region FD is reset by turning on the reset transistor RX, at time T3 the select transistor SX is turned on, and at time TA the reset voltage of the floating diffusion region FD is output to the column line CLi. At time T4, the transfer transistor TX is turned on to transfer the charge of the photodiode PD to the floating diffusion region FD, and at time TB, the pixel voltage of the floating diffusion region FD is output to the column line CLi.

[0088] In the LCG mode, at time T6, the first transistor T1 is turned on by the first control signal LOF1 at a high level, and the first capacitor CP1 is electrically connected to the floating diffusion region FD. At time TC, the pixel voltage of the floating diffusion region FD is output to the column line CLi. At time T7, with the first transistor T1 turned on, the floating diffusion region FD is reset again by turning on the reset transistor RX. At time TD, the reset voltage of the floating diffusion region FD is output to the column line CLi. As explained above, when pixel PXd provides HCG mode, MCG mode, and LCG mode, pixel PXd can operate in the same manner as the embodiment described with reference to FIG. 4D.

[0089] FIG. 8A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXe in FIG. 8A corresponds to pixel PX in image sensor 100 in FIG. Detailed description of overlapping or similar parts will be omitted with reference to FIGS. 3A to 7C. Referring to FIG. 8A, the pixel PXe according to the embodiment of the present invention differs from the pixel PXd described with reference to FIG. 7A in that it includes a conversion gain transistor CGT connecting the second node N2 and the floating diffusion region FD. The second node N2 is selectively electrically coupled to the floating diffusion region FD by turning on or off the conversion gain transistor CGT. The first capacitor CP1 and / or the second capacitor CP2 are selectively electrically coupled to the floating diffusion region FD by turning on or off the first transistor T1 and / or the second transistor T2 and the conversion gain transistor CGT.

[0090] In one embodiment, at least one of the first capacitor CP1 and the second capacitor CP2 comprises a lateral overflow storage capacitor LOFIC. Pixels PXe according to embodiments of the present invention can operate in a global shutter mode using a reduced number of transistors. In addition, the paths between the first capacitor CP1 and the floating diffusion region FD and the paths between the second capacitor CP2 and the floating diffusion region FD are symmetrical to each other. Therefore, correlated double sampling (CDS) can be performed accurately even in global shutter mode. In addition, in the pixel PXd, the second node N2 is isolated from the floating diffusion region FD in the HCG mode of the rolling shutter mode, thereby improving the quality of the image generated by the image sensor 100.

[0091] FIG. 8B is a timing diagram illustrating the operation of pixel PXe in the global shutter mode of the pixel of FIG. 8A. The operation of pixel PXe, which will be described with reference to FIG. 8B, stores a reset voltage and a pixel voltage in first capacitor CP1 and second capacitor CP2, respectively. The following mainly describes the differences from the operation of pixel PXd described with reference to FIG. 7B. In pixel PXe, the conversion gain transistor CGT is maintained in a turned-off state by a low level conversion gain control signal DCG in the signal dump operation, and maintained in a turned-on state by a high level conversion gain control signal DCG in the rolling readout operation.

[0092] In the signal dump operation, at time TA, the reset voltage is stored in the first capacitor CP1 through the first feedback transistor FBT1, which is turned on by the first feedback control signal FB1 at a high level. At time TB, the pixel voltage is stored in the second capacitor CP2 through the second feedback transistor FBT2, which is turned on by the second feedback control signal FB2 at a high level. During the rolling readout operation, at time TC, the reset voltage stored in the first capacitor CP1 is transferred to the floating diffusion region FD by the first transistor T1, which is turned on by the first control signal LOF1, and the reset voltage is output to the column line CLi. At time TD, the second transistor T2 is turned on by the second control signal LOF2, and the pixel voltage stored in the second capacitor CP2 is transferred to the floating diffusion region FD, and the pixel voltage is output to the column line CLi.

[0093] FIG. 8C is a timing diagram illustrating the operation of pixel PXe in the rolling shutter mode of the pixel of FIG. 8A. The operation of pixel PXe, as described with reference to FIG. 8C, provides multiple conversion gain modes. The following mainly describes the differences from the operation of pixel PXd described with reference to FIG. 7C. In one embodiment, the plurality of conversion gain modes includes an HCG mode and an LCG mode. In the LCG mode, the capacitance of the first capacitor CP1 or the second capacitor CP2 is provided to the floating diffusion region FD. Alternatively, in the LCG mode, the entire capacitance of the first capacitor CP1 and the second capacitor CP2 is provided to the floating diffusion region FD. Alternatively, in the LCG mode, the junction capacitance of the second node N2 is provided to the floating diffusion region FD.

[0094] In another embodiment, the multiple conversion gain modes include an HCG mode, an MCG mode, and an LCG mode, similar to the embodiment described with reference to FIG. 4D. In this case, the capacitance of the first capacitor CP1 is configured to be different from the capacitance of the second capacitor CP2. Alternatively, in the MCG mode, the capacitance of the first capacitor CP1 or the second capacitor CP2 is provided to the floating diffusion region FD, and in the LCG mode, the capacitance of both the first capacitor CP1 and the second capacitor CP2 is provided to the floating diffusion region FD. Alternatively, in the MCG mode, the junction capacitance of the second node N2 is provided to the floating diffusion region FD, and in the LCG mode, the capacitance of the first capacitor CP1 or the second capacitor CP2 is provided to the floating diffusion region FD.

[0095] The operation of pixel PXe described with reference to FIG. 8C will be described assuming that the multiple conversion gain modes include an HCG mode and an LCG mode. Also, in the LCG mode, it is assumed that the capacitance of the first capacitor CP1 is provided to the floating diffusion region FD. The conversion gain transistor CGT remains turned off in the HCG mode and remains turned on in the LCG mode. The first transistor T1 is turned off in the HCG mode and turned on in the LCG mode to provide the capacitance of the first capacitor CP1 to the floating diffusion region FD. In the LCG mode, the pixel PXe samples (outputs to the column line CLi) the pixel voltage and the reset voltage at the time TC and the time TD, respectively, with the first capacitor CP1 electrically connected to the floating diffusion region FD.

[0096] In other embodiments not shown in FIG. 8C, operation of pixel PXe can include HCG mode, MCG mode, and LCG mode. In this case, the pixel PXe provides the junction capacitance of the second node N2 to the floating diffusion region FD in the MCG mode by turning on the conversion gain transistor CGT. In addition, in the LCG mode, the pixel PXe provides the junction capacitance of the second node N2 and the capacitance of the first capacitor CP1 to the floating diffusion region FD by turning on the conversion gain transistor CGT and the first transistor T1.

[0097] FIG. 9A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXf in FIG. 9A corresponds to pixel PX of image sensor 100 in FIG. Detailed description of overlapping or similar parts will be omitted with reference to FIGS. 3A to 8C. Referring to FIG. 9A, pixel PXf according to an embodiment of the present invention differs from pixel PXd described with reference to FIG. 7A in that a third feedback transistor FBT3 is additionally connected in parallel between first node N1 and second node N2.

[0098] In addition, a third capacitor CP3 is additionally connected in parallel between the first node N1 and the second node N2. That is, the first feedback transistor FBT1, the second feedback transistor FBT2, and the third feedback transistor FBT3 are connected in parallel between the first node N1 and the second node N2. In addition, the first capacitor CP1, the second capacitor CP2, and the third capacitor CP3, which are respectively connected to one terminal of the first feedback transistor FBT1, the second feedback transistor FBT2, and the third feedback transistor FBT3, are also connected in parallel with each other. The first transistor T1, the second transistor T2, and the third transistor T3 are connected in series with the first feedback transistor FBT1, the second feedback transistor FBT2, and the third feedback transistor FBT3, respectively. In one embodiment, at least one of the first capacitor CP1, the second capacitor CP2, and the third capacitor CP3 comprises a lateral overflow storage capacitor LOFIC.

[0099] Pixels PXf according to embodiments of the present invention operate in a global shutter mode using a reduced number of transistors. In addition, the paths between the first capacitor CP1, the second capacitor CP2, and the third capacitor CP3 and the floating diffusion region FD are symmetrical to one another. Therefore, correlated double sampling (CDS) is performed accurately even in global shutter mode.

[0100] Although the embodiments described with reference to FIGS. 9A to 9C are described assuming that pixel PXf is a dual photodiode pixel, pixel PXf may be a super photodiode pixel in some embodiments. The pixel PXf may correspond to some or all of the pixels PXs included in the pixel array 110 of the image sensor 100 in FIG. The pixel PXf generates a pixel voltage for autofocusing operation in global shutter mode. For example, in a signal dump operation in the global shutter mode, voltages corresponding to photocharges generated by a plurality of photodiodes (PD1, PD2) are stored separately in different capacitors (CP1, CP2).

[0101] Alternatively, the second capacitor CP2 stores a voltage corresponding to the photocharges generated in the first photodiode PD1, and the first capacitor CP1 stores both voltages corresponding to the photocharges generated in the first photodiode PD1 and the second photodiode PD2. The image sensor 100 performs autofocusing in global shutter mode using a pixel voltage corresponding to the photocharge generated in the first photodiode PD1 of the pixel PXc and a pixel voltage corresponding to the photocharge generated in the second photodiode PD2. In one embodiment, if pixel PXf, which generates the phase data used for autofocusing, is configured as a superphotodiode pixel, the output of pixel PXf in rolling shutter mode is not used for image generation and a bad pixel correction process is performed.

[0102] FIG. 9B is a timing diagram for explaining the operation of pixel PXf of FIG. 9A in the global shutter mode. The operation of pixel PXf described with reference to FIG. 9B will be described assuming that the second capacitor CP2 stores a voltage corresponding to the photocharge generated in the first photodiode PD1, and the third capacitor CP3 stores both voltages corresponding to the photocharge generated in the first photodiode PD1 and the second photodiode PD2. The first capacitor CP1 stores a reset voltage. The following mainly describes the differences from the operation of pixel PXd described with reference to FIG. 7B.

[0103] In the signal dump operation, at time TA, the reset voltage is stored in the first capacitor CP1 through the first feedback transistor that is turned on by the first feedback control signal FB1 at a high level. At time TB, the pixel voltage corresponding to the photocharge of the first photodiode PD1 is stored in the second capacitor CP2 through the second feedback transistor that is turned on by the second feedback control signal FB2 at a high level. At time TC, a pixel voltage corresponding to all the photocharges in the first photodiode PD1 and the second photodiode PD2 is stored in the third capacitor CP3 through the third feedback transistor that is turned on by the third feedback control signal FB3 at a high level.

[0104] During the rolling readout operation, at time TD, the reset voltage stored in the first capacitor CP1 is transferred to the floating diffusion region FD by the first transistor T1, which is turned on by the first control signal LOF1, and the reset voltage is output to the column line CLi. At time TE, the pixel voltage stored in the second capacitor CP2 is transferred to the floating diffusion region FD by the second transistor T2, which is turned on by the second control signal LOF2. A pixel voltage corresponding to the photocharge of the first photodiode PD1 is output to the column line CLi. At time TF, the pixel voltage stored in the third capacitor CP3 is transferred to the floating diffusion region FD. A pixel voltage corresponding to all the photocharges in the first photodiode PD1 and the second photodiode PD2 is output to the column line CLi.

[0105] FIG. 9C is a timing diagram for explaining the operation of pixel PXf of FIG. 9A in the rolling shutter mode. The operation of pixel PXf described with reference to FIG. 9C will be described assuming that pixel PXf is a dual photodiode pixel. The following mainly describes the operation of the pixel PXe described with reference to FIG. 8C and the differences therebetween. The operation of pixel PXf, as described with reference to FIG. 9C, provides multiple conversion gain modes. In one embodiment, the plurality of conversion gain modes includes an HCG mode and an LCG mode.

[0106] In pixel PXf, the second and third control signals (LOF2, LOF3) maintain a low level throughout the entire readout operation in the HCG mode and the LCG mode, and the second and third transistors (T2, T3) maintain a turned-off state. The first, second, and third feedback transistors (FBT1, FBT2, FBT3) remain low during all readout operations. In the HCG mode, at time TA, after the reset voltage is sampled, the first and second transmission transistors (TX1, TX2) are simultaneously turned on by the first and second transmission control signals (TG1, TG2). Therefore, the photocharges generated by the first and second photodiodes (PD1, PD2) are simultaneously transferred to the floating diffusion region FD, and the pixel voltage is sampled at time TB. In the LCG mode, the first transistor T1 is turned on to electrically connect the first capacitor CP1 to the floating diffusion region FD. With the first capacitor CP1 electrically connected to the floating diffusion region FD, the pixel voltage in the LCG mode is sampled at time TC. At time T7, the reset transistor RX is turned on, and at time TD, the reset voltage of the LCG mode is sampled.

[0107] FIG. 10A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXg in FIG. 10A corresponds to pixel PX in image sensor 100 in FIG. Detailed description of overlapping or similar parts will be omitted with reference to FIGS. 3A to 9C. Referring to FIG. 10A, the pixel PXg according to the embodiment of the present invention differs from the pixel PXf described with reference to FIG. 9A in that it includes a conversion gain transistor CGT connecting the second node N2 and the floating diffusion region FD.

[0108] In one embodiment, the second node N2 is selectively electrically coupled to the floating diffusion region FD by turning on or off the conversion gain transistor CGT. In another embodiment, at least one of the first capacitor CP1, the second capacitor CP2, and the third capacitor CP3 is selectively electrically coupled to the floating diffusion region FD by turning on or off the first transistor T1, the second transistor T2, the third transistor T3, and the conversion gain transistor CGT. In one embodiment, at least one of the first capacitor CP1, the second capacitor CP2, and the third capacitor CP3 comprises a lateral overflow storage capacitor LOFIC. The pixel PXg according to the embodiment of the present invention can operate in a global shutter mode using a small number of transistors, and the paths between each of the capacitors (CP1, CP2, CP3) and the floating diffusion region FD are symmetrical to each other. Therefore, correlated double sampling (CDS) is performed accurately even in global shutter mode.

[0109] The pixel PXg generates a pixel voltage for autofocusing operation in global shutter mode. The pixel PXg selectively provides the junction capacitance of the second node N2 to the floating diffusion region FD by turning on or off the conversion gain transistor CGT. In addition, pixel PXg selectively provides at least one capacitance among capacitors (CP1, CP2, CP3) to floating diffusion region FD by turning on conversion gain transistor CGT and selectively turning on or off first, second, and third transistors (T1, T2, T3). Thus, pixel PXg provides multiple conversion gain modes in rolling shutter mode. In addition, in the pixel PXg, the second node N2 is isolated from the floating diffusion region FD in the HCG mode of the rolling shutter mode, thereby improving the quality of the image generated by the image sensor 100.

[0110] Although the embodiments described with reference to FIGS. 10A to 10C are described assuming that the pixel PXg is a dual photodiode pixel, the pixel PXg may be a super photodiode pixel in some embodiments. The pixel PXg may correspond to some or all of the pixels PXs included in the pixel array 110 of the image sensor 100 in FIG. In one embodiment, if the pixel PXg that generates the phase data used for autofocusing is composed of a superphotodiode pixel, in rolling shutter mode the output of the pixel PXg is not used for image generation and a bad pixel correction process is performed.

[0111] FIG. 10B is a timing diagram illustrating the operation of pixel PXg in the global shutter mode of the pixel of FIG. 10A. The following mainly describes the differences from the operation of pixel PXf described with reference to FIG. 9B. The operation of pixel PXg described with reference to FIG. 10B will be described assuming that the second capacitor CP2 stores a voltage corresponding to the photocharge generated in the first photodiode PD1, and the third capacitor CP3 stores both voltages corresponding to the photocharge generated in the first photodiode PD1 and the second photodiode PD2.

[0112] The first capacitor CP1 stores a reset voltage. The following mainly describes the differences from the operation of pixel PXf described with reference to FIG. 9B. The conversion gain transistor CGT maintains a turned-off state in the signal dump operation when the conversion gain control signal DCG is at a low level, and maintains a turned-on state in the rolling readout operation when the conversion gain control signal DCG is at a high level.

[0113] FIG. 10C is a timing diagram for explaining the operation of the pixel PXg of FIG. 10A in the rolling shutter mode. The operation of pixel PXg described with reference to FIG. 10C will be described assuming that pixel PXg is a dual photodiode pixel. The following mainly describes the differences from the operation of pixel PXf described with reference to FIG. 9C.

[0114] The operation of pixel PXg, as described with reference to FIG. 10C, provides multiple conversion gain modes. In one embodiment, the plurality of conversion gain modes includes an HCG mode and an LCG mode. The conversion gain transistor CGT remains turned off in the HCG mode and remains turned on in the LCG mode. Therefore, in the HCG mode, the second node N2 is isolated from the floating diffusion region FD, thereby improving the quality of the image generated by the image sensor 100.

[0115] In other embodiments not shown in FIG. 10C, the operation of pixel PXg includes an HCG mode, an MCG mode, and an LCG mode. In this case, the pixel PXg provides the junction capacitance of the second node N2 to the floating diffusion region FD in the MCG mode by turning on the conversion gain transistor CGT. In addition, in the LCG mode, the pixel PXg provides the junction capacitance of the second node N2 and the capacitance of the first capacitor CP1 to the floating diffusion region FD by turning on the conversion gain transistor CGT and the first transistor T1. Therefore, by isolating the second node N2 and the floating diffusion region FD by the conversion gain transistor CGT, the image quality is improved in the HCG mode and a greater number of conversion gain modes can be provided.

[0116] FIG. 11A is a circuit diagram of a pixel of an image sensor according to one embodiment of the present invention. Pixel PXh in FIG. 11A corresponds to pixel PX in image sensor 100 in FIG. Detailed description of overlapping or similar parts will be omitted with reference to FIGS. 3A to 10C. Referring to FIG. 11A, a pixel PXh according to an embodiment of the present invention includes a photodiode PD and a transfer transistor TX, unlike the pixel PXc described with reference to FIG. 6A.

[0117] In the pixel PXh according to an embodiment of the present invention, when the image sensor 100 operates in global shutter mode, the charge overflowing from the photodiode PD during the accumulation time exceeds the potential barrier of the conversion gain transistor CGT and is stored in the third capacitor CP3, which is composed of a lateral overflow storage capacitor LOFIC. In this case, the reset control signal RS has a low level and the reset transistor RX is turned off. The third transistor T3 is turned on to electrically connect the second node N2 and the third capacitor CP3. The pixel PXh reads out the voltage corresponding to the overflowed photocharge stored in the third capacitor CP3 separately from the voltage corresponding to the photocharge stored in the first capacitor CP1. That is, even when the image sensor 100 is in a global shutter mode, the pixel PXh can generate an image signal based on the charge overflowed in the photodiode PD in response to a high-illumination environment.

[0118] The pixel PXh performs a signal dump operation in the global shutter mode of the image sensor 100 . The pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and stored in the first capacitor CP1, and the reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and stored in the second capacitor CP2. Alternatively, the reset voltage is stored in the first capacitor CP1 and the pixel voltage is stored in the second capacitor CP2. At this time, the selection transistor SX is turned off. In addition, during readout operation in global shutter mode, pixel PXh can reduce degradation of image quality by transferring the charge corresponding to the pixel voltage and / or reset voltage stored in the first capacitor CP1 and / or the second capacitor CP2, respectively, to the floating diffusion region FD through one of the read transistors (RT1, RT2). In addition, in the pixel PXh, the second node N2 is isolated from the floating diffusion region FD in the HCG mode of the rolling shutter mode, thereby improving the quality of the image generated by the image sensor 100.

[0119] In one embodiment, the third transistor T3 is omitted, and the second node N2 and the third capacitor CP3 are isolated from each other. In one embodiment, the dual conversion gain transistor DCG is omitted and the second node N2 and the floating diffusion region FD are directly connected. In this case, it operates similarly to the embodiment of FIG. 3A. In one embodiment, pixel PXh may include an additional capacitor connected in parallel with the first to third capacitors CP1 to CP3 to support autofocusing operations. In this case, the photodiode is configured as two dual photodiodes and can operate similarly to pixel PXc in FIG. 6A.

[0120] FIG. 11B is a timing diagram for explaining the operation of pixel PXh of FIG. 11A in the global shutter mode. The operation of pixel PXh described with reference to FIG. 11B will be described assuming that the pixel voltage is stored in the first capacitor CP1, the reset voltage is stored in the second capacitor CP2, and the charge overflowing from the photodiode PD is stored in the third capacitor CP3. In the signal dump operation, the read transistors RT1 and RT2, the second transistor T2, and the third transistor T3 are maintained in the turned-off state by the low level read control signals RD1 and RD2, the second control signal LOF2, and the third control signal LOF3.

[0121] At time T1, the reset control signal RS and the conversion gain control signal DCG are at high levels, so that the reset transistor RX and the conversion gain transistor CGT are turned on, and the floating diffusion region FD is reset. At time T2, the source follower transistor SF outputs a reset voltage to the first node N1 in response to the voltage of the floating diffusion region FD. The feedback control signal FB and the first control signal LOF1 are at high levels, which turn on the feedback transistor FBT and the first transistor T1. At time TA, the reset voltage of the first node N1 is stored in the second capacitor CP2. At time T3, the first transistor T1 is turned off by the first control signal LOF1, and at time T4, the pixel voltage corresponding to the photocharges generated in the photodiode PD due to the turn-on of the transfer transistor TX is output to the first node N1. At time TB, the pixel voltage at the first node N1, which corresponds to the photocharges generated in the photodiode PD, is stored in the first capacitor CP1.

[0122] For the rolling readout operation, at time T7, the reset control signal RS and the conversion gain control signal DCG transition to a high level, the reset transistor RX and the conversion gain transistor CGT are turned on, and the floating diffusion region FD is precharged. The selection control signal SEL remains at a high level during the rolling readout operation of the pixel voltage and the reset voltage, and the selection transistor SX remains turned on. At time T8, the reset transistor RX and the conversion gain transistor CGT are turned off, and at time T9, the second read control signal RD2 transitions to a high level, turning on the second read transistor RT2. The charge stored in the second capacitor CP2 is transferred to the floating diffusion region FD through the second read transistor RT2. At time TC, the reset voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0123] At time T10, the second read transistor RT2 is turned off by the low level second read control signal RD2, and at time T11, the reset control signal RS and the conversion gain control signal DCG transition to high levels, the reset transistor RX and the conversion gain transistor CGT are turned on, and the floating diffusion region FD is precharged again. At time T12, the reset transistor RX and the conversion gain transistor CGT are turned off, and at time T13, the first read control signal RD1 transitions to a high level, turning on the first read transistor RT1. The charge stored in the first capacitor CP1 is transferred to the floating diffusion region FD through the first read transistor RT1. At time TD, the pixel voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX. At time T14, the first read transistor RT1 is turned off, and at time T15, the third control signal LOF3 and the conversion gain control signal DCG transition to a high level, turning on the third transistor T3 and the conversion gain transistor CGT. The overflowed charge stored in the third capacitor CP3 is transferred to the floating diffusion region FD through the third transistor T3 and the conversion gain transistor CGT. At time TE, the voltage of the floating diffusion region FD is amplified by the source follower transistor SF and output to the column line CLi via the selection transistor SX.

[0124] According to an embodiment of the present invention, the voltage of the floating diffusion region FD output at the time TE of the pixel PXh may be the sum of the voltage corresponding to the overflowed charge stored in the third capacitor CP3 and the pixel voltage of the photodiode PD. That is, the floating diffusion region FD does not need to be precharged before the overflowed charge stored in the third capacitor CP3 is transferred to the floating diffusion region FD. In one embodiment, the signal output to the column line CLi at time TD and the signal output to the column line CLi at time TE are each converted into a digital pixel signal based on a reset voltage, and one of the digital pixel signals can be determined as a final pixel signal by a signal processing circuit outside the pixel. Therefore, pixel PXh can generate an image that is not saturated even at high illumination.

[0125] FIG. 11C is a timing diagram illustrating the operation of pixel PXh of FIG. 11A in the rolling shutter mode. The following mainly describes the operation of pixel PXc described with reference to FIG. 6C and the differences therebetween. The operation of pixel PXh, as described with reference to FIG. 11C, provides multiple conversion gain modes. In one embodiment, the plurality of conversion gain modes includes an HCG mode and an LCG mode. The pixel PXh can operate in the same manner as the pixel PXc in the rolling shutter mode described with reference to FIG. 6C. However, unlike FIG. 6C, there is only one transmission transistor control signal TG.

[0126] FIG. 11D is a timing diagram illustrating the operation of pixel PXh of FIG. 11A in the rolling shutter mode. The following mainly describes the operation of pixel PXc described with reference to FIG. 6D and the differences therebetween. The operation of pixel PXh, as described with reference to FIG. 11D, provides multiple conversion gain modes. In one embodiment, the multiple conversion gain modes include an HCG mode, an MCG mode, and an LCG mode. The pixel PXh can operate in the same manner as the pixel PXc in the rolling shutter mode described with reference to FIG. 6D. However, unlike FIG. 6D, there is only one transmission transistor control signal TG.

[0127] FIG. 12 is a diagram illustrating pixel groups in a pixel array according to an embodiment of the present invention. The pixel group described with reference to FIG. 12 corresponds to a portion of pixel array 110 of image sensor 100 of FIG. The pixels in FIG. 12 correspond to any one of the pixels in the embodiments described with reference to FIGS. 1 to 11D. The pixel array 110 will be described with reference to FIGS.

[0128] In one embodiment, pixel array 110 includes consecutive pixels having the same color filter. Pixels containing the same color filter are called a pixel group. FIG. 12 will be described assuming an embodiment in which the pixel array 110 has a tetracell structure, with four pixels having the same color filter constituting a pixel group. In this case, the first pixel group PG1 and the fourth pixel group PG4 include green color filters, the second pixel group PG2 includes red color filters, and the third pixel group PG3 includes blue color filters. That is, the pixel groups (PG1, PG2, PG3, PG4) are arranged in a Bayer pattern. In the pixel array 110, pixel groups (PG1, PG2, PG3, PG4) as shown in FIG. 12 are repeatedly arranged.

[0129] An image sensor 100 including a pixel array 110 according to the embodiment of FIG. 12 operates in either tetra mode or normal mode. When the external environment is low in illumination, the image sensor 100 operates in the tetra mode. When the external environment has normal illuminance, the image sensor 100 operates in the normal mode. In normal mode, the pixel array 110 outputs an analog signal at each of the pixels included in the pixel groups (PG1, PG2, PG3, PG4). In tetra mode, the pixel array 110 outputs analog signals for each pixel group (PG1, PG2, PG3, PG4) instead of outputting analog signals for each pixel. That is, the pixel array 110 operates in units of pixel groups. For example, pixels included in the same pixel group are controlled in the same way, and signals output from pixels included in the same pixel group are binned.

[0130] In one embodiment, the pixel group includes pixels in an M×N format (M and N are integers equal to or greater than 2). The MxN format is a format in which M pixel lines are arranged vertically. Each of the M pixel lines includes N pixels arranged consecutively in the horizontal direction. In the embodiment with reference to FIG. 12, it is assumed that M and N are 2, but the present invention is not limited thereto, and M and N may be 3 or greater. Also, M and N can be different integers.

[0131] FIG. 13 is a perspective view showing a schematic configuration of an image sensor 100a according to an embodiment of the present invention. Detailed explanations of parts that overlap with those previously explained will be omitted. The image sensor 100a includes a first substrate 10a and a second substrate 20a that are stacked together. The first substrate 10a is stacked on the second substrate 20a, for example, in a direction D3 perpendicular to the plane of the substrate (a plane parallel to D1 and D2). The first substrate 10a and the second substrate 20a are electrically connected. For example, the first substrate 10a and the second substrate 20a transmit pixel signals or control signals through through silicon vias (TSVs) between pads located in the peripheral regions of the substrates. The first substrate 10a and the second substrate 20a are also electrically connected through in-pixel contacts (IN_CT) inside the pixels PXi. The in-pixel contact can be, for example, a Cu-to-Cu (C2C) bonding contact. The pixel signals (or pixel data) of the first substrate 10a are transmitted to the readout circuitry (or image signal processing logic) of the second substrate 20a. The second board 20a may include readout circuits, timing controllers, logic such as image signal processing logic, and interface circuits. The readout circuit may include an ADC.

[0132] FIG. 14 is a perspective view showing a schematic configuration of an image sensor 100b according to an embodiment of the present invention. Detailed explanations of parts that overlap with those previously explained will be omitted. The image sensor 100b includes a first substrate 10b and a second substrate 20b that are stacked together. The first substrate 10b and the second substrate 20b are connected to each other through a wafer bonding process using pixel-level C2C interconnection. The first substrate 10b and the second substrate 20b are electrically connected not only through in-pixel contacts within the pixels PXj but also through a C2C (Cu-to-Cu) array located in the peripheral region of the substrates. Control signals are transmitted through the C2C array to control the pixel circuits. Through the in-pixel contacts, pixel signals (or pixel data) of the first substrate 10b are transmitted to a readout circuit (or image signal processing logic) of the second substrate 20b.

[0133] FIG. 15 is a perspective view showing a schematic configuration of an image sensor 100c according to one embodiment of the present invention. Detailed explanations of parts that overlap with those previously explained will be omitted. Referring to FIG. 15, an image sensor 100c further includes a third substrate 30c in addition to a first substrate 10c and a second substrate 20c. The third substrate 30c, the second substrate 20c, and the first substrate 10c are sequentially stacked in a direction D3 perpendicular to the plane of the substrates (a plane parallel to D1 and D2). The third substrate 30c includes a memory device. For example, the third substrate 30c may include a volatile memory device such as a DRAM or an SRAM. The third substrate 30c receives signals from the first substrate 10c and the second substrate 20c and processes the signals through a memory device.

[0134] FIG. 16A is a perspective view showing a schematic configuration of an image sensor 100d according to an embodiment of the present invention. Detailed explanations of parts that overlap with those previously explained will be omitted. Referring to FIG. 16A, an image sensor 100d includes a first substrate 10d, a second substrate 20d, and a third substrate 30d. The third substrate 30d, the second substrate 20d, and the first substrate 10d are sequentially stacked in a direction D3 perpendicular to the plane of the substrates (a plane parallel to D1 and D2). In one embodiment, a part of the pixel circuits (PXl_a, PXl_b) is formed on each of the first substrate 10d and the second substrate 20d. A first partial circuit (PXl_a) of the pixel is disposed on the first substrate 10d, and the remaining second partial circuit (PXl_b) of the pixel is disposed on the second substrate 20d. The third board 30d may include logic such as readout circuits, timing controllers, image signal processing logic, and interface circuits. The readout circuit may include an ADC.

[0135] For example, in the pixels (PXa to PXh) according to the embodiment of FIGS. 1 to 11, the photodiodes are disposed on the first substrate 10d, and the remaining pixel circuits are disposed on the second substrate 20d. Alternatively, in the pixels (PXa to PXh), the photodiode, transfer transistor, reset transistor, source follower transistor, and selection transistor may be arranged on the first substrate 10d, and depending on the embodiment, the dual conversion gain transistor, capacitor, transistor connected to the capacitor, and feedback transistor may be arranged on the second substrate 20d. Alternatively, in the pixels (PXa to PXh), the photodiode, transfer transistor, reset transistor, dual conversion gain transistor, capacitor, and transistor connected to the capacitor are arranged on the first substrate 10d, and the remaining circuits are arranged on the second substrate 20d. The arrangement of the circuits constituting the pixels (PXa to PXh) on the first substrate 10d and the second substrate 20d is not limited to this.

[0136] The first substrate 10d and the second substrate 20d are electrically connected to each other. In one embodiment, the first substrate 10d and the second substrate 20d transmit pixel signals or control signals through through silicon vias TSVs located in the peripheral regions of the substrates. In one embodiment, the first partial circuit (PXl_a) of the pixel of the first substrate 10d and the second partial circuit (PXl_b) of the pixel of the second substrate 20d are also electrically connected through a first inter-substrate connection structure INTC1. The inter-substrate connection structure INTC1 can be a Cu-to-Cu (C2C) bonding contact, deep contact structure. The deep contact structure includes a through silicon electrode.

[0137] The following description will be given with reference to Figures 16B and 16C. The inter-substrate connection structure INTC1 electrically connects the in-pixel contact (IN_CT1) electrically connected to the element of the first partial circuit (PXl_a) of the pixel and the in-pixel contact (IN_CT2) electrically connected to the element of the second partial circuit (PXl_b) of the pixel to each other. In one embodiment, the first substrate 10d and / or the second substrate 20d are electrically connected to the third substrate 30d through through silicon vias TSVs and / or second inter-substrate connection structures INTC2. Signals from the first substrate 10d and / or the second substrate 20d are transmitted to a readout circuit (or image signal processing logic) on the third substrate 30d through the through silicon vias TSVs and / or the second inter-substrate connection structures INTC2. In one embodiment, the pixel's second sub-circuit (PXl_b) is electrically connected to the circuitry of the third substrate 30d through Cu-to-Cu (C2C) bonding contacts. The second inter-substrate connection structure INTC2 includes a Cu-to-Cu (C2C) bonding contact. In one embodiment, the second partial circuit (PXl_b) of the pixel is electrically connected to the circuit of the third substrate 30d through TSC (Thru-silicon Copper).

[0138] FIG. 16B is a cross-sectional view showing a schematic configuration of the image sensor 100d of FIG. 16A according to one embodiment. Detailed explanations of parts that overlap with those previously explained will be omitted. Referring to FIG. 16B, the image sensor 100d1 includes a first structure S1, a second structure S2, and a third structure S3. In one embodiment, the first structure S1 includes a photodiode PD, a transmission gate TG, and a floating diffusion region FD. In one embodiment, the pixel circuit of each of the pixels (PXl_1, PXl_2) is disposed in the second structure S2. Or, in one embodiment, a part of the pixel circuit of each of the pixels (PXl_1, PXI_2) is disposed in the first structure S1, and another part is disposed in the second structure S2.

[0139] That is, FIG. 16B exemplarily shows that the floating diffusion region FD of the first structure S1 is directly connected to the transistor TR of the second structure S2. However, unlike FIG. 16B, the floating diffusion region FD of the first structure S1 may be electrically connected to the transistor TR of the second structure S2 through another pixel circuit of the first structure S1. In one embodiment, the third structure S3 may include logic such as readout circuits, timing controllers, image signal processing logic, and interface circuits. In one embodiment, the first structure S1, the second structure S2, and the third structure S3 include a wiring layer WS for transmitting electrical signals. In one embodiment, the first structure S1 includes a first surface FS1 and a second surface BS1 facing each other. The first surface FS1 may be the front surface of the first structure S1, and the second surface BS1 may be the back surface of the first structure S1. For example, the image sensor 100d1 may be a backside illumination (BSI) image sensor in which light is incident on the rear surface of the first structure S1.

[0140] In one embodiment, the pixels (PXl_1, PXl_2) arranged in the first structure S1 each include a photodiode PD, a color filter (CFa, CFb), and a microlens (MLa, MLb). While FIG. 16B shows that each of the pixels (PXl_1, PXl_2) includes a different microlens (MLa, MLb), alternatively, multiple pixels of the image sensor 100d1 can share one microlens. Alternatively, multiple photodiodes can share one microlens. That is, one microlens can be formed to extend across multiple pixels or multiple photodiodes. For example, the pixels of image sensor 100d1 may be dual-photodiode pixels in which multiple photodiodes in one pixel share one microlens. Alternatively, the pixels of image sensor 100d1 may be superpixels, in which multiple pixels share one microlens.

[0141] In one embodiment, a plurality of pixel isolation films DTI extending from the second surface BS1 toward the first surface FS1 are formed between the first surface FS1 and the second surface BS1 of the first substrate W1 of the first structure S1. The pixels (PXl_1, PXl_2) are separated from each other by the pixel isolation film DTI. In one embodiment, the first structure S1 includes an isolation region STI. In one embodiment, the isolation portion STI extends from the first surface FS1 of the first substrate W1 toward the second surface BS1 to a predetermined depth and includes an insulating material. In this case, the element isolation portion STI is connected to the pixel isolation film DTI, and the boundary between the element isolation portion STI and the pixel isolation film DTI may be unclear. In one embodiment, the element isolation portion STI is formed as a doped region having a predetermined depth from the first surface FS1 toward the second surface BS1 of the first substrate W1. The doped region is doped with a P-type material.

[0142] In one embodiment, the second structure S2 includes a second substrate W2. In one embodiment, the second substrate W2 may be a silicon on insulator (SOI) substrate. In this case, after the SOI substrate is bonded to the first structure S1, a portion of the SOI substrate is separated by grinding, polishing, or ion cutting. In this case, the second substrate S2 includes an oxide layer OX and a buried oxide (BOX) layer. The second substrate W2 may be referred to as the active layer. In one embodiment, unlike the exemplary embodiment shown in FIG. 16B, the second substrate W2 may not include a buried oxide BOX layer. That is, the second substrate W2 may be a general semiconductor substrate other than an SOI substrate.

[0143] In one embodiment, the first structure S1 and the second structure S2 are electrically connected to each other through a deep contact structure DCNT. The deep contact structure DCNT is formed by a contact that crosses at least a portion of the first structure S1 and at least a portion of the second structure S2. The deep contact structure DCNT is formed after bonding the first structure S1 and the second structure S2. In one embodiment, the deep contact structure DCNT may include an electrical connection path made of tungsten. Alternatively, in one embodiment, unlike that shown in FIG. 16B, the first structure S1 and the second structure S2 may be electrically connected to each other through a through silicon electrode.

[0144] Alternatively, in one embodiment, the first structure S1 and the second structure S2 may be electrically connected to each other through Cu-to-Cu (C2C) bonding contacts. Alternatively, in one embodiment, the first structure S1 and the second structure S2 may be electrically connected to each other through all of a Cu-to-Cu (C2C) bonding contact, a deep contact structure DCNT, and a through silicon electrode. In one embodiment, the second structure S2 and the third structure S3 are electrically connected through Cu-to-Cu (C2C) bonding contacts. Alternatively, different from what is shown in FIG. 16B, the second structure S2 and the third structure S3 can be electrically connected to each other through a through silicon electrode and / or a TSC. In one embodiment, the first surface FS1 of the first substrate W1 and the third surface BS2 of the second substrate W2 face each other, and the fourth surface FS2 of the second substrate W2 and the fifth surface FS3 of the third substrate W3 face each other.

[0145] FIG. 16C is a cross-sectional view showing a schematic configuration of the image sensor 100d of FIG. 16A according to one embodiment. Detailed descriptions of portions that overlap or are similar to the description referring to the image sensor 100d1 in FIG. 16B will be omitted. Referring to FIG. 16C, the image sensor 100d2 includes a first structure S1, a second structure S2, and a third structure S3. In one embodiment, the first structure S1, the second structure S2, and the third structure S3 each include a substrate (W1, W2, W3). In one embodiment, the first structure S1 and the second structure S2 are electrically connected to each other through Cu-to-Cu (C2C) bonding contacts.

[0146] Alternatively, unlike the example shown in FIG. 16C, the first structure S1 and the second structure S2 can be electrically connected to each other through a through silicon electrode. Alternatively, the first structure S1 and the second structure S2 may be electrically connected to each other through both Cu-to-Cu (C2C) bonding contacts and through-silicon electrodes. In one embodiment, the second structure S2 and the third structure S3 are electrically connected through TSC and / or Cu-to-Cu (C2C) bonding contacts. The TSC includes Cu-to-Cu (C2C) bonding contacts formed through the second substrate W2. Alternatively, unlike what is shown in FIG. 16C, the second structure S2 and the third structure S3 can be electrically connected to each other via through-silicon electrodes and / or Cu-to-Cu (C2C) bonding contacts. In one embodiment, the first surface FS1 of the first substrate W1 and the fourth surface FS2 of the second substrate W2 face each other, and the third surface BS2 of the second substrate W2 and the fifth surface FS3 of the third substrate W3 face each other.

[0147] FIG. 17 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention. Detailed explanations of parts that overlap with those previously explained will be omitted. The electronic device 1000 includes an imaging unit 1100 , an image sensor 1200 , and a processor 1300 . The electronic device 1000 performs autofocusing based on phase data provided to the processor 1300 from the image sensor 1200 . The phase data is generated by the image signal processor 1240 based on the pixel voltages of the pixels (PXc, PXf, PXg) described with reference to Figures 6A, 9A and 10A.

[0148] The processor 1300 controls the overall operation of the electronic device 1000 . The processor 1300 provides control signals to the lens driver 1120 to control the position of the lens 1110 . As a result, the focal length is controlled. The imaging unit 1100 includes a lens 1110 and a lens driver 1120 as components that receive light. The lens 1110 includes a plurality of lenses. The lens driver 1120 moves the lens 1110 in a direction in which the distance from the object S increases or decreases based on a control signal from the processor 1300 .

[0149] The image sensor 1200 generates image data and phase data based on the incident light. The image sensor 1200 includes a pixel array 1210 , a timing controller 1220 , an ADC 1230 , and an image signal processor 1240 . A pixel of the pixel array 1210 includes at least one photoelectric conversion element. Pixels of pixel array 1210 according to embodiments of the present invention can operate in a global shutter mode or a rolling shutter mode. The image signal processor 1240 generates a mode control signal MC based on the shooting mode signal MODE transmitted by the processor 1300 . The pixel operates in either a global shutter mode or a rolling shutter mode based on a mode control signal MC transmitted by the image signal processor 1240 .

[0150] The processor 1300 utilizes the phase data to perform disparity operations. The processor 1300 provides a control signal based on the phase difference calculation result to the lens driver 1120 to move the position of the lens 1110 . The processor 1300 provides an operation mode control signal (INFO_MD) to the timing controller 1220 . The timing controller 1220 controls the operation of the pixel array 1210 based on the operation mode control signal (INFO_MD).

[0151] FIG. 18 is a block diagram showing a schematic configuration of an application processor 1300a according to an embodiment of the present invention. Detailed explanations of parts that overlap with those previously explained will be omitted. The application processor 1300 a includes an image signal processing unit 1310 . The image signal processing device 1310 includes a plurality of image signal processing units (ISP1, ISP2, ISP3) (1311 to 1313), a camera module control unit 1314, and a camera interface 1315.

[0152] The camera module control unit 1314 transmits control signals (CSa, CSb, CSc) to the multiple camera modules. Although FIG. 18 illustrates the transmission of control signals (CSa, CSb, CSc) to three camera modules, the embodiment is not limited to this. Depending on the embodiment, the camera module control unit 1314 may transmit control signals to two camera modules, or may transmit control signals to four or more camera modules. The camera module control unit 1314 according to an embodiment of the present invention transmits control signals (CSa, CSb, CSc) to operate at least one of the camera modules in a global shutter mode. Image signals (ISa, ISb, ISc) are stored in an external memory 1400 via a camera interface 1315 from multiple cameras.

[0153] The image signal processing units (ISP1, ISP2) process the image signals (ISa, ISb, ISc) stored in the external memory 1400 and display them on a display, or perform autofocusing. The image signals (ISa, ISb, ISc) include image data and phase data. The image signals (ISa, ISb, ISc) stored in the external memory 1400 are encoded image signals. The image signal processors ISP1 and ISP2 read and decode the encoded image signal from the external memory 1400, and display image data generated based on the decoded image signal.

[0154] FIG. 19 is a flowchart illustrating a method of operating an image sensor according to an embodiment of the present invention. The image sensor may be the image sensor 100 of FIG. The image sensor 100 receives a control signal in step S110. The control signals are provided by an image processor or electronic device. The control signal is a signal that instructs image capture in global shutter mode or a signal that instructs image capture in rolling shutter mode.

[0155] If the control signal indicates the global shutter mode in step S120, step S130 is executed, and if the control signal indicates the rolling shutter mode, step S150 is executed. In step S130, the image sensor 100 performs a signal dumping operation on the reset voltage and the pixel voltage. The pixel of the image sensor 100 may be any one of Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A. The signal dumping operation is performed by storing a first pixel voltage output by the source follower transistor in a first capacitor and storing a first reset voltage of the floating diffusion region output by the source follower transistor in a second capacitor in response to photocharges generated in a photodiode included in each of a plurality of pixels exposed to light during the same time period. The signal dumping operation can operate as shown in the timing diagrams of FIGS. 3D, 4B, 5B, 6B, 7B, 8B, 9B, and 10B.

[0156] In step S140, the image sensor 100 outputs the output of the source follower transistor to the column line in response to the first pixel voltage stored in the first capacitor and the first reset voltage stored in the second capacitor, respectively, in the rolling readout. The rolling readout operation can operate as shown in the timing diagrams of FIGS. 3D, 4B, 5B, 6B, 7B, 8B, 9B, and 10B. In step S150, if the control signal instructs imaging in multiple conversion gain modes in rolling shutter mode, the image sensor 100 executes step S160, and if the control signal instructs imaging in single conversion gain mode in rolling shutter mode, the image sensor 100 executes step S180. In step S160, the image sensor 100 selectively provides at least one capacitance of a first capacitor and a second capacitor to the floating diffusion region.

[0157] In step S170, the image sensor 100 outputs a reset voltage and a pixel voltage in a rolling readout manner while electrically isolating or coupling at least one of the first capacitor and the second capacitor to the floating diffusion region. In step S180, the image sensor 100 outputs a reset voltage and a pixel voltage in a rolling readout manner while the coupling or separation between the first capacitor, the second capacitor, and the floating diffusion region is fixed. That is, in one conversion gain mode, the reset voltage and pixel voltage are output in a rolling readout manner.

[0158] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0159] 10b, 10c, 10d 1st board 20b, 20c, 20d 2nd board 30c, 30d 3rd board 100, 100a-d, 100d1, 100d2 image sensors 110 pixel array 120 Low Driver 130 Timing Controller 140 Ramp Signal Generator 150 ADC 151 Comparator 152 Counter Circuit 160 output buffers 161 column memory blocks 162 Sense Amplifier 1000 electronic devices 1100 Imaging unit 1110 Lens 1120 Lens drive unit 1200 image sensor 1210 pixel array 1220 Timing Controller 1230 ADC 1240 Image Signal Processor 1300 processor 1300a Application Processor 1310 Image Signal Processing Device 1311~1313 Image signal processing section 1314 Camera module control unit 1315 Camera Interface 1400 external memory CP1, CP2 (first and second) capacitors FBT Feedback Transistor FD Floating diffusion region PD photodiode PSX Precharge Select Transistor PX precharge transistor PX pixels RX reset transistor SF Source Follower Transistor SX select transistor T1, T2 (first and second) transistors TX Transistor

Claims

1. With a low driver, at least one photodiode; a floating diffusion region for accumulating photocharges generated in the at least one photodiode through a transfer transistor; a reset transistor that provides a voltage at a pixel power supply terminal to the floating diffusion region based on a reset control signal; a source follower transistor that amplifies the voltage of the floating diffusion region and outputs the amplified voltage to a first node; a selection transistor connecting the first node to an output line; a second node connected to the reset transistor; a first capacitor and a second capacitor disposed on a path connecting the first node and the second node; a plurality of transistors located between the first node and the second node and connected to the first capacitor and the second capacitor, respectively; In the global shutter mode signal-dump operation, the row driver controls the plurality of transistors to store a pixel voltage in the first capacitor through the first node; storing a reset voltage in the second capacitor through the first node; In a rolling shutter mode, at least one of the first capacitor and the second capacitor is a lateral overflow integration capacitor (LOFIC) configured to store charge overflowing from the at least one photodiode.

2. 2. The image sensor of claim 1, wherein, in the readout operation of the global shutter mode, the row driver controls at least some of the plurality of transistors to transfer the reset voltage stored in the second capacitor to the floating diffusion region through the second node.

3. The image sensor of claim 1 , wherein the second node has an equipotential with the floating diffusion region.

4. 2. The image sensor of claim 1, further comprising a converting gain transistor connecting the second node and the floating diffusion region.

5. In the readout operation of the rolling shutter mode, the row driver controls at least some of the plurality of transistors so that the second capacitor is selectively electrically connected to the floating diffusion region; 2. The image sensor of claim 1, wherein the second capacitor comprises a lateral overflow storage capacitor.

6. 2. The image sensor of claim 1, wherein in the global shutter mode and the rolling shutter mode, the reset voltage or the pixel voltage stored in the floating diffusion region is amplified by the source follower transistor.

7. a precharge transistor and a precharge select transistor connected in series between the first node and ground; a feedback transistor, a first transistor, and a second transistor connected in series between the first node and the second node; the first capacitor connected to the first node through the feedback transistor; the second capacitor connected to the first node through the feedback transistor and the first transistor; The image sensor of claim 1 , further comprising: a second transistor connecting the second capacitor and the second node.

8. In the rolling shutter mode, the row driver turns off the feedback transistor and the first transistor; 8. The image sensor of claim 7, wherein in the global shutter mode, the row driver selectively turns off the feedback transistor and the first transistor.

9. In the signal dump operation of the global shutter mode, the row driver turning on the feedback transistor and the first transistor; 8. The image sensor of claim 7, wherein the second transistor is turned off to store a reset voltage in the second capacitor.

10. In the signal dump operation of the global shutter mode, the row driver turning on the feedback transistor; 10. The image sensor of claim 9, wherein the first transistor is turned off to store a pixel voltage in the first capacitor.

11. a first read transistor connecting the first capacitor and the floating diffusion region; In the readout operation of the global shutter mode, the row driver controlling the first read transistor to transfer the pixel voltage stored in the first capacitor to the floating diffusion region; 11. The image sensor of claim 10, wherein the second read transistor is controlled to transfer the reset voltage stored in the second capacitor to the floating diffusion region through the second node.

12. a precharge transistor and a precharge select transistor connected in series between the first node and ground; a first feedback transistor and a second feedback transistor connected in parallel with each other between the first node and the second node; a third transistor connected to the first capacitor and the second node; a fourth transistor connected to the second capacitor and the third node, the first capacitor is connected to the first node through the first feedback transistor; The image sensor of claim 1 , wherein the second capacitor is connected to the first node through the second feedback transistor.

13. a converting gain transistor connecting the second node and the floating diffusion region; 2. The image sensor of claim 1, wherein, during a readout operation in the global shutter mode, the row driver controls the reset transistor and the converting gain transistor to precharge the floating diffusion region before the reset voltage and the pixel voltage are transferred to the floating diffusion region.

14. a third capacitor having one end connected to a path connecting the first node and the second node and the other end connected to ground; the at least one photodiode includes a first photodiode and a second photodiode; In the signal dump operation in the global shutter mode, the row driver controls at least some of the plurality of transistors to storing a pixel voltage corresponding to photocharges generated by the first photodiode in the first capacitor; 2. The image sensor of claim 1, wherein a pixel voltage corresponding to photocharges generated in the second photodiode or photocharges generated in both the first and second photodiodes is stored in the third capacitor.

15. 15. The image sensor of claim 14, further comprising a second read transistor connecting the third capacitor and the floating diffusion region.

16. With a low driver, at least one photodiode; a floating diffusion region configured to accumulate photocharges generated in the at least one photodiode through a transfer transistor; a reset transistor that provides a voltage of a pixel power supply terminal to the floating diffusion region based on a reset control signal; a source follower transistor that amplifies the voltage of the floating diffusion region and outputs the amplified voltage to a first node; a selection transistor connecting the first node and an output line; a plurality of capacitors connected to the first node through a plurality of transistors; In a signal dump operation in a global shutter mode, the row driver controls at least some of the plurality of transistors to store a pixel voltage or a reset voltage from the floating diffusion region in the plurality of capacitors through the source follower transistor and the first node; At least one of the plurality of capacitors is a lateral overflow integration capacitor (LOFIC) configured to store charge overflowing from the at least one photodiode in a rolling shutter mode.

17. 17. The image sensor of claim 16, wherein, in a readout operation in a rolling shutter mode, the row driver controls at least some of the plurality of transistors to transfer charge that has overflowed from the at least one photodiode among the plurality of capacitors and is stored in a first capacitor to a second node connected to the reset transistor.

18. 18. The image sensor of claim 17, wherein the row driver controls a converting gain transistor to transfer the overflowed charge to the floating diffusion region.

19. 20. The image sensor of claim 18, wherein, in the readout operation of the global shutter mode, the row driver controls the reset transistor and the converting gain transistor to precharge the floating diffusion region.

20. An image sensor including: a plurality of pixels, each including a photodiode and a plurality of transistors; a row driver that supplies a control signal to each of the plurality of pixels; a timing controller that controls driving of the row driver; and a readout circuit that outputs image signals of the plurality of pixels, the image sensor stores a first pixel voltage outputted from a source follower transistor in a first capacitor in response to photocharges generated in a photodiode included in each of the plurality of pixels exposed to light during a same time period in response to a global shutter mode control signal, and stores a first reset voltage of a floating diffusion region outputted from the source follower transistor in a second capacitor; the image sensor outputs, to a column line, outputs of the source follower transistors corresponding to the first pixel voltage stored in the first capacitor and the first reset voltage stored in the second capacitor in a rolling readout from the plurality of pixels in response to the global shutter mode control signal; the image sensor outputs, as a rolling readout, a second pixel voltage outputted from a source follower transistor and a second reset voltage of the floating diffusion region outputted from the source follower transistor in response to photocharges generated in a photodiode included in each of the plurality of pixels exposed to light during at least a portion of different time periods in response to a rolling shutter mode control signal to the column line; and selectively providing the capacitance of the first capacitor or the second capacitor, in which charge overflowing from the photodiode is stored, to the floating diffusion region by a lateral overflow integration scheme in response to the rolling shutter mode control signal.

Images