Image sensor and manufacturing method thereof

Abstract

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor comprises a substrate which comprises a photodiode, a storage node and a floating diffusion region which are arranged in parallel, and the storage node is arranged between the photodiode and the floating diffusion region; the transmission tube grid electrode is arranged between the photodiode and the storage node; the reset tube grid electrode is arranged between the storage node and the floating diffusion region; the protection layer is arranged on the substrate and the grid electrode; the first dielectric layer is arranged on the protective layer; the metal shading structure is arranged in the first dielectric layer on the transmission tube grid electrode, part of the storage nodes and part of the reset tube grid electrode in a segmented manner; the second dielectric layer is arranged on the first dielectric layer and the metal shading structure; and the first metal layer is arranged on the second dielectric layer and is in negative pressure bias connection with the metal shading structure on the storage node. According to the invention, the dark current and parasitic light response of the storage node can be reduced, and the quality of the image sensor is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to an image sensor and its manufacturing method. Background Technology

[0002] CMOS image sensors (Complementary Metal Oxide Semiconductor Image Sensors, CIS) offer advantages such as high integration, low power supply voltage, and low technological barriers, leading to their widespread application in consumer electronics, autonomous driving, biometrics, and security. CMOS image sensors can employ two exposure modes: Global Shutter (GS) mode and Rolling Shutter (RS) mode. In Global Shutter mode, all pixels are exposed at the same time, starting and ending exposure simultaneously. Global Shutter CMOS image sensors are widely used for imaging high-speed moving objects, including in machine vision, industrial measurement, aerospace, and military applications.

[0003] Global shutter pixels can be categorized into two types based on the type of storage node: charge domain and voltage domain. Charge domain global shutter pixels transfer the photogenerated signal charge to the storage area for storage at the end of exposure. Voltage domain global shutter pixels, on the other hand, convert the photogenerated signal charge into voltage through a conversion node at the end of exposure and store it in a capacitor. Compared to voltage domain pixels, charge domain pixels offer advantages such as scalability, low readout noise, and low dark current. Dark current is suppressed through negative gate bias in the transmission transistor and surface P-type implants.

[0004] Dark current can be suppressed by covering the memory node with a transfer transistor and using negative gate bias. This usually requires the transfer transistor to occupy a large pixel area, which limits the full well capacity of the pixel and restricts the improvement of pixel performance. Summary of the Invention

[0005] The purpose of this invention is to provide an image sensor and its manufacturing method. The image sensor and its manufacturing method provided by this invention can save pixel area, reduce dark current and parasitic light response of storage nodes, and increase the full-well capacity of pixels.

[0006] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0007] This invention provides an image sensor, comprising at least:

[0008] A substrate, a photodiode, a storage node, and a floating diffusion region are arranged side by side within the substrate, with the storage node disposed between the photodiode and the floating diffusion region;

[0009] The gate of the transmission transistor is disposed between the photodiode and the memory node;

[0010] The reset gate is disposed between the memory node and the floating diffusion region;

[0011] A protective layer is disposed on the substrate, the gate of the transmission transistor, and the gate of the reset transistor;

[0012] A first dielectric layer is disposed on the protective layer;

[0013] A metal light-shielding structure is disposed within the first dielectric layer, and the metal light-shielding structure is segmented and disposed on the gate of the transmission transistor, part of the memory node and part of the gate of the reset transistor.

[0014] A second dielectric layer is disposed on the first dielectric layer and the metal light-shielding structure; and

[0015] A first metal layer is disposed on the second dielectric layer, and the first metal layer is negatively biased connected to the metal light-shielding structure on the storage node.

[0016] In one embodiment of the present invention, the metal light-shielding structure includes a first portion that covers the gate of the transmission tube and a portion of the photodiode.

[0017] In one embodiment of the present invention, the metal light-shielding structure includes a second portion disposed on a portion of the storage node, and the second portion and the first portion are isolated by the first dielectric layer.

[0018] In one embodiment of the present invention, the metal light-shielding structure includes a third portion, which is disposed on a portion of the gate of the reset transistor, and the third portion and the second portion are isolated by the first dielectric layer.

[0019] In one embodiment of the present invention, the first metal layer is connected to the second portion of the negative voltage bias via a connection structure.

[0020] In one embodiment of the present invention, the first metal layer at least completely covers the storage node.

[0021] In one embodiment of the present invention, the thickness of the second dielectric layer is 5 nm to 50 nm.

[0022] In one embodiment of the present invention, the gate of the transmission tube covers a portion of the storage node and a portion of the photodiode, and the width of the transmission tube gate covering the storage node is one-tenth to one-quarter of the width of the storage node.

[0023] Another object of the present invention is to provide a method for manufacturing an image sensor, comprising at least the following steps:

[0024] A substrate is provided in which a photodiode, a memory node, and a floating diffusion region are formed in parallel, the memory node being disposed between the photodiode and the floating diffusion region;

[0025] A transmission gate is formed between the photodiode and the storage node;

[0026] A reset gate is formed between the storage node and the floating diffusion region;

[0027] A protective layer is formed on the substrate, the gate of the transmission transistor, and the gate of the reset transistor;

[0028] A first dielectric layer is formed on the protective layer;

[0029] A metal light-shielding structure is formed within the first dielectric layer, and the metal light-shielding structure is segmented and disposed on the gate of the transmission transistor, part of the memory node and part of the gate of the reset transistor.

[0030] A second dielectric layer is formed on the first dielectric layer and the metal light-shielding structure; and

[0031] A first metal layer is formed on the second dielectric layer, and the first metal layer is negatively biased connected to the metal light-shielding structure on the storage node.

[0032] In one embodiment of the present invention, the method for manufacturing the metal light-shielding structure includes the following steps:

[0033] A photoresist layer is formed on the first dielectric layer, and a plurality of openings are formed at intervals on the photoresist layer;

[0034] Using the photoresist layer as a mask and the protective layer as an etch stop layer, the first dielectric layer exposed by the opening is removed to form multiple grooves;

[0035] Deposit metallic material on the groove and the first dielectric layer until the metallic material completely fills the groove;

[0036] After a planarization process, the metal material on the first dielectric layer is removed, and the metal material in the groove is retained to form the metal light-shielding structure.

[0037] In summary, this invention provides an image sensor and its fabrication method, which can reduce the size of the transmission transistor gate, apply negative voltage bias only to the metal light-shielding structure on the storage node, reduce the dark current of the storage node while saving pixel area, and increase the full-well capacity of the pixel, further expanding the scalability advantages of the charge domain pixel structure. It can block light entering the storage node, providing light protection and reducing the parasitic light response of the storage node, resulting in an image sensor with extremely low parasitic light response and improved imaging quality. It can reduce dangling bonds on the substrate surface, reduce dark current generation, and increase the depletion width, achieving a high full-well capacity, thereby improving the electrical performance of the image sensor. The first metal layer further enhances the light-shielding effect of the storage node, further reducing the parasitic light response. It can be applied to image sensors with more pixel structure variations to improve image sensor performance.

[0038] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a positioning shallow trench isolation structure in one embodiment.

[0041] Figure 2 This is a schematic diagram of a shallow trench isolation structure in one embodiment.

[0042] Figure 3 This is a schematic diagram of the distribution of multiple well regions formed in one embodiment.

[0043] Figure 4 This is a schematic diagram of the transmission transistor gate and the reset transistor gate in one embodiment.

[0044] Figure 5 This is a schematic diagram of the sidewall structure and protective layer in one embodiment.

[0045] Figure 6 This is a schematic diagram of the formation of a first dielectric layer and a photoresist layer in one embodiment.

[0046] Figure 7 This is a schematic diagram showing the distribution of multiple grooves in one embodiment.

[0047] Figure 8This is a schematic diagram of a metal light-shielding structure formed in one embodiment.

[0048] Figure 9 This is a schematic diagram of an image sensor in one embodiment.

[0049] Label Explanation:

[0050] 10. Substrate; 11. Pad oxide layer; 12. Pad nitride layer; 13. First photoresist layer; 131. Recess; 14. Shallow trench isolation structure; 151. First isolation well region; 152. Second isolation well region; 16. First well region; 17. Second well region; 18. First pinning layer; 19. Memory node; 20. Second pinning layer; 21. Floating diffusion region; 22. Gate dielectric layer; 23. Transmission gate; 24. Reset gate; 25. Side 26. Wall structure; 27. Protective layer; 28. First dielectric layer; 29. ​​Photoresist layer; 20. First opening; 21. Second opening; 22. Third opening; 23. First groove; 24. Second groove; 25. Third groove; 26. Metal light-shielding structure; 27. First dielectric layer; 28. Second dielectric layer; 29. ​​Third dielectric layer; 20. Third dielectric layer; 21. Second dielectric layer; 22. Third dielectric layer; 33. Connecting structure; 34. First metal layer. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0054] Please see Figures 8 to 9 As shown, this invention provides an image sensor, such as a charge-domain global shutter image sensor, comprising at least a photodiode, a storage node 19, and a floating diffusion region 21. The storage node 19 is disposed between the photodiode region and the floating diffusion region 21. A transmission gate 23 is disposed between the photodiode and the storage node 19, covering a portion of the photodiode and the storage node 19. A reset gate 24 is disposed between the storage node 19 and the floating diffusion region 21. Metal light-shielding structures 30 are disposed on the transmission gate 23, the storage node 19, and a portion of the floating diffusion region 21. The metal light-shielding structures 30 are segmented, with the metal light-shielding structures 30 on the storage node 19 spaced apart from those on other regions. The metal light-shielding structures 30 on the storage node 19 are then connected to a first metal layer 34 for negative voltage bias. This allows for a reduction in the size of the transmission gate 23, saving pixel area, reducing the dark current of the storage node 19, and increasing the full-well capacity of the pixel, further expanding the scalability advantages of the charge-domain pixel structure. This application does not limit the pixel structure of the image sensor, such as a 6T or 8T structure. The present invention also provides a method for manufacturing an image sensor, which, in this embodiment, is illustrated, for example, along a cross-section of the photodiode, storage node 19, and floating diffusion region 21.

[0055] Please see Figure 1 As shown, in one embodiment of the present invention, a substrate 10 is first provided. The substrate 10 can be any suitable semiconductor material, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or a silicon wafer, etc. It also includes a stacked structure composed of these semiconductors, or silicon-on-insulator, silicon-on-insulator stacked on insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator, etc., specifically selected according to the fabrication requirements of the image sensor. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, or, for example, a P-type substrate.

[0056] Please see Figure 1As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10. The pad oxide layer 11 is, for example, a dense silicon oxide material, and can be formed on the substrate 10 by methods such as thermal oxidation or in-situ vapor growth. In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced into the furnace tube. The substrate 10 reacts with oxygen at a high temperature to generate a dense pad oxide layer 11, and the thickness of the pad oxide layer 11 is, for example, 10 nm to 30 nm. After the pad oxide layer 11 is formed, a pad nitride layer 12 is formed on the pad oxide layer 11. The pad nitride layer 12 is, for example, silicon nitride or a mixed layer of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride. The pad oxide layer 11 serves as a buffer layer to improve the stress between the substrate 10 and the pad nitride layer 12. In this invention, the pad nitride layer 12 can be formed on the pad oxide layer 11 by methods such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the thickness of the pad nitride layer 12 is, for example, 50 nm to 150 nm, or, for example, 110 nm.

[0057] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, a first photoresist layer 13 is formed on the pad nitride layer 12. Multiple recesses 131 are formed on the first photoresist layer 13 through processes such as exposure and development to locate the shallow trench isolation structure. Using the first photoresist layer 13 as a mask, the pad nitride layer 12 exposed in the recesses 131 is quantitatively removed using etching methods such as dry etching, wet etching, or a combination of both. Then, using the pad nitride layer 12 as a mask, the pad oxide layer 11 and part of the substrate 10 are removed in situ to obtain the shallow trench. In this embodiment, for example, dry etching is used to form the shallow trench, and the etching gas is, for example, one or a combination of several of the following: chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hydrogen bromide (HBr), or oxygen (O2). After etching, wet etching is used to clean the etching byproducts.

[0058] Please see Figures 1 to 2As shown, in one embodiment of the present invention, after forming shallow trenches, an isolation medium is deposited within the shallow trenches, for example, by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD), and the isolation medium is, for example, an insulating material such as silicon oxide. After the isolation medium deposition is completed, a planarization process, such as chemical mechanical polishing (CMP), is used to bring the top of the isolation medium and the pad nitride layer 12 to the same plane, and the pad nitride layer 12 on the substrate 10 is removed to form multiple shallow trench isolation structures 14. The pad nitride layer 12 is removed, for example, by a wet etching process, and the wet etching solution is, for example, hot phosphoric acid. By setting multiple shallow trench isolation structures 14, photodiodes or other semiconductor devices are isolated from each other. The shallow trench isolation structures 14 isolate multiple photodiodes in the image sensor from other semiconductor devices, reducing mutual interference between semiconductor devices and improving the performance of the image sensor.

[0059] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 14, the pad oxide layer 11 is used as an ion implantation buffer layer to perform ion implantation into the substrate, forming multiple well regions. A patterned photoresist layer (not shown) is used as a mask to form isolation well regions around and between the shallow trench isolation structures 14. The isolation well regions include a first isolation well region 151 and a second isolation well region 152. The first isolation well region 151 surrounds the shallow trench isolation structure 14, and the second isolation well regions 152 are spaced apart within the substrate 10 between the first isolation well regions 151. In this embodiment, the impurity ions in the isolation well regions are, for example, P-type impurities such as boron (B), and the doping concentration is greater than the doping concentration of the substrate 10. The first isolation well region 151 is used to prevent the depletion region of the photodiode from widening towards the interface of the shallow trench isolation structure, reducing dark current caused by interface defects. The second isolation well region 152 is used to form the storage region.

[0060] Please see Figure 3As shown, in one embodiment of the present invention, after forming the isolation well region, a new patterned photoresist layer (not shown) is formed on the substrate 10. Using the patterned photoresist layer as a mask and the pad oxide layer 11 as an ion implantation buffer layer, first-type impurity ions are implanted to form a first well region 16. The first well region 16 is in contact with the first isolation well region 151 on one side, and the other side is at a predetermined distance from the second isolation well region 152. Second-type impurity ions are implanted into the first well region 16 with a low implantation energy to form a second well region 17. Due to the different implantation energy, the second well region 17 is formed on the first well region 16, meaning the depth of the first well region 16 is greater than the depth of the second well region 17. The widths of the first well region 16 and the second well region 17 are equal, and the first well region 16 and the second well region 17 constitute a photodiode. The depth of the first well region 16 is less than or equal to the depth of the first isolation well region 151, and the depth of the second well region 17 is, for example, one-hundredth to one-fiftieth of the depth of the first well region 16. In this embodiment, the first type of impurity ions and the second type of impurity ions are of different types. The first type of impurity ions are, for example, N-type impurities such as phosphorus (P) or arsenic (As), while the second type of impurity ions are, for example, P-type impurities such as boron (B). That is, the doping types of the first well region 16 and the second well region 17 are different. In other embodiments, the first type of impurity ions can also be P-type impurities, and the second type of impurity ions can be N-type impurities, which can be selected according to the fabrication requirements of the image sensor. In this embodiment, the doping concentration of the formed second well region 17 is ensured to be greater than the doping concentration of the first well region 16, forming a built-in electric field pointing from the first well region 16 to the second well region 17. By setting a high-doped second well region 17, the depletion region of the first well region 16 is prevented from widening towards the surface of the substrate 10, reducing the dark current caused by dangling bonds on the substrate 10 surface.

[0061] Please see Figure 3 As shown, in one embodiment of the present invention, after forming the second well region 17, a new patterned photoresist layer (not shown) is formed on the substrate 10. Using the patterned photoresist layer as a mask and the pad oxide layer 11 as an ion implantation buffer layer, first-type impurity ions, such as N-type impurities like phosphorus or arsenic, are implanted into the second isolation well region 152 to form a storage node 19 to store the formed charge signal. In this embodiment, the width and depth of the storage node 19 are smaller than the width and depth of the second isolation well region 152, respectively. The patterned photoresist layer is removed, and a new patterned photoresist layer is formed on the substrate 10 to implant impurity ions at a low implantation energy on one side of the second isolation well region 152 opposite to the second well region 17, forming a floating diffusion region 21. The ion implantation type of the floating diffusion region 21 is the same as that of the first well region 16, and the ion implantation depth of the floating diffusion region 21 is on the same order of magnitude as that of the second well region 17. One side of the floating diffusion zone 21 is in contact with the first isolation trap zone 151, and the other side is at a predetermined distance from the second isolation trap zone 152.

[0062] Please see Figure 3 As shown, in one embodiment of the present invention, after forming the floating diffusion region 21, pinning layers are formed on the second well region 17 and the storage node 19. For example, the second well region 17 is defined as the first pinning layer 18, and the storage node 19 is defined as the second pinning layer 20. One side of the first pinning layer 18 is in contact with the first isolation well region 151, and the other side is not aligned with the second well region 17. One side of the second pinning layer 20 is aligned with the storage node 19, and the other side is not aligned with the storage node 19. The doping ions of the pinning layers are, for example, p-type impurities such as boron, and the doping concentration of the pinning layers is greater than the doping concentration of the substrate 10 and less than the doping concentration of the second well region 17. The well region formation steps provided in this embodiment are specific formation steps in one embodiment. In other embodiments, the formation steps of multiple well regions can be adjusted according to the fabrication requirements. By forming pinning layers, dangling bonds on the substrate surface are reduced, dark current generation is reduced, and the depletion width can be increased to achieve a high full-well capacity, thereby improving the electrical performance of the CMOS image sensor.

[0063] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after forming multiple well regions, the pad oxide layer 11 on the surface of the substrate 10 is removed, and a gate dielectric layer 22 of 5nm to 10nm is regrown. The pad oxide layer 11 is removed, for example, by wet etching, and the wet etching solution is, for example, hydrofluoric acid or buffered oxide etch (BOE). In other embodiments, other methods can also be used for removal. The gate dielectric layer 22 is, for example, a silicon oxide layer, and the gate dielectric layer 22 is formed, for example, by chemical vapor deposition, thermal oxidation, or in-situ water vapor growth. After forming the gate dielectric layer 22, by etching, only the gate dielectric layer 22 on the memory node 19 and on the substrates on both sides is retained. In this embodiment, one side of the gate dielectric layer 22 is aligned with the side of the floating diffusion region 21 away from the first isolation well region 151, and the other side of the gate dielectric layer 22 is located on the second well region 17, at a predetermined distance from the first pinning layer 18. By removing the pad oxide layer 11 and reforming the gate dielectric layer 22, the quality of the gate dielectric layer 22 is improved, thereby improving the quality of the image sensor.

[0064] Please see Figures 3 to 4As shown, in one embodiment of the present invention, after forming the gate dielectric layer 22, a plurality of gates, such as the transmission gate 23 and the reset gate 24, are formed on the gate dielectric layer 22 to form the transmission transistor and the reset transistor. Specifically, a gate material layer (not shown in the figure) is formed on the gate dielectric layer 22, such as polysilicon or a metal material, wherein the polysilicon is a heavily doped polysilicon layer, and the metal material can be magnesium, aluminum, nickel, copper, gold, silver, TiAl-based alloy, titanium carbide, tantalum carbide, or tungsten silicide, or an alloy of several materials. After forming the gate material layer, a patterned photoresist layer (not shown in the figure) is formed on the gate material layer. Using the patterned photoresist layer as a mask, the gate material layer is etched, for example, by dry etching, to form the transmission gate 23 and the reset gate 24. The transmission gate 23 is located between the photodiode and the storage node 19, covering part of the storage node 19 and part of the photodiode, and one side of the transmission gate 23 is aligned with one edge of the gate dielectric layer 22. The transmission gate 23 covers a width of the memory node 19, for example, one-tenth to one-quarter of the width of the memory node 19. The reset gate 24 is located between the memory node 19 and the floating diffusion region 21, and its sides are aligned with the edges of the memory node 19 and the floating diffusion region 21. In this application, the size of the formed transmission gate 23 is small, which allows for scalability of the pixel area for different products and makes it suitable for image sensors with different structures.

[0065] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, after the gate is formed, sidewall structures 25 are formed on both sides of the gate. Specifically, sidewall dielectric layers (not shown in the figure) are formed on the gate, the shallow trench isolation structure 14, and the gate dielectric layer 22. The material of the sidewall dielectric layer is, for example, a silicon oxide and silicon nitride stacked material, and the contact layer with the substrate 10 and the gate is silicon oxide. After the sidewall dielectric layers are formed, the sidewall dielectric layers on the gate, the shallow trench isolation structure 14, and part of the substrate 10 can be removed by etching processes such as dry etching, leaving the sidewall dielectric layers on both sides of the transmission transistor gate 23 and the reset transistor gate 24, thus forming the sidewall structure 25. The height of the sidewall structure 25 is the same as the height of the gate, and the shape of the sidewall structure 25 is, for example, rectangular, arc-shaped, or L-shaped. After forming the sidewall structure 25, a protective layer 26 is formed on the substrate. The protective layer 26 covers the substrate 10, the shallow trench isolation structure 14, the top and sidewalls of the gate, and the gate dielectric layer 22. The protective layer 26 is, for example, a silicon nitride layer with a thickness of, for example, 5 nm to 20 nm, and is formed, for example, by chemical vapor deposition or physical vapor deposition (PVD).

[0066] Please see Figures 5 to 6As shown, in one embodiment of the present invention, after forming the protective layer 26, a first dielectric layer 27 is formed on the protective layer 26. The first dielectric layer 27 is, for example, silicon oxide, and is obtained by methods such as chemical vapor deposition. The first dielectric layer 27 protrudes and covers the gate. In other embodiments, the first dielectric layer 27 is, for example, a material such as silicon fluoride (SiF), silicon carbide (SiOC), or silicon fluoride oxyfluoride (SiOF), and the present invention does not impose specific limitations. After forming the first dielectric layer 27, the first dielectric layer 27 is planarized, for example, by using chemical mechanical polishing (CMP) to planarize the first dielectric layer 27 so that the surface of the first dielectric layer 27 is flush. A photoresist layer 28 is then formed on the first dielectric layer 27. After exposure and development processes, the photoresist layer 28 has a first opening 281, a second opening 282, and a third opening 283. The first opening 281 exposes the first dielectric layer 27 on the gate 23 of the transmission transistor and the portion of the first dielectric layer 27 near the photodiode. The second opening 282 exposes a portion of the first dielectric layer 27 on the memory node 19. The edge of the second opening 282 is at a preset distance from the opposite sides of the gate 23 of the transmission transistor and the gate 24 of the reset transistor. The third opening 283 exposes a portion of the first dielectric layer 27 on the gate 24 of the reset transistor.

[0067] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after the photoresist layer 28 is formed, the first dielectric layer 27 is etched using the photoresist layer 28 as a mask and the protective layer 26 as an etch stop layer to form multiple grooves. Specifically, the first dielectric layer 27 exposed by the first opening 281 is removed to form the first groove 291; the first dielectric layer 27 exposed by the second opening 282 is removed to form the second groove 292; and the first dielectric layer 27 exposed by the third opening 283 is removed to form the third groove 293. On the memory node 19, a portion of the first dielectric layer 27 is retained near the edges of the transmission gate 23 and the reset gate 24. When removing the first dielectric layer 27, dry etching, wet etching, or a combination of both can be used, depending on the specific process and fabrication requirements.

[0068] Please see Figures 6 to 7As shown, in one embodiment of the present invention, after the photoresist layer 28 is formed, the first dielectric layer 27 is etched using the photoresist layer 28 as a mask and the protective layer 26 as an etch stop layer to form multiple grooves. Specifically, the first dielectric layer 27 exposed by the first opening 281 is removed to form a first groove 291; the first dielectric layer 27 exposed by the second opening 282 is removed to form a second groove 292; and the first dielectric layer 27 exposed by the third opening 283 is removed to form a third groove 293. On the memory node 19, a portion of the first dielectric layer 27 is retained near the edges of the transmission gate 23 and the reset gate 24. When removing the first dielectric layer 27, dry etching, wet etching, or a combination of both can be used. In this embodiment, dry etching is used, for example.

[0069] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, after forming the groove, a metal material is deposited in the groove and on the first dielectric layer 27 until the metal material completely fills the groove. Then, a planarization process such as chemical mechanical polishing is performed to remove the metal material on the first dielectric layer 27, leaving the metal material in the groove to form a metal light-shielding structure 30. The metal material is, for example, at least one of opaque metal materials such as titanium, titanium nitride, tungsten, aluminum, copper, cobalt, or nickel. The metal material is formed, for example, by plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), or physical vapor deposition.

[0070] Please see Figures 7 to 8As shown, in one embodiment of the present invention, the metal light-shielding structure 30 is segmented, comprising a first portion 301, a second portion 302, and a third portion 303. The first portion 301 is formed within a first groove 291, covering the transmission tube gate 23 and a portion of the photodiode. The second portion 302 is formed within a second groove 292, covering a portion of the storage node 19. The third portion 303 is formed within a third groove 293, covering a portion of the floating diffusion region 21. On the storage node 19, a portion of a first dielectric layer exists on both sides of the second portion 302 to isolate the metal light-shielding structure on the storage node 19 from the metal light-shielding structure on the gate. The dimensions of the first dielectric layers 27 on both sides of the second portion 302 are not specified in this application; electrical insulation is sufficient. By setting up a metal light-shielding structure, light entering the storage node can be blocked, thus protecting the storage node from light and reducing the parasitic light response of the storage node. This results in an image sensor with extremely low parasitic light response, improving the image quality of the image sensor.

[0071] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the metal light-shielding structure 30, a subsequent metal connection layer is fabricated, at least the first metal layer 34 is connected to the second portion 302 of the metal light-shielding structure 30. Specifically, a second dielectric layer 31 is formed on the metal light-shielding structure 30 and the first dielectric layer 27. The second dielectric layer 31 is, for example, made of materials such as silicon fluoride, silicon carbide, or silicon oxyfluoride, and is formed, for example, by chemical vapor deposition. The present invention does not impose specific limitations on the material and deposition method of the second dielectric layer 31. The second dielectric layer 31 is then etched to form a contact hole on the storage node 19. Metal material is deposited in the contact hole and the second dielectric layer 31, and after grinding and etching, the first metal layer 34 and the connection structure 33 are formed. The metal material is, for example, at least one of tungsten, aluminum, or copper, and is formed, for example, by plasma-enhanced chemical vapor deposition, atomic layer deposition, metal-organic vapor deposition, or physical vapor deposition. The connection structure 33 is disposed on the second part 302, connecting the second part 302 and the first metal layer 34, wherein the first metal layer 34 at least completely covers the storage node 19.

[0072] Please see Figures 8 to 9As shown, in one embodiment of the present invention, the first metal layer 34 completely covers the memory node 19 and extends to both sides to the edge of the transmission gate 23 and the reset gate 24. The second dielectric layer 31 has a relatively small thickness, for example, 5nm to 50nm, resulting in a relatively small thickness of the connection structure 33. Therefore, the distance between the first metal layer 34 and the metal light-shielding structure 30 is shortened, enhancing the light-shielding effect of the memory node 19, thereby further reducing the parasitic light response of the memory node and improving the imaging quality of the image sensor. This application does not limit the thickness of the connection structure 33, as long as it meets the fabrication requirements. In a specific embodiment of this application, the thickness of the connection structure 33 is, for example, 5nm to 50nm.

[0073] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, the first metal layer 34 is connected to a negative voltage to negatively bias the storage node 19. Compared to negatively biasing the gate 23 of the transmission transistor, this avoids the gate 23 occupying a large pixel space and avoids further P-type injection processes between the gate 23 and the gate 24 of the reset transistor. In other words, this application uses a segmented metal light-shielding structure 30 to negatively bias the second portion 302 on the storage node 19, which reduces the area of ​​the gate 23 of the transmission transistor. This saves pixel area, reduces the dark current of the storage node 19, and increases the full-well capacity of the pixel, further expanding the scalability advantages of the charge domain pixel structure. Therefore, the metal light-shielding structure 30 has a wide range of applications and can be used in CMOS image sensors with more pixel structure variations to improve the performance of CMOS image sensors.

[0074] Please see Figures 8 to 9 As shown, in one embodiment of the present invention, after forming the first metal layer 34, a third dielectric layer 32 is formed on the first metal layer 34 and the second dielectric layer 31. The third dielectric layer 32 is, for example, made of materials such as silicon fluoride, silicon carbide, or silicon oxyfluoride, and is formed, for example, by chemical vapor deposition. The third dielectric layer 32 may be made of the same material as the second dielectric layer or a different material. After forming the third dielectric layer, subsequent processes such as metal layer fabrication, filtering, or microlens fabrication are performed, which will not be elaborated here.

[0075] In summary, this invention provides an image sensor and its fabrication method. By improving the image sensor, the size of the transmission transistor gate can be reduced, and negative voltage bias is applied only to the metal light-shielding structure on the storage node. This saves pixel area, reduces the dark current of the storage node, and increases the full-well capacity of the pixel, further expanding the scalability advantages of the charge domain pixel structure. It can block light entering the storage node, providing light protection and reducing the parasitic light response of the storage node, resulting in an image sensor with extremely low parasitic light response and improved imaging quality. It can reduce dangling bonds on the substrate surface, reducing dark current generation and increasing the depletion width, achieving a high full-well capacity, thereby improving the electrical performance of the image sensor. The first metal layer further enhances the light-shielding effect of the storage node, further reducing the parasitic light response. It can be applied to image sensors with more pixel structure variations to improve image sensor performance.

[0076] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An image sensor, characterized in that, At least including: A substrate, a photodiode, a storage node, and a floating diffusion region are arranged side by side within the substrate, with the storage node disposed between the photodiode and the floating diffusion region; The gate of the transmission transistor is disposed between the photodiode and the memory node; The reset gate is disposed between the memory node and the floating diffusion region; A protective layer is disposed on the substrate, the gate of the transmission transistor, and the gate of the reset transistor; A first dielectric layer is disposed on the protective layer; A metal light-shielding structure is disposed within the first dielectric layer, and the metal light-shielding structure is segmented and disposed on the gate of the transmission transistor, part of the memory node and part of the gate of the reset transistor. A second dielectric layer is disposed on the first dielectric layer and the metal light-shielding structure; as well as A first metal layer is disposed on the second dielectric layer, and the first metal layer is negatively biased connected to the metal light-shielding structure on the storage node.

2. The image sensor according to claim 1, characterized in that, The metal light-shielding structure includes a first portion that covers the gate of the transmission tube and a portion of the photodiode.

3. The image sensor according to claim 2, characterized in that, The metal light-shielding structure includes a second portion disposed on a portion of the storage node, and the second portion and the first portion are isolated from each other by the first dielectric layer.

4. The image sensor according to claim 3, characterized in that, The metal light-shielding structure includes a third portion disposed on a portion of the gate of the reset transistor, and the third portion and the second portion are isolated by the first dielectric layer.

5. The image sensor according to claim 3, characterized in that, The first metal layer is connected to the second portion under negative voltage bias via a connection structure.

6. The image sensor according to claim 1, characterized in that, The first metal layer at least completely covers the storage node.

7. The image sensor according to claim 1, characterized in that, The thickness of the second dielectric layer is 5 nm to 50 nm.

8. The image sensor according to claim 1, characterized in that, The gate of the transmission tube covers a portion of the memory node and a portion of the photodiode on both sides, and the width of the transmission tube gate covering the memory node is one-tenth to one-quarter of the width of the memory node.

9. A method for manufacturing an image sensor, characterized in that, At least the following steps are included: A substrate is provided in which a photodiode, a memory node, and a floating diffusion region are formed in parallel, the memory node being disposed between the photodiode and the floating diffusion region; A transmission gate is formed between the photodiode and the storage node; A reset gate is formed between the storage node and the floating diffusion region; A protective layer is formed on the substrate, the gate of the transmission transistor, and the gate of the reset transistor; A first dielectric layer is formed on the protective layer; A metal light-shielding structure is formed within the first dielectric layer, and the metal light-shielding structure is segmented and disposed on the gate of the transmission transistor, part of the memory node and part of the gate of the reset transistor. A second dielectric layer is formed on the first dielectric layer and the metal light-shielding structure; as well as A first metal layer is formed on the second dielectric layer, and the first metal layer is negatively biased connected to the metal light-shielding structure on the storage node.

10. The method for manufacturing an image sensor according to claim 9, characterized in that, The method for manufacturing the metal light-shielding structure includes the following steps: A photoresist layer is formed on the first dielectric layer, and a plurality of openings are formed at intervals on the photoresist layer; Using the photoresist layer as a mask and the protective layer as an etch stop layer, the first dielectric layer exposed by the opening is removed to form multiple grooves; Deposit metallic material on the groove and the first dielectric layer until the metallic material completely fills the groove; After a planarization process, the metal material on the first dielectric layer is removed, and the metal material in the groove is retained to form the metal light-shielding structure.

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