Imaging unit and imaging apparatus

Abstract

To densely provide photoelectric converters in an imager comprising a differential comparator for comparing a reference level with the signal level of an analog image signal.SOLUTION: An imaging unit comprises: the imager which comprises a pixel part including the plural photoelectric converters; a signal processor for processing a digital signal outputted from the imager; and the differential comparator which is disposed in the imager, compares the reference level with the signal level of an output signal generated in accordance with an electric charge amount photoelectrically converted by the pixel part, and outputs a digital signal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an imaging unit and an imaging device.

[0002] Conventionally, a digital pixel sensor chip has been provided with a sensor section including a photodiode, a comparison section that compares an output signal from the sensor section with a lamp voltage, and a memory section that records the output from the comparison section (see, for example, Non-Patent Document 1). [Prior art document] [Patent documents] [Non-Patent Document 1] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001,A 10000 Frames / s CMOS Digital Pixel Sensor,Stuart Kleinfelder,SukHwan Lim,Xinqiao Liu,and Abbas El Gamal,Fellow,IEEE Summary of the Invention [Problem to be solved by the invention]

[0003] In the digital pixel sensor chip described above, each pixel has a comparison section and a memory section in addition to a sensor section. Therefore, one pixel is composed of a large number of transistors. Therefore, it is difficult to provide high-density pixels in the digital pixel sensor chip. [Means for solving the problem]

[0004] In a first aspect of the present invention, an imaging unit is provided that includes an imaging section having a pixel section including a plurality of photoelectric conversion sections, a signal processing section that processes a digital signal output from the imaging section, and a differential comparator that is arranged in the imaging section and compares a reference level with the signal level of an output signal generated in accordance with the amount of charge photoelectrically converted in the pixel section, and outputs a digital signal.

[0005] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 4 is a cross-sectional view of a single-lens reflex camera 400. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of an imaging unit 200. [Figure 3] 2 is a circuit schematic diagram of a pixel section 11 and a signal processing circuit 22 of an imaging unit 200 in the first embodiment. FIG. [Figure 4] 4 is a time chart illustrating the operation of the imaging unit 200. FIG. [Figure 5] FIG. 2 is a diagram showing an element layout of a pixel section 11. [Figure 6] 2 is a diagram showing the positional relationship between a photoelectric conversion unit 31, a photoelectric conversion unit 33, and a microlens 50 in a pixel unit 11. FIG. [Figure 7] 10A and 10B are diagrams showing modified examples of the positional relationship between the photoelectric conversion units 31 and 33 and the microlens 50 in the pixel unit 11. FIG. [Figure 8] FIG. 10 is a schematic circuit diagram of a pixel section 12 and a signal processing circuit 22 of an imaging unit 300 in a second embodiment. [Figure 9] FIG. 10 is a time chart illustrating the operation of the imaging unit 300 in the second embodiment. [Figure 10] FIG. 11 is a circuit schematic diagram of a pixel section 13 and a signal processing circuit 22 of an imaging unit 310 in the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] 1 is a cross-sectional view of a single-lens reflex camera 400. The single-lens reflex camera 400, which is an example of an imaging device, includes an imaging unit 200, a lens unit 500, and a camera body 600. The lens unit 500 is attached to the camera body 600. The lens unit 500 includes an optical system arranged along an optical axis 410 within its lens barrel, and guides an incident subject light beam to the imaging unit 200 in the camera body 600.

[0009] In this example, a single-lens reflex camera 400 is used as the imaging device, but the camera body 600 may also be considered the imaging device. The imaging device is not limited to an interchangeable-lens camera equipped with a mirror unit, but may also be an interchangeable-lens camera without a mirror unit, or an integrated-lens camera with or without a mirror unit. In this example, the direction in which the subject light beam travels along the optical axis 410 is referred to as the third direction. Directions perpendicular to the third direction and perpendicular to each other are referred to as the first direction and the second direction.

[0010] Lens mount 550 is coupled to camera body 600. Camera body 600 includes mirror 672 on the third direction side of body mount 660. Mirror 672 is fixed to an axis so as to be rotatable between an oblique position where it is tilted with respect to the subject light beam incident from lens unit 500 in the third direction, and a retracted position where it is retracted from the subject light beam.

[0011] When mirror 672 is in the oblique position, most of the subject light beam incident through lens unit 500 is reflected by mirror 672 and directed to focusing screen 652. Focusing screen 652 is disposed at a position conjugate with the light receiving surface of imaging unit 200, and visualizes the subject image formed by the optical system of lens unit 500. The subject image formed on focusing screen 652 is observed through viewfinder 650 via pentaprism 654 and viewfinder optical system 656.

[0012] The focusing screen 652, the pentaprism 654, and the mirror 672 are supported by a structural body, that is, a mirror box 670. The imaging unit 200 is attached to the mirror box 670. When the mirror 672 is retracted to the retracted position and the front and rear curtains of the shutter unit 340 are opened, the subject light beam that passes through the lens unit 500 reaches the light receiving surface of the imaging unit 200.

[0013] A body substrate 620 and a rear display unit 634 are arranged in this order on the opposite side of the imaging unit 200 from the shutter unit 340. The rear display unit 634, which employs a liquid crystal panel or the like, is located on the rear side of the camera body 600. Electronic circuits such as a CPU 622 and an image processing unit 624 are mounted on the body substrate 620. The output of the imaging unit 200 is passed to the image processing unit 624.

[0014] 2 is a block diagram showing an example configuration of an imaging unit 200. The imaging unit 200 includes an imaging section 10 and a signal processing section 20. The imaging section 10 may be a chip having the functions of the imaging section 10, and the signal processing section 20 may be a chip having the functions of the signal processing section 20. A light beam is incident on the imaging section 10 from a third direction. The imaging section 10 and the signal processing section 20 are provided so as to at least partially overlap in the direction of the optical axis 410. In this example, the entire imaging section 10 is provided so as to almost completely overlap the signal processing section 20. The imaging section 10 and the signal processing section 20 are electrically connected to each other via bumps 15.

[0015] The imaging unit 10 has a pixel unit 11. The pixel unit 11 has a plurality of photoelectric conversion units arranged two-dimensionally in a first direction and a second direction. Each of the plurality of photoelectric conversion units photoelectrically converts incident light. That is, each of the plurality of photoelectric conversion units generates an electric charge according to the amount of light of a light beam incident from a third direction. Therefore, the pixel unit 11 generates an analog image signal according to the amount of the photoelectrically converted electric charge. Furthermore, the pixel unit 11 converts the analog image signal into a digital signal. Thereafter, the pixel unit 11 outputs the converted digital signal to the signal processing circuit 22 of the signal processing unit 20.

[0016] The signal processing unit 20 has a signal processing circuit 22 and a focus detection unit 26. The signal processing circuit 22 processes digital signals. The signal processing circuit 22 includes a latch unit 24. The latch unit 24 has a counter circuit. The latch unit 24 counts the digital signals output from the imaging unit 10 using the counter circuit, thereby generating pixel values ​​corresponding to the analog image signals. The generated pixel values ​​are output from the latch unit 24 to the focus detection unit 26 and the image processing unit 624.

[0017] The focus detection unit 26 detects the focal position of the optical system through which incident light has passed. Specifically, the focus detection unit 26 detects the amount of image misalignment between a pair of images based on digital image signals. Furthermore, the focus detection unit 26 performs calculations according to the amount of image misalignment to calculate the amount of defocus, which is the deviation of the current imaging plane from the planned imaging plane. To adjust the amount of defocus, the position of the lens within the lens unit 500 of the single-lens reflex camera 400 is adjusted.

[0018] The image processing unit 624 has an image processing ASIC 625 and a recording unit 626. The image processing ASIC 625 performs various image processes using the recording unit 626 as a workspace to generate image data. When generating image data in JPEG file format, the image processing ASIC 625 performs white balance processing, gamma processing, etc., and then executes compression processing. The generated image data is recorded in the recording unit 626. In addition, the rear display unit 634 displays an image corresponding to the image data recorded in the recording unit 626 for a preset time.

[0019] 3 is a circuit schematic diagram of the pixel section 11 and signal processing circuit 22 of the imaging unit 200 in the first embodiment. In this example, unless otherwise specified, each transistor is an n-type MOS transistor. Of the two terminals other than the gate of an n-type MOS transistor, the high-potential terminal is referred to as the drain, and the low-potential terminal is referred to as the source. In contrast, of the two terminals other than the gate of a p-type MOS transistor, the high-potential terminal is referred to as the source, and the low-potential terminal is referred to as the drain.

[0020] First, the configurations of the pixel section 11 and the signal processing circuit 22 will be described. The pixel section 11 has a plurality of pixel sharing sections 48. Note that while Fig. 3 only shows a first pixel sharing section 48-1 and a second pixel sharing section 48-2 that are adjacent in the second direction, a plurality of pixel sharing sections 48 are provided in the first and second directions. A common voltage VDD is applied to each pixel sharing section 48.

[0021] One pixel shared unit 48 includes first to fourth photoelectric conversion units 31-L, 31-R, 33-L, and 33-R, first to fourth transfer transistors 32-L, 32-R, 34-L, and 34-R, first and second switching transistors 38-L and 38-R, and a differential comparator 49. In this example, the pixel unit 11 in the imaging unit 10 includes the differential comparator 49. That is, the imaging unit 10 and the differential comparator 49 are provided on the same semiconductor chip. As described above, the signal processing circuit 22 includes the latch unit 24 and the signal source 25, and the latch unit 24 includes multiple counter circuits 28.

[0022] A common terminal Tx1_L is connected to the gates of the first transfer transistors 32-L in the first pixel shared portion 48-1 and the second pixel shared portion 48-2. Similarly, a common terminal Tx1_R is connected to the gates of the second transfer transistors 32-R in the first pixel shared portion 48-1 and the second pixel shared portion 48-2. Furthermore, a common terminal Tx2_R is connected to the gates of the third transfer transistors 34-L, and a common terminal Tx2_L is connected to the gates of the fourth transfer transistors 34-R.

[0023] Furthermore, in the other multiple pixel shared units 48 consecutive in the second direction, a common terminal Tx1_L is connected to the gate of the first transfer transistor 32-L, a common terminal Tx1_R is connected to the gate of the second transfer transistor 32-R, a common terminal Tx2_L is connected to the gate of the third transfer transistor 34-L, and a common terminal Tx2_R is connected to the gate of the fourth transfer transistor 34-R. Note that different terminals Tx1_L, Tx1_R, Tx2_L, and Tx2_R are provided in rows different from the rows in which the first pixel shared unit 48-1 and the second pixel shared unit 48-2 are located.

[0024] Furthermore, the latch unit 24 has a set of counter circuits 28 corresponding to a plurality of pixel sharing units 48 that are continuous in the second direction. FIG. 3 shows counter circuits 28-1 to 28-4 that make up the set of counter circuits 28. Counter circuit 28-1 is connected to the second output unit 44, and counter circuit 28-2 is connected to the first output unit 43. Two counter circuits 28 are provided for one pixel sharing unit 48. The latch unit 24 has a plurality of counter circuits 28 that are different from the set of counter circuits 28 described above, corresponding to rows that are different from the rows in which the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located.

[0025] The differential comparator 49 includes a first input section 41, a second input section 42, a first output section 43, and a second output section 44. The differential comparator 49 includes a transistor 35-L, whose gate is connected to the first input section 41, and a transistor 35-R, whose gate is connected to the second input section 42. The sources of the transistors 35-L and 35-R are shorted and connected to the drain of the transistor 30. The source of the transistor 30 is connected to a constant current source. The constant current source connected to the source of the transistor 30 is a constant current source that determines the current flowing through the differential comparator 49.

[0026] The differential comparator 49 includes p-type transistors 36-L and 36-R. A voltage VDD is applied to the sources of the p-type transistors 36-L and 36-R. The gates of the p-type transistors 36-L and 36-R are shorted together and connected to the drain of the p-type transistor 39. The p-type transistors 36-L and 36-R function as loads for the differential comparator 49. A predetermined constant voltage is applied to the gates of the p-type transistors 36-L and 36-R by the p-type transistor 39 and a constant current source connected to the p-type transistor 39. A predetermined voltage is also applied between the source and drain of the p-type transistors 36-L and 36-R. This causes the p-type transistors 36-L and 36-R to operate in the saturation region. With this configuration, the p-type transistors 36-L and 36-R function as high-resistance loads.

[0027] The drain of p-type transistor 36-L is connected to one of the source and drain of transistor 37 and to the drain of transistor 35-L. Similarly, the drain of p-type transistor 36-R is connected to the other of the source and drain of transistor 37 and to the drain of transistor 35-R.

[0028] One of the source and drain of the P-type transistor 37 is connected to the first output section 43. The other of the source and drain of the P-type transistor 37 is connected to the second output section 44. By turning on the P-type transistor 37, the first output section 43 and the second output section 44 are electrically connected. This makes it possible to make the voltage levels of the first output section 43 and the second output section 44 equal.

[0029] The pixel unit 11 inputs an output signal generated in accordance with the amount of charge photoelectrically converted in the photoelectric conversion unit 31 or 33 to one of the first input unit 41 and the second input unit 42. The pixel unit 11 also inputs a reference level signal from the DAC 46 to the other of the first input unit 41 and the second input unit 42. The differential comparator 49 of this example compares the reference level with the signal level of the voltage signal input to the first input unit 41 and the second input unit 42, and outputs a digital signal according to the comparison result from either the first output unit 43 or the second output unit 44.

[0030] In this example, one DAC 46 is provided for each of a plurality of pixel sharing units 48 that are consecutive in the second direction. That is, a different DAC 46 is provided for each row that is different from the row in which the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located. Similarly, one terminal Tx1_L, one terminal Tx1_R, one terminal Tx2_L, and one terminal Tx2_R are provided for each of a plurality of pixel sharing units 48 that are consecutive in the second direction. That is, a different terminal Tx1_L, one terminal Tx1_R, one terminal Tx2_L, and one terminal Tx2_R are provided for each of a plurality of pixel sharing units 48 that are consecutive in the second direction. In other words, a different terminal Tx1_L, one terminal Tx1_R, one terminal Tx2_L, and one terminal Tx2_R are provided for each of a plurality of pixel sharing units 48 that are consecutive in the second direction. Note that, as a variant, only one DAC 46 may be provided. In this case, the output of the DAC 46 is provided for each row using a selector or a decoder.

[0031] A first digital signal, which is a result of comparing the signal level of the first photoelectric conversion unit 31-L or the third photoelectric conversion unit 33-L with a reference level input from the DAC 46, is input to the counter circuit 28-2 of the latch unit 24. A second digital signal, which is a result of comparing the signal level of the second photoelectric conversion unit 31-R or the fourth photoelectric conversion unit 33-R with a reference level input from the DAC 46, is input to the counter circuit 28-1 of the latch unit 24. When the first digital signal is input from the first output unit 43 to the counter circuit 28-2, the second digital signal does not need to be used. Conversely, when the second digital signal is input from the second output unit 44 to the counter circuit 28-1, the first digital signal does not need to be used. In other words, the latch unit 24 may alternately input the first digital signal and the second digital signal.

[0032] In this example, when the voltage value of the signal input to the first input section 41 is lower than the voltage value of the signal input to the second input section 42, a high voltage signal is output from the first output section 43 to the counter circuit 28-2. On the other hand, when the voltage value of the signal input to the first input section 41 is higher than the voltage value of the signal input to the second input section 42, a low voltage signal is output from the first output section 43 to the counter circuit 28-2.

[0033] Similarly, when the voltage value input to the second input section 42 is lower than the voltage value input to the first input section 41, a high voltage signal is output from the second output section 44 to the counter circuit 28-1. On the other hand, when the voltage value input to the second input section 42 is higher than the voltage value input to the first input section 41, a low voltage signal is output from the second output section 44 to the counter circuit 28-1.

[0034] The signal source 25 supplies a pulse signal with a constant period to each counter circuit 28. In this example, the pulse signal with a constant period is used to identify the timing at which the magnitude relationship between the voltage value of the first input section 41 or the second input section 42 and the voltage value of the ramp waveform reference signal of the DAC 46 changes. The constant period of the pulse signal may have a time width corresponding to the minimum step width of the voltage value in the ramp waveform output by the DAC 46.

[0035] The counter circuit 28-2 counts the number of pulses from the signal source 25 during a period from when a monotonically increasing ramp waveform is input to the second input section 42 to when the voltage value of the second input section 42 becomes equal to or greater than the voltage value of the first input section 41. This period is conveniently referred to as the first count period. The number of pulses counted during the first count period is treated as a reset level in the photoelectric conversion section 31 or 33. The counter circuit 28-2 also counts the number of pulses from the signal source 25 during a period from when a monotonically decreasing ramp waveform is input to the second input section 42 to when the voltage value of the second input section 42 becomes equal to or less than the voltage value of the first input section 41. This period is conveniently referred to as the second count period. The number of pulses counted during the second count period is treated as an output level in the photoelectric conversion section 31 or 33. The value obtained by subtracting the reset level from the output level is treated as a pixel value in a digital image signal. It should be noted that the larger the amount of charge accumulated in the photoelectric conversion unit 31 or 33, the longer the second count period, and therefore the larger the number of pulses counted in the second count period.

[0036] The cathode of the first photoelectric conversion unit 31-L is connected to the source of the first transfer transistor 32-L. The drain of the first transfer transistor 32-L is connected to the first input unit 41. The first transfer transistor 32-L switches whether or not the first photoelectric conversion unit 31-L is connected to the first input unit 41. The cathode of the second photoelectric conversion unit 31-R is connected to the source of the second transfer transistor 32-R. The drain of the second transfer transistor 32-R is connected to the second input unit 42. The second transfer transistor 32-R switches whether or not the second photoelectric conversion unit 31-R is connected to the second input unit 42.

[0037] The cathode of the third photoelectric conversion unit 33-L is connected to the source of the third transfer transistor 34-L. The drain of the third transfer transistor 34-L is connected to the first input unit 41. The third transfer transistor 34-L switches whether or not the third photoelectric conversion unit 33-L is connected to the first input unit 41. The cathode of the fourth photoelectric conversion unit 33-R is connected to the source of the fourth transfer transistor 34-R. The drain of the fourth transfer transistor 34-R is connected to the second input unit 42. The fourth transfer transistor 34-R switches whether or not the fourth photoelectric conversion unit 33-R is connected to the second input unit 42.

[0038] A DAC46, which is a digital-to-analog converter, is provided in the imaging unit 200. The drain of the first switching transistor 38-L and the drain of the second switching transistor 38-R are both connected to the DAC46. The gate of the first switching transistor 38-L is connected to the terminal R_L, and the gate of the second switching transistor 38-R is connected to the terminal R_R. The source of the first switching transistor 38-L is connected to the first input section 41, and the source of the second switching transistor 38-R is connected to the second input section 42.

[0039] The DAC 46 sequentially generates a reference level having a ramp waveform and a reset level having a pulse waveform. For example, to reset the charge accumulated in the first input section 41, the DAC 46 generates a reset level signal having a pulse waveform. Then, the terminal R_L outputs a high voltage to turn on the first switching transistor 38-L. This allows the first switching transistor 38-L to input a reset level signal to the wiring between the first input section 41 and the first transfer transistor 32-L before connecting the first photoelectric conversion section 31-L to the first input section 41. This removes the charge accumulated in the first input section 41.

[0040] Similarly, to reset the charge accumulated in the second input section 42, the DAC 46 generates a reset-level signal having a pulse waveform. Then, the terminal R_R outputs a high voltage to turn on the second switching transistor 38-R. This allows the second switching transistor 38-R to input a reset-level signal to the wiring between the second input section 42 and the second transfer transistor 32-R before connecting the second photoelectric conversion section 31-R to the second input section 42. This removes the charge accumulated in the second input section 42.

[0041] The first switching transistor 38-L also switches whether or not the reference level of the DAC 46 is input to the first input section 41. Similarly, the second switching transistor 38-R switches whether or not the reference level of the DAC 46 is input to the second input section 42. For example, when a reference level with a ramp waveform is input to the first input section 41, the DAC 46 generates a signal with the ramp waveform. Then, the terminal R_L outputs a high voltage, turning the first switching transistor 38-L on. Note that when the terminal R_L outputs a low voltage, the first switching transistor 38-L is turned off.

[0042] In this example, the latch unit 24 is provided in the signal processing circuit 22 in the signal processing unit 20, rather than in the imaging unit 10. As a result, an area in the imaging unit 10 corresponding to the latch unit 24 can be allocated to the pixel sharing unit 48. In addition, in the pixel sharing unit 48, one differential comparator 49 is provided for the first to fourth photoelectric conversion units 31-L to 33-R. As a result, the area occupied by the photoelectric conversion units 31 and 33 in the pixel unit 11 can be made larger compared to the conventional example in which one comparison unit is provided for one photodiode. Therefore, in the pixel unit 11 having the differential comparator 49, the photoelectric conversion units 31 and 33 can be provided at a higher density than in the conventional example.

[0043] In this example, the constant current source connected to the drain of p-type transistor 39 and the constant current source connected to the source of transistor 30 are described as components of the pixel section 11. However, the constant current source may be provided in the imaging unit 200 and is not necessarily provided in the pixel section 11. Also, one constant current source may be provided in one pixel shared section 48 and connected in common to the drain of p-type transistor 39 and the source of transistor 30.

[0044] Next, the operation of the differential comparator 49 will be described. The differential comparator 49 of this example compares the voltage value of the analog image signal input to the first input section 41 with the voltage value of the ramp voltage of the DAC 46 input to the second input section 42. In this specification, this comparison operation is referred to as a first comparison operation. In the first comparison operation, the differential comparator 49 compares, for example, the signal level of the first photoelectric conversion section 31-L with a reference level of a ramp waveform. In this case, the pixel section 11 inputs the output signal of the first photoelectric conversion section 31-L to the first input section 41 and inputs the reference level of the ramp waveform to the second input section 42.

[0045] In the first comparison operation, an analog image signal is input to the first input section 41 from either the first photoelectric conversion section 31-L or the third photoelectric conversion section 33-L. The first transfer transistor 32-L outputs the charge accumulated in the first photoelectric conversion section 31-L to the first input section 41. Similarly, the third transfer transistor 34-L outputs the charge accumulated in the third photoelectric conversion section 33-L to the first input section 41. By selectively setting the terminals Tx1_L and Tx2_L to a high voltage at different times, the first transfer transistor 32-L and the third transfer transistor 34-L can be selectively turned on. As a result, the first transfer transistor 32-L and the third transfer transistor 34-L output the charge accumulated in the first photoelectric conversion section 31-L and the third photoelectric conversion section 33-L to the first input section 41 at different times. Therefore, analog image signals are input to the first input unit 41 from the first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L at different timings.

[0046] In a first comparison operation, a reference signal with a ramp waveform is input from the DAC 46 to the second input section 42. The voltage value of the reference signal with a ramp waveform monotonically increases or decreases over time. In the first comparison operation, the DAC 46 of this example inputs a reference signal that monotonically decreases from a high voltage value to a low voltage value to the second input section 42. In another operation, the DAC 46 inputs a high voltage reference signal to the second input section 42 for a fixed period of time. In yet another operation, the DAC 46 inputs a reference signal that monotonically decreases from a low voltage value to a high voltage value to the second input section 42.

[0047] When the first comparison operation is not performed, the terminal R_L outputs a high voltage to turn on the first switching transistor 38-L, and the DAC 46 outputs a high voltage, so that the first input section 41 can be set to the high voltage of the DAC 46. This makes it possible to remove the charge output to the first input section 41, and therefore the charge output to the first input section 41 is not affected by the charge previously output.

[0048] Furthermore, the differential comparator 49 of this example compares the voltage signal of the analog image signal input to the second input section 42 with the ramp waveform reference signal of the DAC 46 input to the first input section 41. In this specification, this comparison operation is referred to as a second comparison operation. For example, in the second comparison operation, the differential comparator 49 compares the signal level of the second photoelectric conversion section 31-R with a reference level. In this case, the pixel section 11 inputs the output signal of the second photoelectric conversion section 31-R to the second input section 42 and inputs the reference level to the first input section 41.

[0049] In the second comparison operation, an analog image signal is input to the second input section 42 from either the second photoelectric conversion section 31-R or the fourth photoelectric conversion section 33-R. The second transfer transistor 32-R outputs the charge accumulated in the second photoelectric conversion section 31-R to the second input section 42. Similarly, the fourth transfer transistor 34-R outputs the charge accumulated in the fourth photoelectric conversion section 33-R to the second input section 42. By selectively setting the terminals Tx1_R and Tx2_R to a high voltage at different times, the second transfer transistor 32-R and the fourth transfer transistor 34-R can be selectively turned on. As a result, the second transfer transistor 32-R and the fourth transfer transistor 34-R output the charge accumulated in the second photoelectric conversion section 31-R and the fourth photoelectric conversion section 33-R to the second input section 42 at different times. Therefore, analog image signals are input to the second input section 42 from the second photoelectric conversion section 31-R and the fourth photoelectric conversion section 33-R at different timings.

[0050] In the second comparison operation, a ramp voltage is input from the DAC 46 to the first input section 41. The voltage signal of the DAC 46 in the second comparison operation is the same as that in the first comparison operation. When the second comparison operation is not performed, the terminal R_R outputs a high voltage to turn on the second switching transistor 38-R, and the DAC 46 outputs a high voltage, so that the second input section 42 can be set to the high voltage of the DAC 46. This makes it possible to remove the charge output to the second input section 42. Therefore, the charge output to the second input section 42 is not affected by the charge previously output.

[0051] FIG. 4 is a time chart illustrating the operation of the imaging unit 200. The horizontal axis represents time. The vertical axis of each signal represents voltage. Tx1_L and Tx1_R represent voltage values ​​output from terminals Tx1_L and Tx1_R in FIG. 3, respectively. Tx2_L and Tx2_R represent voltage values ​​output from terminals Tx2_L and Tx2_R in FIG. 3, respectively. R_L and R_R represent voltage values ​​output from terminals R_L and R_R in FIG. 3, respectively. R_c represents the voltage value of the gate of the P-type transistor 37 in FIG. 3. DAC represents the voltage value output by the DAC 46 in FIG. 3. FIG. 4 also represents the voltage values ​​of the first input section 41, the second input section 42, the first output section 43, and the second output section 44 in FIG. 3, respectively.

[0052] From time t1 to t9, the charges photoelectrically converted in the first photoelectric conversion unit 31-L are output as a digital signal to the counter circuit 28-2. The period from time t1 to t9 corresponds to the first comparison operation. From time t9 to t10, the charges photoelectrically converted in the second photoelectric conversion unit 31-R are output as a digital signal to the counter circuit 28-1. The period from time t9 to t10 corresponds to the second comparison operation.

[0053] From time t10 to t11, the charges photoelectrically converted in the third photoelectric conversion unit 33-L are output to the counter circuit 28-2. From time t11 onwards, the charges photoelectrically converted in the fourth photoelectric conversion unit 33-R are output to the counter circuit 28-1. Note that the operation from time t9 onwards is a repetition of the operation from time t1 to t9, so only the operation from time t1 to t9 will be described below. Also, from time t1 to t9, the output of the second output unit 44 is not used by the counter circuit 28-1, so it is illustrated as a low voltage. Similarly, in other periods, outputs not used by the counter circuit 28 are illustrated as low voltages.

[0054] At time t1, the terminal R_L becomes a high voltage. Also at time t1, the DAC 46 outputs a reset voltage. This turns on the first switching transistor 38-L, resetting the charge in the first input section 41. Also at time t1, R_c becomes a low voltage. This turns on the P-type transistor 37, and the first input section 41 and the second input section 42 become the same potential. The high voltages of the terminal R_L and the DAC 46 continue until time t2. R_c changes to a high voltage before time t2. From time t1 to t2, the first input section 41 becomes a high voltage.

[0055] At time t2, the terminal R_L and the DAC 46 become low voltages. This turns off the first switching transistor 38-L. Also at time t2, the terminal R_R becomes high voltages. This turns on the second switching transistor 38-R. While the second switching transistor 38-R is on, the potential of the second input section 42 can follow the potential of the DAC 46 and become high voltages. The DAC 46 is at low voltage until time t3. Note that since the reset operation is completed, the terminal R_L becomes low voltage from t2 to t9, turning off the first switching transistor 38-L.

[0056] At time t3, the second switching transistor 38-R is in an ON state. Also, the DAC 46 inputs a monotonically increasing ramp voltage. Since the terminal R_R maintains a high voltage, the monotonically increasing ramp voltage is input to the second input section 42. Note that the maximum value of the ramp voltage output by the DAC 46 is greater than the reset voltage output by the DAC 46 at time t1.

[0057] After time t3 and before time t4, the potential of the first input section 41 is higher than the reference voltage input to the second input section 42. Therefore, the first output section 43 outputs a low voltage. However, at time t4, the potential of the first input section 41 becomes lower than the reference voltage input to the second input section 42. This causes the first output section 43 to output a high voltage. Note that the period from t3, when a monotonically increasing ramp waveform is input to the second input section 42, to t4, when the voltage value of the second input section 42 becomes equal to or greater than the voltage value of the first input section 41, corresponds to the first count period described in the description of FIG. 3.

[0058] At time t5, the terminal Tx1_L becomes a high voltage. This starts the transfer of charge from the first photoelectric conversion unit 31-L to the first input unit 41. Between time t5 and time t6, the terminal Tx1_L maintains a high voltage. This causes the potential of the first input unit 41 to drop by an amount corresponding to the voltage according to the amount of accumulated charge between time t5 and time t6.

[0059] From time t6 to t7, the DAC 46 maintains a high voltage. At time t7, the DAC 46 starts inputting a monotonically decreasing ramp voltage. Also, at time t7, the terminal R_R is in the ON state. This turns on the second switching transistor 38-R, and the monotonically decreasing ramp voltage is input to the second input section 42.

[0060] At time t8, the potential of the first input section 41 becomes higher than the reference voltage input to the second input section 42. Therefore, the first output section 43 outputs a low voltage. Note that the period from t7, when a monotonically decreasing ramp waveform is input to the second input section 42, to t8, when the voltage value of the second input section 42 becomes equal to or lower than the voltage value of the first input section 41, corresponds to the second count period described in the description of FIG. 3.

[0061] FIG. 5 is a diagram showing the element layout of the pixel unit 11. As in FIG. 3, the first pixel shared unit 48-1 and the second pixel shared unit 48-2 are indicated by dotted lines. The first pixel shared unit 48-1 and the second pixel shared unit 48-2 have the same configuration. The first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L are arranged side by side in a first direction. The second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R are also arranged side by side in the first direction. The first photoelectric conversion unit 31-L and the third photoelectric conversion unit 31-R are also arranged side by side in a second direction perpendicular to the first direction. The third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R are also arranged side by side in the second direction.

[0062] A first transfer transistor 32-L is provided overlapping the region of the first photoelectric conversion unit 31-L. Furthermore, a second transfer transistor 32-R is provided overlapping the region of the second photoelectric conversion unit 31-R. Furthermore, a third transfer transistor 34-L is provided overlapping the region of the third photoelectric conversion unit 33-L. Additionally, a fourth transfer transistor 34-R is provided overlapping the region of the fourth photoelectric conversion unit 33-R.

[0063] The differential comparator 49 is provided between the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R, and between the third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R. The differential comparator 49 is indicated by a dotted frame. The first input unit 41 and the second input unit 42 are provided so that their long sides are parallel to the first direction. The first input unit 41 is adjacent to the first transfer transistor 32-L and the third transfer transistor 34-L in the second direction. Similarly, the second input unit 42 is adjacent to the second transfer transistor 32-R and the fourth transfer transistor 34-R in the second direction.

[0064] This configuration allows the first input section 41 to be located close to the first transfer transistor 32-L and the third transfer transistor 34-L. It is also possible to locate the second input section 42 close to the second transfer transistor 32-R and the fourth transfer transistor 34-R. This shortens the wiring length between the input section and the transfer transistors 32 and 34. This reduces signal delays between the input section and the transfer transistors 32 and 34, and noise between the input section and the transfer transistors 32 and 34.

[0065] FIG. 6 is a diagram showing the positional relationship between the photoelectric conversion unit 31, the photoelectric conversion unit 33, and the microlens 50 in the pixel unit 11. The first photoelectric conversion unit 31-L, the second photoelectric conversion unit 31-R, the third photoelectric conversion unit 33-L, and the fourth photoelectric conversion unit 33-R are the same as those in FIG. 5. For simplicity, the photoelectric conversion units 31 and 33 are indicated by squares. The microlens 50 is indicated by a circle. The microlens 50 and the photoelectric conversion unit 31 and the photoelectric conversion unit 33 are arranged in the third direction in the order of the microlens 50 and the photoelectric conversion unit 31 or the photoelectric conversion unit 33. A light beam incident from a subject passes through each microlens 50 and enters the photoelectric conversion unit 31 and the photoelectric conversion unit 33.

[0066] 7 is a diagram showing a modified example of the positional relationship between the photoelectric conversion unit 31, the photoelectric conversion unit 33, and the microlens 50 in the pixel unit 11. This example differs from the example in FIG. 6 in that a first photoelectric conversion unit 31-L and a second photoelectric conversion unit 31-R or a third photoelectric conversion unit 33-L and a fourth photoelectric conversion unit 33-R are provided corresponding to one microlens 50. For example, one microlens 50 is provided in common to the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R.

[0067] The first photoelectric conversion unit 31-L and the second photoelectric conversion unit 33-L are adjacent in the first direction. The second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R are also adjacent in the first direction. The first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R are also adjacent in the second direction. The third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R are also adjacent in the second direction.

[0068] The focus detection line 70 includes a plurality of first photoelectric conversion units 31-L and second photoelectric conversion units 31-R adjacent to each other in the second direction. One image is generated from charges photoelectrically converted in the plurality of first photoelectric conversion units 31-L in the focus detection line 70. Another image is generated from charges photoelectrically converted in the plurality of second photoelectric conversion units 31-R in the focus detection line 70. By comparing the one image with the other image, the amount of image misalignment between the pair of images described above is calculated. Therefore, the focus of the optical system can be detected using the focus detection line 70.

[0069] 8 is a circuit schematic diagram of the pixel section 12 and the signal processing circuit 22 of the imaging unit 300 in the second embodiment. The difference from the first embodiment is the configuration of the pixel sharing section 58. In addition to the configuration of the pixel sharing section 48 in the first embodiment, the pixel sharing section 58 of this example further includes a fifth transfer transistor 82-L and a sixth transfer transistor 82-R, a first diode 81-L and a second diode 81-R, a seventh transfer transistor 84-L and an eighth transfer transistor 84-R, and a third diode 83-L and a fourth diode 83-R.

[0070] The fifth transfer transistor 82-L is provided between the first transfer transistor 32-L and the first input section 41. The sixth transfer transistor 82-R is provided between the second transfer transistor 32-R and the second input section 42. Similarly, the seventh transfer transistor 84-L is provided between the third transfer transistor 34-L and the first input section 41, and the eighth transfer transistor 84-R is provided between the fourth transfer transistor 34-R and the second input section 42.

[0071] The cathode of the first diode 81-L is provided between the drain of the first transfer transistor 32-L and the source of the fifth transfer transistor 82-L. The anode of the first diode 81-L is grounded. The cathode of the second diode 81-R is provided between the drain of the second transfer transistor 32-R and the source of the sixth transfer transistor 82-R. The cathode of the third diode 83-L is provided between the drain of the third transfer transistor 34-L and the source of the seventh transfer transistor 84-L. The cathode of the fourth diode 83-R is provided between the drain of the fourth transfer transistor 34-R and the source of the eighth transfer transistor 84-R. The anodes of the second diode 81-R, the third diode 83-L, and the fourth diode 83-R are grounded.

[0072] The fifth transfer transistor 82-L switches whether or not to output the charge transferred from the first transfer transistor 32-L to the first input section 41. Similarly, the seventh transfer transistor 84-L switches whether or not to output the charge transferred from the third transfer transistor 34-L to the first input section 41. Furthermore, the sixth transfer transistor 82-R switches whether or not to output the charge transferred from the second transfer transistor 32-R to the second input section 42. Similarly, the eighth transfer transistor 84-R switches whether or not to output the charge transferred from the fourth transfer transistor 34-R to the second input section 42.

[0073] The charge transferred from the first transfer transistor 32-L to the cathode of the first diode 81-L is held at the cathode of the first diode 81-L for a predetermined period. By appropriately adjusting the characteristics of the first diode 81-L, the pn junction interface of the first diode 81-L is completely depleted. This prevents the charge from flowing to ground and being lost, as the charge is transferred to and held at the cathode of the first diode 81-L. The second diode 81-R, the third diode 83-L, and the fourth diode 83-R similarly hold the charge transferred to their cathodes.

[0074] FIG. 9 is a timing chart illustrating the operation of the imaging unit 300 according to the second embodiment. This example employs a so-called global shutter system. In the global shutter system, all of the first transfer transistors 32-L, second transfer transistors 32-R, third transfer transistors 34-L, and fourth transfer transistors 34-R in all of the pixel shared portions 58 in the pixel section 12 are simultaneously turned on. As a result, the charges accumulated in the first photoelectric conversion unit 31-L, second photoelectric conversion unit 31-R, third photoelectric conversion unit 33-L, and fourth photoelectric conversion unit 33-R are simultaneously transferred from the first transfer transistor 32-L, second transfer transistor 32-R, third transfer transistor 34-L, and fourth transfer transistor 34-R to the cathodes of the first diode 81-L, second diode 81-R, third diode 83-L, and fourth diode 83-R, respectively. This makes it possible to improve image distortion when capturing an image of a moving subject, compared to the rolling shutter method in which charge transfer is performed for each of multiple photoelectric conversion units 31 or multiple photoelectric conversion units 33 arranged consecutively in the first direction.

[0075] In this example, the first transfer transistor 32-L and the second transfer transistor 32-R, and the third transfer transistor 34-L and the fourth transfer transistor 34-R are simultaneously turned on from time t1 to t2. Note that in pixel shared portions 58 other than the illustrated pixel shared portion 58, the first transfer transistor 32-L and the second transfer transistor 32-R, and the third transfer transistor 34-L and the fourth transfer transistor 34-R are also simultaneously turned on from time t1 to t2.

[0076] The charges transferred from the first transfer transistor 32-L, the second transfer transistor 32-R, the third transfer transistor 34-L, and the fourth transfer transistor 34-R are temporarily held at the cathodes of the first diode 81-L, the second diode 81-R, the third diode 83-L, and the fourth diode 83-R, respectively. The subsequent operation is the same as that of the first embodiment in FIG. 4. Note that Tx in FIG. 4 corresponds to Ts in FIG. 9. In other words, the charges held at the cathodes of the first diode 81-L, the second diode 81-R, the third diode 83-L, and the fourth diode 83-R are sequentially transferred to the first input section 41 or the second input section 42 by sequentially turning on the fifth transfer transistor 82-L, the sixth transfer transistor 82-R, the seventh transfer transistor 84-L, and the eighth transfer transistor 84-R. For example, the fifth transfer transistor 82-L is turned on by setting the terminal Ts1_L to a high voltage, and the charge held at the cathode of the first diode 81-L is output to the first input section 41.

[0077] In the first and second embodiments, in one differential comparator 49, the outputs of two photoelectric conversion units 31-L and 33-L are connected to the first input unit 41, and the outputs of the other two photoelectric conversion units 31-R and 33-R are connected to the second input unit 42. However, one differential comparator 49 may be provided with a plurality of photoelectric conversion units. That is, the outputs of four photoelectric conversion units may be connected to the first input unit 41, and the outputs of the other four photoelectric conversion units may be connected to the second input unit 42. Alternatively, the outputs of eight photoelectric conversion units may be connected to the first input unit 41, and the outputs of the other eight photoelectric conversion units may be connected to the second input unit 42. The output from each photoelectric conversion unit to the first input unit 41 or the second input unit 42 may be controlled using a terminal Tx common to the gates of each row, as in the first embodiment, or may be controlled using a terminal Tx and a terminal Ts common to the gates of each row, as in the second embodiment. By connecting the outputs of eight or more photoelectric conversion units to one differential comparator 49, the number of photoelectric conversion units per differential comparator 49 increases compared to when the outputs of four photoelectric conversion units are connected. Since a certain amount of area is required to configure one differential comparator 49, this configuration can reduce the ratio of the area occupied by the differential comparator 49 to one photoelectric conversion unit.

[0078] 10 is a circuit schematic diagram of the pixel section 13 and signal processing circuit 22 of the imaging unit 310 in the third embodiment. The difference from the first embodiment is the configuration of the pixel shared section 68. The pixel shared section 68 of this example has a first photoelectric conversion section 31-L, a first transfer transistor 32-L, a first switching transistor 38-L, a second switching transistor 38-R, and a differential comparator 49. The latch section 24 has one counter circuit 28 for one pixel shared section 68.

[0079] In this example, the signal level of an output signal generated in accordance with the amount of charge photoelectrically converted in the first photoelectric conversion unit 31-L is input to the first input unit 41. Also, the reference level of the DAC 46 is input to the second input unit 42. Then, the signal level of the output signal is compared with the reference level of the DAC 46. The comparison operation is the same as in the first embodiment. The comparison result is output from the first output unit 43 to the counter circuit 28-2.

[0080] In the configuration of this example, the latch unit 24 is provided in the signal processing circuit 22 of the signal processing unit 20, not in the imaging unit 10. As a result, an area corresponding to the latch unit 24 can be allocated to the pixel shared unit 68 in the imaging unit 10. As a result, the area occupied by the photoelectric conversion units 31 and 33 in the pixel unit 13 can be made larger compared to the conventional example in which one differential comparator 49 is provided for one photodiode. Therefore, in the pixel unit 13 having the differential comparator 49, the photoelectric conversion units 31 and 33 can be provided at a higher density than in the conventional example. Note that in the first embodiment, four photoelectric conversion units 31 and 33 are provided for one differential comparator 49. Therefore, in the first embodiment, the ratio of the area occupied by the differential comparator 49 to one photoelectric conversion unit can be made lower than in the third embodiment.

[0081] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0082] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0083] 10 imaging section, 11 pixel section, 12 pixel section, 13 pixel section, 15 bump, 20 signal processing section, 22 signal processing circuit, 24 latch section, 25 signal source, 26 focus detection section, 28 counter circuit, 30 transistor, 31 photoelectric conversion section, 32 transfer transistor, 33 photoelectric conversion section, 34 transfer transistor, 35 transistor, 36 transistor, 37 transistor, 38 switching transistor, 39 transistor, 41 first input section, 42 second input section, 43 first output section, 44 second output section, 46 DAC, 48 pixel shared section, 49 differential comparator, 50 microlens, 58 pixel shared section, 68 pixel shared section, 70 focus detection line, 81 diode, 82 transfer transistor, 83 diode, 84 transfer transistor, 200 imaging unit, 300 imaging unit, 310 Imaging unit, 340 shutter unit, 410 optical axis, 400 single-lens reflex camera, 500 lens unit, 550 lens mount, 600 camera body, 620 body board, 622 CPU, 624 image processing unit, 625 image processing ASIC, 626 recording unit, 634 rear display unit, 650 viewfinder, 652 focusing screen, 654 pentaprism, 656 viewfinder optical system, 660 body mount, 670 mirror box, 672 mirror

Claims

[Claim 1] a first photoelectric conversion unit that converts light into electric charges; a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in the row direction; a first transfer transistor that transfers the charges converted by the first photoelectric conversion unit; a second transfer transistor that transfers the charges converted by the second photoelectric conversion unit; a comparison unit that is a circuit for converting a first signal based on the charge converted by the first photoelectric conversion unit into a digital signal, the comparison unit including a first transistor having a first gate electrically connected to the first transfer transistor, and a second transistor having a second gate to which a signal used for comparison with a signal value of the first signal is input; Equipped with the first gate and the second gate are disposed between the gate of the first transfer transistor and the gate of the second transfer transistor in the row direction; Imaging unit.

Images