Analog-digital conversion circuit and control system

Abstract

To provide an analog-digital conversion circuit capable of controlling a control object and processing an object signal from the control object.SOLUTION: An analog-digital conversion circuit 13 comprises: a conversion control circuit 15 including a period setting register 21, a count circuit 23, and a comparison circuit 25; and an analog-digital converter 17 for performing AD conversion of an object signal SSNS from a control object 12. The count circuit 23 counts clock signals. The comparison circuit 25 generates a comparison signal SCMP from comparison between a count value of the count circuit 23 and a period value of the period setting register 21. For each indication of count termination by the comparison signal SCMP, the comparison circuit 15 makes the count circuit 23 perform counting repeatedly. The conversion control circuit 15 generates a control signal SCNTL having a first value indicating permission of activation of the control object 12 and a second value indicating permission of deactivation of the control object 12 so as to control activation of the control object 12, where a period of activation is equal to or shorter than a count period.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to analog-to-digital conversion circuits and control systems. [Background technology]

[0002] Patent Document 1 discloses a sensor signal processing circuit that reduces current consumption and heat generation of a sensor power supply. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-54736 Summary of the Invention [Problem to be solved by the invention]

[0004] In a control system including a controlled object controlled by a semiconductor device, the semiconductor device controls the controlled object, receives an analog signal from the controlled object, and responds to changes in the analog signal. Specifically, the semiconductor device includes a processing circuit such as a central processing unit (CPU), which controls an output port to control the controlled object. The processing circuit also controls an input port to receive the analog signal from the controlled object, and controls an analog-to-digital conversion circuit to convert the analog signal into a digital signal.

[0005] Since the controlled object is controlled by the processing circuit, this control depends on the period of the clock signal of the processing circuit. The analog-to-digital conversion circuit is also controlled by the processing circuit. Therefore, the control of the analog-to-digital conversion circuit also depends on the period of the clock signal of the processing circuit. Furthermore, direct control of the controlled object and the analog-to-digital conversion circuit by the processing circuit requires resources of the processing circuit.

[0006] An object of the present disclosure is to provide an analog-to-digital conversion circuit and a control system that can control a controlled object and process a target signal from the controlled object. [Means for solving the problem]

[0007] An analog-to-digital conversion circuit according to a first aspect of the present disclosure comprises: a conversion control circuit including a period setting register, a count circuit, and a comparison circuit; and an analog-to-digital converter configured to perform AD conversion of a target signal from at least one controlled object, wherein the count circuit is configured to count a clock signal; the period setting register is configured to store a period value specifying a count period; the comparison circuit is configured to compare the count value of the count circuit with the period value and generate a comparison signal representing the result of the comparison; the comparison circuit causes the count circuit to repeatedly count each time the comparison signal indicates completion of the count; and the conversion control circuit is configured to generate a control signal for controlling activation of the controlled object based on the comparison signal and the count value, wherein the control signal has a first value indicating permission to activate the controlled object and a second value indicating permission to deactivate the controlled object, the activation period being equal to or smaller than the count period; and the analog-to-digital converter performs the AD conversion of the target signal during the count period.

[0008] A control system according to a second aspect of the present disclosure includes the analog-to-digital conversion circuit according to the first aspect, and a control target device that is controlled by the first value and the second value of the control signal. [Effects of the Invention]

[0009] According to the above aspects, an analog-to-digital conversion circuit and a control system are provided that can control a controlled object and process a target signal from the controlled object. [Brief explanation of the drawings]

[0010] [Figure 1]FIG. 1 is a diagram schematically showing a control system according to this embodiment. [Figure 2] FIG. 2 is a diagram illustrating some signal waveforms associated with an analog-to-digital conversion circuit. [Figure 3] FIG. 3 is a diagram illustrating some signal waveforms associated with an analog-to-digital conversion circuit. [Figure 4] FIG. 4 is a diagram illustrating some signal waveforms associated with an analog-to-digital conversion circuit. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Identical parts are designated by the same reference numerals and redundant description will be omitted.

[0012] Figure 1 is a diagram showing a schematic diagram of a control system according to an embodiment of the present invention, and Figure 2 is a diagram showing some signal waveforms associated with an analog-to-digital conversion circuit.

[0013] The control system 10 includes a semiconductor device 11 and a controlled object 12 .

[0014] The semiconductor device 11 includes an analog-to-digital conversion circuit 13. The analog-to-digital conversion circuit 13 includes a conversion control circuit 15 and an analog-to-digital converter 17. The conversion control circuit 15 includes a period setting circuit 27 and a period control circuit 29. The period setting circuit 27 includes a period setting register 21, a count circuit 23, and a comparison circuit 25. The semiconductor device 11 can include a processing circuit 51, which is configured to control the analog-to-digital conversion circuit 13. An exemplary processing circuit 51 can include a central processing unit (CPU).

[0015] The analog-to-digital converter 17 is configured to perform AD conversion of the target signal SSNS from at least one controlled object 12 .

[0016] The period setting register 21 stores a period value VPRD that specifies a count period. The period value VPRD indicates a period that can be used for AD conversion of a target signal SSNS from a certain controlled object 12.

[0017] The count circuit 23 starts counting the clock signal CLK in response to receiving a start signal SRT indicating the start of operation of the count circuit 23. The comparator circuit 25 is configured to compare the count value SCNT of the count circuit 23 with the period value VPRD and generate a comparison signal SCMP indicating the result of the comparison. The comparison signal SCMP is generated each time the count value SCNT of the count circuit 23 becomes equal to the period value VPRD. The count circuit 23 is configured to be reset and released from reset by the comparator circuit 25 in response to the comparison signal SCMP indicating the expiration of the count period, and to start counting the clock signal CLK again.

[0018] The conversion control circuit 15 generates the control signal SCNTL when the count circuit 23 starts operation and when the next count period starts after the comparison signal SCMP indicates the expiration of the count period for the controlled object 12 immediately preceding the current controlled object 12. The control signal SCNTL is configured to specify the operation of the controlled object 12. Specifically, the control signal SCNTL has a first value indicating activation of the controlled object 12 and a second value indicating deactivation of the controlled object 12. The activation period of the controlled object 12 is equal to or shorter than the count period of the count circuit 23.

[0019] According to this analog-digital conversion circuit 13, the conversion control circuit 15 generates the control signal SCNTL based on the operation of the count circuit 23. In the control system 10, the operation of the controlled object 12 is controlled by the control signal SCNTL from the analog-digital conversion circuit 13, specifically, a first value indicating activation of the controlled object 12 and a second value indicating deactivation of the controlled object 12. Accordingly, the controlled object 12 is activated during a period in which the semiconductor device 11 receives the target signal SSNS from the controlled object 12.

[0020] The semiconductor device 11 may include an output port circuit 32, and the output port circuit 32 is connected to the conversion control circuit 15. The semiconductor device 11 provides a control signal SCNTL to the controlled object 12 and the second controlled object 12b via the output port circuit 32.

[0021] Each of the controlled object 12 and the second controlled object 12b may include a switch SW and a controlled element DSNS. The second controlled object 12c does not include a switch SW but includes a controlled element DSNS.

[0022] An exemplary controlled object (12, 12b) may include a transistor as the switch SW, and a sensor element DS (e.g., a temperature sensor) and a load circuit LD as the controlled element DSNS, which are connected in series. The sensor element DS generates a target signal SSNS when the switch SW is conductive and does not generate the target signal SSNS when the switch SW is non-conductive. The conduction and non-conduction of the switch SW is controlled by a control signal SCNTL applied to a control terminal of the switch SW (e.g., a transistor). The exemplary load circuit LD includes a resistor and a capacitor connected in parallel. The control signal SCNTL defines the period during which the sensor element DS is activated.

[0023] The analog-to-digital conversion circuit 13 further includes a selector circuit 31. The selector circuit 31 has a plurality of inputs 31b, which receive electrical signals from the controlled object 12 and one or more second controlled objects 12b, 12c different from the controlled object 12, respectively.

[0024] The selector circuit 31 has an output 31c, which is connected to an input 13b of the analog-to-digital conversion circuit 13. The selector circuit 31 provides a signal from one of the inputs 31b to the output 31c in response to a selection signal SSEL.

[0025] The exemplary semiconductor device 11 includes an input port circuit 33, which is connected to the controlled object 12 and second controlled objects 12b and 12c outside the semiconductor device 11 to receive electrical signals (analog signals) from these controlled objects 12, 12b, and 12c. The input port circuit 33 is connected to an input 31b of the selector circuit 31.

[0026] The semiconductor device 11 receives a target signal SSNS associated with a controlled element DSNS via an input port circuit 33. A selection signal SSEL specifies the target signal SSNS to be AD converted. A control signal SCNTL specifies whether the switch SW of the controlled object 12, 12b is conductive or non-conductive.

[0027] The processing circuit 51 provides a target identification signal SDET to the analog-digital conversion circuit 13 to identify the control target (12, 12b, 12c) to be activated. The analog-digital conversion circuit 13 receives the target identification signal SDET. The timing of receiving the target identification signal SDET can be independent of the period of the counting operation of the period setting circuit 27.

[0028] The conversion control circuit 15 may include at least one store 42. The store 42 provides the period VTRM to the period setting register 21 based on the target specific signal SDET.

[0029] The period control circuit 29 also receives a target identification signal SDET that identifies one of the control targets (12, 12b, 12c). The period control circuit 29 also generates a selection signal SSEL based on the received target identification signal SDET in response to the comparison signal SCMP indicating the expiration of the previous count period or in response to the start signal SRT. The selection signal SSEL is output during the count period following the count period in which the target identification signal SDET was received.

[0030] The processing circuit 51 can provide an enable signal to the analog-to-digital conversion circuit 13, specifically, the conversion control circuit 15 and the analog-to-digital converter 17, to enable the analog-to-digital conversion circuit 13. In addition, the conversion control circuit 15 can provide a completion signal to the processing circuit 51 in response to all of the target signals SSNS being processed by the analog-to-digital converter 17.

[0031] The period control circuit 29 generates an enable control signal SENB based on the received target identification signal SDET. The enable control signal SENB is generated based on the value of the target identification signal SDET at that time in response to the comparison signal SCMP indicating the expiration of the previous count period or in response to the start signal SRT. The enable control signal SENB includes information on a specified control target among the control targets (12, 12b, 12c).

[0032] The conversion control circuit 15 includes a target control circuit 41. The target control circuit 41 receives an enable control signal SENB. The target control circuit 41 also includes a period adjustment circuit 45 and a target identification circuit 47.

[0033] The period adjustment circuit 45 includes a first register 43b, a second register 43c, and a determination circuit 43d. The first register 43b stores a first setting value (e.g., a count value for starting operation) for at least one of the control targets (12, 12b) that sets the control target (12, 12b) to a first state (e.g., operating). The second register 43c can store a second setting value (e.g., a count value for stopping operation) for at least one of the control targets (12, 12b) that sets the control target (12, 12b) to a second state (e.g., operating) different from the first state.

[0034] The determination circuit 43d can compare the first setting value of the first register 43b with the count value SCNT of the count circuit 23 to generate a signal (for example, a first value of the control signal SCNTL) that sets the control object (12, 12b) to a first state. The determination circuit 43d can also compare the second setting value of the second register 43c with the count value SCNT of the count circuit 23 to generate a signal (for example, a second value of the control signal SCNTL) that sets the control object (12, 12b) to a second state.

[0035] The object control circuit 41 can set the activation period of the controlled object (12, 12b) based on the first and second set values ​​within the period value VPRD of the count circuit 23, independently of the start and end of the period value VPRD.

[0036] The exemplary determination circuit 43d may include a first comparator 43f and a second comparator 43g. The first comparator 43f performs a first comparison of a first set value with the count value SCNT and generates a first signal indicating the result of the first comparison. The second comparator 43g performs a second comparison of a second set value with the count value SCNT and generates a second signal indicating the result of the second comparison.

[0037] The conversion control circuit 15 includes a target specifying circuit 47. The target specifying circuit 47 may include a control signal generating circuit 49 and drivers 50, 50c.

[0038] The target identification circuit 47 generates a control signal SCNTL from the first and second signals from the first and second comparators 43f and 43g. Specifically, the control signal generation circuit 49 sets the control signal SCNTL to a first value in response to the generation of the first signal by the first comparator 43f, and sets the control signal SCNTL to a second value in response to the generation of the second signal by the second comparator 43g. This allows the control signal SCNTL to determine the period during which the control signal SCNTL activates the control target (12, 12b). This period is equal to or shorter than the count period of the count circuit 23.

[0039] In the target specifying circuit 47, each of the drivers 50, 50c is connected to one of the outputs of the control signal generating circuit 49. The control signal generating circuit 49 sends a control signal SCNTL from the control signal generating circuit 49 to one of the drivers 50, 50c specified by the enable control signal SENB. The drivers 50, 50c are associated with the control targets (12, 12b, 12c).

[0040] An exemplary target identification circuit 47 may include a driver 50c that is not connected to the output port circuit 32. When the target identification signal SDET identifies a control target 12c, the control signal generation circuit 49 provides a control signal SCNTL to the driver 50c.

[0041] Next, the propagation line of the target signal SSNS will be described. The semiconductor device 11 receives the target signal SSNS of a control target (12, 12b) specified by the control signal SCNTL. The target signal SSNS is input to a selector circuit 31 and provided to an input 17b of an analog-to-digital converter 17 in accordance with a selection signal SSEL. The analog-to-digital converter 17 generates an analog-to-digital conversion value SAD from the target signal SSNS and provides the analog-to-digital conversion value SAD to an output 17c.

[0042] The analog-to-digital conversion circuit 13 further comprises a storage circuit 35 , which is connected to the output 17 c of the analog-to-digital converter 17 .

[0043] The conversion control circuit 15 further includes a storage device specifying circuit 37, which receives a target specifying signal SDET. The storage device specifying circuit 37 provides an input register specifying signal SLAT to the storage circuit 35 based on the received target specifying signal SDET and comparison signal SCMP. In response to the input register specifying signal SLAT, the storage circuit 35 stores the analog-to-digital converted value SAD in the storage circuit 35 in association with the control target (12, 12b, 12c).

[0044] An exemplary storage circuit 35 includes an input selection circuit 35b, a plurality of registers 34, and an output selection circuit 35c. The input selection circuit 35b is connected to the output 17c of the analog-to-digital converter 17. The input selection circuit 35b is connected to the input of the register 34 and provides a selection value to the register 34. The output selection circuit 35c is connected to the output of the register 34 and receives one of the storage values ​​from the register 34.

[0045] Specifically, the input selection circuit 35 b provides the analog-to-digital converted value SAD to one of the registers 34 based on the input register specifying signal SLAT from the storage specifying circuit 37 .

[0046] The input register specifying signal SLAT indicates the register 34 (the register corresponding to the target specifying signal SDET) in which the analog-to-digital conversion value SAD should be stored. The input register specifying signal SLAT is generated in response to the comparison signal SCMP indicating the end of the previous count period or in response to the start signal SRT. The input register specifying signal SLAT enables the corresponding register 34 to store the analog-to-digital conversion value SAD during the period indicating that the count circuit 23 is currently counting. The register 34 may include a latch circuit or a flip-flop circuit. The period during which the signal of the latch circuit or flip-flop circuit can be captured is between the time when the comparison signal SCMP starts counting and the time when the comparison signal SCMP indicates the end of counting.

[0047] Specifically, the output selection circuit 35c outputs the analog-to-digital converted value SAD from one of the registers 34 in response to an output register specifying signal SOUT from the processing circuit 51. The timing of reading from the output selection circuit 35c is independent of the timing of storing in the input selection circuit 35b.

[0048] Referring to FIG. 2, waveforms of main signals when the analog-to-digital conversion circuit 13 processes the target signal SSNS from the controlled object 12 are shown.

[0049] After the processing circuit 51 activates the analog-digital conversion circuit 13 with the signal P0, the analog-digital conversion circuit 13 receives the target identification signal SDET. The processing circuit 51 also provides a start signal SRT to the analog-digital conversion circuit 13. After the target identification signal SDET is provided to the analog-digital conversion circuit 13, the period setting circuit 27 operates in response to receiving the start signal SRT. Specifically, the counting circuit 23 repeats the counting operation, and the counting circuit 23 and the comparison circuit 25 generate a synchronization signal (period VTRM) specific to the analog-digital conversion circuit 13.

[0050] After receiving the target specifying signal SDET, the period control circuit 29 generates an enable control signal SENB to specify the control target (12, 12b, 12c).

[0051] The object control circuit 41 provides a control signal SCNTL to the control object (12, 12b) specified by the object specifying signal SDET.

[0052] The activation period of the control object (12, 12b) specified by the control signal SCNTL is a period VTRM at most. The start of the activation period can be set according to the count value SCNT and a first set value of the first register 43b, and the end of the activation period can be set according to the count value SCNT and a second set value of the second register 43c.

[0053] The controlled objects (12, 12b) are activated for a period designated by the control signal SCNTL, and the input port circuit 33 receives the controlled object signal SSNS from the controlled objects (12, 12b, 12c).

[0054] The period control circuit 29 also generates a select signal SSEL according to the target specification signal SDET. The target signal SSNS from the input port circuit 33 is provided to the analog-to-digital converter 17 via the selector circuit 31. The select signal SSEL enables the selector circuit 31 to provide the target signal SSNS from the input 31b to the output 31c according to the target specification signal SDET within a period specified by the comparison signal SCMP. The end of the selection period of the select signal SSEL can be synchronized with the end of the activation period of the control signal SCNTL.

[0055] The analog-to-digital converter 17 generates an analog-to-digital converted value SAD of the target signal SSNS received from the selector circuit 31 within the period VTRM.

[0056] The analog-to-digital converted value SAD is stored in the storage circuit 35 that corresponds to the controlled object (12, 12b, 12c) among the storage circuits 35 in accordance with the input register specifying signal SLAT.

[0057] FIG. 3 is a diagram illustrating some signal waveforms associated with an analog-to-digital conversion circuit.

[0058] Referring to FIG. 3, the analog-to-digital conversion circuit 13 controls two controlled objects (12, 12b) while receiving three controlled object signals SSNS (SSNS1, SSNS2, SSNS3).

[0059] Specifically, a target identification signal SDET is sequentially provided from the processing circuit 51 to identify multiple control targets (12, 12b). The period control circuit 29 generates an enable control signal SENB for each control target (12, 12b) indicated by the target identification signal SDET. These signals are provided to the target control circuit 41, which generates three control signals SCNTL (SCNTL1, SCNTL2, SCNTL3) for three periods VTRM. These control signals are sequentially provided to the control targets (12, 12b) via the output port circuit 32. The control targets (12, 12b) activated by the control signal SCNTL sequentially generate target signals SSNS (SSNS1, SSNS2, SSNS3). These target signals SSNS (SSNS1, SSNS2, SSNS3) are sequentially provided to the analog-to-digital converter 17 by the selector circuit 31 responsive to the selection signal SSEL. The analog-to-digital converter 17 processes the target signals SSNS (SSNS1, SSNS2, SSNS3) in sequence within the period VTRM. Specifically, the analog-to-digital converter 17 generates analog-to-digital converted values ​​SAD in sequence from the target signals SSNS (SSNS1, SSNS2, SSNS3). These analog-to-digital converted values ​​SAD are associated with the controlled objects (12, 12b, 12c) and stored in the storage circuit 35.

[0060] In the analog-to-digital conversion circuit 13, the processing circuit 51 does not directly control the controlled objects (12, 12b, 12c).

[0061] FIG. 4 is a diagram illustrating some signal waveforms associated with an analog-to-digital conversion circuit.

[0062] Referring to FIG. 4, an analog-to-digital conversion circuit 13 controls two of three controlled objects (12, 12b, 12c) while receiving three controlled object signals SSNS (SSNS1, SSNS2, SSNS4).

[0063] The controlled object (12c) is not controlled by the control signal SCNTL. However, the controlled object signal SSNS4 from the controlled object (12c) is provided to the selector circuit 31 via the input port circuit 33, and the selector circuit 31 provides the controlled object signal SSNS4 to the analog-to-digital converter 17 in response to the selection signal SSEL. The analog-to-digital converter 17 processes the controlled object signal SSNS4 within the period VTRM. Specifically, the analog-to-digital converter 17 generates an analog-to-digital conversion value SAD from the controlled object signal SSNS4. This analog-to-digital conversion value SAD is associated with the controlled object 12c and stored in the storage circuit 35.

[0064] According to this embodiment, an analog-to-digital conversion circuit 13 and a control system 10 are provided that can control the controlled objects (12, 12b) and process the target signals from the controlled objects (12, 12b, 12c).

[0065] As described above, the present embodiment has various aspects as described below.

[0066] An analog-digital conversion circuit according to a first aspect of this embodiment comprises: a conversion control circuit including a period setting register, a count circuit, and a comparison circuit; and an analog-digital converter configured to perform AD conversion of a target signal from at least one control target, wherein the count circuit is configured to count a clock signal; the period setting register is configured to store a period value specifying a count period; the comparison circuit is configured to compare the count value of the count circuit with the period value and generate a comparison signal representing the result of the comparison; the comparison circuit causes the count circuit to repeatedly count each time the comparison signal indicates completion of the count; and the conversion control circuit is configured to generate a control signal for controlling activation of the control target based on the comparison signal and the count value, wherein the control signal has a first value indicating permission to activate the control target and a second value indicating permission to deactivate the control target, the activation period being equal to or smaller than the count period; and the analog-digital converter performs the AD conversion of the target signal during the count period.

[0067] The analog-to-digital conversion circuit of a second aspect according to the first aspect of this embodiment further includes a selector circuit having a plurality of inputs configured to receive a plurality of electrical signals from the controlled object and one or more second controlled objects different from the controlled object, and an output connected to the analog-to-digital converter, and the selector circuit can be configured to provide a signal from any one of the inputs of the selector circuit to an output in response to a selection signal.

[0068] In the analog-to-digital conversion circuit of the third aspect according to the second aspect of this embodiment, the conversion control circuit further includes a period control circuit, and the period control circuit can be configured to receive a target identification signal that identifies one of the control target and the second control target, and to generate the selection signal during the count period based on the received target identification signal.

[0069] In the analog-to-digital conversion circuit of the fourth aspect according to the third aspect of this embodiment, the period control circuit can be configured to generate an enable control signal based on the received target identification signal, and the enable control signal can be configured to identify one of the control target and the second control target as the control target to be activated.

[0070] The analog-to-digital conversion circuit of the fifth aspect according to the third or fourth aspect of this embodiment further comprises a storage circuit connected to the analog-to-digital converter, and the conversion control circuit further comprises a storage identification circuit that receives the object identification signal, and the storage identification circuit can be configured to store the analog-to-digital conversion value of the control object in the storage circuit in correspondence with the control object.

[0071] In the analog-to-digital conversion circuit of the sixth aspect according to the fifth aspect of this embodiment, the storage circuit includes an input selection circuit connected to an output of the analog-to-digital converter, a plurality of registers connected to the input selection circuit, and an output selection circuit connected to the registers, and the input selection circuit provides the analog-to-digital converted value to one of the registers based on an input register selection signal from the storage specifying circuit; The output selection circuit is capable of outputting a stored value from one of the registers based on an output register specification signal from the processing circuit.

[0072] In the analog-to-digital conversion circuit of the seventh aspect according to the sixth aspect of this embodiment, the storage specifying circuit can be configured to generate the input register selection signal based on the received target specifying signal and the comparison signal.

[0073] In the analog-to-digital conversion circuit of the eighth aspect according to any one of the third to seventh aspects of this embodiment, the conversion control circuit includes at least one storage device, and the storage device can provide the period value to the period setting register based on the target-specific signal.

[0074] In the analog-to-digital conversion circuit of the ninth aspect according to any one of the first to eighth aspects of this embodiment, the counting circuit may be configured to be reset and released from reset in response to the comparison signal indicating the expiration of the counting period, thereby performing the counting of the clock signal.

[0075] In an analog-to-digital conversion circuit of a tenth aspect according to any one of the first to ninth aspects of this embodiment, the controlled object may include a switch controlled by the first value and the second value of the control signal.

[0076] In the analog-to-digital converter circuit of the eleventh aspect according to the tenth aspect of this embodiment, the switch may include a transistor, and the control signal may be applied to a control terminal of the transistor.

[0077] In the analog-to-digital conversion circuit of the twelfth aspect according to the tenth or eleventh aspect of this embodiment, the controlled object includes a sensor element connected to the switch, and the target signal can be generated by the sensor element.

[0078] In an analog-to-digital conversion circuit of a thirteenth aspect according to any one of the first to twelfth aspects of this embodiment, the conversion control circuit includes a target control circuit, the target control circuit includes a determination circuit, a first register, and a second register, the first register stores a first setting value for each of the control objects that sets the control object to a first state, the second register stores a second setting value for each of the control objects that sets the control object to a second state different from the first state, and the determination circuit includes a first comparator and a second comparator, The first comparator may include a first comparator that performs a first comparison between the first set value and the count value, and the first comparator may generate a first signal indicative of a result of the first comparison, and the second comparator may include a second comparator that performs a second comparison between the second set value and the count value, and the second comparator may generate a second signal indicative of a result of the second comparison.

[0079] In the analog-to-digital conversion circuit of the fourteenth aspect according to the thirteenth aspect of this embodiment, the target control circuit includes a control signal generation circuit, and the control signal generation circuit can set the control signal to the first value in response to generation of the first signal, and can set the control signal to the second value in response to generation of the second signal.

[0080] The control system of the 15th aspect of this embodiment comprises an analog-to-digital conversion circuit described in any one of the 1st to 14th aspects, and a controlled device that is controlled by the first value and the second value of the control signal.

[0081] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0082] 10. Control system, 11. Semiconductor device, 12, 12b, 12c... Control target, 13. Analog-to-digital conversion circuit, 15... Conversion control circuit, 17. Analog-to-digital converter, 21. Period setting register, 23. Counting circuit, 25...comparison circuit, 27... Period setting circuit, 29... Period control circuit, 31...Selector circuit, 32···Output port circuit, 33···Input port circuit, 34 registers, 35...storage circuit, 35b Input selection circuit, 35c···Output selection circuit, 37···Storage specific circuit, 41...Target control circuit, 42···Hangar, 43b... First register, 43c...Second register, 43d...Determination circuit, 43f...1st comparator, 43g...Second comparator, 45...period adjustment circuit, 47···Target specific circuit, 49....Control signal generating circuit, 50, 50c...driver, 51 Processing circuit, CLK: Clock signal, DS: Sensor element, DSNS: Controlled element, LD...Load circuit, P0...signal, SAD: Analog-to-digital conversion value, SCMP...comparison signal, SCNT: Count value, SCNTL control signal, SDET···Target specific signal, SENB: Enable control signal, SLAT: Input register specific signal, SOUT: Output register specific signal, SRT...start signal, SSEL: Selection signal, SSNS, SSNS1, SSNS2, SSNS3, SSNS4... Target signal, SW Switch VPRD···period value, VTRM···Period.

Claims

1. a conversion control circuit including a period setting register, a count circuit, and a comparison circuit; an analog-to-digital converter configured to perform analog-to-digital conversion of a target signal from at least one control target; Equipped with the counting circuit is configured to count clock signals; the period setting register is configured to store a period value that specifies a count period; the comparison circuit is configured to compare the count value of the count circuit with the period value and generate a comparison signal representing a result of the comparison; the comparison circuit causes the count circuit to repeatedly perform the counting each time the comparison signal indicates the end of counting; the conversion control circuit is configured to generate a control signal for controlling activation of the controlled object based on the comparison signal and the count value; the control signal has a first value indicating permission to activate the control target and a second value indicating permission to deactivate the control target, the activation period is equal to or less than the count period; the analog-to-digital converter performs the AD conversion of the target signal during the count period; Analog-to-digital conversion circuit.

2. a selector circuit having a plurality of inputs configured to receive a plurality of electrical signals from the controlled object and one or more second controlled objects different from the controlled object, and an output connected to the analog-to-digital converter; the selector circuit is configured to provide a signal from any one of the inputs of the selector circuit to an output in response to a selection signal; 2. An analog-to-digital conversion circuit according to claim 1.

3. the conversion control circuit further includes a period control circuit; the period control circuit is configured to receive a target identification signal that identifies one of the control target and the second control target, and to generate the selection signal during the count period based on the received target identification signal; 3. An analog-to-digital conversion circuit according to claim 2.

4. The period control circuit generates an enable control signal based on the received target specific signal; the enable control signal is configured to identify one of the control object and the second control object as a control object to be activated.

4. An analog-to-digital conversion circuit according to claim 3.

5. a storage circuit coupled to the analog-to-digital converter; the conversion control circuit further comprises a storage identification circuit that receives the object identification signal; the storage device specifying circuit is configured to store the analog-to-digital converted value of the control object in the storage circuit in association with the control object; 4. An analog-to-digital conversion circuit according to claim 3.

6. the storage circuit includes an input selection circuit connected to an output of the analog-to-digital converter, a plurality of registers connected to the input selection circuit, and an output selection circuit connected to the registers; the input selection circuit provides the analog-to-digital converted value to one of the registers based on an input register selection signal from the storage specification circuit; the output selection circuit outputs a stored value from one of the registers based on an output register specifying signal from the processing circuit; 6. An analog-to-digital conversion circuit according to claim 5.

7. the storage specifying circuit is configured to generate the input register selection signal based on the received target specifying signal and the comparison signal; 7. An analog-to-digital conversion circuit according to claim 6.

8. the conversion control circuit includes at least one storage cell; the storage provides the period value to the period setting register based on the target specific signal; 4. An analog-to-digital conversion circuit according to claim 3.

9. the counting circuit is configured to be reset and released in response to the comparison signal indicating the expiration of the counting period, to perform the counting of the clock signal.

2. An analog-to-digital conversion circuit according to claim 1.

10. the controlled object includes a switch controlled by the first value and the second value of the control signal; 2. An analog-to-digital conversion circuit according to claim 1.

11. the switch includes a transistor; the control signal is applied to a control terminal of the transistor; 11. An analog-to-digital conversion circuit according to claim 10.

12. the controlled object includes a sensor element connected to the switch, the target signal is generated by the sensor element; 11. An analog-to-digital conversion circuit according to claim 10.

13. the conversion control circuit includes a target control circuit; the target control circuit includes a determination circuit, a first register, and a second register; the first register stores a first setting value for each of the control objects that sets the control object to a first state; the second register stores, for each of the control objects, a second setting value that sets the control object to a second state different from the first state; the determination circuit includes a first comparator and a second comparator; the first comparator includes a first comparator that performs a first comparison between the first set value and the count value; the first comparator generates a first signal indicative of a result of the first comparison; the second comparator includes a second comparator that performs a second comparison between the second set value and the count value; the second comparator generates a second signal indicative of a result of the second comparison.

2. An analog-to-digital conversion circuit according to claim 1.

14. the target control circuit includes a control signal generation circuit; the control signal generating circuit sets the control signal to the first value in response to generation of the first signal, and sets the control signal to the second value in response to generation of the second signal; 14. An analog-to-digital conversion circuit according to claim 13.

15. An analog-to-digital conversion circuit according to any one of claims 1 to 14; a control target device that is controlled by the first value and the second value of the control signal; A control system comprising:

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