Multi-channel parallel sampling high dynamic response analog-to-digital conversion method, system and device, and storage medium

Abstract

The invention discloses a multi-channel parallel sampling high-dynamic response analog-to-digital conversion method, system and equipment and a storage medium, and belongs to the technical field of power electronics and signal processing, and the method comprises the steps: configuring a high-speed analog-to-digital converter channel to form a parallel sampling module, carrying out the alternate sampling of an input power grid analog signal, and generating a discrete sampling sequence group; inputting to a control unit to extract feature data, and calculating to obtain a fluctuation feature value; constructing a channel clock control vector, sending the channel clock control vector to each high-speed analog-to-digital converter channel, adjusting a sampling trigger moment, and re-executing analog signal sampling to obtain a sampling sequence after phase compensation processing; performing waveform reconstruction processing to obtain continuous reconstruction waveform data; and performing electric energy integral operation, and outputting a dynamic metering result. According to the invention, the problems of slow response, sampling distortion and large metering error of the analog-to-digital conversion system under the conditions of frequency fluctuation, unsteady disturbance and bidirectional power in the prior art are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics and signal processing, and in particular to a multi-channel parallel sampling high dynamic response analog-digital conversion method, system, device and storage medium. BACKGROUND

[0002] Under the background of the gradual penetration of smart grid, microgrid and new energy system, high-precision sampling and dynamic metering of power grid power signals have become an important application direction of analog-digital conversion systems. Traditional analog-digital conversion methods generally use single-channel high-speed ADC combined with timing sampling mechanism to perform isochronous sampling processing on voltage, current and other analog quantities under steady-state conditions. However, in complex power environments such as grid frequency fluctuation, power flow switching, nonlinear load and distributed power supply access, the signal frequency deviates sharply and the harmonic components are rich, and the single-channel sampling system often has problems such as insufficient sampling density, time sequence drift and waveform distortion, which seriously affects the accuracy and real-time performance of subsequent power metering, protection control and state perception.

[0003] Some existing technologies attempt to introduce multi-channel sampling structure or increase ADC sampling rate to cope with dynamic signal environment, but still cannot effectively compensate for the sampling distortion caused by phase shift under frequency disturbance conditions. In addition, most existing analog-digital conversion methods lack a cooperative clock synchronization mechanism and dynamic frequency perception capability among channels, resulting in significant metering result errors in scenes such as harmonic mutation and reverse power flow. At the same time, the traditional signal processing process does not fully consider the energy integration correction requirement under the change of power flow direction, and it is difficult to meet the high reliability requirement of smart distribution network and bidirectional power metering. SUMMARY

[0004] To solve the above technical problems, a multi-channel parallel sampling high dynamic response analog-digital conversion method is proposed, which includes configuring N high-speed analog-digital converter channels to form a parallel sampling module, alternately sampling the input grid analog signal, and generating a discrete sampling sequence group;

[0005] The discrete sampling sequence group is input to a DSP control unit, feature data representing the trend of grid frequency change is extracted, and a frequency fluctuation feature value at the current time is calculated;

[0006] A channel clock control vector is constructed based on the frequency fluctuation feature value, the channel clock control vector is sent to each high-speed analog-digital converter channel, the sampling trigger time is adjusted according to the respective control parameters, and the analog signal sampling is re-executed to obtain a phase-compensated sampling sequence;

[0007] The phase-compensated sampling sequence is subjected to waveform reconstruction processing to obtain continuous reconstructed waveform data;

[0008] The continuous complete waveform data is subjected to an electric energy integral operation in combination with a trend direction marking signal, and a dynamic measurement result is output.

[0009] As a preferred scheme of the high dynamic response analog-digital conversion method of multi-channel parallel sampling, in the scheme, each high-speed analog-digital converter channel in the parallel sampling module operates at a unified clock frequency, and the sampling phase difference between any two channels is a variable by setting a sampling initial phase offset, and the discrete sampling sequence groups are sequentially output according to sampling time, covering the whole sampling period.

[0010] As a preferred scheme of the high dynamic response analog-digital conversion method of multi-channel parallel sampling, in the scheme, the DSP control unit extracts a frequency variation indication quantity for calculating the frequency fluctuation characteristic value based on the discrete sampling sequence groups.

[0011] The frequency variation indication quantity represents a phase variation trend or a period characteristic of the power grid analog signal in the current sampling period.

[0012] As a preferred scheme of the high dynamic response analog-digital conversion method of multi-channel parallel sampling, in the scheme, the DSP control unit constructs a channel clock control vector according to the frequency fluctuation characteristic value.

[0013] The channel clock control vector contains a sampling trigger parameter configuration field of each high-speed analog-digital converter channel, representing the sampling phase difference adjustment relationship between channels.

[0014] As a preferred scheme of the high dynamic response analog-digital conversion method of multi-channel parallel sampling, in the scheme, after each high-speed analog-digital converter channel receives the channel clock control vector, the sampling trigger parameter of the corresponding channel is extracted therefrom, and the parameter is configured to a sampling control unit.

[0015] The sampling control unit adjusts the excitation time of the sampling trigger circuit according to the configured parameter, and re-executes the sampling of the analog signal to generate a sampling sequence after phase compensation processing.

[0016] The preferred technical scheme has the beneficial effects that: through the sampling trigger control at the channel level, the sampling phase is quickly corrected in the current period, avoiding the problems of sampling window overlap or omission caused by channel timing offset; the time consistency of multi-channel sampling under the condition of non-steady-state power grid signals is improved, the waveform reconstruction error caused by phase jitter between sampling points is reduced; the adaptive ability of the system to dynamic frequency variation is enhanced without global synchronization intervention, and the structural integrity and time continuity of the sampling data are improved.

[0017] As a preferred scheme of the multi-channel parallel sampling high dynamic response analog-digital conversion method, wherein: the waveform reconstruction processing of the phase compensation sampling sequence includes,

[0018] Performing time domain supplement point processing on the phase compensation sampling sequence based on Lagrange interpolation method to reconstruct an isochronous sample sequence;

[0019] Performing fast Fourier transform on the reconstructed sequence to extract main harmonic and distortion components;

[0020] According to the harmonic correction model defined by IEEE 1459 standard, dynamically adjusting the amplitude and phase of each frequency band to complete the frequency domain harmonic correction;

[0021] Performing inverse transform on the corrected frequency domain data to restore the time domain waveform and generate continuous complete waveform data;

[0022] The frequency domain harmonic correction adopts a dynamic window width adaptive algorithm;

[0023] When the frequency change exceeds a set threshold, the FFT transform window is shortened;

[0024] In the frequency stable state, the window is expanded to optimize the harmonic frequency resolution;

[0025] The window length is adjusted as a driving factor of the frequency change rate and meets the minimum frequency leakage criterion.

[0026] The beneficial effects of the preferred technical scheme are: the uniformity of the sampling points on the time axis under non-uniform sampling conditions is improved, and the amplitude distortion caused by sampling jitter in the reconstructed waveform is reduced;

[0027] The adaptability to harmonic drift and sudden distortion in non-stationary power grid signals is enhanced, and the accuracy of harmonic identification and compensation is improved; by introducing a frequency-driven window width adaptive mechanism, the continuity and stability of the waveform reconstruction result are effectively guaranteed under the premise of considering the frequency response speed and frequency domain resolution, which provides high-fidelity input data for subsequent integration and direction judgment.

[0028] As a preferred scheme of the multi-channel parallel sampling high dynamic response analog-digital conversion method, wherein: the waveform reconstruction processing of the phase compensation sampling sequence includes,

[0029] Combining the power flow direction marker signal on the access side of the power grid to determine the active direction corresponding to the current waveform data;

[0030] Performing periodic integration operation on the continuous complete waveform data to calculate the periodic energy value;

[0031] Correct the integral sign based on the result of the power flow direction judgment, and output the dynamic metering result consistent with the direction;

[0032] The dynamic metering result is processed by sliding average, and the power and energy curves with high time resolution are output.

[0033] The beneficial effects of the preferred technical scheme are: the problem of inaccurate direction judgment of electric energy integral result in the bidirectional power flow scene is solved, the real-time and stability of active power direction identification are improved; the integral sign continuity of electric energy calculation in the power flow switching process is ensured, and the metering accumulation error caused by direction drift is avoided; by introducing the sliding average processing mechanism, the time resolution and curve smoothness of dynamic power output are enhanced, which is beneficial to realize stable and accurate energy metering under the conditions of new energy access and frequent load variation.

[0034] Another object of the present application is to provide a multi-channel parallel sampling high dynamic response analog-digital conversion system, which solves the problems of slow response, sampling distortion and large metering error of the analog-digital conversion system in the prior art under the conditions of frequency fluctuation, non-steady-state disturbance and bidirectional power.

[0035] As a preferred scheme of the multi-channel parallel sampling high dynamic response analog-digital conversion system, it is characterized by comprising a parallel sampling module, a frequency extraction and sampling control module, a waveform reconstruction and harmonic correction module, and an electric energy integration and direction judgment module.

[0036] The parallel sampling module is configured with a plurality of high-speed analog-digital converter channels, which operate at a unified clock frequency. By setting the initial phase offset of sampling, the channels are alternately sampled to generate a group of discrete sampling sequences covering the entire sampling period.

[0037] The frequency extraction and sampling control module extracts the frequency variation characteristics in the discrete sampling sequence, calculates the frequency fluctuation characteristic value, constructs a channel clock control vector based on the characteristic value, and sends it to each sampling channel to adjust the sampling trigger time, thereby generating a phase compensation sampling sequence.

[0038] The waveform reconstruction and harmonic correction module performs interpolation point filling and frequency domain correction on the phase compensation sampling sequence to generate continuous and complete waveform data.

[0039] The electric energy integration and direction judgment module combines the power flow direction marking signal to perform period-by-period integration and sign correction on the continuous waveform data, and outputs the dynamic metering result with high time resolution.

[0040] A computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the steps of the multi-channel parallel sampling high dynamic response analog-digital conversion method when executing the computer program.

[0041] A computer readable storage medium stores a computer program, and the computer program implements the steps of the multi-channel parallel sampling high dynamic response analog-digital conversion method when executed by a processor.

[0042] The present application has the following beneficial effects: the present application constructs a multi-channel high-speed ADC parallel sampling architecture with a phase difference of 2π / N, and combines a DSP control unit to extract the frequency fluctuation characteristics in real time, thereby realizing a fast response to frequency dynamic disturbance. The channel clock control vector generated dynamically is used to drive each ADC channel to perform sampling trigger phase compensation, thereby effectively improving the sampling density and significantly reducing the sampling drift error caused by frequency offset. Finally, the continuous complete waveform is reconstructed through time domain interpolation and frequency domain harmonic correction, thereby ensuring the high dynamic response capability of analog-digital conversion and the accuracy of power grid signal restoration.

[0043] The present application adopts a dynamic metering method linked with the power grid flow direction signal, thereby realizing high-precision output of energy integration calculation based on waveform reconstruction, and accurately identifying the active power flow direction through the direction marking mechanism, and being suitable for the distributed energy bidirectional power flow scene. Compared with the traditional one-way sampling metering method, the metering accuracy and power flow tracking capability in the complex operation mode of new energy power grid and electric energy bidirectional transaction are significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0045] Figure 1 A multi-channel parallel sampling high dynamic response analog-digital conversion method provided by an embodiment of the present application has a general flowchart. DETAILED DESCRIPTION

[0046] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings in the specification. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the protection scope of the present application.

[0047] Example 1, referring to Figure 1 This is the first embodiment of the present invention, which provides a high dynamic response analog-to-digital conversion method with multi-channel parallel sampling, comprising:

[0048] S1. Configure N high-speed analog-to-digital converter channels to form a parallel sampling module, which alternately samples the input power grid analog signal to generate a discrete sampling sequence group;

[0049] S11: Configure N ADC channels, where N is a positive integer, and the multiple ADC channels form a parallel sampling module with the same clock frequency;

[0050] S12: For the input single-phase or three-phase power grid analog signal, set the initial sampling phase of each ADC channel so that the sampling phase difference between two adjacent channels is 2π / N;

[0051] S13: Each ADC channel sequentially acquires analog signal samples according to the set phase difference, generating a discrete sampling sequence group containing N discrete sampling sequences;

[0052] S14: After marking the discrete sampling sequence groups with time tags, output them synchronously to form a unified data stream format for subsequent processing modules to parse.

[0053] The above steps, by constructing a phase-interleaved ADC channel structure, achieve high time-resolution sampling of power grid analog signals, providing a high-quality data foundation for subsequent frequency dynamic modeling and sampling accuracy improvement.

[0054] S2. Input the discrete sampling sequence group into the DSP control unit, extract the feature data characterizing the trend of power grid frequency change, and calculate the frequency fluctuation feature value at the current moment;

[0055] S21: Input the discrete sampling sequence group to the DSP control unit and extract the sampling peak value, zero crossing point and period length of each channel;

[0056] S22: Construct a short-time Fourier transform window based on the extracted feature points, and perform time-frequency transformation on the sampling sequence of each channel;

[0057] S23: Extract the main frequency component and its instantaneous offset based on the transformation result, and calculate the frequency fluctuation characteristic value of the current power grid signal. The calculation formula is as follows:

[0058]

[0059] Among them, f var φ(t) represents the frequency fluctuation characteristic value at time t, and φ(t) represents the instantaneous change function of the fundamental phase over time, extracted by short-time Fourier transform. The derivative, representing the phase change, reflects the trend of signal frequency shift;

[0060] S24: Perform median filtering on the frequency fluctuation characteristic values ​​to suppress the impact of abnormal fluctuations on control accuracy;

[0061] The above steps extract frequency fluctuation characteristics through the DSP unit, effectively capturing frequency disturbance behavior in the power grid signal, and providing real-time basis for dynamic sampling phase adjustment and error suppression.

[0062] S3. Construct a channel clock control vector based on the frequency fluctuation characteristic value, send the channel clock control vector to each high-speed analog-to-digital converter channel, adjust the sampling trigger time according to their respective control parameters, and re-execute analog signal sampling to obtain the sampling sequence after phase compensation processing;

[0063] In a preferred embodiment of the present invention, the channel clock control vector is constructed and sent to each high-speed analog-to-digital converter channel, and the sampling trigger time is adjusted according to their respective control parameters.

[0064] S31: Construct the channel clock control function based on the frequency fluctuation characteristic value calculated in S2;

[0065] S32: Based on the current sampling period, dynamically solve for the optimal sampling phase offset of each ADC channel;

[0066] S33: Organize the sampling phase offset of each channel into a channel clock control vector, and generate a phase modulation identifier field for each channel;

[0067] S34: Upload the channel clock control vector to the ADC channel synchronization control module for dynamic calibration of sampling timing;

[0068] The above steps, by establishing a frequency-aware channel clock control vector mechanism, enable real-time optimization and adjustment of the ADC sampling phase, thereby improving the response sensitivity of the analog-to-digital conversion system under frequency disturbance conditions.

[0069] S35: Receive channel clock control vector for each ADC channel, and calculate the corresponding actual sampling delay;

[0070] S36: Map the sampling delay to the hardware sampling trigger circuit, and adjust the trigger time through a delay phase-locked loop (DLL) or a digital delay module;

[0071] S37: Resample the analog signal at the adjusted trigger time to generate a phase-compensated sampling sequence;

[0072] S38: Compare the sampling phase difference before and after phase compensation, record the dynamic correction offset and upload it to the data feedback interface.

[0073] The above steps effectively achieve dynamic phase compensation for each ADC channel by adjusting the sampling trigger time driven by phase control, thereby improving the time consistency of multi-channel sampling under frequency variation conditions.

[0074] In one optional embodiment of the present invention, the process of constructing a channel clock control vector and using it to dynamically adjust the sampling trigger time of each high-speed analog-to-digital converter channel includes the following steps:

[0075] S31′: Based on the frequency fluctuation characteristic value obtained in step S2, determine the target sampling phase correction amount of multiple channels according to the preset piecewise linear mapping function. The mapping function takes the frequency offset amplitude as input and adaptively outputs the phase offset reference value.

[0076] S32′: Based on the current system synchronization reference clock, construct a channel control instruction set containing the channel number, sampling time adjustment amount, and timing valid identifier fields. The instruction set is used to describe the timing redefinition parameters of the sampling trigger behavior of each channel.

[0077] S33′: The channel control instruction set is sent to the corresponding high-speed analog-to-digital converter channel control unit through a serial peripheral interface (such as SPI or I2C). The control unit receives and loads the timing adjustment parameters before the start of the next sampling period.

[0078] S34′: Each high-speed analog-to-digital converter channel adjusts the amount of the received sampling time, calculates the actual trigger delay value in its internal timer, and uses digital delay control logic to realize the time offset of the sampling start signal, so that each channel can re-complete the analog signal sampling and generate a sampling sequence after phase compensation processing.

[0079] It should be further explained that:

[0080] This preferred embodiment constructs a frequency-aware channel clock control function in the DSP control unit, and calculates the optimal sampling phase offset for each channel in real time based on this function. This generates a channel clock control vector containing a phase modulation identifier field, which is then synchronously uploaded to the sampling control module of the ADC channel, achieving dynamic adjustment within the sampling trigger time period. After receiving the control vector, each high-speed analog-to-digital converter channel calculates the sampling delay and performs trigger correction through a digital delay module or delay-locked loop (DLL), generating a sampling sequence after phase compensation processing.

[0081] This scheme effectively establishes a closed-loop control link of "frequency disturbance detection - control vector generation - dynamic phase adjustment compensation", which can adjust the phase relationship of multi-channel sampling in real time according to the grid frequency fluctuation. Under non-steady-state operating scenarios such as grid signal frequency change and periodic drift, it can still maintain the consistency and relative stability of the sampling timing between channels, providing structurally continuous and temporally uniform sampling data support for subsequent waveform reconstruction and energy integration, and significantly improving the phase consistency and response sensitivity of the analog-to-digital conversion system under dynamic operating conditions.

[0082] S4. Perform waveform reconstruction processing on the sampled sequence after phase compensation to obtain continuously reconstructed waveform data;

[0083] In a preferred embodiment of the present invention, waveform reconstruction processing is as follows:

[0084] S41: Perform time-domain interpolation based on Lagrange interpolation on the phase-compensated sampling sequence to reconstruct the sample sequence at the same time step. The Lagrange interpolation calculation formula is as follows:

[0085]

[0086] Where x(t) represents the reconstructed signal value at time t after interpolation, x i t represents the known value of the i-th sampling point. i ,t j These are the known sampling times, and n represents the interpolation order, which is usually 2 or 3 to balance accuracy and computational cost.

[0087] S42: Perform a fast Fourier transform on the reconstructed sequence to extract the main harmonics and their distortion components;

[0088] S43: Based on the harmonic correction model defined by the IEEE 1459 standard, dynamically adjust the amplitude and phase of each frequency band to complete frequency domain harmonic correction;

[0089] S44: Perform an inverse transform on the corrected frequency domain data to restore it to the time domain waveform, generating continuous and complete waveform data;

[0090] The above steps combine time-domain interpolation with frequency-domain harmonic compensation to reconstruct high-precision power grid signal waveforms, enhancing the analog-to-digital conversion system's ability to recover distorted signals.

[0091] In an optional embodiment of the present invention, waveform reconstruction processing of the sampled sequence after phase compensation includes the following steps:

[0092] S41′: Perform time alignment processing based on piecewise linear interpolation on the phase-compensated sampling sequence to construct a reconstructed sampling point sequence with equal time intervals. The linear interpolation is approximated by a linear function between two adjacent known sampling points.

[0093] S42′: Input the time-aligned reconstructed sampling point sequence into the multi-resolution wavelet transform module, and use the Daubechies wavelet to perform multi-scale decomposition to extract signal components and abnormal disturbance features in different frequency bands.

[0094] S43′: Based on the set amplitude threshold and frequency band distribution rules, filter the non-fundamental part of the wavelet coefficients to remove local interference introduced by frequency abrupt changes, and retain the fundamental and low-order effective harmonic components.

[0095] S44′: Perform inverse wavelet transform on the wavelet components that retain valid information to reconstruct a complete time-domain signal, resulting in continuously reconstructed waveform data.

[0096] This preferred embodiment introduces time-domain reconstruction processing based on Lagrange interpolation on top of the phase-compensated sampling sequence, reconstructing the sampling points into a sample sequence with equal time distribution on the time axis, thereby eliminating the time offset problem caused by inconsistent sampling timing of each channel. Subsequently, the main harmonics and distortion components in the frequency domain are extracted by Fast Fourier Transform, and the amplitude and phase of each component in the frequency band are dynamically corrected based on the harmonic correction model defined by the IEEE 1459 standard. Finally, the corrected frequency domain data is inversely transformed into a time domain waveform to obtain continuous waveform data with complete structure and consistent timing.

[0097] This processing flow organically combines interpolation reconstruction with frequency domain harmonic analysis, constructing a composite recovery path from non-uniform sampling data to standard time-series waveforms. It can effectively restore the original waveform characteristics of the signal under non-ideal conditions such as high-order harmonic interference and phase jumps, providing accurate basic data for subsequent energy integration and direction determination.

[0098] S5. Combine the power flow direction marking signal to perform energy integration calculation on the continuous complete waveform data, and output dynamic metering results.

[0099] S51: Combine the power flow direction marking signal on the grid side to determine the active power direction corresponding to the current waveform data;

[0100] S52: Performs cycle-by-cycle integration on continuous complete waveform data to calculate the cycle energy value;

[0101] S53: Correct the integral sign based on the power flow direction judgment result, and output dynamic measurement results with consistent direction;

[0102] S54: Performs moving average processing on the dynamic metering results and outputs power and energy curves with high time resolution.

[0103] The above steps, by introducing power flow direction markers and combining them with high-precision integral calculation methods, improve the accuracy of the analog-to-digital conversion system in sensing and measuring the power grid energy flow direction.

[0104] Frequency domain harmonic correction employs a dynamic window width adaptive algorithm, specifically including:

[0105] When the frequency change exceeds a set threshold, shorten the FFT transform window to improve response speed;

[0106] In a frequency-stable state, the window is expanded to improve harmonic frequency resolution;

[0107] The window length adjustment is driven by the frequency change rate and satisfies the minimum frequency leakage criterion.

[0108] Example 2 is the second embodiment of the present invention, which differs from the previous embodiment in that:

[0109] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0110] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0111] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0112] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0113] Example 3 is the third embodiment of the present invention. This embodiment provides a high dynamic response analog-to-digital conversion system with multi-channel parallel sampling, including a parallel sampling module, a frequency extraction and sampling control module, a waveform reconstruction and harmonic correction module, and an energy integration and direction determination module.

[0114] The parallel sampling module is configured with several high-speed analog-to-digital converter channels, which operate at a uniform clock frequency. By setting the initial sampling phase offset, it completes alternating sampling between channels and generates a discrete sampling sequence group covering the entire sampling period.

[0115] The frequency extraction and sampling control module extracts the frequency change features in the discrete sampling sequence, calculates the frequency fluctuation feature value, constructs a channel clock control vector based on the feature value, sends it to each sampling channel to adjust the sampling trigger time, and generates a phase-compensated sampling sequence.

[0116] The waveform reconstruction and harmonic correction module performs interpolation and frequency domain correction on the phase-compensated sampling sequence to generate continuous and complete waveform data.

[0117] The energy integration and direction determination module combines the power flow direction marker signal to perform cycle-by-cycle integration and sign correction on continuous waveform data, and outputs dynamic measurement results with high time resolution.

[0118] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high dynamic response analog-to-digital conversion method with multi-channel parallel sampling, characterized in that: include, A parallel sampling module is configured with N high-speed analog-to-digital converter channels to alternately sample the input power grid analog signal and generate a discrete sampling sequence group. The discrete sampling sequence group is input to the DSP control unit to extract feature data characterizing the trend of power grid frequency change, and to calculate the frequency fluctuation feature value at the current moment. Based on the frequency fluctuation characteristic value, a channel clock control vector is constructed. The channel clock control vector is sent to each high-speed analog-to-digital converter channel. The sampling trigger time is adjusted according to their respective control parameters, and the analog signal sampling is re-executed to obtain the sampling sequence after phase compensation processing. The sampled sequence after phase compensation is subjected to waveform reconstruction processing to obtain continuously reconstructed waveform data. The continuous and complete waveform data is integrated with the power flow direction marker signal to perform energy integration calculation and output dynamic metering results.

2. The high dynamic response analog-to-digital conversion method with multi-channel parallel sampling as described in claim 1, characterized in that: Each high-speed analog-to-digital converter channel in the parallel sampling module operates at a uniform clock frequency. By setting the initial sampling phase offset, the sampling phase difference between any two channels is used as the independent variable. The discrete sampling sequence group is output in the order of sampling time, covering the entire sampling period.

3. The high dynamic response analog-to-digital conversion method with multi-channel parallel sampling as described in claim 2, characterized in that: The DSP control unit extracts frequency change indicators for calculating frequency fluctuation characteristic values ​​based on discrete sampling sequence groups; The frequency change indicator characterizes the phase change trend or periodic characteristics of the power grid analog signal within the current sampling period.

4. The high dynamic response analog-to-digital conversion method with multi-channel parallel sampling as described in claim 3, characterized in that: The DSP control unit constructs a channel clock control vector based on the frequency fluctuation characteristic value; The channel clock control vector contains several sampling trigger parameter configuration fields for high-speed analog-to-digital converter channels, representing the sampling phase difference adjustment relationship between channels.

5. The high dynamic response analog-to-digital conversion method with multi-channel parallel sampling as described in claim 4, characterized in that: After receiving the channel clock control vector, each high-speed analog-to-digital converter channel extracts the corresponding channel's sampling trigger parameters and configures the parameters to the sampling control unit. The sampling control unit adjusts the excitation time of the sampling trigger circuit according to the configured parameters, and re-executes analog signal sampling to generate a sampling sequence after phase compensation processing.

6. The high dynamic response analog-to-digital conversion method with multi-channel parallel sampling as described in claim 4, characterized in that: The step of performing waveform reconstruction processing on the phase-compensated sampled sequence to obtain continuously reconstructed waveform data includes, The phase-compensated sampling sequence is subjected to time-domain interpolation based on Lagrange interpolation to reconstruct the sample sequence at the same time step. Perform a Fast Fourier Transform on the reconstructed sequence to extract the main harmonics and distortion components; Based on the harmonic correction model defined in the IEEE 1459 standard, the amplitude and phase of each frequency band are dynamically adjusted to complete the frequency domain harmonic correction. Perform an inverse transform on the corrected frequency domain data to restore it to the time domain waveform, generating continuous and complete waveform data; The frequency domain harmonic correction employs a dynamic window width adaptive algorithm. When the frequency change exceeds a set threshold, the FFT transform window is shortened; Under stable frequency conditions, the extended window optimizes harmonic frequency resolution; The window length adjustment is driven by the frequency change rate and satisfies the minimum frequency leakage criterion.

7. The high dynamic response analog-to-digital conversion method with multi-channel parallel sampling as described in claim 4, characterized in that: The step of performing energy integration calculations on the continuous and complete waveform data in conjunction with the power flow direction marker signal, and outputting dynamic metering results, includes... By combining the power flow direction marking signal on the grid side, the active power direction corresponding to the current waveform data is determined; Perform cycle-by-cycle integration on the continuous complete waveform data to calculate the cycle energy value; The integral sign is corrected based on the power flow direction judgment result, and the dynamic measurement result with the same direction is output. The dynamic measurement results are processed by moving average and output with high time resolution power and energy curves.

8. A high dynamic response analog-to-digital converter system with multi-channel parallel sampling, employing the high dynamic response analog-to-digital converter method with multi-channel parallel sampling as described in any one of claims 1 to 7, characterized in that, Includes: a parallel sampling module, a frequency extraction and sampling control module, a waveform reconstruction and harmonic correction module, and an energy integration and direction determination module; The parallel sampling module is configured with several high-speed analog-to-digital converter channels, which operate at a uniform clock frequency. By setting the initial sampling phase offset, it completes alternating sampling between channels and generates a discrete sampling sequence group covering the entire sampling period. The frequency extraction and sampling control module extracts the frequency change features in the discrete sampling sequence, calculates the frequency fluctuation feature value, constructs a channel clock control vector based on the feature value, sends it to each sampling channel to adjust the sampling trigger time, and generates a phase-compensated sampling sequence. The waveform reconstruction and harmonic correction module performs interpolation and frequency domain correction on the phase-compensated sampling sequence to generate continuous and complete waveform data. The energy integration and direction determination module combines the power flow direction marker signal to perform cycle-by-cycle integration and sign correction on continuous waveform data, and outputs dynamic measurement results with high time resolution.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the high dynamic response analog-to-digital conversion method for multi-channel parallel sampling as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the high dynamic response analog-to-digital conversion method for multi-channel parallel sampling as described in any one of claims 1 to 7.

Images