Pixel circuit and display device including the same

Abstract

To provide a pixel circuit in which the reliability of compensation voltage is improved, and a display device including the same.SOLUTION: A pixel circuit includes a first transistor that applies a driving current to a second node in response to the voltage at a first node, a second transistor that applies a data voltage to a third node in response to a writing gate signal, a third transistor that couples the first and second nodes in response to the writing gate signal, a fourth transistor that couples the second and fourth nodes in response to a light emission signal, a fifth transistor that applies an initializing voltage to the fourth node in response to a bias gate signal, a sixth transistor that applies a reference voltage to the third node in response to an initializing gate signal, a seventh transistor that applies the reference voltage to the first node in response to a pre-stage writing gate signal, a light-emitting element, and a first accumulation capacitor including a first electrode coupled to the third node and a second electrode coupled to the first node.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a pixel circuit and a display device including the same, and more particularly to a pixel circuit with improved integration and a display device including the same. [Background technology]

[0002] In general, a display device includes a display panel and a display panel driver. The display panel includes gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver that provides gate signals to the plurality of gate lines, a data driver that provides data voltages to the data lines, an emission driver that provides emission signals to the emission lines, and a driver controller that controls the gate driver, the data driver, and the emission driver.

[0003] In a conventional pixel circuit with internal compensation, the body effect reduces the reliability of the compensation voltage, which in turn reduces the light emission reliability of the pixel circuit. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a pixel circuit with improved reliability of the compensation voltage.

[0005] Another object of the present invention is to provide a display device including the pixel circuit.

[0006] However, the problem to be solved by the present invention is not limited to the above problem, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0007] a sixth transistor for providing a reference voltage to the third node in response to a previous-stage write gate signal; a seventh transistor for providing the reference voltage to the first node in response to a previous-stage write gate signal; a light-emitting element including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage; and a first storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node.

[0008] The data voltage has one of a first data voltage to a K-th data voltage (where K is a natural number), and the value of the reference voltage has a value between the first data voltage to the K-th data voltage.

[0009] The reference voltage has an intermediate value between the first data voltage and the Kth data voltage.

[0010] The frame period in which the pixel circuit is driven includes a data write period, a hold period, and an emission period, and in the data write period, the write gate signal has an activation level, in the hold period, the emission signal has an activation level, and the bias gate signal has an activation level, and in the emission period, the emission signal has an activation level, and the bias gate signal has a deactivation level.

[0011] In the hold interval, the fourth transistor is turned on and the fifth transistor is turned on.

[0012] In a first section of a frame period in which the pixel circuit is driven, the previous stage write gate signal has an activation level, the initialization gate signal has an activation level, the sixth transistor is turned on, and the seventh transistor is turned on.

[0013] In the first interval, the bias gate signal has an activation level and the fifth transistor is turned on.

[0014] In a second interval following the first interval, the write gate signal has an activation level, and the second transistor and the third transistor are turned on.

[0015] In the second interval, the activation level of the bias gate signal is maintained, and the fifth transistor is maintained in an on state.

[0016] In a third interval following the second interval, the initialization gate signal has an activation level, and the sixth transistor is turned on.

[0017] In the third interval, the bias gate signal has an activation level, and the fifth transistor is turned on.

[0018] In a fourth interval following the third interval, the light-emitting signal has an activated level, the bias gate signal has a deactivated level, and the fifth transistor is turned off.

[0019] The first transistor further includes a second storage capacitor, and the first transistor includes a control electrode coupled to the first node, a first electrode to which a first power supply voltage is applied, and a second electrode coupled to the second node, and the second storage capacitor includes a first electrode coupled to the first node and a second electrode to which the first power supply voltage is applied.

[0020] The first transistor includes a control electrode connected to the first node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the second node, the second transistor includes a control electrode to which the write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the third node, the third transistor includes a control electrode to which the write gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the first node, and the fourth transistor includes a control electrode to which the light-emitting signal is applied, and a second electrode connected to the second node. the fifth transistor includes a control electrode to which the bias gate signal is applied, a first electrode connected to the fourth node, and a second electrode to which the initialization voltage is applied; the sixth transistor includes a control electrode to which the initialization gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the third node; and the seventh transistor includes a control electrode to which the previous stage write gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node.

[0021] a sixth transistor for providing a reference voltage to the third node in response to an initialization gate signal; a seventh transistor for providing the reference voltage to the first node in response to a control gate signal; a light-emitting element including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage; and a first storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node.

[0022] The data voltage has one of a first data voltage to a K-th data voltage (where K is a natural number), and the value of the reference voltage has a value between the first data voltage to the K-th data voltage.

[0023] The reference voltage has an intermediate value between the first data voltage and the Kth data voltage.

[0024] The frame period in which the pixel circuit is driven includes a data write period, a hold period, and an emission period, and in the data write period, the write gate signal has an activation level, in the hold period, the emission signal has an activation level, and the bias gate signal has an activation level, and in the emission period, the emission signal has an activation level, and the bias gate signal has a deactivation level.

[0025] A display device according to the present invention includes a display panel including a pixel circuit, a gate driver that outputs a write gate signal, a previous stage write gate signal, an initialization gate signal, and a bias gate signal to the display panel, a data driver that applies a data voltage to the display panel, and an emission driver that applies an emission signal to the display panel, wherein the pixel circuit includes a first transistor that applies a drive current to a second node in response to a voltage of a first node, a second transistor that applies the data voltage to a third node in response to the write gate signal, a third transistor that connects the first node and the second node in response to the write gate signal, and a third transistor that outputs a voltage to the emission signal. a fourth transistor responsively connecting the second node and a fourth node; a fifth transistor responsive to the bias gate signal to provide an initialization voltage to the fourth node; a sixth transistor responsive to the initialization gate signal to provide a reference voltage to the third node; a seventh transistor responsive to the previous stage write gate signal to provide the reference voltage to the first node; a light emitting element including a first electrode connected to the fourth node and a second electrode to which a second power supply voltage is applied; and a first storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node.

[0026] The data voltage has one of a first data voltage to a K-th data voltage (where K is a natural number), and the value of the reference voltage has a value between the first data voltage to the K-th data voltage.

[0027] The reference voltage has an intermediate value between the first data voltage and the Kth data voltage.

[0028] The frame period in which the pixel circuit is driven includes a data write period, a hold period, and an emission period, and in the data write period, the write gate signal has an activation level, in the hold period, the emission signal has an activation level, and the bias gate signal has an activation level, and in the emission period, the emission signal has an activation level, and the bias gate signal has a deactivation level.

[0029] The frame period in which the pixel circuit is driven includes a first period, a second period, a third period, and a fourth period, and in the first period, the bias gate signal has an activated level, the light emitting signal has an inactivated level, the previous stage write gate signal has an activated level, the initialization gate signal has an activated level, and the write gate signal has an inactivated level; and in the second period, the bias gate signal has an activated level, the light emitting signal has an inactivated level, the previous stage write gate signal has an inactivated level, and the initialization gate signal has an inactivated level. The write gate signal has an activation level, and in the third section, the bias gate signal has an activation level, the light emission signal has an activation level, the previous stage write gate signal has a deactivation level, the initialization gate signal has an activation level, and the write gate signal has a deactivation level, and in the fourth section, the bias gate signal has a deactivation level, the light emission signal has an activation level, the previous stage write gate signal has a deactivation level, the initialization gate signal has an activation level, and the write gate signal has a deactivation level.

[0030] The pixel circuit is disposed on a silicon-based substrate. [Effects of the Invention]

[0031] In such a pixel circuit and a display device including the same, a data voltage is not written through a source electrode of a drive transistor of the pixel circuit. Only the first power supply voltage can be applied to the source electrode of the drive transistor. As a result, the voltage applied to the source electrode of the drive transistor does not change. Because the voltage applied to the source electrode of the drive transistor does not change, the threshold voltage of the drive transistor does not change due to the body effect. In addition, the threshold voltage of the drive transistor remains substantially constant throughout the frame period. This improves the accuracy of the compensation voltage. The improved accuracy of the compensation voltage further improves the driving reliability and light emission reliability of the pixel circuit.

[0032] Furthermore, the reference voltage applied to the pixel circuit is greater than the first data voltage and less than the Kth data voltage. For example, the reference voltage has a value between the first data voltage and the Kth data voltage. This reduces the storage voltage, which is the voltage between the first electrode and the second electrode of the storage capacitor.

[0033] Furthermore, the frame period during which the pixel circuit is driven includes a hold period. During the hold period, a current flows along a path formed by the drive transistor, the light-emitting transistor, and the initialization transistor. This reduces the influence of parasitic capacitance during the light-emitting period. For example, when the pixel circuit must display black, the influence of parasitic capacitance is reduced, and the light-emitting element does not emit light. This improves the light-emitting reliability of the pixel circuit. Since the light-emitting reliability of the pixel circuit is improved, the display quality of the display panel is improved.

[0034] However, the effects of the present invention are not limited to the effects mentioned above, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0035] [Figure 1] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. [Figure 2]FIG. 2 is a cross-sectional view showing an example of a pixel transistor included in a pixel circuit of the display device of FIG. [Figure 3] FIG. 3 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. [Figure 4] FIG. 4 is a timing diagram showing input signals applied to the pixel circuit of FIG. [Figure 5] FIG. 5 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the first section of FIG. [Figure 6] FIG. 6 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the second interval of FIG. [Figure 7] FIG. 7 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the third interval of FIG. [Figure 8] FIG. 8 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the fourth interval of FIG. [Figure 9] FIG. 9 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. [Figure 10] FIG. 10 is a cross-sectional view showing an example of a storage capacitor included in the pixel circuit of FIG. [Figure 11] FIG. 11 is a plan view showing an example of a storage capacitor included in the pixel circuit of FIG. [Figure 12] FIG. 12 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. [Figure 13] FIG. 13 is a timing diagram showing input signals applied to the pixel circuit of FIG. [Figure 14] FIG. 14 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. [Figure 15] FIG. 15 is a diagram showing an example in which the pixel circuit of FIG. 2 is arranged on a substrate. [Figure 16] FIG. 16 is a block diagram illustrating an electronic device according to an embodiment of the present invention. [Figure 17] FIG. 17 is a diagram illustrating an example in which the electronic device of FIG. 16 is implemented as a smartphone. [Figure 18] FIG. 18 is a diagram illustrating an example in which the electronic device of FIG. 16 is implemented in a virtual reality display system. DETAILED DESCRIPTION OF THE INVENTION

[0036] The present invention will now be described in more detail with reference to the accompanying drawings.

[0037] FIG. 1 is a block diagram showing a display device 1 according to one embodiment of the present invention.

[0038] 1, the display device 1 includes a display panel 100 and a display panel driver. The display panel driver includes a driver control unit 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a light emitting driver 600.

[0039] The display panel 100 includes a display section that displays an image, and a peripheral section that is disposed adjacent to the display section.

[0040] The display panel 100 includes gate lines (GL), data lines (DL), emission lines (EL), and pixel circuits (PX) electrically connected to the gate lines (GL), data lines (DL), and emission lines (EL), respectively. The gate lines (GL) extend in a first direction (D1). The data lines (DL) extend in a second direction (D2) that intersects with the first direction (D1). The emission lines (EL) extend in the first direction (D1).

[0041] The drive control unit 200 may receive input image data (IMG) and an input control signal (CONT) from an external device. For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signal (CONT) may include a master clock signal and a data enable signal. The input control signal (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal.

[0042] The drive control unit 200 generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), and a data signal (DATA) based on input image data (IMG) and an input control signal (CONT).

[0043] The driving control unit 200 generates a first control signal (CONT1) for controlling the operation of the gate driver 300 based on the input control signal (CONT), and outputs the first control signal (CONT1) to the gate driver 300. The first control signal (CONT1) includes a vertical start signal and a gate clock signal.

[0044] The driving control unit 200 generates a second control signal (CONT2) for controlling the operation of the data driver 500 based on the input control signal (CONT), and outputs the second control signal (CONT2) to the data driver 500. The second control signal (CONT2) includes a horizontal start signal and a load signal.

[0045] The driving control unit 200 generates a data signal (DATA) based on the input image data (IMG), and outputs the data signal (DATA) to the data driver 500.

[0046] The drive control unit 200 generates a third control signal (CONT3) for controlling the operation of the gamma reference voltage generation unit 400 based on the input control signal (CONT), and outputs the third control signal to the gamma reference voltage generation unit 400.

[0047] The drive control unit 200 generates the fourth control signal (CONT4) for controlling the operation of the light emitting drive unit 600 based on the input control signal (CONT), and outputs the fourth control signal (CONT4) to the light emitting drive unit 600.

[0048] The gate driver 300 generates gate signals for driving the gate lines (GL) in response to a first control signal (CONT1) input from the drive control unit 200. The gate driver 300 outputs the gate signals to the gate lines (GL). For example, the gate signals include an initialization gate signal (GI in FIG. 3), a write gate signal (GW[n] in FIG. 3), a previous stage write gate signal (GW[n-1] in FIG. 3), a bias gate signal (GB in FIG. 3), and a control gate signal (GR in FIG. 12).

[0049] In one embodiment, the gate driver 300 is integrated into the periphery of the display panel 100. In one embodiment, the gate driver 300 is implemented in the periphery of the display panel 100.

[0050] The gamma reference voltage generator 400 generates a gamma reference voltage (VGREF) in response to a third control signal (CONT3) input from the driving control unit 200. The gamma reference voltage generator 400 provides the gamma reference voltage (VGREF) to the data driver 500. The gamma reference voltage (VGREF) has a value corresponding to each data signal (DATA).

[0051] For example, the gamma reference voltage generator 400 may be disposed in the driving control unit 200 or the data driver 500 .

[0052] The data driver 500 receives the second control signal (CONT2) and the data signal (DATA) from the drive control unit 200 and receives the gamma reference voltage (VGREF) from the gamma reference voltage generator 400. The data driver 500 converts the data signal (DATA) into an analog data voltage (VDATA) using the gamma reference voltage (VGREF). The data driver 500 outputs the data voltage (VDATA) to the data line (DL). The data voltages (VDATA) include a first data voltage to a K-th data voltage (where K is a natural number). For example, the first data voltage means a voltage for the pixel circuit (PX) to display 0 gradation. For example, the K-th data voltage means a voltage for the pixel circuit to display 255 gradation. However, the present invention is not limited to the gradations that the pixel circuit (PX) can display.

[0053] The light emission driving unit 600 generates a light emission signal (EM in FIG. 3) in response to a fourth control signal (CONT4) input from the driving control unit 200. The light emission driving unit 600 outputs the light emission signal (EM in FIG. 3) to the display panel 100.

[0054] In one embodiment, the light emitting driver 600 is integrated into the periphery of the display panel 100. In one embodiment, the light emitting driver 600 is mounted on the periphery of the display panel 100.

[0055] 1, for convenience of explanation, the gate driver 300 is shown to be disposed on a first side of the display panel 100 and the light-emitting driver 600 is shown to be disposed on a second side of the display panel 100, but this is not limiting. For example, both the gate driver 300 and the light-emitting driver 600 may be disposed on the first side of the display panel 100. For example, both the gate driver 300 and the light-emitting driver 600 may be disposed on both sides of the display panel 100. For example, the gate driver 300 and the light-emitting driver 600 may be integrally formed.

[0056] FIG. 2 is a cross-sectional view showing an example of a pixel transistor (TR) included in the pixel circuit (PX) of the display device 1 of FIG.

[0057] As shown in FIGS. 1 and 2, the substrate (PSUB) is a silicon substrate. For example, the substrate (PSUB) is a P-type silicon substrate. The substrate (PSUB) includes a well region (NWELL). The well region (NWELL) is an N-well. In this case, P means holes and N means electrons. A substrate voltage (VSUB) is applied to the substrate (PSUB). For example, the substrate voltage (VSUB) is a low power supply voltage (VSS). For example, the substrate voltage (VSUB) is the lowest voltage applied to the pixel circuit (PX).

[0058] The substrate (PSUB) includes a source region (SOURCE), a drain region (DRAIN), and a body region (BODY). For example, the source region (SOURCE) is a P-source region. For example, the drain region (DRAIN) is a P-drain region. For example, the body region (BODY) is an N-body region. For example, a source voltage (VS) is applied to the source region (SOURCE). A drain voltage (VD) is applied to the drain region (DRAIN). A body voltage (VB) is applied to the body region (BODY). For example, if the pixel transistor (TR) is a P-type transistor, the body voltage (VB) is a high power supply voltage (VDD) higher than the low power supply voltage (VSS). For example, the body voltage (VB) is the highest voltage applied to the pixel circuit (PX).

[0059] When the pixel transistor (TR) operates, the source voltage (VS) decreases. When the source voltage (VS) decreases, the absolute value of the threshold voltage of the pixel transistor (TR) changes. For example, the absolute value of the threshold voltage of the pixel transistor (TR) changes due to the body effect. For example, the absolute value of the threshold voltage of the pixel transistor (TR) changes according to Equation 1.

[0060] [Number 1] TIFF2025148278000002.tif558 Here, Vth is the threshold voltage after the change, Vth0 is the threshold voltage before the change, r is the body effect constant, sp is the surface potential of the well region (NWELL), and VSB is the difference between the source voltage (VS) and the body voltage (VB).

[0061] For example, if the pixel transistor (TR) is a P-type transistor, when the source voltage (VS) decreases, the absolute value of the threshold voltage of the pixel transistor (TR) increases.

[0062] When a data write operation is performed in a conventional pixel circuit, the reliability of the data write operation is reduced due to the body effect. For example, in the conventional pixel circuit, a conventional compensation voltage that takes into account the threshold voltage after the change due to the body effect is stored in a conventional storage capacitor. As a result, the conventional pixel circuit emits light based on the conventional compensation voltage, resulting in reduced driving reliability.

[0063] A gate insulating layer (GIL) is disposed on the substrate (PSUB). The gate insulating layer (GIL) may comprise an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiCx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), etc., which may be used alone or in combination with each other.

[0064] A gate electrode (GATE) is disposed on the gate insulating layer (GIL). The gate electrode (GATE) may include a metal, an alloy metal nitride, a conductive metal oxide, a transparent conductive material, etc. Examples of the metal include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and scandium (Sc). Examples of the conductive metal oxide include indium tin oxide and indium zinc oxide. Examples of the metal nitride include aluminum nitride (AlNx), tungsten nitride (WNx), and chromium nitride (CrNx).

[0065] FIG. 3 is a circuit diagram showing an example of a pixel circuit (PX) included in the display device 1 of FIG.

[0066] As shown in Figures 1 to 3, the pixel circuit (PXA) includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), a storage capacitor (CST), and a light-emitting element (EE).

[0067] The first transistor (T1) includes a control electrode coupled to a first node (N1), a first electrode to which a first power supply voltage (ELVDD) is applied, and a second electrode coupled to a second node (N2). The first transistor (T1) generates a drive current based on the voltage at the first node (N1). The first transistor (T1) provides the drive current to the second node (N2) in response to the voltage at the first node (N1). For example, the first transistor (T1) may be referred to as a drive transistor.

[0068] The second transistor (T2) includes a control electrode to which a write gate signal (GW[n]) is applied, a first electrode to which a data voltage (VDATA) is applied, and a second electrode connected to the third node (N3). The second transistor (T2) applies the data voltage (VDATA) to the third node (N3) in response to the write gate signal (GW[n]). For example, the second transistor (T2) is referred to as a write transistor.

[0069] The third transistor (T3) includes a control electrode to which a write gate signal (GW[n]) is applied, a first electrode coupled to the second node (N2), and a second electrode coupled to the first node (N1). The third transistor (T3) couples the first node (N1) and the second node (N2) in response to the write gate signal (GW[n]). The third transistor (T3) diode-connects the first transistor (T1) in response to the write gate signal (GW[n]). For example, the third transistor (T3) is referred to as a compensation transistor.

[0070] The fourth transistor (T4) includes a control electrode to which an emission signal (EM) is applied, a first electrode connected to the second node (N2), and a second electrode connected to the fourth node (N4). The fourth transistor (T4) connects the second node (N2) and the fourth node (N4) in response to the emission signal (EM). The fourth transistor (T4) provides the driving current to the fourth node (N4) in response to the emission signal (EM). For example, the fourth transistor (T4) is referred to as an emission transistor.

[0071] The fifth transistor (T5) includes a control electrode to which a bias gate signal (GB) is applied, a first electrode coupled to the fourth node (N4), and a second electrode to which an initialization voltage (VINT) is applied. The fifth transistor (T5) applies the initialization voltage (VINT) to the fourth node (N4) in response to the bias gate signal (GB). For example, the fifth transistor (T5) is referred to as a first initialization transistor.

[0072] In this embodiment, the initialization voltage (VINT) is lower than the second power supply voltage (ELVSS). For example, the value of the initialization voltage (VINT) is lower than the sum of the second power supply voltage (ELVSS) and the threshold voltage of the light-emitting element (EE) minus the absolute value of the threshold voltage of the fifth transistor (T5). As a result, when the initialization voltage (VINT) is applied to the fourth node (N4), the light-emitting element (EE) does not emit light. For example, when the initialization voltage (VINT) is applied to the fourth node (N4), the pixel circuit (PXA) displays black. Because the initialization voltage (VINT) is lower than the second power supply voltage (ELVSS), the black characteristics of the pixel circuit (PXA) are improved.

[0073] The initialization voltage (VINT) is the lowest voltage among the voltages applied to the pixel circuit (PXA), and is therefore the same as the substrate voltage (VSUB).

[0074] The sixth transistor (T6) includes a control electrode to which an initialization gate signal (GI) is applied, a first electrode to which a reference voltage (VREF) is applied, and a second electrode connected to the third node (N3). The sixth transistor (T6) applies the reference voltage (VREF) to the third node (N3) in response to the initialization gate signal (GI). For example, the sixth transistor (T6) is referred to as a second initialization transistor.

[0075] In this embodiment, the reference voltage (VREF) is greater than the first data voltage and less than the Kth data voltage. For example, the value of the reference voltage (VREF) is between the first data voltage and the Kth data voltage. In one embodiment, the value of the reference voltage (VREF) is an intermediate value between the first data voltage and the Kth data voltage. This reduces the storage voltage (VST in FIG. 9), which is the voltage between the first electrode and the second electrode of the storage capacitor (CST).

[0076] The seventh transistor (T7) includes a control electrode receiving a previous stage write gate signal (GW[n-1]), a first electrode receiving a reference voltage (VREF), and a second electrode coupled to the first node (N1). The seventh transistor (T7) provides the reference voltage (VREF) to the third node (N3) in response to the previous stage write gate signal (GW[n-1]). For example, the seventh transistor (T7) is referred to as a third initialization transistor.

[0077] The storage capacitor (CST) includes a first electrode coupled to the third node (N3) and a second electrode coupled to the first node (N1). The storage capacitor (CST) stores the difference between the voltage at the first node (N1) and the voltage at the third node (N3). The storage capacitor (CST) couples the change in the voltage at the third node (N3) and provides the coupled voltage to the first node (N1). For example, the storage capacitor (CST) is referred to as a first storage capacitor.

[0078] The light emitting element (EE) includes a first electrode coupled to the fourth node (N4) and a second electrode receiving the second power supply voltage (ELVSS). In one embodiment, the light emitting element (EE) is an organic light emitting diode (OLED), but is not limited thereto. In other embodiments, the light emitting element (EE) is a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other light emitting element.

[0079] FIG. 4 is a timing diagram showing input signals applied to the pixel circuit (PXA) of FIG.

[0080] As shown in Figures 1 to 4, the frame period in which the pixel circuit (PXA) is driven includes a first period (TP1A), a second period (TP2A), a third period (TP3A), and a fourth period (TP4A).

[0081] In the first section (TP1A), the bias gate signal (GB) has an activated level. The light emission signal (EM) has a deactivated level. The previous stage write gate signal (GW[n-1]) has an activated level. The initialization gate signal (GI) has an activated level. The write gate signal (GW[n]) has a deactivated level. For example, the first section (TP1A) is referred to as an initialization section.

[0082] In the second section (TP2A), the bias gate signal (GB) has an activated level. The light emission signal (EM) has an inactivated level. The previous stage write gate signal (GW[n-1]) has an inactivated level. The initialization gate signal (GI) has an inactivated level. The write gate signal (GW[n]) has an inactivated level. For example, the second section (TP2A) is referred to as a data write section.

[0083] In the third section (TP3A), the bias gate signal (GB) has an activated level. The light emission signal (EM) has an activated level. The previous stage write gate signal (GW[n-1]) has an inactivated level. The initialization gate signal (GI) has an activated level. The write gate signal (GW[n]) has an inactivated level. For example, the third section (TP3A) is referred to as a hold section.

[0084] In the fourth section (TP4A), the bias gate signal (GB) has an inactive level. The light emission signal (EM) has an active level. The previous stage write gate signal (GW[n-1]) has an inactive level. The initialization gate signal (GI) has an active level. The write gate signal (GW[n]) has an inactive level. For example, the fourth section (TP4A) is referred to as the light emission section.

[0085] FIG. 5 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in the first interval (TP1A) of FIG.

[0086] As shown in FIGS. 4 and 5, in the first section (TP1A), the sixth transistor (T6) is turned on in response to the initialization gate signal (GI). Since the sixth transistor (T6) is turned on, the reference voltage (VREF) is applied to the third node (N3). Since the sixth transistor (T6) is turned on, the reference voltage (VREF) is applied to the third node (N3). Since the seventh transistor (T7) is turned on, the reference voltage (VREF) is applied to the first node (N1). For example, the first node (N1) is initialized to the reference voltage (VREF). For example, the third node (N3) is initialized to the reference voltage (VREF). Since the reference voltage (VREF) is applied to the first node (N1) and the reference voltage (VREF) is applied to the third node (N3), the voltages of the first node (N1) and the third node (N3) are substantially the same. This initializes the storage capacitor (CST).

[0087] In the first section (TP1A), the first transistor (T1) is turned on in response to the voltage of the first node (N1).

[0088] In the first section (TP1A), the fifth transistor (T5) is turned on in response to the bias gate signal (GB). Since the fifth transistor (T5) is turned on, the initialization voltage (VINT) is applied to the fourth node (N4). Since the initialization voltage (VINT) is applied to the fourth node (N4), the light-emitting element (EE) stops emitting light.

[0089] FIG. 6 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in the second interval (TP2A) of FIG.

[0090] 4 and 6, in the second section (TP2A), the second transistor (T2) is turned on in response to the write gate signal (GW[n]). Since the second transistor (T2) is turned on, the data voltage (VDATA) is applied to the third node (N3).

[0091] In the second section (TP2A), the third transistor (T3) is turned on in response to the write gate signal (GW[n]). Because the third transistor (T3) is turned on, the first transistor (T1) is diode-connected. Because the first transistor (T1) is diode-connected, a voltage obtained by adding the threshold voltage of the first transistor (T1) and the first power supply voltage (ELVDD) is applied to the first node (N1). For example, the voltage obtained by adding the threshold voltage of the first transistor (T1) and the first power supply voltage (ELVDD) is referred to as a compensation voltage. The storage capacitor (CST) can store the difference between the data voltage (VDATA) and the compensation voltage.

[0092] In this embodiment, the first electrode of the first transistor T1 is a source electrode. Furthermore, the data voltage VDATA is not written through the source electrode of the first transistor T1. The source electrode of the first transistor T1 is applied with the first power supply voltage ELVDD. For example, the source electrode of the first transistor T1 is applied with only the first power supply voltage ELVDD. Therefore, the voltage applied to the source electrode of the first transistor T1 does not change. Since the voltage applied to the source electrode of the first transistor T1 does not change, the threshold voltage of the first transistor T1 does not change due to the body effect. Furthermore, the threshold voltage of the first transistor T1 remains substantially constant throughout the frame period. This improves the accuracy of the compensation voltage. This improves the driving reliability and light emission reliability of the pixel circuit PXA.

[0093] In the second section (TP2A), the fifth transistor (T5) is maintained in an on state in response to the bias gate signal (GB) having the inactivation level.

[0094] FIG. 7 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in the third period (TP3A) of FIG.

[0095] As shown in FIGS. 4 and 7, in the third section (TP3A), the sixth transistor (T6) is turned on in response to the initialization gate signal (GI). Because the sixth transistor (T6) is turned on, the reference voltage (VREF) is applied to the third node (N3). Because the third transistor (T3) is turned off, the first node (N1) is floating. The storage capacitor (CST) couples the voltage change at the third node (N3). The storage capacitor (CST) couples the voltage change at the third node (N3) and applies a coupling voltage to the first node (N1). Because the coupling voltage is applied to the first node (N1), the first node (N1) has a voltage that is equal to the compensation voltage and the data voltage (VDATA).

[0096] In the third section (TP3A), the first transistor (T1) generates the driving current based on the voltage of the first node (N1).

[0097] In the third section (TP3A), the fourth transistor (T4) is turned on in response to the light emitting signal (EM). Also, the fifth transistor (T5) is maintained in the on state in response to the bias gate signal (GB). As a result, the light emitting element (EE) does not emit light.

[0098] In a conventional pixel circuit, during an emission period, the reliability of the current supplied to a conventional light-emitting element included in the conventional pixel circuit is reduced due to the parasitic capacitance of at least one of the transistors included in the conventional pixel circuit. For example, when the conventional pixel circuit must display black, the parasitic capacitance supplies current to the conventional light-emitting element, causing the conventional light-emitting element to emit light. When the conventional pixel circuit must display black, the conventional light-emitting element emits light, resulting in a reduction in display quality.

[0099] However, the frame period in which the pixel circuit (PXA) is driven includes a third period (TP3A). During the third period (TP3A), a current flows along a path formed by the first transistor (T1), the fourth transistor (T4), and the fifth transistor (T5). This reduces the influence of the parasitic capacitance during the light-emitting period. For example, when the pixel circuit (PXA) needs to display black, the influence of the parasitic capacitance is reduced, and the light-emitting element (EE) does not emit light. This improves the light-emitting reliability of the pixel circuit (PXA). Since the light-emitting reliability of the pixel circuit (PXA) is improved, the display quality of the display panel 100 is improved.

[0100] FIG. 8 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in the fourth period (TP4A) of FIG.

[0101] 4 and 8, in the fourth section (TP4A), the fifth transistor (T5) is turned off in response to the bias gate signal (GB). This causes the driving current to be applied to the light-emitting element (EE). In the fourth section (TP4A), the light-emitting element (EE) emits light based on the driving current.

[0102] Fig. 9 is a circuit diagram showing an example of a pixel circuit (PXA) included in the display device 1 of Fig. 1. Fig. 10 is a cross-sectional view showing an example of a storage capacitor (CST) included in the pixel circuit (PXA) of Fig. 9.

[0103] 1, 9, and 10, the storage capacitor (CST) includes a first metal layer (METI1), an insulating layer (INS), and a second metal layer (METI2). The insulating layer (INS) is disposed on the first metal layer (METI1). The second metal layer (METI2) is disposed on the insulating layer (INS). For example, the storage capacitor (CST) has a metal layer-insulating layer-metal layer (MIM) structure.

[0104] In this embodiment, the reference voltage (VREF) is greater than the first data voltage and less than the K data voltage. For example, the value of the reference voltage (VREF) is between the first data voltage and the K data voltage. In one embodiment, the value of the reference voltage (VREF) is an intermediate value between the first data voltage and the K data voltage. This reduces the storage voltage (VST), which is the voltage between the first electrode and the second electrode of the storage capacitor (CST). Because the storage voltage (VST) is reduced, the metal pattern distance (MSO) is shortened. Because the metal pattern distance (MSO) is shortened, the integration degree of the pixel circuit (PXA) is improved. This makes the pixel circuit (PXA) applicable to ultra-high resolution display devices.

[0105] FIG. 11 is a plan view showing an example of a storage capacitor included in the pixel circuit of FIG.

[0106] 1, 9, and 11, the storage capacitor (CST) includes a first metal layer (METO1) and a second metal layer (METI2). For example, the storage capacitor (CST) has a metal layer-oxide-metal layer (MOM) structure.

[0107] In this embodiment, the reference voltage (VREF) is greater than the first data voltage and less than the K data voltage. For example, the value of the reference voltage (VREF) is between the first data voltage and the K data voltage. In one embodiment, the value of the reference voltage (VREF) is an intermediate value between the first data voltage and the K data voltage. This reduces the storage voltage (VST), which is the voltage between the first electrode and the second electrode of the storage capacitor (CST). Because the storage voltage (VST) is reduced, the metal pattern distance (MSO) is shortened. Because the metal pattern distance (MSO) is shortened, the integration degree of the pixel circuit (PXA) is improved. This makes the pixel circuit (PXA) applicable to ultra-high resolution display devices.

[0108] FIG. 12 is a circuit diagram showing an example of a pixel circuit (PX) included in the display device 1 of FIG.

[0109] 12, the pixel circuit (PXB) includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7B). Except for the fact that a control gate signal (GR) is applied to the seventh transistor (T7B) of the pixel circuit (PXB), the pixel circuit (PXB) is substantially the same as the pixel circuit (PXA). Therefore, components that are the same as or similar to those of the pixel circuit (PXA) are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0110] FIG. 13 is a timing diagram showing input signals applied to the pixel circuit (PXB) of FIG.

[0111] As shown in Fig. 13, the frame period in which the pixel circuit (PXB) is driven includes a first period (TP1B), a second period (TP2B), a third period (TP3B), and a fourth period (TP4B). The timing diagram of Fig. 13 is substantially the same as the timing diagram of Fig. 4 except for the length of the first period (TP1B). Therefore, input signals that are the same as or similar to those in the timing diagram of Fig. 4 are denoted by the same reference numerals and redundant description will be omitted.

[0112] 12 and 13, the control gate signal (GR) has an activated level in a first period (TP1B), an inactivated level in a second period (TP2B), an inactivated level in a third period (TP3B), and an inactivated level in a fourth period (TP4B).

[0113] In this embodiment, the frame period in which the pixel circuit (PXB) is driven includes a third period (TP3B). During the third period (TP3B), a current flows along a path formed by the first transistor (T1), the fourth transistor (T4), and the fifth transistor (T5). This reduces the influence of the parasitic capacitance during the light-emitting period. For example, when the pixel circuit (PXB) needs to display black, the influence of the parasitic capacitance is reduced, and the light-emitting element (EE) does not emit light. This improves the light-emitting reliability of the pixel circuit (PXB). Since the light-emitting reliability of the pixel circuit (PXB) is improved, the display quality of the display panel 100 is improved.

[0114] FIG. 14 is a circuit diagram showing an example of a pixel circuit (PX) included in the display device 1 of FIG.

[0115] 1 and 14, the pixel circuit (PXC) includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), a first storage capacitor (CST1), and a second storage capacitor (CST2). Except for the inclusion of the second storage capacitor (CST2), the pixel circuit (PXC) is substantially the same as the pixel circuit (PXA). Therefore, components that are the same as or similar to those in the pixel circuit (PXA) are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0116] In this embodiment, the pixel circuit (PXC) includes a second storage capacitor (CST2). The voltage of the first node (N1) is distributed to the first storage capacitor (CST1) and the second storage capacitor (CST2). This reduces the voltage load applied to the control electrode of the first transistor (T1). Because the voltage load is reduced, the element stability of the first transistor (T1) is improved. Furthermore, because the voltage load is reduced, the voltage range of the first data voltage to the Kth data voltage is increased.

[0117] FIG. 15 is a diagram showing an example in which the pixel circuit (PX) of FIG.

[0118] As shown in Figure 15, the pixel circuit (PX) is disposed on a substrate 101. In one embodiment, the substrate 101 is a silicon-based substrate. In one embodiment, the pixel circuit (PX) is disposed on a silicon-based substrate. Because the pixel circuit (PX) is disposed on a silicon-based substrate, the voltage level of the input signal provided to the pixel circuit (PX) can be set more precisely.

[0119] Fig. 16 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Fig. 17 is a diagram illustrating an example in which the electronic device 1000 of Fig. 16 is implemented as a smartphone.

[0120] 16, the electronic device 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be the display device 1 of FIG. 1. The electronic device 1000 also includes a number of ports for communicating with a video card, a sound card, a memory card, a USB device, etc., or for communicating with other systems.

[0121] 17, the electronic device 1000 is embodied as a smartphone. However, this is merely an example and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be embodied as a mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a laptop computer, a head-mounted display device, etc.

[0122] The processor 1010 performs specific calculations or tasks. Depending on the embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be coupled to different components via an address bus, a control bus, a data bus, etc. Depending on the embodiment, the processor 1010 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

[0123] The processor 1010 outputs the input image data (IMG) and the input control signal (CONT) to the drive control unit 200 of FIG.

[0124] The memory device 1020 stores data necessary for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase change random access memory (PRAM) devices, resistance random access memory (RRAM) devices, nano floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM), ferroelectric random access memory (FRAM) devices, etc., and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, mobile DRAM devices, etc.

[0125] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device 1040 may include input means such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc., and output means such as a speaker, a printer, etc. Depending on the embodiment, a display device 1060 may also be included in the input / output device 1040. The power supply 1050 provides power necessary for operation of the electronic device 1000. The display device 1060 may be connected to other components via the bus or other communication link.

[0126] 17 shows the electronic device of the present invention implemented as a smartphone, but the present invention is not limited thereto. The electronic device may be a television, a monitor, a laptop computer, or a tablet. The electronic device may also be a car.

[0127] FIG. 18 is a diagram illustrating an example in which the electronic device of FIG. 16 is implemented in a virtual reality display system.

[0128] 16 and 18, the virtual reality display system includes a lens unit 10, a display device 20, and a housing 30. The display device 20 is disposed adjacent to the lens unit 10. The housing 30 accommodates the lens unit 10 and the display device 20. Although FIG. 18 shows that the lens unit 10 and the display device 20 are accommodated on a first side of the housing 30, the present invention is not limited thereto. For example, the lens unit 10 may be accommodated on a first side of the housing 30, and the display device 20 may be accommodated on a second side of the housing 30 opposite to the first side of the housing 30. When the lens unit 10 and the display device 20 are accommodated on different sides of the housing 30, the housing 30 may have a transmissive portion for transmitting light.

[0129] For example, the virtual reality display system may be a head-mounted display system worn on the user's head. Although not shown, the virtual reality display system may further include a headband unit for wearing on the user's head.

[0130] Alternatively, the virtual reality display system may have the shape of smart glasses, which are embodied in the shape of glasses.

[0131] The electronic device may also be implemented in an augmented reality display system, a mixed reality display system, or an augmented reality display system. [Industrial Applicability]

[0132] The present invention is applicable to a display device and an electronic device including the same. For example, the display device of the present invention can be applied to computers, laptops, mobile phones, smartphones, smart pads, smart watches, PMPs, PDAs, MP3 players, etc.

[0133] Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. [Explanation of symbols]

[0134] 1: Display device 100: Display panel 200: Drive control unit 300: Gate driver 400: Gamma reference voltage generator 500: Data Drive 600: Light emitting driver PX, PXA, PXB, PXC: Pixel circuit

Claims

1. a first transistor responsive to a voltage at a first node to provide a drive current to a second node; a second transistor responsive to a write gate signal to provide a data voltage to a third node; a third transistor connecting the first node and the second node in response to the write gate signal; a fourth transistor connecting the second node and a fourth node in response to a light-emitting signal; a fifth transistor responsive to a bias gate signal to provide an initialization voltage to the fourth node; a sixth transistor for providing a reference voltage to the third node in response to an initialization gate signal; a seventh transistor responsive to a previous stage write gate signal to provide the reference voltage to the first node; a light emitting device including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage; a first storage capacitor having a first electrode coupled to the third node and a second electrode coupled to the first node.

2. the data voltage includes one of a first data voltage to a Kth data voltage (where K is a natural number); 2. The pixel circuit according to claim 1, wherein the reference voltage has a value between the first data voltage and the Kth data voltage.

3. 3. The pixel circuit according to claim 2, wherein the reference voltage has an intermediate value between the first data voltage and the Kth data voltage.

4. a frame period in which the pixel circuit is driven includes a data writing period, a data holding period, and a light emitting period; In the data write period, the write gate signal has an activation level; In the hold section, the light-emitting signal has an activation level, and the bias gate signal has an activation level; The pixel circuit according to claim 1 , wherein, in the light-emitting period, the light-emitting signal has an activation level and the bias gate signal has a deactivation level.

5. 5. The pixel circuit according to claim 4, wherein in the hold period, the fourth transistor is turned on and the fifth transistor is turned on.

6. In a first section of a frame section in which the pixel circuit is driven, the previous stage write gate signal has an activation level, and the initialization gate signal has an activation level; 2. The pixel circuit of claim 1, wherein the sixth transistor is turned on and the seventh transistor is turned on.

7. In the first section, 7. The pixel circuit of claim 6, wherein the bias gate signal has an activation level, and the fifth transistor is turned on.

8. In a second section following the first section, the write gate signal has an activation level; 7. The pixel circuit of claim 6, wherein the second transistor and the third transistor are turned on.

9. In the second section, 9. The pixel circuit according to claim 8, wherein the activation level of the bias gate signal is maintained, and the fifth transistor is maintained in an on state.

10. In a third section following the second section, 9. The pixel circuit of claim 8, wherein the initialization gate signal has an activation level, and the sixth transistor is turned on.

11. In the third section, 11. The pixel circuit of claim 10, wherein the bias gate signal has an activation level, and the fifth transistor is turned on.

12. In a fourth section following the third section, the light-emitting signal has an activation level and the bias gate signal has a deactivation level; 11. The pixel circuit of claim 10, wherein the fifth transistor is turned off.

13. further comprising a second storage capacitor; the first transistor includes a control electrode coupled to the first node, a first electrode to which a first power supply voltage is applied, and a second electrode coupled to the second node; 2. The pixel circuit of claim 1, wherein the second storage capacitor includes a first electrode coupled to the first node and a second electrode to which the first power supply voltage is applied.

14. the first transistor includes a control electrode coupled to the first node, a first electrode to which a first power supply voltage is applied, and a second electrode coupled to the second node; the second transistor includes a control electrode to which the write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the third node; the third transistor includes a control electrode to which the write gate signal is applied, a first electrode coupled to the second node, and a second electrode coupled to the first node; the fourth transistor includes a control electrode to which the light-emitting signal is applied, a first electrode coupled to the second node, and a second electrode coupled to the fourth node; the fifth transistor includes a control electrode to which the bias gate signal is applied, a first electrode connected to the fourth node, and a second electrode to which the initialization voltage is applied; the sixth transistor includes a control electrode receiving the initialization gate signal, a first electrode receiving the reference voltage, and a second electrode coupled to the third node; 2. The pixel circuit of claim 1, wherein the seventh transistor includes a control electrode to which the previous stage write gate signal is applied, a first electrode to which the reference voltage is applied, and a second electrode connected to the first node.

15. a first transistor responsive to a voltage at a first node to provide a drive current to a second node; a second transistor responsive to a write gate signal to provide a data voltage to a third node; a third transistor connecting the first node and the second node in response to the write gate signal; a fourth transistor connecting the second node and a fourth node in response to a light-emitting signal; a fifth transistor responsive to a bias gate signal to provide an initialization voltage to the fourth node; a sixth transistor for providing a reference voltage to the third node in response to an initialization gate signal; a seventh transistor responsive to a control gate signal to provide the reference voltage to the first node; a light emitting device including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage; a first storage capacitor having a first electrode coupled to the third node and a second electrode coupled to the first node.

16. the data voltage includes any one of a first data voltage to a K-th data voltage (where K is a natural number); 16. The pixel circuit according to claim 15, wherein the reference voltage has a value between the first data voltage and the Kth data voltage.

17. 17. The pixel circuit according to claim 16, wherein the reference voltage has an intermediate value between the first data voltage and the Kth data voltage.

18. a frame period in which the pixel circuit is driven includes a data writing period, a data holding period, and a light emitting period; In the data write period, the write gate signal has an activation level; In the hold section, the light-emitting signal has an activation level, and the bias gate signal has an activation level; The pixel circuit of claim 15 , wherein, in the light-emitting period, the light-emitting signal has an activation level and the bias gate signal has a deactivation level.

19. a display panel including pixel circuits; a gate driver for outputting a write gate signal, a previous stage write gate signal, an initialization gate signal, and a bias gate signal to the pixel circuit; a data driver for applying a data voltage to the display panel; a light-emission driving unit that supplies a light-emission signal to the pixel circuit; The pixel circuit a first transistor responsive to a voltage at a first node to provide a drive current to a second node; a second transistor responsive to the write gate signal to provide the data voltage to a third node; a third transistor connecting the first node and the second node in response to the write gate signal; a fourth transistor connecting the second node and a fourth node in response to the light-emitting signal; a fifth transistor for applying an initialization voltage to the fourth node in response to the bias gate signal; a sixth transistor for providing a reference voltage to the third node in response to the initialization gate signal; a seventh transistor responsive to the previous stage write gate signal to provide the reference voltage to the first node; a light emitting device including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage; a first storage capacitor having a first electrode coupled to the third node and a second electrode coupled to the first node.

20. the data voltage includes any one of a first data voltage to a K-th data voltage (where K is a natural number); 20. The display device according to claim 19, wherein the reference voltage has a value between the first data voltage and the Kth data voltage.

21. 21. The display device according to claim 20, wherein the reference voltage has an intermediate value between the first data voltage and the Kth data voltage.

22. a frame period in which the pixel circuit is driven includes a data writing period, a data holding period, and a light emitting period; In the data write period, the write gate signal has an activation level; In the hold section, the light-emitting signal has an activation level, and the bias gate signal has an activation level; The display device of claim 19, wherein, in the light-emitting period, the light-emitting signal has an activation level and the bias gate signal has a deactivation level.

23. a frame period in which the pixel circuit is driven includes a first period, a second period, a third period, and a fourth period; In the first section, the bias gate signal has an activation level, the light emission signal has a deactivation level, the previous stage write gate signal has an activation level, the initialization gate signal has an activation level, and the write gate signal has a deactivation level; In the second section, the bias gate signal has an activation level, the light emission signal has a deactivation level, the previous stage write gate signal has a deactivation level, the initialization gate signal has a deactivation level, and the write gate signal has an activation level; In the third section, the bias gate signal has an activation level, the light emitting signal has an activation level, the previous stage write gate signal has an inactivation level, the initialization gate signal has an activation level, and the write gate signal has an inactivation level; 20. The display device of claim 19, wherein, in the fourth period, the bias gate signal has an inactive level, the light emitting signal has an active level, the previous stage write gate signal has an inactive level, the initialization gate signal has an active level, and the write gate signal has an inactive level.

24. 20. The display device according to claim 19, wherein the pixel circuit is disposed on a silicon-based substrate.

25. a display panel including pixel circuits; a gate driver for outputting a write gate signal, a previous stage write gate signal, an initialization gate signal, and a bias gate signal to the pixel circuit; a data driver for applying a data voltage to the display panel; a light emission driver that supplies a light emission signal to the pixel circuit; a driving control unit that controls the gate driver, the data driver, and the light emitting driver based on an input control signal; a processor that outputs the input control signal; The pixel circuit a first transistor responsive to a voltage at a first node to provide a drive current to a second node; a second transistor responsive to the write gate signal to provide the data voltage to a third node; a third transistor connecting the first node and the second node in response to the write gate signal; a fourth transistor connecting the second node and a fourth node in response to the light-emitting signal; a fifth transistor for applying an initialization voltage to the fourth node in response to the bias gate signal; a sixth transistor for providing a reference voltage to the third node in response to the initialization gate signal; a seventh transistor responsive to the previous stage write gate signal to provide the reference voltage to the first node; a light emitting device including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage; a first storage capacitor having a first electrode coupled to the third node and a second electrode coupled to the first node.

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