Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing leakage of a bonding layer from a die pad.SOLUTION: A semiconductor device A10 includes: a die pad 20 having a pad portion 21; a semiconductor element 10 located on one side of the pad portion 21 in a first direction z; and a bonding layer 19 bonding the pad portion 21 and the semiconductor element 10. The pad portion 21 has a mounting surface 211 and a first peripheral surface 213. The semiconductor element 10 is bonded to the mounting surface 211. The die pad 20 includes a first protrusion 24 protruding from the first peripheral surface 213. The first protrusion 24 has a first surface 241 facing the same side as the mounting surface 211 in the first direction z. The first surface 241 is located on the opposite side to the mounting surface 211 with respect to the first peripheral surface 213 in the first direction z.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Resin packaged semiconductor devices are widely known, such as the semiconductor device disclosed in Patent Document 1. The semiconductor device disclosed in Patent Document 1 includes a semiconductor element, a first lead and a third lead that are electrically connected to the semiconductor element, a second lead on which the semiconductor element is mounted, and a sealing resin that covers the semiconductor element.

[0003] In the semiconductor device disclosed in Patent Document 1, a semiconductor element is bonded to the second pad surface of the second pad portion of the second lead via a bonding layer. In this case, if the area of ​​the element surface of the semiconductor element is relatively large compared to the area of ​​the second pad surface, the bonding layer will leak from the second pad surface. If the leakage of the bonding layer becomes excessive, there is a risk that the bonding layer will reach the portion of the second lead located outside the sealing resin. This can cause problems when mounting the semiconductor device on a wiring board. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-60908

[0005] [overview] In view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress leakage of a bonding layer from a die pad.

[0006] The semiconductor device provided by the present disclosure comprises a die pad having a pad portion, a semiconductor element located on one side of the pad portion in a first direction, and a bonding layer bonding the pad portion to the semiconductor element. The pad portion has a mounting surface facing the semiconductor element and a first peripheral surface facing in a direction perpendicular to the first direction. The semiconductor element is bonded to the mounting surface. The die pad has a first protruding portion protruding from the first peripheral surface. The first protruding portion has a first surface facing the same side as the mounting surface in the first direction. The first surface is located on the opposite side of the mounting surface in the first direction with respect to the first peripheral surface.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view of the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a plan view corresponding to FIG. 2, seen through the sealing resin. [Figure 4] FIG. 4 is a bottom view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a bottom view corresponding to FIG. 4, seen through the sealing resin. [Figure 6] FIG. 6 is a front view of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a right side view of the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a left side view of the semiconductor device shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a partial enlarged view of FIG. 3, showing the bonding layer. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a partially enlarged cross-sectional view of a semiconductor device according to a first modification of the first embodiment of the present disclosure, and corresponds to FIG. [Figure 15] FIG. 15 is a partially enlarged cross-sectional view of a semiconductor device according to a second modification of the first embodiment of the present disclosure, and corresponds to FIG. [Figure 16] FIG. 16 is a partially enlarged plan view of the semiconductor device according to the second embodiment of the present disclosure, and corresponds to FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a partially enlarged plan view of the semiconductor device according to the third embodiment of the present disclosure, and corresponds to FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG.

[0009] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0010] [First embodiment] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 13. The semiconductor device A10 includes a semiconductor element 10, a die pad 20, a plurality of first terminals 31, a plurality of second terminals 32, a plurality of wires 40, and a sealing resin 50. The semiconductor device A10 is packaged in a small outline package (SOP). However, the packaging format of the semiconductor device A10 is not limited to SOP. For ease of understanding, FIGS. 3 and 5 show the sealing resin 50 in a see-through manner. In FIGS. 3 and 5, the outline of the sealing resin 50 is indicated by an imaginary line (a two-dot chain line). For ease of understanding, FIG. 12 also shows the bonding layer 19 in a see-through manner.

[0011] In the description of the semiconductor device A10, for convenience, the normal direction to the mounting surface 211 of the pad portion 21 (described later) will be referred to as the "first direction z." The direction perpendicular to the first direction z will be referred to as the "second direction x." The direction perpendicular to both the first direction z and the second direction x will be referred to as the "third direction y."

[0012] As shown in FIGS. 9 to 11 , the sealing resin 50 covers the semiconductor element 10, a portion of the die pad 20, a portion of each of the plurality of first terminals 31, a portion of each of the plurality of second terminals 32, and the plurality of wires 40. The sealing resin 50 is an insulator. The sealing resin 50 is made of a material containing, for example, epoxy resin. When viewed in the first direction z, the sealing resin 50 has a rectangular shape.

[0013] As shown in FIGS. 6 to 8, the sealing resin 50 has a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, a third side surface 55, and a fourth side surface 56.

[0014] 6 to 8, the top surface 51 and the bottom surface 52 face in opposite directions in the first direction z. The top surface 51 faces the same side in the first direction z as a mounting surface 211 of the pad portion 21, which will be described later.

[0015] 6, the first side surface 53 faces one side in the second direction x. The second side surface 54 faces the opposite side from the first side surface 53 in the second direction x. Each of the first side surface 53 and the second side surface 54 is located between the top surface 51 and the bottom surface 52 in the first direction z and is connected to the top surface 51 and the bottom surface 52.

[0016] 7 and 8, the third side surface 55 faces one side in the third direction y. The fourth side surface 56 faces the opposite side from the third side surface 55 in the third direction y. Each of the third side surface 55 and the fourth side surface 56 is located between the top surface 51 and the bottom surface 52 in the first direction z and is connected to the top surface 51 and the bottom surface 52.

[0017] The die pad 20, the plurality of first terminals 31, and the plurality of second terminals 32 all contain copper (Cu) in their composition. The die pad 20, the plurality of first terminals 31, and the plurality of second terminals 32 are obtained from the same lead frame.

[0018] 9 to 11, the die pad 20 is located on one side of the semiconductor element 10 in the first direction z. The die pad 20 mounts the semiconductor element 10. The die pad 20 has a pad portion 21, a first support portion 22, a second support portion 23, and a first protruding portion 24.

[0019] As shown in FIG. 3 and FIGS. 9 to 11, the pad portion 21 mounts the semiconductor element 10. When viewed in the first direction z, the pad portion 21 has a rectangular shape. The pad portion 21 has a mounting surface 211, a back surface 212, a first circumferential surface 213, and a second circumferential surface 214. The mounting surface 211 faces one side in the first direction z. The mounting surface 211 faces the semiconductor element 10. The mounting surface 211 is plated with, for example, silver (Ag). The back surface 212 faces the opposite side to the mounting surface 211 in the first direction z. The back surface 212 is exposed from the bottom surface 52 of the sealing resin 50. The first circumferential surface 213 and the second circumferential surface 214 each include a plurality of regions in the pad portion 21. Each of the plurality of regions faces either the second direction x or the third direction y. The second circumferential surface 214 is located on the opposite side of the first circumferential surface 213 from the mounting surface 211 in the first direction z. As viewed in the first direction z, the first circumferential surface 213 is located between the semiconductor element 10 and the second circumferential surface 214. As shown in FIG. 13 , the dimension h2 of the second circumferential surface 214 in the first direction z is larger than the dimension h1 of the first circumferential surface 213 in the first direction z.

[0020] As shown in FIGS. 3 and 9 , the first support portion 22 is connected to one side of the pad portion 21 in the second direction x. The first support portion 22 is located between the pad portion 21 and a first side surface 53 of the sealing resin 50 in the second direction x. The first support portion 22 is bent in the second direction x from the pad portion 21 to the first side surface 53 toward the side toward which the mounting surface 211 of the pad portion 21 faces in the first direction z. Both sides of the first support portion 22 in the first direction z are sandwiched between the sealing resin 50. The first support portion 22 has a first end surface 221 facing one side in the second direction x. The first end surface 221 is exposed from the first side surface 53.

[0021] As shown in FIGS. 3 and 9 , the second support portion 23 is located on the opposite side of the first support portion 22 in the second direction x, with the pad portion 21 sandwiched therebetween. The second support portion 23 is connected to the pad portion 21. The second support portion 23 is located between the pad portion 21 and the second side surface 54 of the sealing resin 50 in the second direction x. The second support portion 23 is bent in the second direction x from the pad portion 21 to the second side surface 54 toward the side toward which the mounting surface 211 of the pad portion 21 faces in the first direction z. Both sides of the second support portion 23 in the first direction z are sandwiched between the sealing resin 50. The second support portion 23 has a second end surface 231 facing one side in the second direction x. The second end surface 231 is exposed from the second side surface 54.

[0022] 3, 5, 10, and 11, the first protrusion 24 protrudes from the first peripheral surface 213 of the pad portion 21. When viewed in the first direction z, the first protrusion 24 extends along the periphery of the mounting surface 211 of the pad portion 21. When viewed in the first direction z, the first protrusion 24 surrounds the semiconductor element 10. The first protrusion 24 is formed by pressing the die pad 20 against the mounting surface 211.

[0023] 12 and 13, the first protruding portion 24 has a first surface 241 and a second surface 242. The first surface 241 faces the same side as the mounting surface 211 of the pad portion 21 in the first direction z. The first surface 241 is located on the opposite side of the mounting surface 211 in the first direction z with the first circumferential surface 213 of the pad portion 21 as a reference. The first surface 241 is located closer to the mounting surface 211 in the first direction z than the back surface 212 of the pad portion 21. A dimension b1 of the first surface 241 in the direction in which the first circumferential surface 213 faces (either the second direction x or the third direction y) is larger than a dimension t of the pad portion 21 in the first direction z. The first surface 241 is in contact with the sealing resin 50.

[0024] 13, the second surface 242 is located on the opposite side of the first circumferential surface 213 of the pad portion 21 with respect to the first surface 241 in the first direction z. As a result, the second circumferential surface 214 of the pad portion 21 is located between the back surface 212 of the pad portion 21 and the second surface 242 in the first direction z. When viewed in the first direction z, the entire second surface 242 overlaps the first surface 241. In a cross section of the first protruding portion 24, the first direction z and the second direction x are in-plane directions (or the first direction z and the third direction y are in-plane directions), the second surface 242 bulges out in a convex shape. The second surface 242 is in contact with the sealing resin 50.

[0025] 3 and 9 to 11, the semiconductor element 10 is bonded to the mounting surface 211 of the pad portion 21 of the die pad 20. The semiconductor element 10 controls the functions of the semiconductor device A10. The type of the semiconductor element 10 is not limited, and it may be an LSI (Large Scale Integration) or the like.

[0026] 3 and 11, the semiconductor element 10 has an element surface 11 and a plurality of electrodes 12. The element surface 11 faces the side opposite to the side facing the mounting surface 211 of the pad portion 21 in the first direction z. The area of ​​the element surface 11 is 70% or more of the area of ​​the mounting surface 211. The plurality of electrodes 12 are provided on the element surface 11. Each of the plurality of electrodes 12 is electrically connected to a circuit configured in the semiconductor element 10.

[0027] As shown in FIGS. 9 to 11, the bonding layer 19 bonds the pad portion 21 of the die pad 20 to the semiconductor element 10. This bonds the semiconductor element 10 to the mounting surface 211 of the pad portion 21. The bonding layer 19 is made of a paste containing metal particles. The metal particles are, for example, silver. Alternatively, the bonding layer 19 may be solder. As shown in FIG. 13, the bonding layer 19 contacts the first peripheral surface 213 of the pad portion 21 and the first surface 241 of the first protruding portion 24 of the die pad 20.

[0028] 3 and 5, the multiple first terminals 31 are located on one side of the die pad 20 in the third direction y. Each of the multiple first terminals 31 is electrically connected to the semiconductor element 10. The multiple first terminals 31 are arranged along the second direction x. Each of the multiple first terminals 31 is exposed from a third side surface 55 of the sealing resin 50.

[0029] As shown in FIGS. 3, 5, and 11, each of the multiple first terminals 31 has a first inner portion 311 and a first outer portion 312. The first inner portion 311 is covered with a sealing resin 50. The first inner portion 311 of each of the multiple first terminals 31 has a first connection surface 311A. The first connection surface 311A ​​faces the same side as the mounting surface 211 of the pad portion 21 in the first direction z. The first connection surface 311A ​​is plated with, for example, silver. The first outer portion 312 is connected to the first inner portion 311 of one of the corresponding multiple first terminals 31. As shown in FIGS. 2 and 4, the first outer portion 312 protrudes from the third side surface 55. The surface of the first outer portion 312 is plated with, for example, tin (Sn). When viewed in the first direction z, the first outer portion 312 extends in the third direction y. As shown in FIGS. 7 and 8, the first outer portion 312 is bent in a gull-wing shape when viewed in the second direction x.

[0030] 3 and 5 , the second terminals 32 are located on the opposite side of the die pad 20 from the first terminals 31 in the third direction y. Each of the second terminals 32 is electrically connected to the semiconductor element 10. The second terminals 32 are arranged along the second direction x. Each of the second terminals 32 is exposed from the fourth side surface 56 of the sealing resin 50.

[0031] As shown in FIGS. 3, 5, and 11, each of the multiple second terminals 32 has a second inner portion 321 and a second outer portion 322. The second inner portion 321 is covered with a sealing resin 50. The second inner portion 321 of one of the multiple second terminals 32 is connected to the first support portion 22 of the die pad 20. The second inner portion 321 of each of the multiple second terminals 32 has a second connection surface 321A. The second connection surface 321A faces the same side as the mounting surface 211 of the pad portion 21 in the first direction z. The second connection surface 321A is plated with, for example, silver. The second outer portion 322 is connected to the second inner portion 321 of one of the corresponding multiple second terminals 32. As shown in FIGS. 2 and 4, the second outer portion 322 protrudes from the fourth side surface 56. The surface of the second outer portion 322 is plated with, for example, tin. When viewed in the first direction z, the second outer part 322 extends in the third direction y. As shown in Figures 6 and 7, when viewed in the second direction x, the second outer part 322 is bent in a gull-wing shape.

[0032] 3 and 11, each of the plurality of wires 40 is conductively bonded to one of the plurality of electrodes 12 of the semiconductor element 10 and to one of the first connection surfaces 311A ​​of each of the plurality of first terminals 31 and the second connection surfaces 321A of each of the plurality of second terminals 32. This allows each of the plurality of first terminals 31 and each of the plurality of second terminals 32 to be electrically connected to the semiconductor element 10. The plurality of wires 40 contains, for example, gold (Au). Alternatively, the plurality of wires 40 may contain aluminum (Al) or copper.

[0033] Next, a semiconductor device A11 according to a first modified example of the first embodiment of the present disclosure will be described with reference to Fig. 14. Here, Fig. 14 corresponds to Fig. 13 showing the semiconductor device A10. In the semiconductor device A11, the configuration of the die pad 20 is different from that of the semiconductor device A10.

[0034] As shown in FIG. 14, a first surface 241 of the first protruding portion 24 of the die pad 20 is curved in a concave shape toward a second surface 242 of the first protruding portion 24.

[0035] Next, a semiconductor device A12 according to a second modification of the first embodiment of the present disclosure will be described with reference to Fig. 15. Here, Fig. 15 corresponds to Fig. 13 showing the semiconductor device A10. In the semiconductor device A12, the configuration of the die pad 20 is different from that of the semiconductor device A10.

[0036] As shown in FIG. 15, the surface roughness of the first surface 241 of the first protruding portion 24 of the die pad 20 is greater than the surface roughness of the back surface 212 of the pad portion 21 of the die pad 20.

[0037] Next, the effects of the semiconductor device A10 will be described.

[0038] The semiconductor device A10 includes a die pad 20 having a pad portion 21, a semiconductor element 10, and a bonding layer 19 bonding the pad portion 21 and the semiconductor element 10. The pad portion 21 has a mounting surface 211 and a first peripheral surface 213. The die pad 20 has a first protruding portion 24 protruding from the first peripheral surface 213. The first protruding portion 24 has a first surface 241 facing the same side as the mounting surface 211 in the first direction z. The first surface 241 is located on the opposite side of the mounting surface 211 from the first peripheral surface 213 in the first direction z. With this configuration, when the semiconductor element 10 is bonded to the mounting surface 211 during manufacturing of the semiconductor device A10, the bonding layer 19 leaking from the mounting surface 211 is received by the first surface 241, as shown in FIG. 13 . Therefore, with this configuration, the semiconductor device A10 can prevent the bonding layer 19 from leaking from the die pad 20.

[0039] The first protruding portion 24 has a second surface 242. When viewed in the first direction z, the entire second surface 242 overlaps the first surface 241. The second surface 242 is convex. This configuration is a trace of the first protruding portion 24 formed by crushing the die pad 20 from the mounting surface 211 of the pad portion 21.

[0040] The pad portion 21 has a back surface 212. In the first direction z, the first surface 241 of the first protruding portion 24 is located closer to the mounting surface 211 of the pad portion 21 than the back surface 212. By adopting this configuration, it is possible to restrict movement of the bonding layer 19 leaking from the mounting surface 211 in the first direction z.

[0041] The pad portion 21 has a second peripheral surface 214. The second peripheral surface 214 is located between the back surface 212 of the pad portion 21 and the second surface 242 of the first protruding portion 24 in the first direction z. The first peripheral surface 213 of the pad portion 21 is located between the semiconductor element 10 and the second peripheral surface 214 as viewed in the first direction z. This configuration allows the dimension b1 of the first surface 241 of the first protruding portion 24 in the direction in which the first peripheral surface 213 faces to be set larger. This effectively prevents leakage of the bonding layer 19. In this case, it is more preferable that the dimension b1 of the first surface 241 be larger than the dimension t of the pad portion 21 in the first direction z.

[0042] The dimension h2 in the first direction z of the second circumferential surface 214 of the pad portion 21 is larger than the dimension h1 in the first direction z of the first circumferential surface 213 of the pad portion 21. By adopting this configuration, movement in the first direction z of the bonding layer 19 leaking from the mounting surface 211 can be effectively restricted.

[0043] When viewed in the first direction z, the first protruding portion 24 surrounds the semiconductor element 10. By adopting this configuration, leakage of the bonding layer 19 can be more reliably suppressed.

[0044] The semiconductor element 10 has an element surface 11. The area of ​​the element surface 11 is 70% or more of the area of ​​the mounting surface 211 of the pad portion 21. Therefore, the configuration of the semiconductor device A10 is suitable for use with a semiconductor element 10 in which the area of ​​the element surface 11 is relatively large compared to the area of ​​the mounting surface 211.

[0045] In the configuration of the semiconductor device A11, the first surface 241 of the first protruding portion 24 is curved toward the second surface 242 of the first protruding portion 24. With this configuration, the movement of the bonding layer 19 that has reached the first surface 241 is more restricted. This makes it possible to more effectively suppress leakage of the bonding layer 19.

[0046] In the configuration of the semiconductor device A12, the surface roughness of the first surface 241 of the first protruding portion 24 is greater than the surface roughness of the back surface 212 of the pad portion 21. With this configuration, when the bonding layer 19 reaches the first surface 241, the frictional force of the bonding layer 19 against the first surface 241 increases, so that the movement of the bonding layer 19 is more restricted. This makes it possible to more effectively suppress leakage of the bonding layer 19.

[0047] The semiconductor device A10 further includes a sealing resin 50 that covers the semiconductor element 10. The back surface 212 of the pad portion 21 is exposed from the sealing resin 50. With this configuration, heat transferred from the semiconductor element 10 to the die pad 20 can be efficiently dissipated to the outside.

[0048] The second surface 242 of the first protruding portion 24 is in contact with the sealing resin 50. By adopting this configuration, the die pad 20 can be effectively prevented from falling off the bottom surface 52 of the sealing resin 50.

[0049] Second Embodiment A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 16 and 17. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 16 corresponds to Figure 12, which shows the semiconductor device A10.

[0050] In the semiconductor device A20, the configuration of the die pad 20 is different from that of the semiconductor device A10.

[0051] 16 and 17 , the first protruding portion 24 of the die pad 20 has a recess 243. The recess 243 is recessed from the first surface 241 of the first protruding portion 24. When viewed in the first direction z, the recess 243 extends along the periphery of the mounting surface 211 of the pad portion 21 of the die pad 20. When viewed in the first direction z, the recess 243 overlaps the second surface 242 of the first protruding portion 24.

[0052] Next, the effects of the semiconductor device A20 will be described.

[0053] The semiconductor device A20 includes a die pad 20 having a pad portion 21, a semiconductor element 10, and a bonding layer 19 bonding the pad portion 21 and the semiconductor element 10. The pad portion 21 has a mounting surface 211 and a first peripheral surface 213. The die pad 20 has a first protruding portion 24 protruding from the first peripheral surface 213. The first protruding portion 24 has a first surface 241 facing the same side as the mounting surface 211 in the first direction z. The first surface 241 is located on the opposite side of the mounting surface 211 relative to the first peripheral surface 213 in the first direction z. Therefore, with this configuration, the semiconductor device A20 can also suppress leakage of the bonding layer 19 from the die pad 20. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0054] In the semiconductor device A20, the first protruding portion 24 has a recess 243 recessed from the first surface 241. With this configuration, as shown in FIG. 17 , when the bonding layer 19 leaking from the mounting surface 211 of the pad portion 21 comes into contact with the boundary between the first surface 241 and the recess 243, the surface tension acting on the bonding layer 19 increases. This makes it possible to effectively suppress the leakage of the bonding layer 19. In this case, by configuring the recess 243 to overlap the second surface 242 of the first protruding portion 24 when viewed in the first direction z, the recess 243 is positioned farther from the first peripheral surface 213 of the pad portion 21. This makes it possible to more effectively suppress the leakage of the bonding layer 19.

[0055] Third Embodiment A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 18 and 19. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 18 corresponds to Figure 12, which shows the semiconductor device A10.

[0056] In the semiconductor device A30, the configuration of the die pad 20 is different from that of the semiconductor device A10.

[0057] 18 and 19, the pad portion 21 of the die pad 20 has a third circumferential surface 215. The third circumferential surface 215 faces the same side as the first circumferential surface 213 of the pad portion 21 in a direction perpendicular to the first direction z.

[0058] 18 and 19 , the die pad 20 has a second protruding portion 25. The second protruding portion 25 protrudes from a third peripheral surface 215 of the pad portion 21. When viewed in the first direction z, the second protruding portion 25 extends along the periphery of the mounting surface 211 of the pad portion 21. When viewed in the first direction z, the second protruding portion 25 surrounds the semiconductor element 10. The second protruding portion 25 is formed by pressing the die pad 20 from the back surface 212 of the pad portion 21.

[0059] As shown in FIGS. 18 and 19 , the second protrusion 25 has a third surface 251 and a fourth surface 252. The third surface 251 faces the same side as the back surface 212 of the pad portion 21 in the first direction z. The third surface 251 is located on the opposite side of the back surface 212 from the third circumferential surface 215 of the pad portion 21 in the first direction z. The third surface 251 is located closer to the back surface 212 in the first direction z than the mounting surface 211 of the pad portion 21. A dimension b1 of the first surface 241 of the first protrusion 24 in a direction in which the first circumferential surface 213 of the pad portion 21 faces (either the second direction x or the third direction y) is larger than a dimension b2 of the third surface 251. When viewed in the first direction z, the third surface 251 overlaps the second circumferential surface 214 of the pad portion 21. The third surface 251 is in contact with the sealing resin 50.

[0060] 19 , the fourth surface 252 is located on the opposite side of the third circumferential surface 215 of the pad portion 21 with respect to the third surface 251 in the first direction z. As a result, the second circumferential surface 214 of the pad portion 21 is located between the fourth surface 252 and the second surface 242 of the first protruding portion 24 in the first direction z. When viewed in the first direction z, the entire fourth surface 252 overlaps the third surface 251. In a cross section of the second protruding portion 25 having the first direction z and the second direction x as in-plane directions (or the first direction z and the third direction y as in-plane directions), the fourth surface 252 bulges out in a convex shape. The fourth surface 252 is in contact with the sealing resin 50.

[0061] Next, the effects of the semiconductor device A30 will be described.

[0062] The semiconductor device A30 includes a die pad 20 having a pad portion 21, a semiconductor element 10, and a bonding layer 19 bonding the pad portion 21 and the semiconductor element 10. The pad portion 21 has a mounting surface 211 and a first peripheral surface 213. The die pad 20 has a first protruding portion 24 protruding from the first peripheral surface 213. The first protruding portion 24 has a first surface 241 facing the same side as the mounting surface 211 in the first direction z. The first surface 241 is located on the opposite side of the mounting surface 211 relative to the first peripheral surface 213 in the first direction z. Therefore, with this configuration, the semiconductor device A30 can also suppress leakage of the bonding layer 19 from the die pad 20. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0063] In the semiconductor device A30, the pad portion 21 has a third peripheral surface 215. The die pad 20 has a second protruding portion 25 protruding from the third peripheral surface 215. The second protruding portion 25 has a third surface 251 facing the same side as the back surface 212 of the pad portion 21 in the first direction z. The third surface 251 is located on the opposite side of the back surface 212 with respect to the third peripheral surface 215 in the first direction z. With this configuration, in the unlikely event that the bonding layer 19 leaks from the first surface 241 of the first protruding portion 24, it reaches the second protruding portion 25 via the second surface 242 of the first protruding portion 24 and the second peripheral surface 214 of the pad portion 21. This makes it possible to more effectively suppress leakage of the bonding layer 19.

[0064] The second protruding portion 25 has a fourth surface 252 located on the opposite side of the third peripheral surface 215 of the pad portion 21 with respect to the third surface 251. The bonding layer 19 leaking from the first protruding portion 24 is received by the fourth surface 252. Furthermore, each of the third surface 251 and the fourth surface 252 is in contact with the sealing resin 50. This more effectively prevents the die pad 20 from falling off the bottom surface 52 of the sealing resin 50.

[0065] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0066] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] a die pad (20) having a pad portion (21); a semiconductor element (10) located on one side of the pad portion in the first direction (z); a bonding layer (19) that bonds the pad portion and the semiconductor element, the pad portion has a mounting surface (211) facing the semiconductor element and a first peripheral surface (213) facing in a direction perpendicular to the first direction, the semiconductor element is bonded to the mounting surface, The die pad has a first protruding portion (24) protruding from the first peripheral surface, the first protrusion has a first surface (241) facing the same side as the mounting surface in the first direction, The semiconductor device (A10) is such that the first surface is located on the opposite side of the mounting surface in the first direction with respect to the first peripheral surface. [Appendix 2] The first protruding portion has a second surface (242) located on the opposite side of the first peripheral surface with respect to the first surface, The semiconductor device (A10) according to Appendix 1, wherein the second surface entirely overlaps the first surface when viewed in the first direction. [Appendix 3] The semiconductor device (A10) according to Appendix 2, wherein the second surface is convex. [Appendix 4] the pad portion has a back surface (212) located on the opposite side to the mounting surface in the first direction, The semiconductor device (A10) according to Appendix 2, wherein the first surface is located closer to the mounting surface than the back surface in the first direction. [Appendix 5] The pad portion has a second peripheral surface (214) facing the same side as the first peripheral surface in a direction perpendicular to the first direction, the second peripheral surface is located between the back surface and the second surface in the first direction, The semiconductor device (A10) according to appendix 4, wherein the first peripheral surface is located between the semiconductor element and the second peripheral surface when viewed in the first direction. [Appendix 6] The semiconductor device (A10) according to Appendix 5, wherein the dimension of the second circumferential surface in the first direction is greater than the dimension of the first circumferential surface in the first direction. [Appendix 7] The semiconductor device (A11) according to Appendix 6, wherein the first surface is curved toward the second surface. [Appendix 8] The semiconductor device (A12) according to Appendix 6, wherein the first surface has a surface roughness greater than the surface roughness of the back surface. [Appendix 9] The semiconductor device (A20) according to appendix 6, wherein the first protruding portion has a recess (243) recessed from the first surface. [Appendix 10] The semiconductor device (A20) according to appendix 9, wherein the recess overlaps the second surface when viewed in the first direction. [Appendix 11] The pad portion has a third peripheral surface (215) facing the same side as the first peripheral surface in a direction perpendicular to the first direction, the die pad has a second protruding portion (25) protruding from the third peripheral surface, the second protruding portion has a third surface (251) facing the same side as the back surface in the first direction, The semiconductor device (A30) according to Appendix 5, wherein the third surface is located on the opposite side to the back surface with respect to the third circumferential surface in the first direction. [Appendix 12] The semiconductor device (A30) according to appendix 11, wherein the dimension of the first surface is greater than the dimension of the third surface in the direction in which the first circumferential surface faces. [Appendix 13] The semiconductor device (A30) according to appendix 12, wherein the third surface overlaps the second circumferential surface when viewed in the first direction. [Appendix 14] The semiconductor device (A10, A20, A30) according to any one of appendixes 4 to 13, wherein the first protruding portion surrounds the semiconductor element when viewed in the first direction. [Appendix 15] The semiconductor device (A10, A20, A30) according to any one of appendixes 4 to 13, wherein a dimension of the first surface in a direction in which the first peripheral surface faces is larger than a dimension of the pad portion in the first direction. [Appendix 16] the semiconductor element has an element surface (11) facing the same side as the mounting surface in the first direction, The semiconductor device (A10, A20, A30) according to any one of appendixes 4 to 13, wherein the area of ​​the element surface is 70% or more of the area of ​​the mounting surface. [Appendix 17] The semiconductor device (A10, A20, A30) according to any one of appendixes 4 to 13, wherein the bonding layer is in contact with the first circumferential surface. [Appendix 18] The semiconductor device (A10, A20, A30) according to Appendix 17, wherein the bonding layer is in contact with the first surface. [Appendix 19] Further provided is a sealing resin (50) that covers the semiconductor element, The semiconductor device (A10, A20, A30) according to any one of appendixes 4 to 13, wherein the back surface is exposed from the sealing resin. [Appendix 20] The semiconductor device (A10, A20, A30) according to Appendix 19, wherein the second surface is in contact with the sealing resin. [Appendix 21] The second protruding portion has a fourth surface (252) located on the opposite side of the third peripheral surface with respect to the third surface, The semiconductor device (A30) according to appendix 13, wherein the fourth surface entirely overlaps the third surface when viewed in the first direction. [Appendix 22] The semiconductor device (A30) according to Appendix 21, wherein the fourth surface is convex. [Appendix 23] The semiconductor device (A30) according to Appendix 21, wherein the third surface is located closer to the back surface than the mounting surface in the first direction. [Appendix 24] Further provided is a first terminal (31) that is electrically connected to the semiconductor element, When viewed in the first direction, the first terminal is located on one side of the die pad, The semiconductor device (A10, A20, A30) according to Appendix 19, wherein a portion of the first terminal protrudes from the sealing resin. [Appendix 25] Further provided is a second terminal (32) that is electrically connected to the semiconductor element, When viewed in the first direction, the second terminal is located on the opposite side to the first terminal with the die pad interposed therebetween, The semiconductor device (A10, A20, A30) according to Appendix 24, wherein a portion of the second terminal protrudes from the sealing resin. [Appendix 26] the die pad has a first support portion (22) connected to one side of the pad portion in a second direction perpendicular to the first direction, The semiconductor device (A10, A20, A30) according to Supplementary Note 25, wherein both sides of the first support part in the first direction are sandwiched by the sealing resin. [Appendix 27] The first support portion has a first end surface (221) facing one side in the second direction, The semiconductor device (A10, A20, A30) according to Supplementary Note 26, wherein the first end surface is exposed from the sealing resin. [Explanation of symbols]

[0067] A10, A11, A12, A20, A30: Semiconductor device 10: Semiconductor element 11: Element surface 12: Electrode 19: Bonding layer 20: Die pad 21: Pad section 211: Mounting surface 212: Back side 213,214,215: 1st peripheral surface, 2nd peripheral surface, 3rd peripheral surface 22: 1st support part 221: First end surface 23:Second support part 231:Second end surface 24: 1st overhang 241,242: 1st page, 2nd page 243: Recess 25:Second overhang 251: 3rd side, 4th side 31: 1st terminal 311: First Inner Section 311A: First connecting surface 312: First Outer Section 32: 2nd terminal 321: Second Inner Section 321A: Second connection surface 322: Second Outer Division 40: Wire 50: Sealing resin 51:Top surface 52: Bottom 53~56: 1st to 4th side z,x,y: 1st direction, 2nd direction, 3rd direction

Claims

1. a die pad having a pad portion; a semiconductor element located on one side of the pad portion in a first direction; a bonding layer that bonds the pad portion and the semiconductor element, the pad portion has a mounting surface facing the semiconductor element and a first peripheral surface facing in a direction perpendicular to the first direction, the semiconductor element is bonded to the mounting surface, the die pad has a first protruding portion protruding from the first peripheral surface, the first protruding portion has a first surface facing the same side as the mounting surface in the first direction, The semiconductor device, wherein the first surface is located on the opposite side of the mounting surface with respect to the first peripheral surface in the first direction.

2. the first protruding portion has a second surface located on the opposite side of the first peripheral surface with respect to the first surface, The semiconductor device according to claim 1 , wherein the second surface entirely overlaps the first surface when viewed in the first direction.

3. The semiconductor device according to claim 2 , wherein the second surface is convex.

4. the pad portion has a back surface located on the opposite side to the mounting surface in the first direction, The semiconductor device according to claim 2 , wherein the first surface is located closer to the mounting surface than the back surface in the first direction.

5. the pad portion has a second circumferential surface facing the same side as the first circumferential surface in a direction perpendicular to the first direction, the second peripheral surface is located between the back surface and the second surface in the first direction, The semiconductor device according to claim 4 , wherein the first peripheral surface is located between the semiconductor element and the second peripheral surface when viewed in the first direction.

6. The semiconductor device according to claim 5 , wherein a dimension of said second peripheral surface in said first direction is larger than a dimension of said first peripheral surface in said first direction.

7. The semiconductor device according to claim 6 , wherein the first surface is curved toward the second surface.

8. The semiconductor device according to claim 6 , wherein the first surface has a surface roughness greater than the surface roughness of the back surface.

9. The semiconductor device according to claim 6 , wherein the first protruding portion has a recess recessed from the first surface.

10. The semiconductor device according to claim 9 , wherein the recess overlaps the second surface when viewed in the first direction.

11. the pad portion has a third circumferential surface facing the same side as the first circumferential surface in a direction perpendicular to the first direction, the die pad has a second protruding portion protruding from the third peripheral surface, the second protruding portion has a third surface facing the same side as the back surface in the first direction, The semiconductor device according to claim 5 , wherein the third surface is located on the opposite side to the back surface with respect to the third circumferential surface in the first direction.

12. The semiconductor device according to claim 11 , wherein a dimension of the first surface is larger than a dimension of the third surface in a direction in which the first peripheral surface faces.

13. The semiconductor device according to claim 12 , wherein the third surface overlaps the second circumferential surface when viewed in the first direction.

14. The semiconductor device according to claim 4 , wherein the first protruding portion surrounds the semiconductor element when viewed in the first direction.

15. 14. The semiconductor device according to claim 4, wherein a dimension of said first surface in a direction in which said first peripheral surface faces is larger than a dimension of said pad portion in said first direction.

16. the semiconductor element has an element surface facing the same side as the mounting surface in the first direction, 14. The semiconductor device according to claim 4, wherein the area of ​​said element surface is 70% or more of the area of ​​said mounting surface.

17. The semiconductor device according to claim 4 , wherein the bonding layer is in contact with the first peripheral surface.

18. The semiconductor device according to claim 17 , wherein the bonding layer is in contact with the first surface.

19. Further, a sealing resin is provided to cover the semiconductor element.

14. The semiconductor device according to claim 4, wherein said back surface is exposed from said sealing resin.

20. The semiconductor device according to claim 19 , wherein the second surface is in contact with the sealing resin.

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