Over-current protection circuit, semiconductor device, and power source device

Abstract

To perform over-current protection operation that is stable not depending on the variation in manufacture, temperature conditions, or the like.SOLUTION: An over-current protection circuit 10 includes a detection resistor R10 connected between a first terminal VIN and a second terminal VOUT, a detection transistor M11 connected in series to the detection resistor R10 between the first terminal VIN and the second terminal VOUT and applying a driving signal G10 of an output transistor M10 to a control electrode, an amplifier A1 connected between the first terminal VIN and an application end of a control signal Vc and outputting a differential signal V11 between a detection voltage Vs appearing between opposite ends of the detection resistor R10 and a predetermined upper-limit voltage Vocp, an output circuit 11 that restricts the control signal Vc in accordance with the differential signal V11, and a driving signal generation circuit 12 that generates the driving signal G10 by applying an offset Vofs to the control signal Vc.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to an overcurrent protection circuit, a semiconductor device, and a power supply device. [Background technology]

[0002] Overcurrent protection circuits that limit monitored currents to a predetermined upper limit or less are used in a variety of applications.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-115646

[0005] [overview] In conventional overcurrent protection circuits, there is a risk that the overcurrent protection operation may become unstable due to manufacturing variations, temperature conditions, and the like.

[0006] For example, an overcurrent protection circuit according to the present disclosure includes a detection resistor connected between a first terminal and a second terminal, a detection transistor connected in series with the detection resistor between the first terminal and the second terminal and configured to apply a drive signal for an output transistor to a control electrode, an amplifier connected between the first terminal or the second terminal and an application terminal of a control signal and configured to output a differential signal between a detection voltage appearing across the detection resistor and a predetermined upper limit voltage, an output circuit configured to limit the control signal or the drive signal in accordance with the differential signal, and a drive signal generation circuit configured to generate the drive signal by applying an offset to the control signal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a comparative example of a power supply device. [Figure 2] FIG. 2 is a diagram showing the output current and the output voltage in the comparative example. [Figure 3] FIG. 3 is a diagram showing a first embodiment of the power supply device. [Figure 4] FIG. 4 is a diagram showing the output current and the output voltage in the first embodiment. [Figure 5] FIG. 5 is a diagram showing a second embodiment of the power supply device. [Figure 6] FIG. 6 is a diagram showing a third embodiment of the power supply device. [Figure 7] FIG. 7 is a diagram showing a fourth embodiment of the power supply device. [Figure 8] FIG. 8 is a diagram showing a fifth embodiment of the power supply device.

[0008] [Detailed explanation] <Comparative Example> 1 is a diagram showing a comparative example (i.e., a configuration to be compared with the embodiments described below) of a power supply device 1. The power supply device 1 of this comparative example is a linear power supply (e.g., an LDO [low drop out] regulator) that generates a desired output voltage Vout from an input voltage Vin.

[0009] Referring to the figure, the power supply device 1 includes an output transistor M10, an overcurrent protection circuit 10, an error amplifier 20, a feedback voltage generation circuit 30, and a reference voltage generation circuit 40. Some or all of these components may be integrated into a semiconductor device 100 (a so-called power supply control IC [integrated circuit]).

[0010] The semiconductor device 100 includes an input terminal VIN, an output terminal VOUT, and a ground terminal GND as means for establishing electrical connection with the outside of the device. The input terminal VIN is connected to an application terminal of an input voltage Vin. The output terminal VOUT is connected to an application terminal of an output voltage Vout. A phase compensation capacitor Co may be externally connected between the output terminal VOUT and the ground terminal. The ground terminal GND is connected to the ground terminal.

[0011] The output transistor M10 is connected between the input terminal VIN and the output terminal VOUT. The output transistor M10 may be a P-channel type. When the output transistor M10 is a PMOSFET (P-channel type metal oxide semiconductor field effect transistor), the source of the output transistor M10 is connected to the input terminal VIN. The drain of the output transistor M10 is connected to the output terminal VOUT. The gate of the output transistor M10 is connected to an application terminal of a drive signal G10. The lower the drive signal G10, the greater the conductivity of the output transistor M10, and the higher the drive signal G10, the smaller the conductivity.

[0012] The overcurrent protection circuit 10 performs an overcurrent protection operation by monitoring the output current Iout flowing through the output transistor M10 (details will be described later).

[0013] The error amplifier 20 generates a control signal Vc1 so that the feedback voltage Vfb input to its non-inverting input terminal (+) matches the reference voltage Vref input to its inverting input terminal (-). The control signal Vc1 is output as a drive signal G10 to the gate of the output transistor M10. The drive signal G10 decreases when the feedback voltage Vfb is lower than the reference voltage Vref. This increases the conductivity of the output transistor M10, thereby increasing the output current Iout. On the other hand, the drive signal G10 increases when the feedback voltage Vfb is higher than the reference voltage Vref. This decreases the conductivity of the output transistor M10, thereby decreasing the output current Iout.

[0014] The feedback voltage generating circuit 30 includes resistors 31 and 32 connected in series between the output terminal VOUT and the ground terminal GND. The feedback voltage generating circuit 30 divides the output voltage Vout applied to the output terminal VOUT to generate a feedback voltage Vfb. The feedback voltage generating circuit 30 may be omitted, and the output voltage Vout may be directly input to the non-inverting input terminal (+) of the error amplifier 20.

[0015] The reference voltage generating circuit 40 generates a predetermined reference voltage Vref from the input voltage Vin and outputs it to the inverting input terminal (−) of the error amplifier 20.

[0016] <Overcurrent protection circuit> Continuing with reference to Figure 1, the overcurrent protection circuit 10 will be described in detail. The overcurrent protection circuit 10 of this comparative example includes an amplifier A1, a detection transistor M11 (e.g., a PMOSFET), a transistor M12 (e.g., a PMOSFET), a transistor M13 (e.g., an NMOSFET), a detection resistor R10, and a resistor R11.

[0017] A first terminal of the detection resistor R10 is connected to the input terminal VIN (= the source of the output transistor M10). Meanwhile, a second terminal of the detection resistor R10 is connected to the source of the detection transistor M11. A drain of the detection transistor M11 is connected to the output terminal VOUT (= the drain of the output transistor M10). A gate of the detection transistor M11 is connected to the gate of the output transistor M10 (= the application terminal of the drive signal G10). In this manner, the detection resistor R10 is connected between the input terminal VIN and the output terminal VOUT. Furthermore, the detection transistor M11 is connected in series with the detection resistor R10 between the input terminal VIN and the output terminal VOUT. The drive signal G10 for the output transistor M10 is applied to the gate of the detection transistor M11.

[0018] The on-resistance (conductivity) of the detection transistor M11 connected in this manner is controlled in the same manner as the on-resistance (conductivity) of the output transistor M10. Therefore, a detection signal Is (=Iout / m, where m>1) proportional to the output current Iout flows through the detection transistor M11. The detection signal Is flows through a current path from the input terminal VIN to the output terminal VOUT via the detection resistor R10 and the detection transistor M11. Therefore, a detection voltage Vs (=Is×R10) corresponding to the detection signal Is appears across the detection resistor R10.

[0019] The upper power supply terminal of the amplifier A1 is connected to the input terminal VIN. Meanwhile, the lower power supply terminal of the amplifier A1 is connected to the terminal to which the drive signal G10 is applied. A voltage (=Vin-Vocp) obtained by subtracting a predetermined upper limit voltage Vocp from the input voltage Vin is applied to the inverting input terminal (-) of the amplifier A1. A voltage (=Vin-Vs) obtained by subtracting a detection voltage Vs from the input voltage Vin is applied to the non-inverting input terminal (+) of the amplifier A1. The amplifier A1 connected in this manner outputs a difference signal V11 between the detection voltage Vs and the upper limit voltage Vocp.

[0020] The source of the transistor M12 and the drain of the transistor M13 are all connected to the input terminal VIN. The drain of the transistor M12, the gate of the transistor M13, and a first terminal of the resistor R11 are all connected to an application terminal of the voltage signal V12. The source of the transistor M13 and a second terminal of the resistor R11 are all connected to an application terminal of the drive signal G10. The gate of the transistor M12 is connected to an application terminal of the differential signal V11. The transistors M12 and M13 and the resistor R11 connected in this manner form an output circuit 11 that limits the drive signal G10 (and therefore the control signal Vc1) in response to the differential signal V11.

[0021] When the detection voltage Vs is lower than the upper limit voltage Vocp, the differential signal V11 output from amplifier A1 is stuck at a high level (≒ Vin). Therefore, transistor M12 is fully off, and the voltage signal V12 becomes approximately equal to the drive signal G10. As a result, transistor M13 is fully off, and the gate-source of output transistor M10 is open. Therefore, the on-resistance of output transistor M10 is not increased, and no restrictions are placed on the output current Iout flowing through output transistor M10 (i.e., overcurrent protection is deactivated).

[0022] On the other hand, if the output current Iout increases due to an output abnormality or the like, and the detection voltage Vs becomes higher than the upper limit voltage Vocp, the differential signal V11 output from the amplifier A1 according to the difference between the two voltages drops from high level, and the transistor M12 turns on, causing the voltage signal V12 to rise from low level (≒G10).

[0023] At this time, a drive current I11 (corresponding to the overcurrent protection signal) flows between the gate and source of the output transistor M10 via transistor M13. This causes the drive signal G10 to rise, pulling down the gate-source voltage of the output transistor M10. As a result, the on-resistance of the output transistor M10 rises, and the output current Iout is limited (overcurrent protection operation is activated). Ultimately, the drive current I11 balances when the detection voltage Vs and the upper limit voltage Vocp are imaginarily shorted out.

[0024] With a configuration including such an overcurrent protection circuit 10, even in a situation where an excessively large output current Iout may flow through the output transistor M10, the output current Iout can be limited, thereby protecting the power supply device 1 and its peripheral circuits (including the load).

[0025] In the overcurrent protection circuit 10 of this comparative example, the amplifier A1 and the output circuit 11 are both connected between the input terminal VIN and the application terminal of the drive signal G10. With this configuration, the drive current I11 of the overcurrent protection circuit 10 flows from the input terminal VIN to the application terminal of the drive signal G10. Therefore, there is an effect that this does not lead to an increase in the current consumption of the semiconductor device 100.

[0026] <Considerations on the stability of overcurrent protection operation> However, the operating voltage range of the overcurrent protection circuit 10 connected between the input terminal VIN and the application terminal of the drive signal G10 is narrowed, so depending on manufacturing variations and temperature conditions, the overcurrent protection operation may not work, or even if the overcurrent protection operation works, the overcurrent limit value Iocp may vary greatly.

[0027] 2 is a diagram showing the relationship between the output current Iout and the output voltage Vout in the power supply device 1 of this comparative example. This diagram illustrates how the overcurrent limit value Iocp increases due to manufacturing variations, temperature conditions, and the like. When this happens, an output current Iout that is greater than originally expected flows, making it impossible to adequately protect the power supply device 1 and its peripheral circuits (including the load).

[0028] In view of the above considerations, a novel embodiment is proposed below that is capable of performing stable overcurrent protection operation regardless of manufacturing variations, temperature conditions, and the like.

[0029] First Embodiment Fig. 3 is a diagram showing a first embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the comparative example (Fig. 1) described above, with modifications made to the overcurrent protection circuit 10. Referring to this figure, the overcurrent protection circuit 10 further includes a drive signal generation circuit 12 in addition to the components described above.

[0030] The drive signal generation circuit 12 adds an offset voltage Vofs to the control signal Vc1 to generate the drive signal G10 (=Vc1+Vofs).

[0031] Referring to this figure, the drive signal generating circuit 12 includes resistors R12 and R13. The resistor R12 is connected between an application terminal of the control signal Vc1 and an application terminal of the drive signal G10. The resistor R13 is connected between the input terminal VIN and an application terminal of the drive signal G10.

[0032] The amplifier A1 and the output circuit 11 are connected between the input terminal VIN and the application terminal of the control signal Vc1. That is, the output circuit 11 limits the control signal Vc1 in accordance with the difference signal V11.

[0033] With this configuration, an offset voltage Vofs determined by the ratio of resistors R12 and R13 is generated across resistor R12. As a result, the operating voltage range of the overcurrent protection circuit 10 is expanded without affecting the operation of the power supply 1. This enables stable overcurrent protection operation independent of manufacturing variations, temperature conditions, and the like.

[0034] The introduction of resistor R12 widens the operating voltage range of the overcurrent protection circuit 10, but at the cost of potentially increasing the minimum operating voltage of the power supply device 1 by the offset voltage Vofs. Therefore, the ratio of resistors R12 and R13 may be fine-tuned taking into account the above trade-off. For example, the offset voltage Vofs may be set to 100 to 200 mV.

[0035] Although not shown, the aforementioned transistor M13 and resistor R11 may be omitted from the output circuit 11. When this modification is adopted, the drain of the transistor M12 may be directly connected to the application terminal of either the control signal Vc1 or the drive signal V10. Thus, when the drive signal generation circuit 12 is introduced, the configuration of the output circuit 11 is not limited to that of the aforementioned comparative example (FIG. 1).

[0036] 4 is a diagram showing the relationship between the output current Iout and the output voltage Vout in the power supply device 1 of the first embodiment. This diagram illustrates how the overcurrent limit value Iocp is set to a desired value regardless of manufacturing variations, temperature conditions, etc. Therefore, the power supply device 1 and its peripheral circuits (including the load) can be appropriately protected.

[0037] Second Embodiment 5 is a diagram showing a second embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the first embodiment (FIG. 3), but the drive signal generation circuit 12 is modified.

[0038] Referring to this diagram, in the drive signal generating circuit 12, the aforementioned resistor R12 is replaced with a transistor M14 (e.g., a PMOSFET). The source of the transistor M14 is connected to the application terminal of the drive signal G10. The gate and drain of the transistor M14 are both connected to the control signal Vc1. In other words, the transistor M14 is diode-connected between the application terminal of the control signal Vc1 and the application terminal of the drive signal G10.

[0039] With this configuration, an offset voltage Vofs (= the on-threshold voltage Vth of the transistor M14) is generated between the drain and source of the transistor M14. As a result, as in the first embodiment (FIG. 3), the operating voltage range of the overcurrent protection circuit 10 is expanded without affecting the operation of the power supply device 1.

[0040] Furthermore, the transistor M14 can be replaced with a diode D1. In this case, the cathode of the diode D1 is connected to the application terminal of the control signal Vc1, and the anode is connected to the application terminal of the drive signal G10. In this modification, an offset voltage Vofs (= forward drop voltage Vf of the diode D1) is generated between the anode and cathode of the diode D1.

[0041] It should be noted that the introduction of transistor M14 or diode D1 may increase the minimum operating voltage of power supply device 1 by the offset voltage Vofs. Therefore, it is necessary to consider whether this will have an effect on the operation of power supply device 1.

[0042] Also, as depicted in the dashed line frame in this figure, the transistor M14 may be replaced with a diode-connected NMOSFET or a similarly diode-connected pnp-type or npn-type bipolar transistor.

[0043] Third Embodiment 6 is a diagram showing a third embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the first embodiment (FIG. 3), but the drive signal generation circuit 12 is modified.

[0044] Referring to this figure, in the drive signal generation circuit 12, the resistor R13 mentioned above has been replaced with a current source CS1. The current source CS1 is connected between the input terminal VIN and the application terminal of the drive signal G10, and generates a constant current I12. This configuration also provides the same functions and effects as the first embodiment (FIG. 3).

[0045] <Fourth embodiment> 7 is a diagram showing a fourth embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the first embodiment (FIG. 3) described above, but includes an N-channel output transistor M20 instead of the P-channel output transistor M10. When the output transistor M20 is an NMOSFET (N-channel type MOSFET), the drain of the output transistor M20 is connected to the input terminal VIN. The source of the output transistor M20 is connected to the output terminal VOUT.

[0046] Furthermore, due to the above changes, the input polarity of the error amplifier 20 is reversed from that described above. That is, the non-inverting input terminal (+) of the error amplifier 20 is connected to the terminal to which the reference voltage Vref is applied. The inverting input terminal (-) of the error amplifier 20 is connected to the terminal to which the feedback voltage Vfb is applied. The error amplifier 20 generates a control signal Vc2 so that the feedback voltage Vfb and the reference voltage Vref coincide with each other.

[0047] Furthermore, in accordance with the above changes, there has also been a change in the circuit configuration of the overcurrent protection circuit 10. Referring to this figure, the overcurrent protection circuit 10 includes an amplifier A2, a detection transistor M21 (e.g., an NMOSFET), a transistor M22 (e.g., an NMOSFET), a transistor M23 (e.g., a PMOSFET), a detection resistor R20, and a resistor R21.

[0048] A first terminal of the detection resistor R20 is connected to the output terminal VOUT (= the source of the output transistor M20). Meanwhile, a second terminal of the detection resistor R20 is connected to the source of the detection transistor M21. A drain of the detection transistor M21 is connected to the input terminal VIN (= the drain of the output transistor M20). A gate of the detection transistor M21 is connected to the gate of the output transistor M20 (= the application terminal of the drive signal G20). In this manner, the detection resistor R20 is connected between the input terminal VIN and the output terminal VOUT. Furthermore, the detection transistor M21 is connected in series with the detection resistor R20 between the input terminal VIN and the output terminal VOUT. The drive signal G20 for the output transistor M20 is applied to the gate of the detection transistor M21.

[0049] The on-resistance (conductivity) of the detection transistor M21 connected in this manner is controlled in the same manner as the on-resistance (conductivity) of the output transistor M20. Therefore, a detection signal Is (=Iout / m, where m>1) proportional to the output current Iout flows through the detection transistor M21. The detection signal Is flows through a current path from the input terminal VIN to the output terminal VOUT via the detection transistor M21 and detection resistor R20. Therefore, a detection voltage Vs (=Is×R20) corresponding to the detection signal Is appears across the detection resistor R20.

[0050] The upper power supply terminal of amplifier A2 is connected to the terminal to which control signal Vc2 is applied. Meanwhile, the lower power supply terminal of amplifier A2 is connected to output terminal VOUT. A voltage (=Vout+Vocp) obtained by adding a predetermined upper limit voltage Vocp to the output voltage Vout is applied to the inverting input terminal (-) of amplifier A2. A voltage (=Vout+Vs) obtained by adding a detection voltage Vs to the output voltage Vout is applied to the non-inverting input terminal (+) of amplifier A2. Amplifier A2 connected in this manner outputs a difference signal V21 between the detection voltage Vs and the upper limit voltage Vocp.

[0051] The source of the transistor M22 and the drain of the transistor M23 are all connected to the output terminal VOUT. The drain of the transistor M22, the gate of the transistor M23, and a first terminal of the resistor R21 are all connected to an application terminal of the voltage signal V22. The source of the transistor M23 and a second terminal of the resistor R21 are all connected to an application terminal of the control signal Vc2. The gate of the transistor M22 is connected to an application terminal of the differential signal V21. The transistors M22 and M23 and the resistor R21 connected in this manner form an output circuit 11 that limits the control signal Vc1 in response to the differential signal V21.

[0052] When the detection voltage Vs is lower than the upper limit voltage Vocp, the differential signal V21 output from the amplifier A2 is stuck at a low level (≒Vout). Therefore, the transistor M22 is fully off, and the voltage signal V22 becomes approximately equal to the control signal Vc2. As a result, the transistor M23 is fully off, and the gate-source of the output transistor M20 is open. Therefore, the on-resistance of the output transistor M20 is not increased, and no restriction is placed on the output current Iout flowing through the output transistor M20 (i.e., the overcurrent protection operation is released).

[0053] On the other hand, if the output current Iout increases due to an output abnormality or the like, and the detection voltage Vs becomes higher than the upper limit voltage Vocp, the differential signal V21 output from the amplifier A2 according to the difference between the two voltages rises from low level, and the transistor M22 turns on, causing the voltage signal V22 to fall from high level (≒G20).

[0054] At this time, a drive current I21 (corresponding to the overcurrent protection signal) flows between the gate and source of the output transistor M20 via transistor M23. As a result, the drive signal G20 drops, pulling down the gate-source voltage of the output transistor M20. As a result, the on-resistance of the output transistor M20 increases, and the output current Iout is limited (overcurrent protection operation is activated). Ultimately, the drive current I21 balances when the detection voltage Vs and the upper limit voltage Vocp are imaginarily shorted.

[0055] With a configuration including such an overcurrent protection circuit 10, even in a situation where an excessively large output current Iout may flow through the output transistor M20, the output current Iout can be limited, thereby protecting the power supply device 1 and its peripheral circuits (including the load).

[0056] In the overcurrent protection circuit 10 of this embodiment, the amplifier A2 and the output circuit 11 are both connected between the application terminal of the control signal Vc2 and the output terminal VOUT. With this configuration, the drive current I21 of the overcurrent protection circuit 10 flows from the application terminal of the control signal Vc2 to the output terminal VOUT. Therefore, an increase in current consumption of the semiconductor device 100 is suppressed.

[0057] The drive signal generation circuit 12 adds an offset voltage Vofs to the control signal Vc2 to generate the drive signal G20 (=Vc2-Vofs).

[0058] Referring to this figure, the drive signal generation circuit 12 includes resistors R22 and R23. The resistor R22 is connected between an application terminal of the control signal Vc2 and an application terminal of the drive signal G20. The resistor R23 is connected between the output terminal VOUT and an application terminal of the drive signal G20.

[0059] The amplifier A2 and the output circuit 11 are connected between the output terminal VOUT and the application terminal of the control signal Vc2. That is, the output circuit 11 limits the control signal Vc2 in accordance with the difference signal V21.

[0060] With this configuration, an offset voltage Vofs determined by the ratio of resistors R22 and R23 is generated across resistor R22. As a result, the operating voltage range of the overcurrent protection circuit 10 is expanded without affecting the operation of the power supply 1. This enables stable overcurrent protection operation independent of manufacturing variations, temperature conditions, and the like.

[0061] Note that the introduction of resistor R22 widens the operating voltage range of the overcurrent protection circuit 10, but at the cost of potentially increasing the minimum operating voltage of the power supply device 1 by the offset voltage Vofs. Therefore, the ratio of resistors R22 and R23 may be fine-tuned taking into account the above trade-off. For example, the offset voltage Vofs may be set to 100 to 200 mV.

[0062] Fifth Embodiment 8 is a diagram showing a fifth embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the fourth embodiment (FIG. 7), but the drive signal generating circuit 12 is modified.

[0063] Referring to this figure, in the drive signal generation circuit 12, the resistor R23 mentioned above has been replaced with a current source CS2. The current source CS2 is connected between the ground terminal GND and the application terminal of the drive signal G20 to generate a constant current I22. This configuration also provides the same functions and effects as the fourth embodiment (FIG. 7).

[0064] <Combination of embodiments> The first to fifth embodiments described above may be combined as appropriate as long as no contradictions occur. For example, although not shown separately, the resistor R22 in the fourth embodiment (FIG. 7) or the fifth embodiment (FIG. 8) may be replaced with a diode-connected transistor (or a diode) in accordance with the second embodiment (FIG. 5).

[0065] <Additional Notes> The overcurrent protection circuit according to the present disclosure can perform stable overcurrent protection operation regardless of manufacturing variations, temperature conditions, etc. The following additional notes are provided regarding the above disclosure.

[0066] [Appendix 1] Detecting resistors (R10, R20) connected between the first terminal (VIN) and the second terminal (VOUT); detection transistors (M11, M21) connected in series with the detection resistors (R10, R20) between the first terminal (VIN) and the second terminal (VOUT), and configured so that drive signals (G10, G20) for output transistors (M10, M20) are applied to control electrodes thereof; an amplifier (A1, A2) connected between the first terminal (VIN) or the second terminal (VOUT) and an application terminal of a control signal (Vc1, Vc2), and configured to output a difference signal (V11, V21) between a detection voltage (Vs) appearing across both ends of the detection resistor (R10, R20) and a predetermined upper limit voltage (Vocp); an output circuit (11) configured to limit the control signals (Vc1, Vc2) or the drive signals (G10, G20) in response to the differential signals (V11, V21); a drive signal generating circuit (12) configured to generate the drive signals (G10, G20) by adding an offset (Vofs) to the control signals (Vc1, Vc2); An overcurrent protection circuit (10).

[0067] [Appendix 2] The overcurrent protection circuit (10) described in Appendix 1, wherein the drive signal generation circuit (12) includes first resistors (R12, R22) connected between an application terminal of the control signal (Vc1, Vc2) and an application terminal of the drive signal (G10, G20).

[0068] [Appendix 3] The overcurrent protection circuit (10) according to appendix 1 or 2, wherein the drive signal generation circuit (12) includes a transistor (M14) diode-connected between an application terminal of the control signal (Vc1, Vc2) and an application terminal of the drive signal (G10, G20).

[0069] [Appendix 4] The overcurrent protection circuit (10) according to any one of Appendices 1 to 3, wherein the drive signal generation circuit (12) includes a diode (D1) connected between an application terminal of the control signal (Vc1, Vc2) and an application terminal of the drive signal (G10, G20).

[0070] [Appendix 5] The overcurrent protection circuit (10) according to any one of Appendices 1 to 4, wherein the drive signal generation circuit (12) includes a second resistor (R13, R23) connected between the first terminal (VIN) or the second terminal (VOUT) and an application terminal of the drive signal (G10, G20).

[0071] [Appendix 6] The overcurrent protection circuit (10) according to any one of Appendices 1 to 4, wherein the drive signal generation circuit (12) includes current sources (CS1, CS2) connected to application terminals of the drive signals (G10, G20) and configured to generate constant currents (I12, I22).

[0072] [Appendix 7] An overcurrent protection circuit (10) according to any one of Supplementary Notes 1 to 6; the first terminal (VIN) and the second terminal (VOUT); the output transistors (M10, M20) connected between the first terminal (VIN) and the second terminal (VOUT); an error amplifier (20) configured to perform feedback control of the control signals (Vc1, Vc2) so that a feedback voltage Vfb corresponding to a voltage applied to the second terminal (VOUT) coincides with a reference voltage Vref; A semiconductor device (100) comprising:

[0073] [Appendix 8] The output transistor (M10) is a P-channel type or a PNP type, 8. The semiconductor device (100) according to claim 7, wherein the amplifier (A1) and the output circuit (11) are both connected between the first terminal (VIN) and an application terminal of the control signal (Vc1).

[0074] [Appendix 9] The output transistor (M20) is an N-channel type or an npn type, The semiconductor device (100) described in Appendix 7, wherein the amplifier (A2) and the output circuit (11) are both connected between the second terminal (VOUT) and an application terminal of the control signal (Vc2).

[0075] [Appendix 10] A semiconductor device (100) according to any one of Supplementary Notes 7 to 9, The power supply device (1) generates a desired output voltage (Vout) from an input voltage (Vin) input to the first terminal (VIN) and outputs the output voltage to the second terminal (VOUT).

[0076] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. For example, the NMOSFET and PMOSFET can be replaced with npn-type and pnp-type bipolar transistors, respectively. In such a case, the drain, source, and gate described above can be read as the emitter, collector, and base, respectively.

[0077] As such, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. The technical scope of the present disclosure is defined by the claims, and it should be understood that all modifications within the meaning and scope of the claims are included. [Explanation of symbols]

[0078] 1 Power supply (linear power supply) 10 Overcurrent protection circuit 11 Output circuit 12 Drive signal generation circuit 20 Error amplifier 30 Feedback voltage generation circuit 31, 32 Resistor 40 Reference voltage generation circuit 100 Semiconductor device A1, A2 amplifiers Co capacitor CS1, CS2 current source D1 Diode GND Grounding terminal M10 Output transistor (PMOSFET) M11 Detect transistor (PMOSFET) M12 Transistor (PMOSFET) M13 Transistor (NMOSFET) M14 Transistor (PMOSFET) M20 Output transistor (NMOSFET) M21 Detect transistor (NMOSFET) M22 transistor (NMOSFET) M23 Transistor (PMOSFET) OUT output terminal R10, R20 detection resistors R11~R13, R21~R23 resistance VIN input terminal

Claims

1. a sense resistor connected between the first terminal and the second terminal; a detection transistor connected in series with the detection resistor between the first terminal and the second terminal, the detection transistor configured to receive a drive signal for an output transistor at a control electrode thereof; an amplifier connected between the first terminal or the second terminal and a terminal to which a control signal is applied, and configured to output a differential signal between a detection voltage appearing across both ends of the detection resistor and a predetermined upper limit voltage; an output circuit configured to limit the control signal or the drive signal in response to the differential signal; a drive signal generating circuit configured to generate the drive signal by adding an offset to the control signal; An overcurrent protection circuit comprising:

2. 2. The overcurrent protection circuit according to claim 1, wherein the drive signal generation circuit includes a first resistor connected between an application terminal of the control signal and an application terminal of the drive signal.

3. 2. The overcurrent protection circuit according to claim 1, wherein the drive signal generation circuit includes a transistor diode-connected between an application terminal of the control signal and an application terminal of the drive signal.

4. 2. The overcurrent protection circuit according to claim 1, wherein the drive signal generation circuit includes a diode connected between an application terminal of the control signal and an application terminal of the drive signal.

5. The overcurrent protection circuit according to claim 1 , wherein the drive signal generation circuit includes a second resistor connected between the first terminal or the second terminal and an application terminal of the drive signal.

6. The overcurrent protection circuit according to claim 1 , wherein the drive signal generation circuit includes a current source connected to an application terminal of the drive signal and configured to generate a constant current.

7. an overcurrent protection circuit according to claim 1; the first terminal and the second terminal; the output transistor connected between the first terminal and the second terminal; an error amplifier configured to perform feedback control of the control signal so that a feedback voltage corresponding to a voltage applied to the second terminal coincides with a reference voltage; A semiconductor device comprising:

8. the output transistor is a P-channel type or a PNP type; 8. The semiconductor device according to claim 7, wherein the amplifier and the output circuit are both connected between the first terminal and an application terminal of the control signal.

9. the output transistor is an N-channel type or an npn type, 8. The semiconductor device according to claim 7, wherein the amplifier and the output circuit are both connected between the second terminal and an application terminal of the control signal.

10. A semiconductor device according to any one of claims 7 to 9, A power supply device that generates a desired output voltage from an input voltage input to the first terminal and outputs the output voltage to the second terminal.

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