Information processing program, information processing method, and information processing device

Abstract

To reduce the processing time that is required when executing a quantum circuit.SOLUTION: An information processing device 100 acquires the result of having executed, by a DD type quantum simulator 106, a quantum circuit 108 which solves a second problem by performing arithmetic operation on a plurality of second quantum bits for each of a plurality of schemes 103, and for which the scheme is adopted. The information processing device 100 selects one scheme to be applied to a quantum circuit 101 that solves a first problem among the plurality of schemes 103 on the basis of the result of having executed the quantum circuit 108, for which acquired respective schemes are adopted, by the DD type quantum simulator 106. The information processing device 100 generates a quantum circuit 109 which solves the first problem by performing arithmetic operation on a plurality of first quantum bits, and for which the selected one scheme is adopted. The information processing device 100 executes the generated quantum circuit 109 by the DD type quantum simulator 106 and thereby acquires the result of having solved the first problem.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing program, an information processing method, and an information processing device. [Background technology]

[0002] Conventionally, there are quantum simulators that use a decision diagram to represent vectors that represent the quantum states of multiple quantum bits. This quantum simulator has the property that the processing time required to execute a quantum circuit that performs operations on multiple quantum bits varies depending on the order in which the multiple quantum bits are arranged. Therefore, it is desirable to reduce the processing time required to execute a quantum circuit by inserting gates that swap different quantum bits into the quantum circuit. There is also a method for implementing this quantum simulator using parallel processing on multiple computing devices.

[0003] In contrast, prior art techniques include, for example, implementing a parallelization component that can permute a first qubit, which may be a control qubit, with a second qubit, and a replication component that can simulate a controlled-NOT gate during the permute by the parallelization component. Other techniques include, for example, inserting a SWAP gate so that all gates in a quantum circuit are local. Other techniques include, for example, estimating the fidelity of a quantum computing system. Other techniques include, for example, converting a first quantum circuit into a second quantum circuit that includes a set of standard trapped-ion gates. Other techniques include, for example, restricting the properties of the extended Clifford group to a special case and approximating it on a 2n-dimensional complex vector space. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2022-510138 [Patent Document 2] US Patent Application Publication No. 2020 / 0242295 [Patent Document 3] US Patent Application Publication No. 2022 / 0374750 [Patent Document 4] Special Publication No. 2023-543703 [Patent Document 5] Japanese Patent Application Laid-Open No. 2012-063838 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional techniques can increase the processing time required to execute a quantum circuit. For example, it is not possible to determine how to insert gates that swap different quantum bits into a quantum circuit executed by a quantum simulator that represents combinations of quantum states as a decision diagram, which increases the processing time required to execute the quantum circuit.

[0006] In one aspect, the present invention aims to reduce the processing time required to execute a quantum circuit. [Means for solving the problem]

[0007] According to one embodiment, there are provided a plurality of methods for swapping local and global quantum bits so as to reduce the cost of solving a problem by inserting gates that swap different quantum bits into a quantum circuit that solves the problem, the method including a first method for swapping local and global quantum bits so as to reduce a difference in the arrangement of quantum bits in the quantum circuit that solves the problem before and after inserting the gate into the quantum circuit that solves the problem, and a second method for swapping local and global quantum bits so as to reduce the number of times the gate is inserted into the quantum circuit that solves the problem, and each of the methods is performed according to the same algorithm as for the first problem. and solving a second problem smaller in scale than the first problem by applying the method to the quantum circuit, obtaining the results of executing the quantum circuit to which the method is applied in a quantum simulator that represents combinations of different quantum states as a decision diagram, and based on the results of executing the quantum circuits to which the method for solving the second problem is applied in the quantum simulator, selecting one of the multiple methods to apply to the quantum circuit that solves the first problem, and solving the first problem by performing operations on multiple first quantum bits in accordance with the algorithm.An information processing program, an information processing method, and an information processing device are proposed that obtain the results of solving the first problem by executing the quantum circuit to which the selected method is applied in the quantum simulator. [Effects of the Invention]

[0008] According to one aspect, it is possible to reduce the processing time required to execute a quantum circuit. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is an explanatory diagram illustrating an example of an information processing method according to an embodiment. [Figure 2] FIG. 2 is an explanatory diagram illustrating an example of an information processing system 200. As shown in FIG. [Figure 3] FIG. 3 is a block diagram showing an example of the hardware configuration of the information processing device 100. As shown in FIG. [Figure 4] FIG. 4 is a block diagram showing an example of the functional configuration of the information processing device 100. As shown in FIG. [Figure 5] FIG. 5 is an explanatory diagram showing an example of a DD type simulator. [Figure 6] FIG. 6 is an explanatory diagram showing an example of the operation of the information processing device 100. [Figure 7] FIG. 7 is a flowchart (part 1) illustrating an example of the overall processing procedure. [Figure 8] FIG. 8 is a flowchart (part 2) illustrating an example of the overall processing procedure. [Figure 9] FIG. 9 is a flowchart illustrating an example of a procedure of the first insertion process. [Figure 10] FIG. 10 is a flowchart illustrating an example of a procedure of the second insertion process. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an information processing program, an information processing method, and an information processing device according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0011] (An example of an information processing method according to an embodiment) 1 is an explanatory diagram illustrating an example of an information processing method according to an embodiment. The information processing device 100 is a computer for inserting gates that swap different quantum bits into a quantum circuit that solves a target problem. The information processing device 100 is, for example, a server or a PC (Personal Computer).

[0012] A quantum circuit is, for example, information that indicates what operation is to be performed on one or more quantum bits. A quantum circuit includes one or more gates that indicate the content of the operation to be performed on the quantum bits. The gates are, for example, a Hadamard gate, a controlled X gate, a controlled Y gate, a controlled Z gate, or a rotation gate. A quantum circuit is executed, for example, on an actual quantum computer or a quantum simulator that simulates a quantum computer. Execution involves performing an operation on one or more quantum bits to transition the quantum states represented by each quantum bit and determine the final combination of quantum states represented by each quantum bit.

[0013] For example, a real quantum computer may be in a situation where the number of users who can use it is limited. Furthermore, a real quantum computer may be shared by multiple users, resulting in waiting times for use. For example, a real quantum computer may be in a situation where the cost of using it is relatively high. For example, a real quantum computer may be in a situation where errors occur due to environmental noise, interference between qubits, and noise during qubit operation. Given these circumstances, it may be desirable to run a quantum circuit that solves a target problem on a quantum simulator.

[0014] There are quantum simulators that handle combinations of quantum states represented by each of a plurality of quantum bits using a decision graph. A decision graph includes a plurality of graph nodes. The graph nodes are connected by edges. In a decision graph, for example, the edges connected to the graph nodes represent coefficients. In a decision graph, for example, a path from the root to a leaf represents a combination of quantum states. In a decision graph, for example, the product of the coefficients of the edges on the path corresponds to the probability of the combination of quantum states. An example of a decision graph will be described later using Figure 5.

[0015] In the following explanation, the decision diagram may be abbreviated as "DD." Also, in the following explanation, this quantum simulator may be abbreviated as "DD-type quantum simulator." DD-type quantum simulators are thought to be able to suppress the increase in memory usage required to store the combinations of quantum states represented by each quantum bit. DD-type quantum simulators are also thought to be effective for quantum algorithms such as the Shor algorithm. In DD-type quantum simulators, the processing time required to execute a quantum circuit tends to vary depending on the shape of the DD used to represent the combinations of quantum states represented by each quantum bit.

[0016] Furthermore, in order to reduce the processing time required to execute a quantum circuit, it may be desirable to realize a DD quantum simulator by parallel processing of multiple computing devices connected to each other in a communicative manner. For example, since the DD tends to become larger as the number of quantum bits increases, it may be desirable to share and handle the DD among multiple processes on multiple computing devices. Here, one computing device may be responsible for two or more processes. A computing device is also called a node. The method of realizing a DD quantum simulator by parallel processing of multiple computing devices is also called a multi-node.

[0017] Here, in a multi-node, when a quantum circuit is executed, if an operation is performed on one or more qubits and the quantum state of one or more qubits is transitioned, inter-process communication may occur. Furthermore, if inter-process communication occurs between two or more processes that exist on different computing devices, inter-node communication may also occur. A qubit that causes inter-process communication may be called, for example, a "global qubit." A qubit that does not cause inter-process communication may be called, for example, a "local qubit."

[0018] For example, the DD for N quantum bits is 2 MWhen handling N qubits, the first NM qubits tend to be local qubits, and the last M qubits tend to be global qubits. For example, the number of processes handling DD is called the parallelism. Here, the parallelism is 2 M Therefore, when the quantum state of any of the M qubits at the end of the N qubits is to be transitioned, inter-node communication may occur. Here, the time required for inter-node communication tends to be relatively long. Furthermore, when inter-node communication occurs, it leads to an increase in the processing time required to execute the quantum circuit.

[0019] Thus, depending on the order in which multiple quantum bits are arranged, the processing time required to execute a quantum circuit may increase due to the global quantum bit described above. Therefore, in order to reduce the processing time required to execute a quantum circuit, it is preferable to control the order in which multiple quantum bits are arranged so that the local quantum bit and the global quantum bit are swapped. Specifically, it is preferable to insert a gate that swaps different quantum bits into the quantum circuit in order to reduce the processing time required to execute the quantum circuit. The gate that swaps different quantum bits is, for example, a SWAP gate.

[0020] However, conventional methods have been unable to properly determine how to insert gates that swap different qubits into quantum circuits executed by DD quantum simulators, which can result in increased processing time when executing the quantum circuit. For example, one possible method is to update the quantum circuit by inserting a gate representing an operation that swaps a local qubit with a global qubit immediately before a gate representing an operation that generates inter-node communication.

[0021] This method is intended for application to quantum simulators that handle combinations of quantum states represented by each qubit as state vectors. This method may not be suitable for use with DD quantum simulators, and may instead increase the processing time required to execute a quantum circuit. Furthermore, no method suitable for use with DD quantum simulators has been proposed for automatically inserting gates that swap different qubits into a quantum circuit. For this reason, it has traditionally been difficult to reduce the processing time required to execute a quantum circuit.

[0022] Therefore, in this embodiment, an information processing method that can reduce the processing time required to execute a quantum circuit will be described. According to this information processing method, gates that swap different quantum bits can be appropriately inserted into a quantum circuit that solves a target problem so as to reduce the processing time required to execute the quantum circuit.

[0023] 1, an information processing device 100 acquires a quantum circuit 101 that solves a first problem by performing an operation on a plurality of first quantum bits according to a predetermined algorithm. The information processing device 100 acquires the quantum circuit 101 based on, for example, a user's operation input via an input device (not shown). Here, it is assumed that the order in which the plurality of first quantum bits are initially arranged is fixed.

[0024] The information processing device 100 acquires a quantum circuit 102 that solves a second problem, the second problem being smaller in scale than the first problem, by performing an operation on a plurality of second quantum bits according to the same algorithm as the first problem. The number of first quantum bits and the number of second quantum bits may, for example, be the same or different. The information processing device 100 acquires the quantum circuit 102, for example, based on a user's operation input via an input device (not shown). The information processing device 100 may, for example, acquire a quantum circuit 102 that has been set in advance by a user. The information processing device 100 may, for example, acquire the quantum circuit 102 by generating it with reference to the quantum circuit 101.

[0025] The information processing device 100 stores a plurality of methods 103 for swapping local and global quantum bits so as to reduce the cost of solving a problem by inserting a gate that swaps different quantum bits into a quantum circuit that solves the problem. The gate that swaps different quantum bits is, for example, a SWAP gate.

[0026] The multiple techniques 103 include, for example, a first technique 104 that swaps local quantum bits and global quantum bits so that a difference in the arrangement of quantum bits in a quantum circuit that solves a problem before and after inserting a gate into the quantum circuit that solves the problem becomes small. The multiple techniques 103 include, for example, a second technique 105 that swaps local quantum bits and global quantum bits so that a number of times gates are inserted into the quantum circuit that solves the problem becomes small. The multiple techniques 103 may also include, for example, one or more other techniques different from first technique 104 and second technique 105.

[0027] As shown in FIG. 1 , specifically, one of the plurality of methods 103 functions to insert a swap gate 121 into a quantum circuit 110 to generate a quantum circuit 120 that is logically equivalent to the quantum circuit 110. In the quantum circuit 110, for example, it is possible that quantum bits a and b are local quantum bits and quantum bits c and d are global quantum bits. In this case, if gates 111, 112, etc., that relate to the global quantum bit exist, inter-process communication occurs. In contrast, one of the plurality of methods 103 functions to suppress inter-process communication by, for example, using the swap gate 121, preventing gates 122, 123, etc., that correspond to gates 111, 112, from being involved in the global quantum bit.

[0028] The information processing device 100 can use a DD quantum simulator 106. The DD quantum simulator 106 handles combinations of different quantum states by expressing them in DD. The DD quantum simulator 106 is realized, for example, by parallel processing of multiple arithmetic devices connected to each other in a communicative manner. The information processing device 100 may operate as any one of the multiple arithmetic devices. The information processing device 100 can acquire the results of executing a quantum circuit using the DD quantum simulator 106. The information processing device 100 acquires the parallel number 107 of the DD quantum simulator 106.

[0029] (1-1) The information processing device 100 acquires a result of executing, on the DD quantum simulator 106, a quantum circuit 108 to which each of the multiple methods 103 is applied, which solves a second problem by performing an operation on a plurality of second quantum bits. The quantum circuit 108 is, for example, logically equivalent to the quantum circuit 102. The quantum circuit 108 represents performing an operation on a plurality of second quantum bits according to a predetermined algorithm. For example, the information processing device 100 acquires, as a result of executing, on the DD quantum simulator 106, the quantum circuit 108 to which each method is applied, the processing time required when the quantum circuit 108 to which each method is applied is executed.

[0030] Specifically, the information processing device 100 references the parallelism number 107 and applies the method to the acquired quantum circuit 102 for each method, thereby generating a quantum circuit 108. Specifically, the information processing device 100 uses the DD quantum simulator 106 to acquire a result of executing the generated quantum circuit 108 with the DD quantum simulator 106. More specifically, the information processing device 100 acquires, as a result of executing the generated quantum circuit 108 with the DD quantum simulator 106, the processing time required to execute the generated quantum circuit 108 with the DD quantum simulator 106. This allows the information processing device 100 to evaluate whether each of the multiple methods 103 is useful from the perspective of reducing the processing time required to solve the first problem.

[0031] (1-2) The information processing device 100 selects one of the multiple methods 103 to be applied to the quantum circuit 101 that solves the first problem, based on the results of executing the acquired quantum circuits 108 to which each method is applied, using the DD quantum simulator 106. The information processing device 100 selects, for example, the method with the shortest acquired processing time from the multiple methods 103, as the method to be applied to the quantum circuit 101 that solves the first problem. This allows the information processing device 100 to appropriately select, from the multiple methods 103, a method that is useful from the perspective of reducing the processing time required to solve the first problem.

[0032] (1-3) The information processing device 100 generates a quantum circuit 109 by applying one of the selected methods, which solves the first problem by performing an operation on a plurality of first quantum bits. The quantum circuit 109 is logically equivalent to, for example, the quantum circuit 101. The information processing device 100 executes the generated quantum circuit 109 in a DD quantum simulator 106 to obtain a result of solving the first problem. The information processing device 100 obtains, for example, a final combination of quantum states represented by each of the first quantum bits as a result of solving the first problem.

[0033] This allows the information processing device 100 to appropriately insert a gate that swaps different first quantum bits into the quantum circuit 101 that solves the first problem. Therefore, the information processing device 100 can generate a quantum circuit 109 that solves the first problem, which can be executed in a shorter processing time than the quantum circuit 101 that solves the first problem. The information processing device 100 can suppress an increase in the processing time required to execute the quantum circuit 109 that solves the first problem. By executing the quantum circuit 109 that solves the first problem, the information processing device 100 can reduce the processing time required to solve the first problem.

[0034] Here, the case where the information processing device 100 initially arranges the first quantum bits in a fixed order has been described, but this is not limiting. For example, the information processing device 100 may consider an order that is useful from the perspective of reducing the processing time required to solve the first problem, from among multiple orders in which the first quantum bits are initially arranged.

[0035] For example, the information processing device 100 considers an order that is useful from the perspective of reducing the processing time required to solve the first problem, and then selects one of the multiple methods 103 to apply to the quantum circuit 101 that solves the first problem. The case where the information processing device 100 considers an order from the multiple orders that is useful from the perspective of reducing the processing time required to solve the first problem will be described later with reference to, for example, FIGS. 5 and 6.

[0036] Here, the case where the functions of the information processing device 100 are realized by a single computer has been described, but this is not limiting. For example, the functions of the information processing device 100 may be realized by cooperation of multiple computers. For example, the functions of the information processing device 100 may be realized on the cloud.

[0037] (An example of the information processing system 200) Next, an example of an information processing system 200 to which the information processing device 100 shown in FIG. 1 is applied will be described with reference to FIG.

[0038] 2 is an explanatory diagram showing an example of an information processing system 200. In FIG. 2, the information processing system 200 includes an information processing device 100, a parallel processing system 202 including a plurality of arithmetic devices 201, and one or more client devices 203.

[0039] In the information processing system 200, the information processing device 100 and the arithmetic device 201 are connected via a wired or wireless network 210. The network 210 is, for example, a local area network (LAN), a wide area network (WAN), the Internet, etc. In the information processing system 200, the information processing device 100 and the client device 203 are connected via the wired or wireless network 210.

[0040] The information processing device 100 is a computer for inserting a SWAP gate into a quantum circuit that solves a target problem. The target problem is, for example, a first problem. The information processing device 100 receives a processing request to solve the first problem from a client device 203. The processing request includes, for example, a quantum circuit that solves the first problem. The processing request includes, for example, a quantum circuit that solves a second problem that is smaller in scale than the first problem.

[0041] The quantum circuit that solves the first problem is information that, for a plurality of first quantum bits, defines gates that represent each operation of a series of operations to be performed on the plurality of first quantum bits in a time series. The quantum circuit that solves the first problem is information that makes it possible to solve the first problem by performing a series of operations on the plurality of first quantum bits.

[0042] The quantum circuit that solves the second problem is information that specifies, in time sequence, gates that represent each operation in a series of operations to be performed on the second quantum bits, and that enables the second problem to be solved by performing a series of operations on the second quantum bits according to the same algorithm as the first problem.

[0043] The information processing device 100 stores multiple methods for swapping local and global quantum bits to reduce the cost of solving a problem by inserting a SWAP gate into the quantum circuit that solves the problem. The cost is, for example, processing time.

[0044] The multiple techniques include, for example, a first technique of swapping local qubits and global qubits so that the difference in the arrangement of qubits in a quantum circuit that solves a problem is reduced before and after inserting a SWAP gate into the quantum circuit that solves the problem. Specifically, the first technique reduces the difference in the arrangement of qubits in the quantum circuit before and after each insertion of one or more SWAP gates to swap local qubits and global qubits into the quantum circuit. The multiple techniques include, for example, a second technique of swapping local qubits and global qubits so that the number of times SWAP gates are inserted into the quantum circuit that solves the problem is reduced.

[0045] The information processing device 100 acquires a quantum circuit that solves a first problem. For example, the information processing device 100 acquires the quantum circuit that solves the first problem by extracting it from a received processing request. The information processing device 100 acquires a quantum circuit that solves a second problem. For example, the information processing device 100 acquires the quantum circuit that solves the second problem by extracting it from a received processing request. For example, the information processing device 100 may acquire the quantum circuit that solves the second problem by generating it based on the acquired quantum circuit that solves the first problem.

[0046] As will be described below, the information processing device 100 generates another quantum circuit that is logically equivalent to the acquired quantum circuit that solves the first problem, so as to reduce the processing time required to solve the first problem.

[0047] For example, the information processing device 100 considers an order that is useful from the perspective of reducing the processing time required to solve the first problem from among a plurality of orders for initially arranging a plurality of first quantum bits, and selects one of the orders. Specifically, the information processing device 100 stores a plurality of types of orders for arranging quantum bits. The plurality of types includes, for example, at least the first type and the second type of orders, among a first type in which the quantum bits are arranged in the original order, a second type in which the quantum bits are arranged in the reverse order of the original order, and a third type in which the quantum bits are arranged in the order in which they were specified.

[0048] Specifically, the information processing device 100 generates, for each of the multiple types, a quantum circuit for solving the second problem that performs an operation on multiple second quantum bits in the order of the types, based on the acquired quantum circuit for solving the second problem. Specifically, the information processing device 100 controls the parallel processing system 202 to execute, in a DD quantum simulator, the quantum circuit for solving the second problem that performs an operation on multiple second quantum bits in the order of each type. Specifically, the information processing device 100 controls the parallel processing system 202 by transmitting the quantum circuit for solving the second problem that performs an operation on multiple second quantum bits in the order of each type to each arithmetic device 201.

[0049] Specifically, the information processing device 100 executes a quantum circuit that solves a second problem, which performs an operation on a plurality of second quantum bits in the order of each type, and measures the processing time required to execute the quantum circuit that solves the second problem. Specifically, the information processing device 100 selects, from among the plurality of types, one type with the shortest measured processing time as the type that is useful from the perspective of reducing the processing time required to solve the first problem. In this way, the information processing device 100 considers an order that is useful from the perspective of reducing the processing time required to solve the first problem.

[0050] For example, the information processing device 100 considers a method from among a plurality of methods that is useful from the perspective of reducing the processing time required to solve the first problem, and selects one of the methods. Specifically, the information processing device 100 applies each method to a quantum circuit that solves a second problem that performs an operation on a plurality of second quantum bits in any of the selected types of order, thereby generating a quantum circuit that solves the second problem to which each method is applied.

[0051] Specifically, the information processing device 100 controls the parallel processing system 202 to execute, in a DD quantum simulator, a quantum circuit that solves the second problem to which each method is applied. Specifically, the information processing device 100 controls the parallel processing system 202 by transmitting, to each arithmetic device 201, a quantum circuit that solves the second problem to which each method is applied.

[0052] Specifically, the information processing device 100 executes a quantum circuit that solves the second problem to which each of the methods is applied, and measures the processing time required to execute the quantum circuit that solves the second problem to which each of the methods is applied. Specifically, the information processing device 100 selects, from among the multiple methods, one of the methods that has the shortest measured processing time as a method that is useful from the perspective of reducing the processing time required to solve the first problem.

[0053] The information processing device 100 generates another quantum circuit that is logically equivalent to the quantum circuit that solves the acquired first problem, for example, based on any of the selected types and any of the selected methods. Specifically, the information processing device 100 generates a quantum circuit that solves the first problem, which performs an operation on multiple first quantum bits in an order of any of the selected types, based on the quantum circuit that solves the acquired first problem.

[0054] Specifically, the information processing device 100 applies one of the selected methods to the generated quantum circuit for solving the first problem, thereby generating a quantum circuit for solving the first problem to which one of the selected methods has been applied. In this way, the information processing device 100 generates another quantum circuit that is logically equivalent to the acquired quantum circuit for solving the first problem, so as to reduce the processing time required to solve the first problem.

[0055] The information processing device 100 controls the parallel processing system 202 to execute, in a DD quantum simulator, the generated quantum circuit that solves the first problem to which any of the methods has been applied. Specifically, the information processing device 100 controls the parallel processing system 202 by transmitting the generated quantum circuit that solves the first problem to which any of the methods has been applied to each arithmetic device 201. The information processing device 100 receives, from the arithmetic device 201, the probabilities of the final combinations of quantum states as a result of executing the quantum circuit that solves the first problem.

[0056] The information processing device 100 transmits the result of executing the received quantum circuit for solving the first problem to the client device 203. This allows the information processing device 100 to reduce the processing time required to execute the quantum circuit for solving the first problem, and reduces the processing time required to solve the first problem. The information processing device 100 is, for example, a server or a PC.

[0057] The arithmetic device 201 is a computer for parallel processing a DD-type quantum simulator that simulates changes in quantum state combinations due to calculations. The arithmetic device 201 has a process for managing a DD that represents a combination of quantum states. The arithmetic device 201 executes a quantum circuit under the control of the information processing device 100. For example, the arithmetic device 201 receives a quantum circuit to be executed from the information processing device 100. For example, the arithmetic device 201 cooperates with other arithmetic devices 201 and executes the received quantum circuit to update the DD that it manages. The arithmetic device 201 transmits the result of executing the quantum circuit to the information processing device 100. For example, the arithmetic device 201 transmits the probability of the final quantum state combination to the information processing device 100 as the result of executing the quantum circuit based on the updated DD. The arithmetic device 201 is, for example, a server or a PC.

[0058] The client device 203 is a computer used by a worker. The client device 203 accepts designation of a quantum circuit for solving a first problem based on operational input by the worker via an input device (not shown). The client device 203 accepts designation of a quantum circuit for solving a second problem based on operational input by the worker via an input device (not shown). The client device 203 generates a processing request including a quantum circuit for solving the first problem for which designation has been accepted and a quantum circuit for solving the second problem for which designation has been accepted, and transmits the processing request to the information processing device 100. The client device 203 receives a result of solving the first problem from the information processing device 100. The client device 203 outputs the result of solving the first problem so that the worker can refer to it. The client device 203 is, for example, a PC, a tablet terminal, or a smartphone.

[0059] Here, the case where the information processing device 100 is a device different from the arithmetic device 201 has been described, but this is not limiting. For example, the information processing device 100 may have the function of the arithmetic device 201 and operate as the arithmetic device 201. Here, the case where the information processing device 100 is a device different from the client device 203 has been described, but this is not limiting. For example, the information processing device 100 may have the function of the client device 203 and operate as the client device 203.

[0060] (Example of hardware configuration of information processing device 100) Next, an example of the hardware configuration of the information processing device 100 will be described with reference to FIG.

[0061] Fig. 3 is a block diagram showing an example of the hardware configuration of the information processing device 100. In Fig. 3, the information processing device 100 has a CPU (Central Processing Unit) 301, a memory 302, a network I / F (Interface) 303, a recording medium I / F 304, and a recording medium 305. Furthermore, each component is connected to each other by a bus 300.

[0062] Here, CPU 301 is responsible for overall control of information processing device 100. Memory 302 includes, for example, a read-only memory (ROM), a random access memory (RAM), and a flash ROM. Specifically, for example, the flash ROM or ROM stores various programs, and RAM is used as a work area for CPU 301. The programs stored in memory 302 are loaded into CPU 301, causing CPU 301 to execute coded processes.

[0063] The network I / F 303 is connected to the network 210 via a communication line, and is connected to other computers via the network 210. The network I / F 303 manages the internal interface with the network 210 and controls the input and output of data from other computers. The network I / F 303 is, for example, a modem or a LAN adapter.

[0064] The recording medium I / F 304 controls reading and writing of data from and to the recording medium 305 under the control of the CPU 301. The recording medium I / F 304 is, for example, a disk drive, a solid state drive (SSD), or a universal serial bus (USB) port. The recording medium 305 is a non-volatile memory that stores data written under the control of the recording medium I / F 304. The recording medium 305 is, for example, a disk, a semiconductor memory, or a USB memory. The recording medium 305 may be detachable from the information processing device 100.

[0065] In addition to the components described above, the information processing device 100 may also include, for example, a keyboard, a mouse, a display, a printer, a scanner, a microphone, a speaker, etc. The information processing device 100 may also include a plurality of recording medium I / Fs 304 and recording media 305. The information processing device 100 may also not include the recording medium I / Fs 304 and recording media 305.

[0066] (Example of hardware configuration of arithmetic device 201) A specific example of the hardware configuration of the arithmetic device 201 is similar to the example of the hardware configuration of the information processing device 100 shown in FIG. 3, and therefore a description thereof will be omitted.

[0067] (Example of hardware configuration of client device 203) A specific example of the hardware configuration of the client device 203 is similar to the example of the hardware configuration of the information processing device 100 shown in FIG. 3, and therefore a description thereof will be omitted.

[0068] (Example of functional configuration of information processing device 100) Next, an example of the functional configuration of the information processing device 100 will be described with reference to FIG.

[0069] Fig. 4 is a block diagram showing an example of the functional configuration of the information processing device 100. In Fig. 4, the information processing device 100 can use a DD quantum simulator 410. The DD quantum simulator 410 is realized, for example, by parallel processing of a plurality of arithmetic devices 201 that are communicatively connected.

[0070] The information processing device 100 includes a storage unit 400 , an acquisition unit 401 , a first selection unit 402 , a second selection unit 403 , an execution unit 404 , and an output unit 405 .

[0071] The storage unit 400 is realized by, for example, a storage area such as the memory 302 or the recording medium 305 shown in Fig. 3. In the following, a case where the storage unit 400 is included in the information processing device 100 will be described, but this is not limiting. For example, the storage unit 400 may be included in a device different from the information processing device 100, and the stored contents of the storage unit 400 may be accessible from the information processing device 100.

[0072] The acquiring unit 401 to the output unit 405 function as an example of a control unit. Specifically, the acquiring unit 401 to the output unit 405 realize their functions by causing the CPU 301 to execute a program stored in a storage area such as the memory 302 or the recording medium 305 shown in Fig. 3, or by using the network I / F 303. The processing results of each functional unit are stored in a storage area such as the memory 302 or the recording medium 305 shown in Fig. 3, for example.

[0073] The storage unit 400 stores various information that is referenced or updated during processing by each functional unit. The storage unit 400 stores, for example, one of the quantum circuits executed when solving the first problem, which is the target problem. In the following description, the quantum circuit executed when solving the first problem may be referred to as the "quantum circuit that solves the first problem." The quantum circuit that solves the first problem is information related to multiple first quantum bits. The quantum circuit that solves the first problem is, for example, information that enables the first problem to be solved by performing operations on the multiple first quantum bits according to a predetermined algorithm. The quantum circuit that solves the first problem is acquired, for example, by the acquisition unit 401. The storage unit 400 stores, for example, identification information that identifies each first quantum bit of the multiple first quantum bits that perform operations when solving the first problem. The identification information that identifies the first quantum bit is acquired, for example, by the acquisition unit 401.

[0074] The storage unit 400 stores, for example, one of the quantum circuits executed when solving a second problem that is smaller in scale than the first problem. In the following description, the quantum circuit executed when solving the second problem may be referred to as a "quantum circuit that solves the second problem." The quantum circuit that solves the second problem is information about multiple second quantum bits. The first quantum bits and the second quantum bits may be the same or different. The quantum circuit that solves the second problem is information that enables the second problem to be solved by performing operations on multiple second quantum bits according to the same predetermined algorithm as the first problem. The quantum circuit that solves the second problem is acquired, for example, by the acquisition unit 401. The storage unit 400 stores, for example, identification information that identifies each second quantum bit of the multiple second quantum bits that perform operations when solving the second problem. The identification information that identifies the second quantum bits is acquired, for example, by the acquisition unit 401.

[0075] The storage unit 400 stores a plurality of methods for swapping at least a local qubit and a global qubit in a quantum circuit that solves a certain problem, for example, to reduce the cost of solving the problem. The cost may be, for example, processing time or processing load. Each method swaps at least a local qubit and a global qubit by inserting a gate that swaps different qubits into the quantum circuit that solves the certain problem.

[0076] The multiple techniques include, for example, a first technique of swapping local qubits and global qubits so that the difference in the arrangement of qubits in a quantum circuit that solves a problem before and after inserting a gate into the quantum circuit that solves the problem is reduced. Specifically, the first technique is such that, each time one or more SWAP gates are inserted into the quantum circuit to swap local qubits and global qubits, the difference in the arrangement of qubits in the quantum circuit before and after the insertion is reduced. The multiple techniques include, for example, a second technique of swapping local qubits and global qubits so that the number of times gates are inserted into the quantum circuit that solves the problem is reduced. The multiple techniques are acquired, for example, by the acquiring unit 401. The multiple techniques may be set in advance by a user, for example.

[0077] The storage unit 400 stores, for example, multiple types of orders for arranging quantum bits. The multiple types include, for example, at least the first type and the second type of a first type for arranging quantum bits in the original order, a second type for arranging quantum bits in the reverse order of the original order, and a third type for arranging quantum bits in the order specified and accepted. The first type is, for example, set by a user in advance. The second type is, for example, set by a user in advance. The third type is, for example, acquired by the acquisition unit 401. The third type may, for example, be set by a user in advance.

[0078] The acquisition unit 401 acquires various types of information used in processing by each functional unit. The acquisition unit 401 stores the acquired various types of information in the storage unit 400 or outputs it to each functional unit. The acquisition unit 401 may also output the various types of information stored in the storage unit 400 to each functional unit. The acquisition unit 401 acquires various types of information based on, for example, a user's operation input. The acquisition unit 401 may receive various types of information from, for example, a device different from the information processing device 100.

[0079] The acquiring unit 401 acquires, for example, a processing request requesting the solution of a first problem. The processing request includes, for example, one of the quantum circuits that solves the first problem. The processing request includes, for example, identification information that identifies each of the first quantum bits of the multiple first quantum bits. The processing request includes, for example, one of the quantum circuits that solves the second problem. The processing request includes, for example, identification information that identifies each of the second quantum bits of the multiple second quantum bits. Specifically, the acquiring unit 401 acquires the processing request requesting the solution of the first problem by accepting an input of the processing request requesting the solution of the first problem. Specifically, the acquiring unit 401 may acquire the processing request requesting the solution of the first problem by receiving the processing request requesting the solution of the first problem from another computer. The other computer is, for example, the client device 203.

[0080] The acquiring unit 401 acquires, for example, one of the quantum circuits that solves the first problem. Specifically, the acquiring unit 401 acquires one of the quantum circuits that solves the first problem by extracting one of the quantum circuits that solves the first problem from the acquired processing request. Specifically, the acquiring unit 401 acquires one of the quantum circuits that solves the first problem by accepting input of one of the quantum circuits that solves the first problem. Specifically, the acquiring unit 401 may acquire one of the quantum circuits that solves the first problem by receiving one of the quantum circuits that solves the first problem from another computer. The other computer is, for example, the client device 203. In the following description, one of the quantum circuits that solves the first problem acquired by the acquiring unit 401 may be referred to as an "initial quantum circuit that solves the first problem."

[0081] The acquiring unit 401 acquires, for example, one of the quantum circuits that solves the second problem. Specifically, the acquiring unit 401 acquires one of the quantum circuits that solves the second problem by extracting one of the quantum circuits that solves the second problem from the acquired processing request. Specifically, the acquiring unit 401 acquires one of the quantum circuits that solves the second problem by accepting input of one of the quantum circuits that solves the second problem. Specifically, the acquiring unit 401 may acquire one of the quantum circuits that solves the second problem by receiving one of the quantum circuits that solves the second problem from another computer. The other computer is, for example, the client device 203. In the following description, one of the quantum circuits that solves the second problem acquired by the acquiring unit 401 may be referred to as an "initial quantum circuit that solves the second problem."

[0082] The acquiring unit 401 acquires, for example, identification information identifying each of the multiple first quantum bits. Specifically, the acquiring unit 401 acquires the identification information identifying each of the first quantum bits by receiving input of the identification information identifying each of the first quantum bits. Specifically, the acquiring unit 401 may acquire the identification information identifying each of the first quantum bits by receiving the identification information identifying each of the first quantum bits from another computer. The other computer is, for example, the client device 203.

[0083] The acquiring unit 401 acquires, for example, identification information identifying each second quantum bit of the plurality of second quantum bits. Specifically, the acquiring unit 401 acquires the identification information identifying each second quantum bit by receiving input of the identification information identifying each second quantum bit. Specifically, the acquiring unit 401 may acquire the identification information identifying each second quantum bit by receiving the identification information identifying each second quantum bit from another computer. The other computer is, for example, the client device 203.

[0084] The acquisition unit 401 acquires, for example, a plurality of techniques. Specifically, the acquisition unit 401 acquires the plurality of techniques by receiving input of the plurality of techniques. Specifically, the acquisition unit 401 may acquire the plurality of techniques by receiving the plurality of techniques from another computer. The other computer is, for example, the client device 203.

[0085] The acquiring unit 401 acquires, for example, the third type. Specifically, the acquiring unit 401 acquires the third type by accepting input of the third type. Specifically, the acquiring unit 401 may acquire the third type by receiving the third type from another computer. The other computer is, for example, the client device 203. The acquiring unit 401 may acquire a specific example of the order of the plurality of first quantum bits of the third type without acquiring the third type. The acquiring unit 401 may acquire a specific example of the order of the plurality of second quantum bits of the third type without acquiring the third type.

[0086] The acquisition unit 401 may receive a start trigger to start processing by any of the functional units. The start trigger may be, for example, a predetermined operation input by a user. The start trigger may be, for example, reception of predetermined information from another computer. The start trigger may be, for example, output of predetermined information by any of the functional units. The acquisition unit 401 may receive, for example, acquisition of a processing request as a start trigger to start processing by the first selection unit 402, the second selection unit 403, and the execution unit 404.

[0087] The first selection unit 402 acquires the results of executing, for each of the multiple types, a quantum circuit that solves the second problem by performing an operation on multiple second quantum bits in the order of the type, in the DD quantum simulator 410. The first selection unit 402 generates, for each of the multiple types, a quantum circuit that solves the second problem by performing an operation on multiple second quantum bits in the order of the type, based on, for example, the acquired initial quantum circuit that solves the second problem.

[0088] The first selection unit 402 controls the parallel processing system 202, for example, to execute, in the DD quantum simulator 410, a quantum circuit that solves a second problem by performing an operation on the generated second quantum bits in the respective order of their types. The first selection unit 402 detects, for example, that the DD quantum simulator 410 has completed execution of the quantum circuit that solves the second problem by performing an operation on the generated second quantum bits in the respective order of their types.

[0089] The first selection unit 402 measures the processing time required to execute a quantum circuit that solves the second problem by performing an operation on a plurality of second quantum bits in an order of each type, using the DD quantum simulator 410. This allows the first selection unit 402 to evaluate whether or not each of the plurality of types is useful from the perspective of reducing the processing time required to solve the first problem.

[0090] The first selection unit 402 selects one of the multiple types to be applied to the quantum circuit that solves the first problem, based on the result of execution by the DD quantum simulator 410 obtained by the first selection unit 402. The first selection unit 402 selects, for example, the type with the shortest measured processing time from the multiple types as the type to be applied to the quantum circuit that solves the first problem. In this way, the first selection unit 402 can appropriately select one of the multiple types to be applied to the quantum circuit that solves the first problem, taking into consideration whether each of the multiple types is useful from the perspective of reducing the processing time required to solve the first problem.

[0091] The second selection unit 403 acquires the results of executing, in the DD quantum simulator 410, a quantum circuit to which the method is applied, which solves the second problem by performing an operation on a plurality of second quantum bits in a specific type order for each of the multiple methods. The specific type is, for example, one of the types selected by the first selection unit 402. The specific type may be fixed, for example, to the first type or the second type. The second selection unit 403 generates, for each method, a quantum circuit to which the method is applied, which solves the second problem by performing an operation on a plurality of second quantum bits in a specific type order, based on, for example, the initial quantum circuit to solve the second problem acquired.

[0092] The second selection unit 403, for example, controls the parallel processing system 202 to execute, in the DD quantum simulator 410, the quantum circuits that solve the second problem to which each of the generated methods is applied. The second selection unit 403, for example, detects that the quantum circuits that solve the second problem to which each of the methods is applied have been executed completely in the DD quantum simulator 410. The second selection unit 403, for example, measures the processing time required to execute the quantum circuits that solve the second problem to which each of the methods is applied, as a result of executing the quantum circuits that solve the second problem to which each of the methods is applied in the DD quantum simulator 410. This allows the second selection unit 403 to evaluate whether each of the multiple methods is useful from the perspective of reducing the processing time required to solve the first problem.

[0093] The second selection unit 403 selects one of the multiple methods to be applied to the quantum circuit that solves the first problem, based on the result of execution by the DD quantum simulator 410 obtained by the second selection unit 403. The second selection unit 403 selects, for example, one of the multiple methods that has the shortest measured processing time as one of the methods to be applied to the quantum circuit that solves the first problem. In this way, the first selection unit 402 can appropriately select one of the multiple methods to be applied to the quantum circuit that solves the first problem, taking into consideration whether each of the multiple methods is useful from the perspective of reducing the processing time required to solve the first problem.

[0094] The execution unit 404 obtains the result of solving the first problem. The execution unit 404 generates a quantum circuit applying one of the methods selected by the second selection unit 403, which solves the first problem by performing an operation on a plurality of first quantum bits in a specific type order, for example. The specific type is, for example, one of the types selected by the first selection unit 402. The specific type may be fixed to, for example, the first type or the second type. The execution unit 404 obtains the result of solving the first problem by, for example, controlling the parallel processing system 202 to execute the generated quantum circuit in the DD quantum simulator 410. This allows the execution unit 404 to reduce the processing time required to solve the first problem.

[0095] The output unit 405 outputs the processing result of at least one of the functional units. The output format is, for example, display on a display, printout to a printer, transmission to an external device via the network I / F 303, or storage in a storage area such as the memory 302 or the recording medium 305. In this way, the output unit 405 can notify the user of the processing result of at least one of the functional units, thereby improving the convenience of the information processing device 100.

[0096] The output unit 405 outputs, for example, the result of solving the first problem acquired by the execution unit 404. Specifically, the output unit 405 outputs the result of solving the first problem so that it can be referenced by the user. Specifically, the output unit 405 transmits the result of solving the first problem to another computer. The other computer is, for example, the client device 203. In this way, the output unit 405 can make the result of solving the first problem available externally.

[0097] Here, the case where the information processing device 100 includes the acquisition unit 401, the first selection unit 402, the second selection unit 403, the execution unit 404, and the output unit 405 has been described, but this is not limiting. For example, the information processing device 100 may not include any of the functional units. Specifically, the information processing device 100 may not include the first selection unit 402.

[0098] (Example of operation of information processing device 100) Next, an example of the operation of the information processing device 100 will be described with reference to Fig. 5 and Fig. 6. First, an example of a DD type simulator will be described with reference to Fig. 5, for example.

[0099] FIG. 5 is an explanatory diagram showing an example of a DD-type simulator. As described above, the DD-type simulator handles multiple combinations of quantum states represented by each of multiple quantum bits by expressing them in DD. In the example of FIG. 5, it is assumed that there are three quantum bits. Therefore, the combinations of quantum states represented by each quantum bit are 2 3 = 8. Specifically, the combinations of quantum states represented by each quantum bit are 000, 001, 010, 011, 100, 101, 110, and 111. The left side of table 500 in FIG. 5 is an index that represents the combination of quantum states represented by each quantum bit. The right side of table 500 in FIG. 5 is a value that represents the probability of the combination of quantum states represented by each quantum bit.

[0100] DD 510 in FIG. 5 corresponds to table 500. DD 510 represents combinations of quantum states represented by each quantum bit and the probabilities of those combinations. DD 510 includes multiple graph nodes. The graph nodes are connected by edges. In DD 510, for example, edges connected to graph nodes represent coefficients. In the example of FIG. 5, the coefficients are specifically 1 / 2 or -1. Edges for which the coefficients are not shown represent a coefficient of 1.

[0101] In DD510, for example, the path from the root to the leaves represents a combination of quantum states. Specifically, passing through the left edge represents the quantum state 0, and passing through the right edge represents the quantum state 1. Therefore, the path from the root, passing through the left edge, then the right edge, and then the left edge again represents Index010. In DD510, for example, the product of the coefficients of the edges on the path corresponds to the probability of the combination of quantum states. Specifically, in DD510, the probability of Index010 is -i / 2, which is obtained by multiplying the coefficients 1 / 2, 1, 1, and -i. Next, an example of the operation of the information processing apparatus 100 using the DD-type simulator will be described with reference to FIG. 6.

[0102] FIG. 6 is an explanatory diagram showing an example of the operation of the information processing apparatus 100. In FIG. 6, (6-1) the information processing apparatus 100 can utilize a DD-type quantum simulator. The information processing apparatus 100 obtains M = 1 that defines the parallel number 2 in the DD-type quantum simulator. The information processing apparatus 100 obtains a large-scale quantum circuit 600 for solving a target problem according to a predetermined algorithm. The large-scale quantum circuit 600 represents operations on X first qubits. M The information processing apparatus 100 obtains a small-scale quantum circuit 601 for solving a problem with a smaller scale than the target problem according to the same algorithm as the large-scale quantum circuit 600. The small-scale quantum circuit 601 represents operations on N second qubits. In the example of FIG. 6, it is assumed that N = 5. Specifically, it is assumed that there are second qubits a, b, c, d, and e. Also, it is preferable that N < X.

[0103] Specifically, the large-scale quantum circuit 600 and the small-scale quantum circuit 601 may be quantum circuits for performing factorization. In this case, specifically, the large-scale quantum circuit 600 may represent a series of operations for performing factorization on a relatively large value A. The small-scale quantum circuit 601 may represent a series of operations for performing factorization on a value B smaller than the value A.

[0104]

[0105] ​ Specifically, the large-scale quantum circuit 600 and the small-scale quantum circuit 601 may be quantum circuits that perform an inverse Fourier transform. In this case, the large-scale quantum circuit 600 may represent a series of operations that perform an inverse Fourier transform using a relatively large number of bits, A. The small-scale quantum circuit 601 may represent a series of operations that perform an inverse Fourier transform using a smaller number of bits, B.

[0106] (6-2) The information processing device 100 stores multiple types of ordering for arranging quantum bits. The multiple types include, for example, a first type for ordering quantum bits in the original order, a second type for ordering quantum bits in the reverse order of the original order, and a third type for ordering quantum bits in the order specified by the user. In the example of FIG. 6, the first type ordering 611 for the second quantum bits a, b, c, d, and e is [a, b, c, d, e]. The second type ordering 612 for the second quantum bits a, b, c, d, and e is [e, d, c, b, a]. The third type ordering 613 for the second quantum bits a, b, c, d, and e is [d, a, c, b, e].

[0107] (6-3) The information processing device 100 stores a plurality of methods for swapping at least local quantum bits with global quantum bits by inserting one or more SWAP gates into a quantum circuit for solving a problem involving multiple quantum bits. The plurality of methods includes, for example, a method according to the characteristics of a DD-type simulator.

[0108] Specifically, the information processing device 100 stores a first method 621 for swapping at least local quantum bits and global quantum bits so that the difference in the arrangement of quantum bits in a quantum circuit is small before and after inserting one or more SWAP gates into the quantum circuit.

[0109] The first method 621 is effective when, for example, depending on the characteristics of the DD simulator, the initial order of the qubits in the quantum circuit is considered to be relatively useful from the viewpoint of reducing the processing time required to solve the problem. Specifically, the first method 621 is effective when applied to a quantum circuit for solving problems such as the inverse quantum Fourier transform.

[0110] Specifically, the information processing device 100 stores a second technique 622 for swapping at least local quantum bits and global quantum bits so as to reduce the number of times that swap gates are inserted into the quantum circuit. The second technique 622 is effective, for example, when prioritizing reducing communication traffic. The second technique 622 is effective, for example, when applied to quantum circuits such as random circuits.

[0111] (6-4) The information processing device 100 considers which of the multiple types is useful when executing the large-scale quantum circuit 600, and selects one of the types to be applied to the large-scale quantum circuit 600.

[0112] The information processing device 100 measures, for example, the processing time when an original small-scale quantum circuit 601 that performs an operation on a plurality of second quantum bits in a first type order 611 is executed by a DD quantum simulator. The information processing device 100 generates, for example, a small-scale quantum circuit 601-A that performs an operation on a plurality of second quantum bits in a second type order 612 based on the original small-scale quantum circuit 601, and measures the processing time when executed by the DD quantum simulator.

[0113] For example, the information processing device 100 generates a small-scale quantum circuit 601-B that performs an operation on a plurality of second qubits, which is a third type of order 613, based on the original small-scale quantum circuit 601, and measures the processing time when executed on a DD quantum simulator. The information processing device 100 selects one of the multiple types that has the shortest measured processing time as the type to be applied to the large-scale quantum circuit 600.

[0114] This allows the information processing device 100 to appropriately select one of the multiple types to be applied to the large-scale quantum circuit 600, taking into consideration whether each type is useful from the perspective of reducing the processing time required to execute the large-scale quantum circuit 600. In the example of Fig. 6, it is assumed that the information processing device 100 selects the first type.

[0115] (6-5) The information processing device 100 considers which of the multiple methods is useful when executing the large-scale quantum circuit 600, and selects one of the methods to be applied to the large-scale quantum circuit 600.

[0116] For example, the information processing device 100 applies the first method to the original small-scale quantum circuit 601 to generate a small-scale quantum circuit 601-b that applies the first method, which performs an operation on multiple second qubits in a first type of order 611. For example, it may be desirable to move qubit c to the end. In this case, the first method changes the order [a, b, c, d, e] to [a, b, d, e, c] by inserting SWAP(3, 4) and SWAP(4, 5). SWAP(i, j) represents a SWAP gate that swaps the i-th qubit with the j-th qubit. For example, the information processing device 100 measures the processing time when the generated small-scale quantum circuit 601-b is executed in a DD quantum simulator.

[0117] For example, the information processing device 100 applies the second method to the original small-scale quantum circuit 601 to generate a small-scale quantum circuit 601-a to which the second method is applied, which performs an operation on multiple second qubits in a first type of order 611. For example, it may be desirable to move qubit c to the end. In this case, the second method inserts a SWAP(3,5) to change the order from [a, b, c, d, e] to [a, b, e, d, c]. For example, the information processing device 100 measures the processing time when the generated small-scale quantum circuit 601-a is executed in a DD quantum simulator. The information processing device 100 selects one of the methods with the shortest measured processing time as the method to be applied to the large-scale quantum circuit 600.

[0118] This allows the information processing device 100 to appropriately select one of the multiple methods to be applied to the large-scale quantum circuit 600, taking into consideration whether each method is useful from the perspective of reducing the processing time required to execute the large-scale quantum circuit 600. In the example of Fig. 6, it is assumed that the information processing device 100 selects the first method.

[0119] (6-8) The information processing device 100 executes the large-scale quantum circuit 600 in a DD quantum simulator based on any of the selected types and any of the selected techniques, thereby obtaining the results of executing the large-scale quantum circuit 600.

[0120] The information processing device 100 generates a large-scale quantum circuit 600-α to which the first method for performing an operation on a plurality of first qubits in the selected first type of order has been applied, for example, by applying the selected first method to the original large-scale quantum circuit 600. The information processing device 100 executes the generated large-scale quantum circuit 600-α in a DD quantum simulator, thereby acquiring the result of executing the large-scale quantum circuit 600-α as the result of executing the large-scale quantum circuit 600.

[0121] This allows the information processing device 100 to execute the large-scale quantum circuit 600-α, which is logically equivalent to the large-scale quantum circuit 600. Therefore, the information processing device 100 can essentially obtain the results of executing the large-scale quantum circuit 600. The information processing device 100 can essentially reduce the processing time required to execute the large-scale quantum circuit 600.

[0122] Here, in the conventional method, when inserting a SWAP gate into the large-scale quantum circuit 600, it is conceivable that a quantum bit that is relatively often acted upon by a rotation gate may be placed in a global quantum bit. For this reason, in the conventional method, it is difficult to reduce the processing time required to execute the large-scale quantum circuit 600. Specifically, in the large-scale quantum circuit 600 that performs an inverse Fourier transform, a quantum bit that is relatively often acted upon by a rotation gate may be placed in a global quantum bit, which may actually increase the processing time required to execute the large-scale quantum circuit 600.

[0123] In contrast, the information processing device 100 can reduce the processing time required to execute the large-scale quantum circuit 600. The information processing device 100 can examine the usefulness of each of a plurality of techniques for inserting a swap gate in a small-scale quantum circuit 601 that is expected to have properties similar to those of the large-scale quantum circuit 600. Therefore, the information processing device 100 can easily reduce the processing time required to execute the large-scale quantum circuit 600. Furthermore, because the information processing device 100 examines the usefulness of each of a plurality of techniques for inserting a swap gate in the small-scale quantum circuit 601, it is possible to suppress an increase in the processing time required for the examination.

[0124] (Overall processing procedure) 7 and 8, an example of an overall processing procedure executed by the information processing device 100 will be described. The overall processing is realized by, for example, the CPU 301, storage areas such as the memory 302 and the recording medium 305, and the network I / F 303 shown in FIG.

[0125] 7 and 8 are flowcharts showing an example of the overall processing procedure. In Fig. 7, the information processing device 100 acquires a small-scale quantum circuit (step S701).

[0126] Next, the information processing device 100 acquires the processing time required to execute the small-scale quantum circuit based on the results of executing the acquired small-scale quantum circuit with a DD quantum simulator for the original order of the multiple quantum bits (step S702).

[0127] In addition, the information processing device 100 acquires the processing time required to execute the small-scale quantum circuit based on the results of executing the acquired small-scale quantum circuit in a DD quantum simulator for the reverse order of the multiple quantum bits (step S703).

[0128] In addition, the information processing device 100 acquires the processing time required to execute the small-scale quantum circuit based on the results of executing the acquired small-scale quantum circuit with a DD quantum simulator for the specified order of multiple quantum bits (step S704).

[0129] Then, the information processing device 100 selects one of the multiple orders of the multiple quantum bits that has the shortest acquired processing time (step S705).

[0130] Next, the information processing device 100 acquires the parallelism number of the DD quantum simulator (step S706). Then, the information processing device 100 identifies the range of local quantum bits and the range of global quantum bits based on the acquired parallelism number (step S707).

[0131] Next, the information processing device 100 applies a first technique for inserting a SWAP gate to the acquired small-scale quantum circuit by a first insertion process described later in Fig. 9 based on the identified range (step S708). Then, the information processing device 100 acquires the processing time required to execute the small-scale quantum circuit to which the first technique is applied, based on the results of executing the small-scale quantum circuit to which the first technique is applied using a DD quantum simulator (step S709). The information processing device 100 proceeds to the process of step S801 in Fig. 8.

[0132] 8, the information processing device 100 applies a second technique for inserting a SWAP gate to the acquired small-scale quantum circuit based on the identified range, by a second insertion process described later in FIG. 10 (step S801). Next, the information processing device 100 acquires the processing time required to execute the small-scale quantum circuit to which the second technique is applied, based on the result of executing the small-scale quantum circuit to which the second technique is applied using a DD quantum simulator (step S802).

[0133] Then, the information processing apparatus 100 selects one of the methods for inserting a swap gate that has the shortest acquired processing time (step S803).

[0134] Next, the information processing device 100 acquires a large-scale quantum circuit (step S804). Then, the information processing device 100 updates the acquired large-scale quantum circuit so that operations are performed on multiple quantum bits in one of the selected orders (step S805). Furthermore, the information processing device 100 applies one of the selected methods to the updated large-scale quantum circuit based on the identified range (step S806).

[0135] Next, the information processing device 100 acquires the results of executing the large-scale quantum circuit to which any of the selected methods has been applied using a DD quantum simulator (step S807). Then, the information processing device 100 ends the entire process. This allows the information processing device 100 to reduce the processing time required to substantially execute the large-scale quantum circuit using a DD quantum simulator.

[0136] (First insertion process procedure) Next, an example of a procedure of the first insertion process executed by the information processing device 100 will be described with reference to Fig. 9. The first insertion process is realized by, for example, the CPU 301, storage areas such as the memory 302 and the recording medium 305, and the network I / F 303 shown in Fig. 3.

[0137] 9 is a flowchart showing an example of the procedure of the first insertion process. In FIG. 9, the information processing device 100 identifies a quantum bit to be made global next (step S901).

[0138] Next, the information processing device 100 determines the order of global qubits in accordance with the original order within the range of global qubits based on the determined next qubit to be global (step S902).Then, the information processing device 100 determines the order of local qubits in accordance with the original order within the range of local qubits based on the determined next qubit to be global (step S903).

[0139] Next, the information processing device 100 determines the next order in which to rearrange the multiple quantum bits based on the determined global quantum bit order and the determined local quantum bit order (step S904).Then, the information processing device 100 determines the current order of the multiple quantum bits (step S905).

[0140] Next, the information processing device 100 determines whether i>n is true (step S906). If i>n is true (step S906: Yes), the information processing device 100 ends the first insertion process. On the other hand, if i>n is not true (step S906: No), the information processing device 100 proceeds to the process of step S907.

[0141] In step S907, the information processing device 100 determines whether the i-th quantum bit is different between the identified next order and the identified current order (step S907). If the i-th quantum bit is the same (step S907: No), the information processing device 100 increments i and returns to the processing of step S906. On the other hand, if the i-th quantum bit is different (step S907: Yes), the information processing device 100 proceeds to the processing of step S908.

[0142] In step S908, the information processing device 100 inserts a SWAP gate into the quantum circuit so that the i-th quantum bit in the current order becomes the i-th quantum bit in the next order (step S908). Then, the information processing device 100 increments i and returns to the processing of step S906.

[0143] (Second insertion process procedure) Next, an example of a procedure of the second insertion process executed by the information processing device 100 will be described with reference to Fig. 10. The second insertion process is realized by, for example, the CPU 301, storage areas such as the memory 302 and the recording medium 305, and the network I / F 303 shown in Fig. 3.

[0144] 10 is a flowchart showing an example of the procedure of the second insertion process. In FIG. 10, the information processing device 100 identifies a quantum bit that is currently global (step S1001). Next, the information processing device 100 identifies a quantum bit that will be made global next (step S1002).

[0145] Then, information processing device 100 compares the currently global quantum bit with the quantum bit to be made global next, thereby identifying the quantum bit to be moved from global and the quantum bit to be moved from local (step S1003).

[0146] Next, information processing device 100 determines whether or not there is a quantum bit to be moved from the local area (step S1004). If there is no quantum bit to be moved from the local area (step S1004: No), information processing device 100 ends the second insertion process. On the other hand, if there is a quantum bit to be moved from the local area (step S1004: Yes), information processing device 100 proceeds to the process of step S1005.

[0147] In step S1005, the information processing device 100 inserts a SWAP gate into the quantum circuit to swap the head of the quantum bit moving from global with the head of the quantum bit moving to local (step S1005). Then, the information processing device 100 returns to the processing of step S1004.

[0148] Here, the information processing device 100 may change the order of the processes of some of the steps in the flowcharts of Figures 7 to 10. For example, the order of the processes of steps S1001 and S1002 may be changed. Furthermore, the information processing device 100 may omit the processes of some of the steps in the flowcharts of Figures 7 to 10.

[0149] As described above, the information processing device 100 can store multiple methods for swapping local and global quantum bits to reduce the cost of solving a problem. The information processing device 100 can store, as one of the multiple methods, a first method for reducing the difference in the arrangement of quantum bits in a quantum circuit before and after inserting a gate that swaps different quantum bits into the quantum circuit. The information processing device 100 can store, as one of the multiple methods, a second method for reducing the number of times gates that swap different quantum bits are inserted into a quantum circuit that solves a problem. The information processing device 100 can use a quantum simulator that represents combinations of different quantum states using a decision diagram. For each of the multiple methods, the information processing device 100 can acquire results by running a quantum circuit to which the method is applied, which solves a second problem that is smaller in scale than the first problem according to the same algorithm as the first problem, using the quantum simulator. The information processing device 100 can select one of the multiple methods to apply to a quantum circuit that solves the first problem based on the acquired results of execution using the quantum simulator. According to the information processing device 100, a quantum circuit that applies any of the selected methods to solve the first problem by performing an operation on a plurality of first quantum bits according to an algorithm can be executed in a quantum simulator to obtain the result of solving the first problem. This allows the information processing device 100 to appropriately select a method for inserting gates that swap different quantum bits into the quantum circuit, thereby reducing the processing time required to execute the quantum circuit that solves the first problem.

[0150] The information processing device 100 can store multiple types of orders for arranging quantum bits. The information processing device 100 can acquire results of executing, in a quantum simulator, a quantum circuit that solves a second problem by performing an operation on multiple second quantum bits in the selected order for each of the multiple types according to an algorithm. The information processing device 100 can select one of the multiple types to apply to a quantum circuit that solves a first problem based on the acquired results of execution in the quantum simulator. The information processing device 100 can acquire results of executing, in a quantum simulator, a quantum circuit to which a method is applied that solves a second problem by performing an operation on multiple second quantum bits in the selected order for each method. The information processing device 100 can generate a quantum circuit to which a selected method is applied that solves a first problem by performing an operation on multiple first quantum bits in the selected order. The information processing device 100 can acquire results of solving the first problem by executing the generated quantum circuit in a quantum simulator. This allows the information processing device 100 to appropriately select the type of order in which to arrange the quantum bits, thereby reducing the processing time required to execute the quantum circuit that solves the first problem.

[0151] According to the information processing device 100, it is possible to store a plurality of types including at least the first type and the second type out of a first type in which the quantum bits are arranged in the original order, a second type in which the quantum bits are arranged in the reverse order of the original order, and a third type in which the quantum bits are arranged in the order in which the specification was received. This allows the information processing device 100 to consider various types of orders in which the quantum bits are arranged, and to reduce the processing time required to execute the quantum circuit that solves the first problem.

[0152] The information processing device 100 can utilize a quantum simulator realized by parallel processing of multiple communicatively connected arithmetic devices 201. This allows the information processing device 100 to appropriately reduce the processing time required to execute a quantum circuit that solves the first problem in a situation where inter-process communication may occur.

[0153] The information processing method described in this embodiment can be realized by executing a prepared program on a computer such as a PC or a workstation. The information processing program described in this embodiment is recorded on a computer-readable recording medium and executed by being read from the recording medium by the computer. The recording medium may be a hard disk, a flexible disk, a CD (Compact Disc)-ROM, an MO (Magneto Optical disc), a DVD (Digital Versatile Disc), or the like. The information processing program described in this embodiment may also be distributed via a network such as the Internet.

[0154] The following additional notes are provided regarding the above-described embodiment.

[0155] (Supplementary Note 1) A quantum circuit that solves a problem is provided with a gate that swaps different quantum bits, thereby reducing the cost of solving the problem. For each of a plurality of methods for swapping local quantum bits and global quantum bits, a second problem that is smaller in scale than the first problem is solved according to the same algorithm as the first problem. The quantum circuit to which the method is applied is executed using a quantum simulator that expresses combinations of different quantum states as decision diagrams, and the results are obtained. selecting, based on a result of executing, on the quantum simulator, the quantum circuits to which the respective techniques for solving the second problem have been applied, one of the techniques to be applied to the quantum circuit for solving the first problem; solving the first problem by performing an operation on a plurality of first quantum bits according to the algorithm; and acquiring a result of solving the first problem by executing a quantum circuit to which any of the selected techniques is applied in the quantum simulator. Have the computer execute the process, the plurality of techniques include a first technique of swapping local quantum bits and global quantum bits so that a difference in the arrangement of quantum bits in the quantum circuit that solves the problem before and after inserting the gate into the quantum circuit that solves the problem becomes small, and a second technique of swapping local quantum bits and global quantum bits so that the number of times the gate is inserted into the quantum circuit that solves the problem becomes small.

[0156] (Supplementary Note 2) For each of a plurality of types of orders in which quantum bits are arranged, a quantum circuit that solves the second problem by performing an operation on a plurality of second quantum bits in the order of the types according to the algorithm is executed by the quantum simulator, and a result is obtained; selecting, based on a result of execution by the quantum simulator of a quantum circuit that solves the second problem by performing an operation on the plurality of second quantum bits in the order of the acquired types, any one of the plurality of types to be applied to a quantum circuit that solves the first problem; causing the computer to execute a process; The process of acquiring a result of executing a quantum circuit to which each of the methods for solving the second problem is applied in the quantum simulator includes: For each of the methods, a quantum circuit to which the method is applied is executed on the quantum simulator to solve the second problem by performing an operation on the plurality of second quantum bits in the selected order, and a result is obtained; The process of obtaining a result of solving the first problem includes: 2. The information processing program according to claim 1, wherein the first problem is solved by performing an operation on the plurality of first quantum bits in the selected order of any one of the types, and a result of solving the first problem is obtained by executing a quantum circuit to which any one of the selected techniques is applied in the quantum simulator.

[0157] (Appendix 3) The information processing program according to appendix 2, characterized in that the plurality of types include at least the first type and the second type of a first type that arranges quantum bits in the original order, a second type that arranges quantum bits in the reverse order of the original order, and a third type that arranges quantum bits in the order in which the specification was received.

[0158] (Supplementary Note 4) The information processing program according to any one of Supplementary Notes 1 to 3, wherein the quantum simulator is realized by parallel processing of a plurality of arithmetic devices connected in a communicable manner.

[0159] (Appendix 5) A quantum circuit that solves a problem is inserted with a gate that swaps different quantum bits, thereby reducing the cost of solving the problem. For each of a plurality of methods for swapping local quantum bits and global quantum bits, a second problem that is smaller in scale than the first problem is solved according to the same algorithm as the first problem. The quantum circuit to which the method is applied is executed using a quantum simulator that expresses combinations of different quantum states as a decision diagram, and the results are obtained. selecting, based on a result of executing, on the quantum simulator, the quantum circuits to which the respective techniques for solving the second problem have been applied, one of the techniques to be applied to the quantum circuit for solving the first problem; solving the first problem by performing an operation on a plurality of first quantum bits according to the algorithm; and acquiring a result of solving the first problem by executing a quantum circuit to which any of the selected techniques is applied in the quantum simulator. The computer executes the processing, the plurality of techniques include a first technique of swapping local quantum bits and global quantum bits so that a difference in the arrangement of quantum bits in the quantum circuit that solves the problem before and after inserting the gate into the quantum circuit that solves the problem becomes small, and a second technique of swapping local quantum bits and global quantum bits so that the number of times the gate is inserted into the quantum circuit that solves the problem becomes small.

[0160] (Appendix 6) A quantum circuit that solves a problem is inserted with a gate that swaps different quantum bits, thereby reducing the cost of solving the problem. For each of a plurality of methods for swapping local quantum bits and global quantum bits, a second problem that is smaller in scale than the first problem is solved according to the same algorithm as the first problem. The quantum circuit to which the method is applied is executed with a quantum simulator that expresses combinations of different quantum states as a decision diagram, and the results are obtained. selecting, based on a result of executing, on the quantum simulator, the quantum circuits to which the respective techniques for solving the second problem have been applied, one of the techniques to be applied to the quantum circuit for solving the first problem; solving the first problem by performing an operation on a plurality of first quantum bits according to the algorithm; and acquiring a result of solving the first problem by executing a quantum circuit to which any of the selected techniques is applied in the quantum simulator. A control unit is provided. the plurality of techniques include a first technique of swapping local quantum bits and global quantum bits so that a difference in the arrangement of quantum bits in the quantum circuit that solves the problem before and after the gate is inserted into the quantum circuit that solves the problem becomes small, and a second technique of swapping local quantum bits and global quantum bits so that the number of times the gate is inserted into the quantum circuit that solves the problem becomes small. [Explanation of symbols]

[0161] 100 Information processing device 101,102,108~110,120 quantum circuit 103 Multiple Methods 104,621 1st method 105,622 Second method 106,410 DD type quantum simulator 107 parallel number 111,112,122,123 Gates 121 SWAP Gate 200 Information Processing Systems 201 Arithmetic equipment 202 Parallel Processing System 203 Client Device 210 Network 300 Bus 301 CPU 302 memory 303 Network I / F 304 Recording Media I / F 305 Recording Media 400 Storage section 401 Acquisition Department 402 First Selection Section 403 Second Selection Section 404 Executive Department 405 Output Section 500 tables 510DD 600 Large-scale quantum circuits 601 Small-scale quantum circuits 611~613 order

Claims

1. a quantum circuit for solving a problem, which solves a second problem smaller in scale than the first problem according to the same algorithm as the first problem, by inserting a gate for swapping different quantum bits into the quantum circuit for solving the problem, and acquiring the results of running the quantum circuit to which the method is applied using a quantum simulator that expresses combinations of different quantum states as a decision diagram; selecting, based on a result of executing, on the quantum simulator, the quantum circuits to which the respective techniques for solving the second problem have been applied, one of the techniques to be applied to the quantum circuit for solving the first problem; solving the first problem by performing an operation on a plurality of first quantum bits according to the algorithm; and acquiring a result of solving the first problem by executing a quantum circuit to which any of the selected techniques is applied in the quantum simulator. Have the computer execute the process, the plurality of techniques include a first technique of swapping local quantum bits and global quantum bits so that a difference in the arrangement of quantum bits in the quantum circuit that solves the problem before and after inserting the gate into the quantum circuit that solves the problem becomes small, and a second technique of swapping local quantum bits and global quantum bits so that the number of times the gate is inserted into the quantum circuit that solves the problem becomes small.

2. a quantum circuit that solves the second problem by performing an operation on a plurality of second quantum bits in the order of the types according to the algorithm, for each of a plurality of types of orders in which the quantum bits are arranged, in the quantum simulator; and selecting, based on a result of executing, on the quantum simulator, a quantum circuit that solves the second problem by performing an operation on the plurality of second quantum bits in the order of the acquired types, any one of the plurality of types to be applied to a quantum circuit that solves the first problem; causing the computer to execute a process; The process of acquiring a result of executing a quantum circuit to which each of the methods for solving the second problem is applied in the quantum simulator includes: For each of the methods, a quantum circuit to which the method is applied is executed by the quantum simulator to solve the second problem by performing an operation on the plurality of second quantum bits in the selected order of any one of the types, and a result is obtained; The process of obtaining a result of solving the first problem includes:

2. The information processing program according to claim 1, wherein the first problem is solved by performing an operation on the plurality of first quantum bits in the selected order of any one of the types, and a result of solving the first problem is obtained by executing a quantum circuit to which any one of the selected techniques is applied in the quantum simulator.

3. 3. The information processing program according to claim 1, wherein the quantum simulator is realized by parallel processing of a plurality of computing devices connected to each other in a communicable manner.

4. a quantum circuit for solving a problem, which solves a second problem smaller in scale than the first problem according to the same algorithm as the first problem, by inserting a gate for swapping different quantum bits into the quantum circuit for solving the problem, and acquiring the results of running the quantum circuit to which the method is applied using a quantum simulator that expresses combinations of different quantum states as a decision diagram; selecting, based on a result of executing, on the quantum simulator, the quantum circuits to which the respective techniques for solving the second problem have been applied, one of the techniques to be applied to the quantum circuit for solving the first problem; solving the first problem by performing an operation on a plurality of first quantum bits according to the algorithm; and acquiring a result of solving the first problem by executing a quantum circuit to which any of the selected techniques is applied in the quantum simulator. The computer executes the processing, the plurality of techniques include a first technique of swapping local quantum bits and global quantum bits so that a difference in the arrangement of quantum bits in the quantum circuit that solves the problem before and after inserting the gate into the quantum circuit that solves the problem becomes small, and a second technique of swapping local quantum bits and global quantum bits so that the number of times the gate is inserted into the quantum circuit that solves the problem becomes small.

5. a quantum circuit for solving a problem, which solves a second problem smaller in scale than the first problem according to the same algorithm as the first problem, by inserting a gate for swapping different quantum bits into the quantum circuit for solving the problem, and acquiring the results of running the quantum circuit to which the method is applied using a quantum simulator that expresses combinations of different quantum states as a decision diagram; selecting, based on a result of executing, on the quantum simulator, the quantum circuits to which the respective techniques for solving the second problem have been applied, one of the techniques to be applied to the quantum circuit for solving the first problem; solving the first problem by performing an operation on a plurality of first quantum bits according to the algorithm; and acquiring a result of solving the first problem by executing a quantum circuit to which any of the selected techniques is applied in the quantum simulator. A control unit is provided. the plurality of techniques include a first technique of swapping local quantum bits and global quantum bits so that a difference in the arrangement of quantum bits in the quantum circuit that solves the problem before and after inserting the gate into the quantum circuit that solves the problem becomes small, and a second technique of swapping local quantum bits and global quantum bits so that the number of times the gate is inserted into the quantum circuit that solves the problem becomes small.

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