Semiconductor device manufacturing apparatus and manufacturing method

Abstract

To provide a semiconductor device manufacturing apparatus and manufacturing method that stack a plurality of chips with high accuracy and high yield.SOLUTION: A manufacturing apparatus comprises a first stage 101 that supports a substrate 11, a second stage 102 that supports chips 12a to 12c so as to face the substrate, and a movable camera unit 103 that captures alignment markers of the substrate and the chips. At least one of the first stage and the second stage is movable, and the second stage performs alignment using a reference marker 21 or a chip marker 22a formed on the chip 12a, and a chip marker 22c formed on the chip 12c supported by the second stage, and thereafter stacks the chip 12c on the chips 12a and 12b. A depth of field of an objective lens included in the camera unit is equal to or less than a sum of a thickness of the chip 12b sandwiched between the chip marker 22a and the chip marker 22c, and a distance between the chip 12a and the chip 12c after the alignment.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device manufacturing apparatus and manufacturing method, and is suitable for use in, for example, a semiconductor device in which a plurality of chips are stacked in a direction perpendicular to the surface of a substrate. [Background technology]

[0002] As electronic devices become smaller and more sophisticated, there is a demand for higher integration of semiconductor chips. As a means of improving the integration of semiconductor chips, progress is being made in the development of technology to obtain semiconductor chips by three-dimensionally stacking multiple chips on which semiconductor elements are formed.

[0003] As shown in Figures 8(a) to 8(c), there are three types of three-dimensional chip stacking technologies: CoC (Chip on Chip), CoW (Chip on Wafer), and WoW (Wafer on Wafer).

[0004] The CoC method is a method in which individual chips 12, each having a semiconductor element formed thereon, are bonded together to obtain a semiconductor chip 13 (see FIG. 8(a)). The CoW method is a method in which individual chips 12, each having a semiconductor element formed thereon, are stacked on a wafer (substrate 11) also having semiconductor elements formed thereon, and then the wafer is divided to obtain semiconductor chips 13 (see FIG. 8(b)). The WoW method is a method in which wafers (substrates 11), each having a semiconductor element formed thereon, are bonded together, and then the wafer is divided to obtain semiconductor chips 13 (see FIG. 8(c)).

[0005] Different mounting methods are used depending on the application, but all methods require highly accurate alignment technology. For example, Patent Document 1 discloses an alignment method for a mounting device that mounts chips on a substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-217596 Summary of the Invention [Problem to be solved by the invention]

[0007] The CoC method has a high yield rate because good chips are selected and bonded, and is versatile in that it can bond chips with different functions.However, it has the problem of low throughput because tiny chips must be mounted one by one.

[0008] The WoW method has high throughput and is suitable for stacking wafers with chips of the same size, making it useful for stacking memory elements. However, there are many layout restrictions, such as the need to align the upper and lower chips. Furthermore, as the number of wafers to be bonded increases, the yield rate per wafer becomes significantly affected, which is an issue.

[0009] 9 shows an example of stacking multiple wafers (substrates 11) using the WoW method. If the rate of non-defective products per wafer is 80%, the yield when two substrates 11 are bonded together is 80% x 80%, or 64%. When three substrates 11 are bonded together, the yield drops to approximately 41%, or 80% x 80% x 80%.

[0010] Furthermore, when stacking multiple chips, it is necessary to consider the markers (alignment markers) used for alignment. Figures 10(a) to 10(c) are diagrams explaining alignment when stacking three chips 12a, 12b, and 12c on a substrate 11.

[0011] The first chip 12a is aligned using a chip marker 22a formed on the chip 12a and a reference marker 21 formed on the substrate 11 (see FIG. 10(a)).

[0012] The second chip 12b is aligned using chip marker 22b formed on chip 12b and reference marker 21a formed on the first chip 12a (see FIG. 10(b)). When the first chip 12a is placed on the substrate 11, the reference marker 21 formed on the substrate 11 becomes unclear due to the thickness of the first chip 12a (see reference marker 21 in FIG. 10(b)). Therefore, if the reference marker 21 is used to align the second and subsequent chips, the alignment accuracy will decrease. Therefore, it is necessary to form a reference marker on each of the chips 12a, 12b, and 12c to align the chip with the next chip to be stacked (see reference marker 21a in FIG. 10(a), reference marker 21b in FIG. 10(b), and reference marker 21c in FIG. 10(c)).

[0013] Furthermore, the second chip 12b has dead space because an element cannot be formed in the area 23b where the reference marker 21 of the substrate 11 and the chip marker 22a of the first chip 12a overlap (see area 23b in Figure 10(b)).

[0014] The third chip 12c is aligned using chip marker 22c formed on chip 12c and reference marker 21b formed on the second chip 12b (see FIG. 10(c)). Similar to the second chip 12b, the third chip 12c has region 23c, which is dead space where no elements can be formed (see region 23c in FIG. 10(c)). Furthermore, region 23c includes an area where reference marker 21a of the first chip 12a and chip marker 22 of the second chip 12b overlap, and therefore has a larger area than region 23b of the second chip 12b (see region 23c in FIG. 10(c)).

[0015] In this way, when the number of stacked chips increases, the area occupied by the markers (alignment markers) used for alignment increases, which poses a problem of reducing the area in which semiconductor elements are formed.

[0016] In addition, in the case of the above chip stacking method, alignment markers must be formed in different positions for each of the chips 12a, 12b, and 12c, which means that different chips must be fabricated depending on the number of chips to be stacked. This not only significantly reduces the versatility of the chips, but also increases costs due to the need to fabricate different chips.

[0017] The present disclosure has been made to solve such problems, and has an object to provide a manufacturing apparatus and a manufacturing method for a semiconductor device that stacks multiple chips with high precision and high yield. [Means for solving the problem]

[0018] The semiconductor device manufacturing apparatus according to the present disclosure is an apparatus for manufacturing a semiconductor device in which a plurality of chips are stacked vertically relative to the surface of a substrate, and comprises: a first stage that supports the substrate; a second stage that supports the chips so that they face the substrate; and a movable camera unit that photographs alignment markers on the substrate and the chips, wherein at least one of the first stage and the second stage is movable, and the second stage is configured to align the first chip using a reference marker formed on the substrate or a first chip marker formed on a first chip placed on the substrate, and a second chip marker formed on a second chip supported by the second stage, and then stack the second chip on the first chip, and the depth of field of the objective lens provided in the camera unit is less than or equal to the sum of the thickness of the chip sandwiched between the first chip marker and the second chip marker and the distance between the first chip and the second chip after the alignment.

[0019] The method for manufacturing a semiconductor device according to the present disclosure is a method for manufacturing a semiconductor device in which multiple chips are stacked vertically relative to the surface of a substrate, and the first stage and the second stage are aligned using a reference marker formed on a substrate supported by a first stage or a first chip marker formed on a first chip placed on the substrate, and a second chip marker formed on a second chip supported by a second stage, the second chip is stacked on the first chip, and the depth of field of the objective lens provided in the camera unit used for the alignment is less than or equal to the sum of the thickness of the chip sandwiched between the first chip marker and the second chip marker and the distance between the first chip and the second chip after the alignment. [Effects of the Invention]

[0020] The present disclosure can provide a semiconductor device manufacturing apparatus and method that stacks multiple chips with high precision and high yield. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 2] 1A and 1B are a plan view and a cross-sectional view of a semiconductor device according to the present disclosure. [Figure 3] 1 is a configuration diagram of a semiconductor device manufacturing apparatus according to a first embodiment. [Figure 4] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Figure 5] FIG. 2 is a diagram illustrating the depth of field of the objective lens according to the first embodiment. [Figure 6] FIG. 10 is a configuration diagram of a semiconductor device manufacturing apparatus according to a second embodiment. [Figure 7] 10A to 10C are diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8] 1A and 1B are diagrams illustrating a related semiconductor chip mounting technique. [Figure 9] FIG. 1 is a diagram illustrating the yield of related semiconductor chips. [Figure 10] 10A and 10B are diagrams illustrating the alignment of related semiconductor chips; DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, identical or corresponding components are designated by the same reference numerals, and duplicate explanations will be omitted. In the drawings, components may be omitted or simplified for the sake of convenience. Furthermore, at least some of the embodiments may be combined with each other in any desired manner.

[0023] Before describing the semiconductor device manufacturing apparatus and manufacturing method according to the present disclosure, the manufacturing method according to the present disclosure and the semiconductor device 10 manufactured by the manufacturing method will be described. The manufacturing method according to the present disclosure and the semiconductor device 10 manufactured by the manufacturing method are common to all embodiments.

[0024] 1(a) to 1(d) are schematic diagrams of a semiconductor device 10 manufactured by a semiconductor device manufacturing method according to the present disclosure. The semiconductor device manufacturing method according to the present disclosure employs a CoW (Chip on Wafer) method, in which chips 12 are arranged on a substrate 11 (see FIG. 1(a)), and multiple chips 12 are stacked in a direction perpendicular to the surface of the substrate 11 (see FIG. 1(b)). The substrate 11 is then divided to finally obtain semiconductor chips 13 (see FIG. 1(c)). FIG. 1(d) shows a side view of the semiconductor chip 13 in which m chips 12 are stacked.

[0025] Note that the letter a in the symbol indicates the first chip 12a, b indicates the second chip 12b, and c indicates the third chip 12c, and if no letter is added, it indicates that the symbol can be applied to any chip 12.

[0026] There are no particular restrictions on the substrate 11, but it is preferable to use a material such as a silicon wafer that has high flatness and can be easily polished to a thin film after chip mounting.

[0027] 2(a) is an enlarged plan view of a portion of the substrate 11 and chip 12 shown in FIG. 1, illustrating the alignment performed when placing the chip 12 on the substrate 11. The area 20 surrounded by the dotted line is the field of view for one shot of the camera unit provided in the manufacturing apparatus according to the present disclosure. A reference marker 21 is formed on the substrate 11, and a chip marker 22 is formed on the chip 12.

[0028] The alignment is preferably determined so that W1 to W3 fall within preset values ​​using the width (W1) of each of the reference marker 21 and the chip marker 22, the combined width (W2) of the reference marker 21 and the chip marker 22, and the spacing (W3) between the reference marker 21 and the chip marker 22. There are no particular restrictions on the shapes of the reference marker 21 and the chip marker 22, but as shown in Figure 2(a), a polygonal shape is preferable to a circle because this makes alignment easier, and the reference marker 21 and the chip marker 22 may have different shapes, but it is preferable that W1 be the same.

[0029] As a comparative example, Fig. 2(b) shows a method of aligning by superimposing the reference marker 21 and the chip marker 22. As explained in Figs. 10(a) to 10(c), this method is not preferable because, when multiple chips 12 are stacked, the reference marker 21 becomes unclear, making alignment difficult.

[0030] The semiconductor manufacturing method disclosed herein aligns the reference marker 21 and the chip marker 22 at a distance from each other, so that the reference marker 21 is not blurred, and it is therefore possible to stack multiple chips 12 to obtain a semiconductor chip 13 (see Figure 2(c)).

[0031] As an example, a plan view of a semiconductor chip 13 in which m chips 12a to 12m are stacked is shown in Figure 2(d). When the semiconductor device manufacturing method according to this embodiment is applied, it can be seen that the chip markers 22a to 22m formed on the chips 12a to 12m overlap one another in approximately the same area in a plan view. In this way, the alignment markers can be concentrated in one place on the chip, thereby expanding the manufacturing area of ​​the semiconductor element.

[0032] Furthermore, the method for manufacturing a semiconductor device according to the present disclosure allows for highly accurate alignment even with alignment markers having the same shape as those shown in Figures 10(a) to (c), eliminating the need to change conventional design rules and reducing the burden on chip design.

[0033] Figure 2(e) is an enlarged cross-sectional view of the chip 12b before the chip 12c is stacked on the chip 12b. In the example shown in Figure 2(c) and other figures, for convenience, the chip markers are shown as being embedded inside the chip, but more accurately, the chip markers are formed on the surface of the chip. However, since the thickness of the markers is negligibly thin compared to the thickness of the chip, the surface on which the markers are formed can be considered to be a substantially flat surface. In the following description, the phrase "a chip (chip 12b) sandwiched between two chip markers (chip marker 22b and chip marker 22c)" will be used, but this is based on this cross-sectional view.

[0034] <First Embodiment> 3 shows an example of the configuration of a manufacturing apparatus 100 for manufacturing a semiconductor device 10 according to this embodiment. The manufacturing apparatus 100 includes a first stage 101 for supporting a substrate 11, a second stage 102 for supporting a chip 12, and a camera unit 103.

[0035] The camera unit 103 includes a camera for recognizing the reference marker 21 and the chip marker 22. An infrared camera is particularly preferable as the camera, but if the chip 12 is thin, the chip marker 22 can be recognized by passing through it with visible light from the back side of the chip 12, so a visible light camera or near-infrared camera may also be used.

[0036] The first stage 101, the second stage 102, and the camera unit 103 are movable and can move up, down, left, and right. It is also preferable that the first stage 101 and the second stage 102 can rotate horizontally, as this makes alignment easier.

[0037] The second stage 102 supports the chip 12 on the back side of the chip 12, i.e., the side on which the chip marker 22 is not formed. One method for supporting the chip 12 is to provide a thermal transfer material containing a material that absorbs and melts laser light, which will be described later, between the second stage 102 and the chip 12. In the manufacturing apparatus 100 according to this embodiment, the camera unit 103 recognizes the chip marker 22 through the second stage 102, so it is preferable that the second stage 102 is also sufficiently thin.

[0038] 4(a) to 4(d) will be used to explain a method for manufacturing a semiconductor device 10 using the manufacturing apparatus 100 according to this embodiment. To facilitate understanding of the effects of the manufacturing method according to this embodiment, an example will be shown in which a third chip 12c is stacked on a substrate 11 on which a first chip 12a and a second chip 12b have already been stacked.

[0039] First, the camera unit 103 recognizes the reference marker 21 formed on the substrate 11 supported by the first stage 101 (see FIG. 4(a)). An objective lens 113 is provided inside the camera unit 103, and the camera unit 103 is moved up and down to focus on the reference marker 21.

[0040] The up and down movement of the camera unit 103 may be performed manually, but it is preferable to provide an autofocus function so that the focus is automatically set on the reference marker 21. Furthermore, a laser displacement meter (not shown) that measures the thickness of the plurality of stacked chips 12 may be provided so that autofocusing can be performed based on information about the thickness of the plurality of stacked chips 12.

[0041] Next, the second stage 102, which supports the chip 12c using the above-mentioned thermal transfer material 112, is moved between the first stage 101 and the camera unit 103, and the chip marker 22c formed on the chip 12c is recognized by the camera unit 103 (see FIG. 4(b)). This allows the first stage 101 and the second stage 102 to be aligned.

[0042] In Fig. 4(b), the camera unit 103 is shown moved to the position of the chip marker 22c for convenience of illustration. In reality, as shown in Fig. 2(a), the reference marker 21 and the chip marker 22 are contained within the field of view of one shot, so there is no need to move the camera unit 103 left and right, and it is possible to focus on the chip marker 22c by simply moving it up and down.

[0043] After the first stage 101 and the second stage 102 are aligned, a laser beam 114 is irradiated onto the thermal transfer material 112 between the second stage 102 and the chip 12c using a light source (not shown) that emits laser light (see FIG. 4(c)). This melts or changes the thermal transfer material 112, causing the chip 12c to peel off from the second stage 102 and be stacked on the second chip 12b. Thereafter, the substrate 11 on which the multiple chips are stacked is diced (divided) to obtain semiconductor chips 13 (see FIG. 4(d)).

[0044] Here, the objective lens 113 provided in the camera unit 103 and its depth of field will be described with reference to Figures 5(a) to 5(d). It is preferable that the objective lens 113 according to this embodiment has a large numerical aperture (NA) to reduce the depth of field d.

[0045] First, we will explain the case where each chip has the same thickness. When the thickness of the chip is T and the distance between the already stacked chip 12b and the next stacked chip 12c is g, the depth of field is preferably d≦T+g, more preferably d≦T, and even more preferably d≦T / 2.

[0046] If the depth of field d of the objective lens 113 is large, the focus will also be on the chip marker 22b of the chip 12b located below the chip 12c located on the top surface, resulting in a decrease in alignment accuracy. In the manufacturing apparatus 100 according to this embodiment, by setting the depth of field d of the objective lens 113 to be equal to or less than the sum of the chip thickness T and the distance g between the chips 12b and 12c, the camera unit 103 can recognize only the chip marker 22c of the chip 12c located on the top surface.

[0047] In addition, in order to improve alignment accuracy, a pre-process may be included in the alignment process to remove chip markers 22 that are located in an area outside the depth of field d of the objective lens 113 in the thickness direction of the chip 12, i.e., in the direction perpendicular to the surface of the substrate 11.

[0048] 2(b), the camera unit 103 focuses on the chip marker 22c of the chip 12c, and the chip markers 22a and 22b of the chips 12a and 12b located below the chip 12c are captured out of focus, i.e., as blurred alignment markers. By providing a processing unit (not shown) in the camera unit 103 according to this embodiment and performing alignment by removing out-of-focus areas from the captured image, it is possible to improve the alignment accuracy.

[0049] A specific example of the pre-processing is a process of evaluating the sharpness of the contours of the captured image and extracting only the in-focus area.

[0050] In addition, in Figures 4(a) to (d), an example is shown in which the reference marker 21 of the substrate 11 and the chip marker 22c of the third chip 12c are used to align the first stage 101 and the second stage 102, but the manufacturing method of this embodiment is not limited to this.

[0051] 5(b) shows an example of alignment using chip marker 22b of the second chip 12b instead of the alignment using reference marker 21 of substrate 11 shown in FIG. 4(a). In this example, by setting the depth of field d of objective lens 113 to be equal to or less than the thickness T of the chip, camera unit 103 can recognize only chip marker 22b of chip 12b.

[0052] The above has been a description of the case where the chip thickness T is constant. Next, we will explain the range of the depth of field d when the chip thickness varies and depending on the orientation of the chip marker.

[0053] 5(a) shows an example in which chip markers 22 are formed on the chip surface so that they face downward, i.e., toward the substrate 11. In this case, the depth of field d is preferably set so that only chip marker 22c is recognized and chip marker 22b is not recognized. Therefore, the range of the depth of field d does not depend on the thickness of chip 12c, and it is sufficient that it is equal to or less than the sum of the thickness T of chip 12b and the distance g between chips 12b and 12c.

[0054] On the other hand, as shown in Figure 5(c), when the chip markers 22 are formed on the chip surface so that they face upward, i.e., toward the camera unit 103, the range of the depth of field d does not depend on the thickness of the chip 12b, and can be set to be less than the sum of the thickness T of the chip 12c and the distance g between the chip 12b and the chip 12c.

[0055] 5(a) and (c) show that the possible range of the depth of field d depends on the thickness T of the chip sandwiched between the two chip markers 22b and 22c. The positional relationship of the chip sandwiched between the two chip markers is as shown in Fig. 2(e), and the chip in question refers to chip 12b in the example shown in Fig. 5(a) and to chip 12c in the example shown in Fig. 5(c).

[0056] 5(b) shows an example in which, instead of using the reference marker 21 on the substrate 11, the chip markers 22b of the second chip 12b are used for alignment, and the chip markers 22 are formed on the chip surface so that they face downward, i.e., toward the substrate 11. In this case, the depth of field d is set so that only the chip marker 22b is recognized and the chip marker 22a is not recognized. The range of the depth of field d does not depend on the thickness of the chip 12b, and may be set to be equal to or less than the thickness T of the chip 12a.

[0057] On the other hand, as shown in Figure 5(d), when the chip markers 22 are formed on the chip surface so that they face upward, i.e., toward the camera unit 103, the range of the depth of field d does not depend on the thickness of the chip 12a, and can be set to be equal to or less than the thickness T of the chip 12b.

[0058] 5(b) and (d), it can be seen that the possible range of the depth of field d depends on the thickness T of the chip sandwiched between the two chip markers 22a and 22b. In the example shown in FIG. 5(b), the chip in question refers to chip 12a, and in the example shown in FIG. 5(d), the chip in question refers to chip 12b.

[0059] In this way, it is possible to provide a semiconductor device manufacturing apparatus and method that stacks a plurality of chips with high precision and high yield.

[0060] <Embodiment 2> In the present embodiment 2, a description will be given of a modified example of the semiconductor device manufacturing apparatus according to the embodiment 1. Note that repeated description of the same configuration as that of the embodiment 1 may be omitted.

[0061] 6 shows an example of the configuration of a manufacturing apparatus 200 for manufacturing the semiconductor device 10 according to this embodiment. The manufacturing apparatus 200 includes a first stage 201 for supporting the substrate 11, a second stage 202 for supporting the chip 12, and a camera unit 203.

[0062] Unlike the camera unit 103 described in the first embodiment, the camera unit 203 is a two-view camera having imaging units on the top and bottom, and is provided with an objective lens 213 for recognizing the reference marker 21 on the substrate 11 and an objective lens 223 for recognizing the chip marker 22 on the chip 12. As in the first embodiment, an infrared camera is particularly preferable as the two-view camera, but if the chip 12 is thin, a visible light camera or a near-infrared camera may also be used.

[0063] The first stage 201, the second stage 202, and the camera unit 203 are movable and can move up, down, left, and right. It is also preferable that the first stage 201 and the second stage 202 can rotate horizontally, as this makes alignment easier.

[0064] The second stage 202 supports the chip 12 on the back side of the chip 12, i.e., on the side on which the chip marker 22 is not formed. The manufacturing apparatus 200 according to this embodiment has a configuration in which a bond chuck (not shown) such as an adsorption chuck or an electrostatic chuck is provided on the second stage 102 to support the chip 12.

[0065] In the manufacturing apparatus 200 of this embodiment, the camera unit 203 is a two-field camera, so the chip marker 22 is recognized on the front side of the chip 12, i.e., the surface on which the chip marker 22 is formed, and the thickness of the second stage 202 is not an issue.

[0066] A method for manufacturing a semiconductor device 10 using a manufacturing apparatus 200 according to this embodiment will be described with reference to the cross-sectional view of the manufacturing apparatus 200 shown in FIG. 7. As in the first embodiment, to facilitate understanding of the effects of the manufacturing method according to this embodiment, an example will be shown in which a third chip 12c is stacked on a substrate 11 on which a first chip 12a and a second chip 12b have already been stacked. Note that illustrations and descriptions of steps similar to those in the first embodiment will be omitted.

[0067] The camera unit 203 in this embodiment includes an objective lens 213 that recognizes the alignment markers of the substrate 11 and chip 12 arranged on the first stage 201 side, an objective lens 223 that recognizes the alignment markers of the chip 12 arranged on the second stage 202 side, a two-field camera 224, an eyepiece 225, and a reflector 226.

[0068] The camera unit 203 recognizes the reference marker 21 on the substrate 11 supported by the first stage 201 and the chip marker 22c on the chip 12c supported by the second stage 202, and aligns the first stage 201 and the second stage 202.

[0069] After aligning the first stage 201 and the second stage 202, the camera unit 203 is moved, and the second stage 202 is brought closer to the first stage 201. Thereafter, the support by the bond chuck of the second stage 202 is released, and the chip 12c is stacked on the second chip 12b. Thereafter, the substrate 11 on which the multiple chips are stacked is diced (divided) to obtain semiconductor chips (not shown).

[0070] Of the objective lenses 213 and 223 included in the camera unit 203 according to this embodiment, the depth of field d of the objective lens 213 on the substrate side is preferably equal to or less than the thickness T of the chips 12b and 12c when the chips have the same thickness. This allows the camera unit 203 to recognize only the chip marker of the target chip. There is no particular restriction on the depth of field of the objective lens 223 on the second stage 202 side.

[0071] The cases where the chip thicknesses are different and the orientation of the chip markers are as explained in embodiment 1 and Figures 5(a) to 5(d). The range of the depth of field d of the objective lens 213 on the substrate side depends on the thickness T of the chip (chip 12a in this case) sandwiched between the two chip markers 22a and 22b.

[0072] In this way, it is possible to provide a semiconductor device manufacturing apparatus and method that stacks a plurality of chips with high precision and high yield.

[0073] The invention made by the present inventors has been specifically described above based on the embodiments, but the present disclosure is not limited to the embodiments already described, and various modifications are possible within the scope that does not deviate from the gist of the present disclosure. [Explanation of symbols]

[0074] 10 Semiconductor device 11 Circuit Board 12, 12a, 12b, 12c, …, 12m chips 13 Semiconductor chips 20 areas 21, 21a, 21b, 21c Reference markers 22, 22a, 22b, 22c Chip markers 23b, 23c area 100, 200 manufacturing equipment 101, 201 1st Stage 102, 202 Stage 2 103, 203 camera unit 112 Thermal transfer material 113, 213, 223 objective lenses 114 Laser light 224 Dual-view camera 225 eyepiece 226 Reflector

Claims

1. A manufacturing apparatus for a semiconductor device in which a plurality of chips are stacked in a direction perpendicular to a surface of a substrate, a first stage supporting a substrate; a second stage supporting the chip facing the substrate; a movable camera unit that photographs the substrate and the alignment markers of the chip, At least one of the first stage and the second stage is movable, the second stage is configured to perform alignment using a reference marker formed on the substrate or a first chip marker formed on a first chip placed on the substrate, and a second chip marker formed on a second chip supported by the second stage, and then stack the second chip on the first chip; a depth of field of an objective lens included in the camera unit is equal to or less than a sum of a thickness of a chip sandwiched between the first chip marker and the second chip marker and a distance between the first chip and the second chip after the alignment; Semiconductor device manufacturing equipment.

2. Further, a light source that emits laser light is provided, the second stage is configured to support the second chip using a heat transfer; the step of stacking the second chip on the first chip is performed by irradiating the thermal transfer body with the laser light. The semiconductor device manufacturing apparatus according to claim 1 .

3. the camera unit is disposed between the first stage and the second stage and includes a dual-view camera; the second stage includes a bond chuck that supports the second chip; the second chip is stacked on the first chip and released from the bond chuck; The semiconductor device manufacturing apparatus according to claim 1 .

4. the first chip marker of the first chip and the second chip marker of the second chip after the alignment are superimposed on each other in approximately the same region in a plan view; 4. The semiconductor device manufacturing apparatus according to claim 1.

5. When the first chip marker and the second chip marker are used for the alignment, the depth of field of the objective lens provided in the camera unit is equal to or less than the thickness of a chip sandwiched between the first chip marker and the second chip marker.

4. The semiconductor device manufacturing apparatus according to claim 1.

6. A method of manufacturing a semiconductor device in which a plurality of chips are stacked in a direction perpendicular to a surface of a substrate, comprising: aligning the first stage and the second stage using a reference marker formed on a substrate supported by a first stage or a first chip marker formed on a first chip placed on the substrate, and a second chip marker formed on a second chip supported by a second stage; stacking the second chip on the first chip; a depth of field of an objective lens included in a camera unit used for the alignment is equal to or less than the sum of the thickness of a chip sandwiched between the first chip marker and the second chip marker and the distance between the first chip and the second chip after the alignment; A method for manufacturing a semiconductor device.

7. the second stage is configured to support the second chip using a heat transfer; After the alignment, the second chip is stacked on the first chip by irradiating the thermal transfer with a laser beam. The method for manufacturing a semiconductor device according to claim 6 .

8. the camera unit is disposed between the first stage and the second stage and includes a dual-view camera; the second stage includes a bond chuck that supports the second chip; After the alignment, the second chip is stacked on the first chip by releasing the support by the bond chuck. The method for manufacturing a semiconductor device according to claim 6 .

9. the first chip marker of the first chip and the second chip marker of the second chip after the alignment are superimposed on each other in approximately the same region in a plan view; The method for manufacturing a semiconductor device according to any one of claims 6 to 8.

10. When the first chip marker and the second chip marker are used for the alignment, the depth of field of the objective lens included in the camera unit is equal to or less than the thickness of the second chip. The method for manufacturing a semiconductor device according to any one of claims 6 to 8.

11. a pre-processing step of removing chip markers located in an area outside the depth of field of the objective lens in the vertical direction from the alignment process; The method for manufacturing a semiconductor device according to any one of claims 6 to 8.

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