Signal generator and signal generation method implemented by signal generator

Abstract

To specify the timing of modulation start of SSC in shorter time than before.SOLUTION: A signal generator 1 comprises: a clock source 2 for generating a clock of a reference frequency; a jitter modulation source 3 for generating a jitter clock obtained by modulating the clock of the reference frequency; a signal generation source 4 for generating a signal of a frequency transition pattern specified according to a desired technical standard for input to a measurement object W, at a timing of the jitter clock; and an operation unit 5 for setting a type of the signal of the frequency transition pattern, a start time at which modulation is applied to the clock of the standard frequency, and a frequency deviation amount at the time of applying modulation to the clock of the standard frequency. The signal generation source 4 notifies the jitter modulation source 3 of a timing for switching the signal of the frequency transition pattern applying modulation to the clock of the reference frequency. The jitter modulation source 3 outputs a jitter clock having applied modulation of a frequency deviation amount to the clock of the reference frequency, to the signal generation source 4, when receiving the notification from the signal generator 4.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a signal generating device and a signal generating method that generate a signal using SSC (spread spectrum clocking). [Background technology]

[0002] The standard speed of USB, used for communication between computers and devices, is steadily increasing. As speeds increase, methods for ensuring signal quality are becoming more complex. One such method is spread spectrum clocking (SSC), as disclosed in, for example, Patent Document 1 below. Naturally, the method and frequency of SSC are also specified by the standard. The standard not only defines the product itself, but also defines the testing method for that product, and all manufacturers of products using the USB standard must comply with these standards.

[0003] Here, we will explain a portion of the USB4 v2 Gen4 RX Trit Error Rate test as an example of whether a device under test operates normally when SSC is applied to a 3-bit signal. Figure 4 illustrates the frequency transition pattern sequence specified in USB4 v2 Gen4. To perform a USB4 v2 Gen4 RX Trit Error Rate test, the device under test (DUT) must be presented with data patterns in the following order, as shown in Figure 4: (1) PRBS11 (without SSC) → (2) PRTS7 (without SSC) → (3) PRTS19 (without SSC) → (4) PRTS19 (with SSC). (The error rate measurement itself is performed after this point.) Furthermore, in Figure 4, the transition from (3) to (4) must be completed within 500 μs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 7376521 Summary of the Invention [Problem to be solved by the invention]

[0005] To perform the above-mentioned tests, device manufacturers require a signal generator. While a signal generator's role is to generate a signal, it cannot operate on its own and often requires a separate clock source. Furthermore, when frequency transitions are required, as described above, a device that modulates the clock is also required. One example of such a device is a jitter modulation source. Jitter is a phase fluctuation, and a jitter modulation source can apply a specified pattern and amount of jitter to the input clock and output it. In other words, a Bit Error Rate Test Set (BERTS), which includes a clock source, jitter modulation source, and signal generation source, can meet the demands of a single device.

[0006] In this type of error rate measurement equipment, the clock source, jitter modulation source, and signal generation source are each incorporated into the same equipment as modules. Therefore, naturally, each module can operate cooperatively to a certain extent. Moreover, since the control device of the error rate measurement equipment controls each module, there are no technical issues here.

[0007] However, this is on the order of several hundred milliseconds to several seconds, and as shown in Figure 4, it is not possible to have each module operate cooperatively on the order of microseconds. The control devices of conventional error rate measurement devices are roughly the same as those of ordinary computers, providing a GUI to the user and controlling each module based on input from the user. In other words, because they are based on application software, they are not suited to timing control in the first place. For these reasons, a new mechanism is needed to enable the output shown in Figure 4.

[0008] Therefore, the present invention has been made in consideration of the above problems, and aims to provide a signal generating device and a signal generating method that can specify the timing of starting SSC modulation in a shorter time than conventional methods. [Means for solving the problem]

[0009] In order to achieve the above object, a signal generator according to claim 1 of the present invention comprises a clock source 2 that generates a clock of a reference frequency, a jitter modulation source 3 that generates a jitter clock by modulating the reference frequency clock generated by the clock source, a signal generation source 4 that generates a signal of a frequency transition pattern defined by a desired standard at the timing of the jitter clock to be input to a device under test W, and an operation unit 5 that sets the type of signal of the frequency transition pattern, the start time of modulating the clock of the reference frequency, and the amount of frequency deviation when modulating the clock of the reference frequency, the signal generation source notifies the jitter modulation source of the timing of switching of the frequency transition pattern signal that modulates the clock of the reference frequency; The jitter modulation source is characterized in that, upon receiving the notification from the signal generation source, it outputs to the signal generation source a jitter clock obtained by modulating the reference frequency clock with the amount of frequency deviation.

[0010] The signal generating device according to claim 2 of the present invention is the signal generating device according to claim 1, The clock source 2, the jitter modulation source 3, and the signal generating source 4 are configured as modules that can be selectively attached to and detached from a plurality of slots 1c provided in the device main body 1a.

[0011] The signal generating device according to claim 3 of the present invention is the signal generating device according to claim 2, A selector unit 7 is provided for connecting the modules together, The device is characterized by including a device control unit 8 that controls the selector unit so as to connect the module of the jitter modulation source 3 and the module of the signal generation source 4 at the timing of switching of the signal of the frequency transition pattern that modulates the clock of the reference frequency.

[0012] A signal generating method according to claim 4 of the present invention includes the steps of arranging, in a main body 1a of a signal generating device 1, a clock source 2 that generates a clock of a reference frequency, a jitter modulation source 3 that generates a jitter clock by modulating the clock of the reference frequency generated by said clock source, and a signal generating source 4 that generates a signal having a frequency transition pattern defined by a desired standard at the timing of said jitter clock to be input to a device under test W; setting a type of signal of the frequency transition pattern, a start time of applying modulation to the clock of the reference frequency, and a frequency deviation amount when applying modulation to the clock of the reference frequency; a step of notifying the jitter modulation source of the timing of switching of the frequency transition pattern signal that modulates the clock of the reference frequency from the signal generation source; and when the jitter modulation source receives the notification from the signal generating source, outputting from the jitter modulation source to the signal generating source a jitter clock obtained by modulating the reference frequency clock by the amount of frequency deviation.

[0013] The signal generating method according to claim 5 of the present invention is the signal generating method according to claim 4, The method is characterized by including a step of arranging the clock source 2, the jitter modulation source 3, and the signal generating source 4 as modules that are selectively detachable from a plurality of slots 1c provided in the device main body 1a.

[0014] The signal generating method according to claim 6 of the present invention is the signal generating method according to claim 5, a step of disposing a selector unit 7 for connecting between the modules; The method is characterized by including a step of controlling the selector unit by an apparatus control unit 8 so as to connect between the module of the jitter modulation source 3 and the module of the signal generation source 4 at the timing of switching of the signal of the frequency transition pattern that modulates the clock of the reference frequency. [Effects of the Invention]

[0015] According to the present invention, the timing of starting SSC modulation can be specified to a time (on the order of μs) shorter than conventional times. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a block diagram showing a schematic configuration of a signal generating device according to the present invention; [Figure 2] 1 is a perspective view showing the appearance of a signal generating device according to the present invention. [Figure 3] FIG. 10 is a diagram showing an example of a setting screen for a signal generation source in the signal generating device according to the present invention. [Figure 4] FIG. 10 is a diagram illustrating an example of a signal of a frequency transition pattern defined by a standard. DETAILED DESCRIPTION OF THE INVENTION

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0018] As shown in FIG. 1, the signal generating device 1 of this embodiment is roughly configured to include a clock source 2, a jitter modulation source 3, a signal generating source 4, an operation unit 5, a display unit 6, a selector unit 7, and a device control unit 8, and has a function of generating a signal having a frequency transition pattern defined by a desired standard, for example, as shown in FIG. 4, using SSC (spread spectrum clocking) as a signal to be input to the device under test W before measuring the error rate.

[0019] The device under test W includes an error detection unit W1 that detects whether or not there is an error in the signal input from the signal generation source 4 of the signal generating device 1.

[0020] 2, the signal generating device 1 has a device body 1a made of a rectangular housing, and an opening 1b formed in a side portion of the device body 1a. A plurality of slots (eight slots in the example of FIG. 2) 1c are provided in the opening 1b of the device body 1a.

[0021] The clock source 2, jitter modulation source 3, and signal generating source 4 are configured as modules that can be selectively attached to and detached from slots 1c of the device main body 1a. The example in Figure 2 shows a state in which modules are attached to all slots 1c of the device main body 1a. In practice, the device functions as a signal generating device 1 by selectively attaching the modules of the clock source 2, jitter modulation source 3, and signal generating source 4 (three modules) to slots 1c of the device main body 1a. The modules required to generate a signal with a frequency transition pattern defined by a desired standard are attached in appropriate combinations to slots 1c of the device main body 1a, and modules can be added, removed, or rearranged.

[0022] In addition, by installing an error detector module in slot 1c of device main body 1a, it can also function as an error rate measuring device that receives a signal that is returned when a test signal is input to the device under test W and measures the error rate.

[0023] The clock source 2 generates a reference clock (a clock with a reference frequency) under the control of a device control unit 8 connected via Ethernet (registered trademark), and is composed of an FPGA 2a and a clock generation unit 2b.

[0024] The FPGA 2a includes a module control unit 2aa and a control circuit 2ab. The module control unit 2aa also serves as an interface connecting the device control unit 8 and the control circuit 2ab, and in addition to outputting instructions (commands) from the device control unit 8 to the control circuit 2ab, it also executes some of the processing and control within the clock source 2.

[0025] The control circuit 2ab controls the clock generating unit 2b in response to an instruction (command) from the device control unit 8 to generate a clock of a reference frequency.

[0026] The clock generating unit 2b generates a clock of a reference frequency under the control of the control circuit 2ab based on an instruction (command) from the device control unit 8.

[0027] The jitter modulation source 3 generates a jitter clock by applying the desired modulation to the reference frequency clock generated by the clock source 2 under the control of the device control unit 8 connected via Ethernet (registered trademark), and is composed of an FPGA 3a and a jitter modulation unit 3b.

[0028] The FPGA 3a includes a module control unit 3aa and a control circuit 3ab. The module control unit 3aa also serves as an interface that connects the device control unit 8 and the control circuit 3ab, and in addition to outputting instructions (commands) from the device control unit 8 to the control circuit 3ab, it also executes some of the processing and control within the jitter modulation source 3.

[0029] The control circuit 3ab controls the jitter modulation unit 3b in response to an instruction (command) from the device control unit 8 to generate a jitter clock by applying a desired modulation to the clock of the reference frequency generated by the clock source 2.

[0030] The jitter modulation unit 3b generates a jitter clock by applying a desired modulation to the clock of the reference frequency generated by the clock source 2 under the control of the control circuit 3ab based on an instruction (command) from the device control unit 8.

[0031] The signal generating source 4 generates a signal with a frequency transition pattern defined by a desired standard (a pulse pattern signal with a desired repetitive pattern) to be input to the device under test W under the control of the device control unit 8 connected via Ethernet (registered trademark), using a jitter clock generated by the jitter modulation source 3, and is composed of an FPGA 4a and a data multiplexing unit 4b.

[0032] The FPGA 4a includes a module control unit 4aa and a control circuit 4ab. The module control unit 4aa also serves as an interface connecting the device control unit 8 and the control circuit 4ab, and in addition to outputting instructions (commands) from the device control unit 8 to the control circuit 4ab, it also executes some of the processing and control within the signal generation source 4.

[0033] In response to an instruction (command) from the device control unit 8, the control circuit 4ab outputs a parallel signal that is the source of a desired signal (for example, a signal with a frequency transition pattern defined by a desired standard as shown in FIG. 4: a serial signal) to the data multiplexing unit 4b.

[0034] The data multiplexing unit 4b multiplexes the parallel signals input from the control circuit 4ab in accordance with the timing of the jitter clock generated by the jitter modulation source 3 to generate a desired serial signal (for example, a signal with a frequency transition pattern defined by a desired standard as shown in Figure 4: "PRBS11 (no SSC)" → "PRTS7 (no SSC)" → "PRTS19 (no SSC)" → "PRTS19 (with SSC)").

[0035] The signal generating source 4 notifies the jitter modulation source 3 of the timing of switching the pattern that starts SSC, i.e., the timing of switching the signal of the frequency transition pattern that modulates the reference frequency clock generated by the clock source 2, via a path R (path indicated by the thick arrow in Figure 1) that connects the signal generating source 4 to the jitter modulation source 3 via the selector unit 7.

[0036] The operation unit 5 is composed of, for example, various keys, switches, buttons, and soft keys on the display screen of the display unit 6 that are equipped on the main body of the signal generating device 1, and the like, and the user operates and inputs various information necessary for the signal generating device 1 to generate the desired signal.

[0037] The display unit 6 is composed of display devices such as a liquid crystal display, an EL (electroluminescence) display, a CRT, etc., and under the control of the device control unit 8, displays operation objects such as a setting item screen for generating a desired signal, and buttons, soft keys, pull-down menus, input boxes, etc. for setting various conditions on the setting item screen.

[0038] Here, Fig. 3 shows an example of the setting screen 11 of the signal generator 4. At the top of the setting screen 11 of the signal generator 4 in Fig. 3, an item "Test Pattern" for setting the type of signal for the pattern (frequency transition pattern) is displayed. In this "Test Pattern", the type of signal for the pattern is set by selecting it from pull-down menus 12 and 13. The setting screen 11 of the signal generator 4 in Fig. 3 shows a state in which "All List" has been selected from the "Test Pattern" pull-down menu 12 and "USB4 Clock Switch" has been selected from the pull-down menu 13.

[0039] The signal block order 14 of the frequency transition pattern defined by the desired standard is displayed in the center of the setting screen 11 of the signal generator 4 in Fig. 3. In this frequency transition pattern signal block order 14, the time from when the signal block of the frequency transition pattern switches to when SSC starts (the start time at which modulation of the reference frequency clock generated by the clock source 2 starts) can be set by inputting a desired value in the input box 15. The setting screen 11 of the signal generator 4 in Fig. 3 shows a state in which "300" has been input in the input box 15, setting the time from when the signal block of the frequency transition pattern switches to block #3 to when SSC starts to "300" μs.

[0040] A pattern setting list 16 for each block of signals of the frequency transition pattern defined by the standard is displayed at the bottom of the setting screen 11 of the signal generator 4 in Fig. 3. In this pattern setting list 16 for each block, the order of the patterns to be generated is indicated by Block No., and the pattern for each Block No. is set by selecting it from pull-down menus 17 (17a, 17b, 17c). The setting screen 11 of the signal generator 4 in Fig. 3 shows a state in which "PRBS11" has been selected and set as the pattern for Block #1 from pull-down menu 17a, "PRTS7" has been selected and set as the pattern for Block #2 from pull-down menu 17b, and "PRTS19" has been selected and set as the pattern for Blocks #3 and #4 from pull-down menu 17c.

[0041] In addition, the pull-down menu 17 (17a, 17b, 17c) allows the user to set a pattern selected from pseudo-random patterns that the user has arbitrarily set and registered in advance, as well as PRBS or PRTS with a predetermined number of stages according to the desired standard.

[0042] The selector unit 7 has pairs of input and output wiring that are connected to all modules of the clock source 2, jitter modulation source 3, and signal generation source 4. The selector unit 7 is equipped with a multiplexer that selects the output and a demultiplexer that selects the input under the control of the device control unit 8.

[0043] In this embodiment, the device control unit 8 controls the selector unit 7 so that the multiplexer in the selector unit 7 selects the signal generation source 4 and the demultiplexer in the selector unit 7 selects the jitter modulation source 3. As a result, only the path R (the path indicated by the thick arrow in FIG. 1) that connects from the signal generation source 4 via the selector unit 7 to the jitter modulation source 3 is connected, and path R is enabled.

[0044] The control of the selector unit 7 is performed automatically by the device control unit 8 depending on the modules (clock source 2, jitter modulation source 3, signal generating source 4, etc.) to which the device control unit 8 is connected, or by the device control unit 8 depending on the user's settings.

[0045] Furthermore, in this embodiment, a configuration is made such that a plurality of modules including the clock source 2, jitter modulation source 3, and signal generation source 4 can be freely connected to a plurality of slots 1c. For this reason, the device control unit 8 controls the selector unit 7 to connect only the path R (the path indicated by the thick arrow in FIG. 1) that connects from the signal generation source 4 to the jitter modulation source 3 via the selector unit 7, thereby enabling the path R, but this is not limited to this. For example, in cases where the slots 1c to which the modules of the clock source 2, jitter modulation source 3, and signal generation source 4 are connected are fixed, or in cases where the configuration is provided with only the modules of the clock source 2, jitter modulation source 3, and signal generation source 4, it is also possible to connect the signal generation source 4 and the jitter modulation source 3 with a dedicated path R and eliminate the selector unit 7.

[0046] The device control unit 8 controls the clock source 2, jitter modulation source 3, signal generation source 4, operation unit 5, display unit 6, and selector unit 7. That is, the device control unit 8 controls the display unit 6 to display various setting screens including the setting screen for the signal generation source 4 shown in Fig. 3, controls the clock source 2, jitter modulation source 3, and signal generation source 4 to generate a reference frequency clock based on operation input from the operation unit 5, generates a jitter clock, and generates a desired signal (for example, a signal with a frequency transition pattern defined by a desired standard as shown in Fig. 4), and controls the selector unit 7 to connect and enable only the path R connecting the signal generation source 4 to the jitter modulation source 3.

[0047] Next, the operation of the signal generating device 1 configured as above will be described. Here, the operation when generating a signal with a frequency transition pattern defined in USB4 v2 Gen4 ("PRBS11 (without SSC)" → "PRTS7 (without SSC)" → "PRTS19 (without SSC)" → "PRTS19 (with SSC)") shown in Fig. 4 will be described as an example.

[0048] First, make the various settings required to generate a signal with the frequency transition pattern shown in Fig. 4. Specifically, on the setting screen 11 of the signal generator 4 shown in Fig. 3, select "All List" from the "Test Pattern" pull-down menu 12 and "USB4 Clock Switch" from the pull-down menu 13.

[0049] Then, on the setting screen 11 of the signal generator 4 in FIG. 3, select and set "PRBS11" from the pull-down menu 17a as the pattern for block #1, select and set "PRTS7" from the pull-down menu 17b as the pattern for block #2, and select and set "PRTS19" from the pull-down menu 17c as the pattern for blocks #3 and #4, and set the type of pattern signal.

[0050] Also, on the setting screen 11 of the signal generator 4 in Figure 3, enter "300" in the input box 15 to set the time until the start of SSC (the start time for modulating the reference frequency clock generated by the clock source 2: less than 500 μs).

[0051] 4 is set by inputting the numerical value "-3400" on the setting screen (not shown) of the jitter modulation source 3 by operating the operation unit 5. In addition, precoding on / off setting, polarity inversion on / off setting, etc. are also performed as necessary.

[0052] After completing the above settings, the generation and switching of the frequency transition pattern signal in Fig. 4 is started by operating the "Manual": manual transmit button 18 and the "Transmit": automatic transmit button 19 on the setting screen 11 of the signal generator 4 in Fig. 3. Specifically, as the frequency transition pattern signal in Fig. 4, the "Manual": manual transmit button 18 is operated to manually generate the pattern "PRBS11 (without SSC)" of block #1 and the pattern "PRTS7 (without SSC)" of block #2 in that order. Thereafter, the "Transmit": automatic transmit button 19 is operated to automatically generate the pattern "PRTS19 (without SSC)" of block #3 and the pattern "PRTS19 (with SSC)" of block #4 in that order.

[0053] When generating the frequency transition pattern signal of Figure 4 described above, at the timing of switching the frequency transition pattern signal that modulates the reference frequency clock, i.e., when switching from the pattern "PRTS19 (without SSC)" of block #3 to the pattern "PRTS19 (with SSC)" of block #4, the device control unit 8 controls the selector unit 7 to connect only the path R that connects from the signal generation source 4 to the jitter modulation source 3 via the selector unit 7, and the signal generation source 4 notifies the jitter modulation source 3 of the timing of switching the pattern that starts SSC.

[0054] Then, when the jitter modulation source 3 receives notification from the signal generation source 4 of the timing of switching the pattern at which SSC starts, the jitter modulation unit 3b outputs a jitter clock modulated with a frequency deviation of -3400 PPM to the data multiplexing unit 4b of the signal generation source 4 under the control of the FPGA 3a. As a result, when 300 μs has elapsed from the timing of switching to the pattern "PRTS19 (without SSC)" of block #3, the data multiplexing unit 4b of the signal generation source 4 starts generating the pattern "PRTS19 (with SSC)" of block #4 at the timing of the jitter clock modulated with a frequency deviation of -3400 PPM from the clock from the jitter modulation unit 3b.

[0055] In the above-described embodiment, if the device under test W does not have a built-in error detection unit W1, the device may be configured to include a separate error detector as a module that can be attached to and detached from the slot 1c of the device main body 1a. In this case, the signal generating device 1 functions as an error rate measuring device in which a test signal is input from the signal generating source 4 to the device under test W, and the error detector receives a signal that is looped back from the device under test W in response to the input of this test signal, detects the presence or absence of an error, and measures the error rate.

[0056] In the above-described embodiment, when generating the frequency transition pattern signal of Fig. 4, the pattern "PRBS11 (without SSC)" of block #1 and the pattern "PRTS7 (without SSC)" of block #2 are set to "Manual," and the generation and switching between the pattern "PRBS11 (without SSC)" of block #1 and the pattern "PRTS7 (without SSC)" of block #2 are performed manually by operating the "Manual": manual start button 18 on the setting screen 11 of the signal generator 4 of Fig. 3. However, this is not a limitation. For example, the setting screen 11 of the signal generator 4 of Fig. 3 may have input boxes (input boxes with the same format as the input box 15 of block #3) for inputting and setting the pattern generation times corresponding to blocks #1 and #2 of the block order 14 of the frequency transition pattern signal, and the device control unit 8 may automatically generate and switch patterns based on the generation times input and set in each input box by operating the "Transmit": automatic start button 19.

[0057] As described above, according to this embodiment, the delay due to the added path R, including the selector unit 7, is tens to hundreds of nanoseconds, so it is possible to output data and frequency transition patterns specified by the desired standard while satisfying the specification of the order of several microseconds as shown in FIG. 4. This allows the timing of the start of SSC modulation to be specified in a shorter time (on the order of microseconds) than before, and allows users, i.e., manufacturers of products that use the USB standard, to obtain test input signals for their devices with a single product. Furthermore, the provided GUI is expected to enable use without requiring users to be aware of internal operations, leading to improved user convenience.

[0058] While the best mode for the signal generating device and signal generating method according to the present invention has been described above, the present invention is not limited to the description and drawings of this mode. In other words, all other modes, embodiments, and operational techniques that can be realized by those skilled in the art based on this mode are naturally included in the scope of the present invention. [Explanation of symbols]

[0059] 1. Signal Generator 1a Device body 1b opening 1c slot 2 Clock Sources 2a FPGA 2aa Module control unit 2ab control circuit 2b Clock generation section 3 Jitter Modulation Source 3a FPGA 3aa Module control unit 3ab control circuit 3b Jitter modulation section 4. Signal Source 4a FPGA 4aa Module control unit 4ab control circuit 4b Data multiplexing section 5 Control section 6 Display section 7 Selector section 8 Device control section 11 Settings screen 12,13 Drop-down menu 14 Block order of frequency transition pattern 15 Input box 16 Pattern setting list for each block 17(17a,17b,17c) Pull-down menu 18 Manual Send Button 19 Auto-Submit Button R: A path from the signal generator 4 to the jitter modulation source 3 via the selector unit 7 W Object to be measured W1 Error detection section

Claims

1. A signal generating device (1) comprising: a clock source (2) for generating a reference frequency clock; a jitter modulation source (3) for generating a jitter clock obtained by modulating the reference frequency clock generated by the clock source; a signal generating source (4) for generating a signal of a frequency transition pattern defined by a desired standard at the timing of the jitter clock to be input to a device under test (W); and an operation unit (5) for setting the type of the signal of the frequency transition pattern, the start time for modulating the reference frequency clock, and the frequency deviation amount when modulating the reference frequency clock, the signal generation source notifies the jitter modulation source of the timing of switching of the frequency transition pattern signal that modulates the clock of the reference frequency; A signal generating device characterized in that, when the jitter modulation source receives the notification from the signal generating source, it outputs to the signal generating source a jitter clock that has been modulated by the amount of frequency deviation relative to the clock of the reference frequency.

2. 2. The signal generating device according to claim 1, wherein the clock source (2), the jitter modulation source (3), and the signal generating source (4) are configured as modules selectively detachable from a plurality of slots (1c) provided in the device main body (1a).

3. A selector unit (7) is provided for connecting the modules together; 3. The signal generating device according to claim 2, further comprising a device control unit (8) that controls the selector unit so as to connect the module of the jitter modulation source (3) and the module of the signal generating source (4) at the timing of switching of the signal of the frequency transition pattern that modulates the clock of the reference frequency.

4. a step of disposing, in a main body (1a) of a signal generating device (1), a clock source (2) that generates a clock of a reference frequency, a jitter modulation source (3) that generates a jitter clock obtained by modulating the clock of the reference frequency generated by the clock source, and a signal generating source (4) that generates a signal of a frequency transition pattern defined by a desired standard at the timing of the jitter clock to be input to a device under test (W); setting a type of signal of the frequency transition pattern, a start time of applying modulation to the clock of the reference frequency, and a frequency deviation amount when applying modulation to the clock of the reference frequency; a step of notifying the jitter modulation source of the timing of switching of the frequency transition pattern signal that modulates the clock of the reference frequency from the signal generation source; and when the jitter modulation source receives the notification from the signal generation source, outputting from the jitter modulation source to the signal generation source a jitter clock obtained by modulating the reference frequency clock by the amount of frequency deviation.

5. 5. The signal generating method according to claim 4, further comprising a step of arranging the clock source (2), the jitter modulation source (3), and the signal generating source (4) as modules selectively detachable from a plurality of slots (1c) provided in the device main body (1a).

6. a step of disposing a selector unit (7) for connecting between the modules; 6. The signal generating method according to claim 5, further comprising a step of controlling the selector unit by an apparatus control unit (8) to connect the module of the jitter modulation source (3) and the module of the signal generating source (4) at the timing of switching of the signal of the frequency transition pattern that modulates the clock of the reference frequency.

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