Semiconductor device

Abstract

To provide a new semiconductor device.SOLUTION: A semiconductor device 1A includes an n-type (first conductivity type) semiconductor layer 7 having a first main surface 3, a p-type (second conductivity type) first region 11 extending in the semiconductor layer 7 in a first direction X along the first main surface 3, a p-type second region 12 formed in the semiconductor layer 7 in a region on the first main surface 3 side of the first region 11 and extending in a second direction Y along the first main surface 3 so as to intersect the first region 11 in a three-dimensional manner, and a p-type low concentration region 13 formed in the semiconductor layer 7 at least at the intersection of the first region 11 and the second region 12 and having a concentration lower than both the maximum concentration value of the first region 11 and the maximum concentration value of the second region 12.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 (US2015 / 0028351A1) discloses a semiconductor device having an impurity region introduced into a silicon carbide layer by channeling implantation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2015 / 0028351

[0004] [overview] The present disclosure provides a novel semiconductor device.

[0005] The present disclosure provides a semiconductor device including: a semiconductor layer of a first conductivity type having a main surface; a first region of a second conductivity type extending in the semiconductor layer in a first direction along the main surface; a second region of the second conductivity type formed in a region on the main surface side of the semiconductor layer relative to the first region and extending in a second direction along the main surface so as to intersect the first region in a three-dimensional manner; and a low concentration region of the second conductivity type formed in the semiconductor layer at least at an intersection of the first region and the second region and having a concentration lower than both the maximum concentration value of the first region and the maximum concentration value of the second region.

[0006] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a chip of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a perspective view of the chip shown in FIG. [Figure 3] FIG. 3 is a cross-sectional perspective view showing a main part of a chip together with a pillar region according to a first example. [Figure 4] FIG. 4 is a graph (simulation) showing the impurity concentration in the pillar region. [Figure 5A] FIG. 5A is a plan view showing a first layout example of a pillar region according to the first example. [Figure 5B] FIG. 5B is a plan view showing a second layout example of the pillar region according to the first example. [Figure 5C] FIG. 5C is a plan view showing a third layout example of the pillar region according to the first example. [Figure 6] FIG. 6 is a cross-sectional perspective view showing the main part of the chip together with the pillar region according to the second example. [Figure 7A] FIG. 7A is a plan view showing a first layout example of a pillar region according to the second example. [Figure 7B] FIG. 7B is a plan view showing a second layout example of the pillar region according to the second example. [Figure 7C] FIG. 7C is a plan view showing a third layout example of the pillar region according to the second example. [Figure 8] FIG. 8 is a cross-sectional perspective view showing the main part of the chip together with the pillar region according to the third example. [Figure 9A] FIG. 9A is a plan view showing a first layout example of a pillar region according to the third example. [Figure 9B] FIG. 9B is a plan view showing a second layout example of the pillar region according to the third example. [Figure 9C] FIG. 9C is a plan view showing a third layout example of the pillar region according to the third example. [Figure 10] FIG. 10 is a cross-sectional perspective view showing a main part of a chip together with a pillar region according to a fourth example. [Figure 11] FIG. 11 is a cross-sectional perspective view showing a main part of a chip together with a pillar region according to a fifth example. [Figure 12] FIG. 12 is a cross-sectional perspective view showing a first modified example applied to the pillar regions according to the first to fifth examples. [Figure 13]FIG. 13 is a cross-sectional perspective view showing a second modified example applied to the pillar regions according to the first to fifth examples. [Figure 14] FIG. 14 is a plan view showing a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a plan view showing an example of the layout of the first main surface. [Figure 16] FIG. 16 is an enlarged plan view showing a main part of the active region. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. [Figure 19] FIG. 19 is a cross-sectional perspective view showing a main part of the active region together with the pillar region according to the first example. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view showing a main part of an active region of a semiconductor device according to the third embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing another main part of the active region of the semiconductor device shown in FIG. [Figure 23] FIG. 23 is a cross-sectional perspective view showing a main part of the active region together with the pillar regions according to the first example. [Figure 24] FIG. 24 is an enlarged plan view showing an active region of a semiconductor device according to the fourth embodiment. [Figure 25] FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. [Figure 26] FIG. 26 is a cross-sectional perspective view showing a main part of the active region together with the pillar region according to the first example. [Figure 27] FIG. 27 is an enlarged plan view showing an active region of a semiconductor device according to the fifth embodiment. [Figure 28] FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in FIG. [Figure 29] FIG. 29 is a cross-sectional view taken along line XXIX-XXIX shown in FIG. [Figure 30] FIG. 30 is a cross-sectional perspective view showing a main part of the active region together with the pillar region according to the first example. [Figure 31] FIG. 31 is a cross-sectional view showing the outer region of the semiconductor device shown in FIG. [Figure 32] FIG. 32 is a cross-sectional perspective view showing an active region of a semiconductor device according to the sixth embodiment together with a pillar region according to the first example. [Figure 33] FIG. 33 is a plan view showing a semiconductor device according to the seventh embodiment. [Figure 34] FIG. 34 is a perspective view of the chip shown in FIG. [Figure 35] FIG. 35 is a cross-sectional view taken along the line XXXV-XXXV shown in FIG. [Figure 36] FIG. 36 is a cross-sectional view showing a modification applied to any one of the semiconductor devices according to the second to sixth embodiments.

[0008] [Detailed explanation] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] In this specification, open language such as "including" and "having" is described as a concept that encompasses closed language such as "consisting of." When the term "substantially" is used in this specification, this term not only includes a numerical value (form) that is equal to the numerical value (form) of the comparison target, but also includes a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target.

[0010] In this specification, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0011] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0012] "P-type" is a conductivity type resulting from a trivalent element, while "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] Fig. 1 is a plan view showing a chip 2 of a semiconductor device 1A according to a first embodiment. Fig. 2 is a perspective view of the chip 2 shown in Fig. 1. Fig. 3 is a cross-sectional perspective view showing a main part of the chip 2 together with a pillar region 10 according to a first example.

[0014] 1 to 3, semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be called a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0015] A wide bandgap semiconductor is a semiconductor having a bandgap exceeding that of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0016] Hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes. The chip 2 may also include a cubic crystal or a polycrystal. For example, the chip 2 may include a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystal.

[0017] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0018] The first main surface 3 and the second main surface 4 are formed by the c-plane of the SiC single crystal. The first main surface 3 may be formed by the silicon surface ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon surface ((000-1) plane) of the SiC single crystal.

[0019] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0020] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0021] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. The c-axis ((0001) axis) of the SiC single crystal is inclined by the off-axis angle from a vertical line along the vertical direction Z toward the off-axis direction. The c-plane of the SiC single crystal is inclined by the off-axis angle with respect to the horizontal plane.

[0022] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0023] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (a configuration in which the first main surface 3 is a just plane relative to the c-plane).

[0024] The chip 2 includes an n-type base layer 6 formed in a region on the second main surface 4 side. The base layer 6 may also be referred to as a "base semiconductor layer," a "semiconductor substrate," a "drain layer (region)," or the like. The base layer 6 extends in a layered form along the second main surface 4, and forms a lower layer portion of the chip 2. The base layer 6 is formed over the entire second main surface 4, and forms part of the second main surface 4 of the chip 2 and first to fourth side surfaces 5A to 5D of the chip 2.

[0025] The base layer 6 includes a single crystal of a wide bandgap semiconductor. In this embodiment, the base layer 6 is a SiC substrate including a hexagonal SiC single crystal. In this embodiment, the base layer 6 includes a 4H—SiC single crystal and has the off-orientation and off-angle described above. The base layer 6 may include other polytypes. The base layer 6 may also include a 3C—SiC polycrystal. In this case, the second main surface 4 is formed of the 3C—SiC polycrystal.

[0026] The base layer 6 may have a substantially constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 may be adjusted by a single pentavalent element. The base layer 6 preferably contains a pentavalent element other than phosphorus. In this embodiment, the concentration of the base layer 6 is adjusted by nitrogen as a pentavalent element.

[0027] The base layer 6 may have a thickness greater than 0 μm and less than 500 μm. The thickness of the base layer 6 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 1 μm, 1 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, 300 μm to 350 μm, 350 μm to 400 μm, 400 μm to 450 μm, and 450 μm to 500 μm.

[0028] The chip 2 includes an n-type semiconductor layer 7 formed in a region of the chip 2 on the first main surface 3 side relative to the base layer 6. The semiconductor layer 7 has a stacked structure including an n-type first layer 8 and an n-type second layer 9. The first layer 8 may be referred to as a "first semiconductor layer," a "first SiC layer," a "first drain layer (region)," a "first drift layer (region)," etc., and the second layer 9 may be referred to as a "second semiconductor layer," a "second SiC layer," a "second drain layer (region)," a "second drift layer (region)," etc.

[0029] The first layer 8 is laminated on the base layer 6 and forms a middle layer of the chip 2. The first layer 8 extends in a layered form along the first main surface 3 (base layer 6) and forms part of the first to fourth side surfaces 5A to 5D of the chip 2.

[0030] The first layer 8 includes a single crystal of a wide bandgap semiconductor. In this embodiment, the first layer 8 is a SiC layer including a hexagonal SiC single crystal. In this embodiment, the first layer 8 is an epitaxial layer including a 4H—SiC single crystal (hexagonal), and has the off-orientation and off-angle described above. The first layer 8 may also include other polytypes.

[0031] The first layer 8 has an n-type impurity concentration lower than the n-type impurity concentration of the base layer 6. The n-type impurity concentration of the first layer 8 may be approximately constant in the thickness direction. The n-type impurity concentration of the first layer 8 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0032] The n-type impurity concentration of the first layer 8 is preferably adjusted with at least one pentavalent element. For example, the n-type impurity concentration of the first layer 8 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The first layer 8 preferably contains a pentavalent element other than phosphorus. The first layer 8 preferably contains at least nitrogen as a pentavalent element. When the first layer 8 contains two or more pentavalent elements, the first layer 8 preferably contains at least two of nitrogen, arsenic, and antimony.

[0033] The first layer 8 has a thickness in the thickness direction that is less than the thickness of the base layer 6. The thickness of the first layer 8 may be greater than 0 μm and less than 10 μm. The thickness of the first layer 8 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0034] The second layer 9 is laminated on the first layer 8 and forms the upper layer of the chip 2. The second layer 9 extends in a layered manner along the first main surface 3 (first layer 8) and forms part of the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.

[0035] The second layer 9 includes a single crystal of a wide bandgap semiconductor. In this embodiment, the second layer 9 is a SiC layer including a hexagonal SiC single crystal. In this embodiment, the second layer 9 is an epitaxial layer including a 4H—SiC single crystal (hexagonal), and has the off-orientation and off-angle described above. The second layer 9 may include another polytype. The second layer 9 may have a polytype different from that of the first layer 8.

[0036] The second layer 9 has an n-type impurity concentration lower than the n-type impurity concentration of the base layer 6. The n-type impurity concentration of the second layer 9 is approximately equal to the n-type impurity concentration of the first layer 8. The n-type impurity concentration of the second layer 9 may be higher or lower than the n-type impurity concentration of the first layer 8. The n-type impurity concentration of the second layer 9 may be approximately constant in the thickness direction. The n-type impurity concentration of the second layer 9 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0037] The n-type impurity concentration of the second layer 9 is preferably adjusted with at least one pentavalent element. For example, the n-type impurity concentration of the second layer 9 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The second layer 9 preferably contains a pentavalent element other than phosphorus. The second layer 9 preferably contains at least nitrogen as a pentavalent element. When the second layer 9 contains two or more pentavalent elements, the second layer 9 preferably contains at least two of nitrogen, arsenic, and antimony.

[0038] The second layer 9 has a thickness in the thickness direction that is less than the thickness of the base layer 6. The thickness of the second layer 9 may be approximately equal to the thickness of the first layer 8. The thickness of the second layer 9 may be greater or less than the thickness of the first layer 8. The thickness of the second layer 9 may be greater than 0 μm and equal to or less than 10 μm.

[0039] The thickness of the second layer 9 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more and less than 1 μm, 1 μm or more and less than 2 μm, 2 μm or more and less than 3 μm, 3 μm or more and less than 4 μm, 4 μm or more and less than 5 μm, 5 μm or more and less than 6 μm, 6 μm or more and less than 7 μm, 7 μm or more and less than 8 μm, 8 μm or more and less than 9 μm, and 9 μm or more and less than 10 μm.

[0040] The semiconductor device 1A includes a p-type pillar region 10 formed in the semiconductor layer 7. The configuration of the pillar region 10 will be described below with reference to FIG. 4. FIG. 4 is a graph (simulation) showing the impurity concentration of the pillar region 10. In FIG. 4, the vertical axis represents the impurity concentration [cm -3 The horizontal axis represents the depth [μm]. The pillar region 10 may also be called an "impurity region," a "column region," a "p-type region," or the like.

[0041] The pillar region 10 includes a plurality of p-type first regions 11 formed in the semiconductor layer 7. The first regions 11 may be referred to as "first column regions (layers)," "first pillar regions (layers)," "first p-type regions (layers)," etc. The plurality of first regions 11 are formed in the semiconductor layer 7 at intervals in the thickness direction from the first main surface 3. Specifically, the plurality of first regions 11 are formed in the first layer 8.

[0042] The multiple first regions 11 extend in a band shape in the first direction X in a plan view and are formed at intervals in the second direction Y. The multiple first regions 11 extend in a stripe shape in the first direction X. In this embodiment, the multiple first regions 11 have a length in the first direction X that extends from the second side surface 5B to the fourth side surface 5D and are exposed from both the second side surface 5B and the fourth side surface 5D. The multiple first regions 11 may be formed at intervals inward from either or both of the second side surface 5B and the fourth side surface 5D.

[0043] The multiple first regions 11 are each formed in a pillar shape (column shape) extending vertically in the thickness direction in a cross-sectional view, and each has an upper end portion on the first main surface 3 side (second layer 9 side) and a lower end portion on the second main surface 4 side (base layer 6 side). In this embodiment, the upper end portion is formed at a distance from the second layer 9 toward the second main surface 4, and faces the second layer 9 with a part of the first layer 8 in between. In this embodiment, the multiple first regions 11 are not formed in the second layer 9.

[0044] The lower end is formed at a distance from the base layer 6 toward the first main surface 3, and faces the base layer 6 across a part of the first layer 8. The lower end may be located on the surface layer of the base layer 6, across the boundary between the base layer 6 and the first layer 8.

[0045] The first region 11 may have a width greater than 0 μm and less than or equal to 10 μm. The width of the first region 11 may be less than the thickness of the first layer 8. The width of the first region 11 may be greater than the thickness of the first layer 8.

[0046] The width of the first region 11 may have a value belonging to at least one of the ranges of greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. The width of the first region 11 is preferably 5 μm or less.

[0047] The first region 11 may have a depth greater than 0 μm and less than or equal to 10 μm. The depth of the first region 11 is the distance between the upper end of the first region 11 and the lower end of the first region 11. The depth of the first region 11 may be less than the thickness of the first layer 8. The depth of the first region 11 may be greater than the thickness of the first layer 8.

[0048] The depth of the first region 11 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0049] The first regions 11 may be formed at intervals greater than 0 μm and equal to or less than 10 μm. The intervals between the first regions 11 may be approximately equal to the width of the first regions 11. The intervals between the first regions 11 may be greater or smaller than the width of the first regions 11.

[0050] The spacing between the multiple first regions 11 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0051] In this embodiment, each of the multiple first regions 11 is formed by a single p-type impurity region extending along an axial channel of the SiC single crystal (first layer 8). The axial channel is a region (channel) in which the interatomic distance is relatively large with respect to the SiC single crystal, and is surrounded by atomic rows that form a crystal axis extending in the stacking direction. In other words, the axial channel is a region in which the horizontal interatomic distance (atomic density) is sparse and extends in the thickness direction.

[0052] The axial channel is preferably a region surrounded by a row of atoms along a low-index crystal axis, which is a crystal axis whose absolute values ​​of "a1," "a2," "a3," and "c" are all between 0 and 2 (preferably 1 or less) in terms of Miller indices (a1, a2, a3, c).

[0053] In this embodiment, the axial channel is formed by a region surrounded by atomic rows aligned along the c-axis ((0001) axis) of the SiC single crystal. That is, the first regions 11 extend along the c-axis as the axial channel and have the off-direction and off-angle described above. In other words, the first regions 11 are tilted by the off-angle from the vertical axis toward the off-direction.

[0054] The p-type impurity concentration of first region 11 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of first region 11 is adjusted by a trivalent element that is heavier than carbon. In other words, first region 11 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of first region 11 is adjusted by aluminum.

[0055] The first region 11 has a concentration gradient in which the p-type impurity concentration increases from the bottom end to the top end (see FIG. 4). The first region 11 preferably has a thickness of at least 0.5 μm. The first region 11 preferably includes a gradually tapering portion having a concentration decrease rate of 50% or less within a thickness range of 0.5 μm. The gradually tapering portion preferably occupies a thickness range of 25% to 80% of the thickness of the first region 11.

[0056] The plurality of first regions 11 form a first pn junction with the first layer 8. The plurality of first regions 11 form a first superjunction structure SJ1 having charge balance with the first layer 8. The state having charge balance means a state in which depletion layers spreading from one and the other first regions 11 as origins are connected in the region between the one and the other first regions 11.

[0057] The pillar region 10 includes a plurality of p-type second regions 12 formed in the semiconductor layer 7. The second regions 12 may be referred to as "second column regions (layers)," "second pillar regions (layers)," "second p-type regions (layers)," etc. The plurality of second regions 12 are formed in regions on the first main surface 3 side of the plurality of first regions 11 in the semiconductor layer 7. Specifically, the plurality of second regions 12 are formed in the second layer 9.

[0058] The second regions 12 extend in a different direction from the first regions 11 in a plan view and intersect with the first regions 11 in a three-dimensional manner. As a result, the second regions 12, together with the first regions 11, form one pillar region 10 in a three-dimensional lattice shape. In this embodiment, the second regions 12 each extend in a strip shape in the second direction Y in a plan view and are formed at intervals in the first direction X. The second regions 12 extend in a stripe shape in the second direction Y and intersect with (orthogonal to) the first regions 11.

[0059] In this embodiment, the second regions 12 have a length in the second direction Y extending from the first side surface 5A to the third side surface 5C, and are exposed from both the first side surface 5A and the third side surface 5C. The second regions 12 may be formed at intervals inward from either or both of the first side surface 5A and the third side surface 5C.

[0060] The second regions 12 are each formed in a pillar shape (column shape) that extends vertically in the thickness direction in a cross-sectional view, and each has an upper end portion on the first main surface 3 side and a lower end portion on the second main surface 4 side (first layer 8 side). In this embodiment, the upper end portion is exposed from the first main surface 3. The upper end portion may be formed at an interval from the first main surface 3 in the thickness direction.

[0061] In this embodiment, the lower end crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. The lower end may be formed at a distance from the upper end of the first layer 8 toward the first main surface 3. In other words, the multiple second regions 12 may be formed at a distance from the multiple first layers 8 in the thickness direction.

[0062] The second region 12 may have a width greater than 0 μm and less than or equal to 10 μm. The width of the second region 12 may be less than the thickness of the second layer 9. The width of the second region 12 may be greater than the thickness of the second layer 9. The width of the second region 12 may be approximately equal to the width of the first region 11. The width of the second region 12 may be greater or smaller than the width of the first region 11.

[0063] The width of the second region 12 may be in at least one of the ranges of greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. The width of the second region 12 is preferably 5 μm or less.

[0064] The second region 12 may have a depth greater than 0 μm and less than or equal to 10 μm. The depth of the second region 12 is the distance between the upper end of the second region 12 and the lower end of the second region 12. The depth of the second region 12 may be greater than the thickness of the second layer 9. The depth of the second region 12 may be less than the thickness of the second layer 9. The depth of the second region 12 may be approximately equal to the depth of the first region 11. The depth of the second region 12 may be greater or less than the depth of the first region 11.

[0065] The depth of the second region 12 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0066] The multiple second regions 12 may be formed at intervals greater than 0 μm and equal to or less than 10 μm. The intervals between the second regions 12 may be approximately equal to the width of the second regions 12. The intervals between the second regions 12 may be greater or smaller than the width of the second regions 12. The intervals between the second regions 12 may be approximately equal to the intervals between the first regions 11. The intervals between the second regions 12 may be greater or smaller than the intervals between the first regions 11.

[0067] The spacing between the multiple second regions 12 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0068] In this embodiment, the second regions 12, like the first regions 11, are each formed of a single p-type impurity region extending along the axial channel of the SiC single crystal (second layer 9). That is, the second regions 12 extend along the c-axis as the axial channel and have the off direction and off angle described above. In other words, the second regions 12 are inclined by the off angle from the vertical axis toward the off direction.

[0069] The p-type impurity concentration of second region 12 is preferably adjusted with at least one trivalent element. It is particularly preferable that the p-type impurity concentration of second region 12 is adjusted with a trivalent element that is heavier than carbon. In other words, second region 12 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium).

[0070] In this embodiment, the p-type impurity concentration of the second region 12 is adjusted by aluminum. The trivalent element in the second region 12 is the same as the trivalent element in the first region 11. The trivalent element in the second region 12 may be different from the trivalent element in the first region 11. In this embodiment, the p-type impurity concentration of the second region 12 is approximately equal to the p-type impurity concentration of the first region 11. The p-type impurity concentration of the second region 12 may be higher or lower than the p-type impurity concentration of the first region 11.

[0071] The second region 12 has a concentration gradient in which the p-type impurity concentration increases from the bottom end to the top end (see FIG. 4). The second region 12 preferably has a thickness of at least 0.5 μm. The second region 12 preferably includes a gradually tapering portion in which the concentration decreases by 50% or less within a thickness range of 0.5 μm. The gradually tapering portion preferably occupies a thickness range of 25% to 80% of the thickness of the second region 12.

[0072] The plurality of second regions 12 form second pn junctions with the second layer 9. The plurality of second regions 12 form a second superjunction structure SJ2 having charge balance with the second layer 9. The state having charge balance means a state in which depletion layers extending from one and the other second regions 12 are connected in the region between the one and the other second regions 12.

[0073] The pillar region 10 includes a plurality of p-type low concentration regions 13 formed in the semiconductor layer 7. The low concentration regions 13 may also be referred to as "connection regions (layers)," "boundary regions (layers)," etc. The plurality of low concentration regions 13 are interposed at the intersections of the plurality of first regions 11 and the plurality of second regions 12.

[0074] The plurality of low-concentration regions 13 have a p-type impurity concentration that is lower than both the maximum value of the p-type impurity concentration in the first region 11 and the maximum value of the p-type impurity concentration in the second region 12 (see FIG. 4). The p-type impurity concentration in the low-concentration regions 13 is lower than both the p-type impurity concentration at a thickness position in an intermediate portion of the first region 11 and the p-type impurity concentration at a thickness position in an intermediate portion of the second region 12 (see FIG. 4).

[0075] The p-type impurity concentration of the low-concentration region 13 is adjusted by at least one trivalent element. The trivalent element of the low-concentration region 13 may be the same as or different from the trivalent element of the first region 11. The trivalent element of the low-concentration region 13 may be the same as or different from the trivalent element of the second region 12. The trivalent element of the low-concentration region 13 may be either or both of boron and aluminum.

[0076] In this embodiment, each of the plurality of low concentration regions 13 is formed by a single p-type impurity region. Alternatively, the plurality of low concentration regions 13 may be formed by a plurality of p-type impurity regions formed along the thickness direction.

[0077] The concentration ratio of the maximum value of the p-type impurity concentration in the low-concentration region 13 to the maximum value of the p-type impurity concentration in the first region 11 may be greater than 0 and less than 1. The concentration ratio may have a value belonging to at least one of the ranges of greater than 0 and less than 0.01, 0.01 to 0.05, 0.05 to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, 0.8 to 0.9, and 0.9 to less than 1.

[0078] The plurality of low-concentration regions 13 need only be disposed at least at the intersections, and may extend to regions other than the intersections. The plurality of low-concentration regions 13 may be disposed in either or both of the first layer 8 and the second layer 9 at the intersections. In this embodiment, the plurality of low-concentration regions 13 are disposed in the first layer 8 and formed at the intersections and regions other than the intersections.

[0079] Specifically, the plurality of low-concentration regions 13 are provided in a one-to-one correspondence with the plurality of first regions 11 in a region on the second layer 9 side relative to the plurality of first regions 11. The plurality of low-concentration regions 13 each extend in a strip shape in the first direction X in a plan view, and are formed at intervals in the second direction Y. The plurality of low-concentration regions 13 extend in a strip shape in the first direction X, and intersect (are perpendicular to) the plurality of second regions 12.

[0080] In this embodiment, the plurality of low-concentration regions 13 have a length in the first direction X that extends from the second side surface 5B to the fourth side surface 5D, and are exposed from both the second side surface 5B and the fourth side surface 5D. The plurality of low-concentration regions 13 may be formed at intervals inward from either or both of the second side surface 5B and the fourth side surface 5D. The plurality of low-concentration regions 13 may be formed in a one-to-many correspondence with the corresponding first regions 11, and may be formed at intervals in the first direction X following the extension direction of the corresponding first regions 11.

[0081] The plurality of low-concentration regions 13 have upper ends on the first main surface 3 side and lower ends on the second main surface 4 side (first layer 8 side). The upper ends are connected to corresponding second regions 12. In this embodiment, the upper ends are connected to corresponding second regions 12 within the first layer 8. The upper ends may cross the boundary between the first layer 8 and the second layer 9 and be connected to the second region 12 within the second layer 9.

[0082] The lower ends are located within the first layer 8 and connected to corresponding first regions 11 within the first layer 8. As a result, the plurality of low concentration regions 13 electrically connect the corresponding first regions 11 to the corresponding second regions 12. The lower ends are preferably formed at a distance from the depth position of the middle part of the first layer 8 toward the upper end of the first layer 8.

[0083] The low-concentration region 13 may have a width greater than 0 μm and less than or equal to 10 μm. The width of the low-concentration region 13 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the low-concentration region 13 is preferably less than or equal to 5 μm.

[0084] The low-concentration region 13 may have a depth of more than 0 μm and not more than 2 μm. The depth of the low-concentration region 13 is defined by the distance between the upper end of the low-concentration region 13 (the lower end of the second region 12) and the lower end of the low-concentration region 13 (the upper end of the first region 11). The depth of the low-concentration region 13 is preferably smaller than both the depth of the first region 11 and the depth of the second region 12.

[0085] The depth of the low concentration region 13 may have a value belonging to at least one of the ranges of more than 0 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0086] The low concentration region 13 forms a first concentration transition portion 14 at the intersection where the p-type impurity concentration gradually decreases from the first region 11 (see FIG. 4). The depth of the first concentration transition portion 14 may be less than the depth of the low concentration region 13. The depth of the first concentration transition portion 14 may be greater than the depth of the low concentration region 13.

[0087] The low concentration region 13 forms a second concentration transition portion 15 at the intersection where the p-type impurity concentration gradually increases toward the second region 12 (see FIG. 4). The depth of the second concentration transition portion 15 may be less than the depth of the low concentration region 13. The depth of the second concentration transition portion 15 may be greater than the depth of the low concentration region 13.

[0088] Below, first to third layout examples of the pillar region 10 according to Example 1 are shown. Figures 5A to 5C are plan views showing the first to third layout examples of the pillar region 10 according to Example 1. In Figures 5A to 5C, low-concentration regions 13 are indicated by dotted hatching.

[0089] 5A (first layout example), low-concentration region 13 may have a width approximately equal to that of first region 11. The width of low-concentration region 13 may be approximately equal to that of second region 12. The width of low-concentration region 13 may be larger or smaller than that of second region 12.

[0090] 5B (second layout example), the low-concentration region 13 may have a width greater than that of the first region 11. The width of the low-concentration region 13 may be approximately equal to the width of the second region 12. The width of the low-concentration region 13 may be greater or smaller than the width of the second region 12.

[0091] 5C (third layout example), low-concentration region 13 may have a width smaller than that of first region 11. The width of low-concentration region 13 may be approximately equal to the width of second region 12. The width of low-concentration region 13 may be larger or smaller than the width of second region 12.

[0092] The low-concentration region 13 may have the form shown in Fig. 6. Fig. 6 is a cross-sectional perspective view showing a main portion of the chip 2 together with the pillar region 10 according to the second example. Referring to Fig. 6, the pillar region 10 according to the second example includes a plurality of low-concentration regions 13 interposed at the intersections of a plurality of first regions 11 and a plurality of second regions 12, similar to the pillar region 10 according to the first example.

[0093] In this embodiment, the plurality of low-concentration regions 13 are arranged in the second layer 9. The plurality of low-concentration regions 13 need only be arranged at the intersections, and may extend to regions other than the intersections. In this embodiment, the plurality of low-concentration regions 13 are formed in the second layer 9 at the intersections and regions other than the intersections.

[0094] The plurality of low-concentration regions 13 are provided in a one-to-one correspondence with the plurality of second regions 12 in a region on the first layer 8 side relative to the plurality of second regions 12. The plurality of low-concentration regions 13 each extend in a strip shape in the second direction Y in a plan view and are formed at intervals in the first direction X. The plurality of low-concentration regions 13 extend in a stripe shape in the second direction Y and intersect (orthogonal to) the plurality of first regions 11.

[0095] In this embodiment, the plurality of low-concentration regions 13 have a length in the second direction Y extending from the first side surface 5A to the third side surface 5C, and are exposed from both the first side surface 5A and the third side surface 5C. The plurality of low-concentration regions 13 may be formed at intervals inward from either or both of the first side surface 5A and the third side surface 5C. The plurality of low-concentration regions 13 may be formed in a one-to-many correspondence with the corresponding second regions 12, and may be formed at intervals in the second direction Y following the extension direction of the corresponding second regions 12.

[0096] The plurality of low-concentration regions 13 have upper ends on the first main surface 3 side and lower ends on the second main surface 4 side (first layer 8 side). The upper ends are disposed in the second layer 9 and connected to corresponding second regions 12 in the second layer 9. In this embodiment, the lower ends cross the boundary between the first layer 8 and the second layer 9 and are located in the first layer 8. The lower ends are connected to corresponding first regions 11 in the first layer 8.

[0097] As a result, the plurality of low concentration regions 13 electrically connect the corresponding first region 11 to the corresponding second region 12. When the first region 11 has an upper end located in the second layer 9, the lower end may be connected to the first region 11 within the second layer 9.

[0098] Below, first to third layout examples of the pillar region 10 according to Example 2 are shown. Figures 7A to 7C are plan views showing the first to third layout examples of the pillar region 10 according to Example 2. In Figures 7A to 7C, the low-concentration regions 13 are indicated by dotted hatching.

[0099] 7A (first layout example), low-concentration region 13 may have a width approximately equal to that of second region 12. The width of low-concentration region 13 may be approximately equal to that of first region 11. The width of low-concentration region 13 may be larger or smaller than the width of first region 11.

[0100] 7B (second layout example), the low-concentration region 13 may have a width greater than that of the second region 12. The width of the low-concentration region 13 may be approximately equal to the width of the first region 11. The width of the low-concentration region 13 may be greater or smaller than the width of the first region 11.

[0101] 7C (third layout example), low-concentration region 13 may have a width smaller than that of second region 12. The width of low-concentration region 13 may be approximately equal to the width of first region 11. The width of low-concentration region 13 may be larger or smaller than the width of first region 11.

[0102] The low-concentration region 13 may have the form shown in Fig. 8. Fig. 8 is a cross-sectional perspective view showing a main portion of the chip 2 together with a pillar region 10 according to a third example. Referring to Fig. 8, the pillar region 10 according to the third example includes a plurality of low-concentration regions 13 interposed at the intersections of a plurality of first regions 11 and a plurality of second regions 12, similar to the pillar region 10 according to the first example.

[0103] In this embodiment, the plurality of low-concentration regions 13 are provided at intervals in the first layer 8 in a one-to-one correspondence with the plurality of intersections. Each of the plurality of low-concentration regions 13 may have a side extending in a first direction X following the extension direction of the first region 11 and a side extending in a second direction Y following the extension direction of the second region 12. In this embodiment, the plurality of low-concentration regions 13 are formed in a polygonal (quadrilateral) shape in a plan view. The plurality of low-concentration regions 13 may also be formed in a circular shape in a plan view.

[0104] The plurality of low-concentration regions 13 have upper ends on the first principal surface 3 side (the second layer 9 side) and lower ends on the second principal surface 4 side (the base layer 6 side). In this embodiment, the upper ends are connected to corresponding second regions 12 in the first layer 8. The upper ends may cross the boundary between the first layer 8 and the second layer 9 and be connected to the second regions 12 in the second layer 9.

[0105] The lower ends are connected to corresponding first regions 11 in the first layer 8. As a result, the plurality of low concentration regions 13 electrically connect the corresponding first regions 11 to the corresponding second regions 12. The lower ends are preferably formed at a distance from the depth position of the middle part of the first layer 8 toward the upper end of the first layer 8.

[0106] Below, first to third layout examples of the pillar region 10 according to the third example are shown. Figures 9A to 9C are plan views showing the first to third layout examples of the pillar region 10 according to the third example. In Figures 9A to 9C, the low-concentration regions 13 are indicated by dotted hatching.

[0107] Referring to FIG. 9A (first layout example), low-concentration region 13 may have a planar area substantially equal to the planar area of ​​the corresponding intersection.

[0108] 9B (first layout example), low-concentration regions 13 may have a planar area larger than the planar area of ​​the corresponding intersections. That is, low-concentration regions 13 may be formed at the corresponding intersections and around the corresponding intersections.

[0109] A part of the periphery of the low-concentration region 13 may extend from the intersection to the outside in the first direction X, following the example of the first region 11. Furthermore, a part of the periphery of the low-concentration region 13 may extend from the intersection to the outside in the second direction Y, following the example of the second region 12. The periphery of the low-concentration region 13 may surround the periphery of the corresponding intersection in a plan view.

[0110] 9B (first layout example), low-concentration region 13 may have a planar area smaller than the planar area of ​​the corresponding intersection. In this case, low-concentration region 13 may be surrounded by the periphery of the corresponding intersection in a plan view.

[0111] A part of the periphery of the low-concentration region 13 may extend from the intersection portion to the outside in the first direction X, following the example of the first region 11. Furthermore, a part of the periphery of the low-concentration region 13 may extend from the intersection portion to the outside in the second direction Y, following the example of the second region 12.

[0112] The low-concentration region 13 may have the form shown in Fig. 10. Fig. 10 is a cross-sectional perspective view showing a main portion of the chip 2 together with the pillar region 10 according to the fourth example. Referring to Fig. 10, the pillar region 10 according to the fourth example includes a plurality of low-concentration regions 13 interposed at the intersections of a plurality of first regions 11 and a plurality of second regions 12, similar to the pillar region 10 according to the first example.

[0113] In this embodiment, the plurality of low-concentration regions 13 are provided at intervals in the second layer 9 in a one-to-one correspondence with the plurality of intersections. Each of the plurality of low-concentration regions 13 may have a side extending in a first direction X following the extension direction of the first region 11 and a side extending in a second direction Y following the extension direction of the second region 12. In this embodiment, the plurality of low-concentration regions 13 are formed in a polygonal (quadrilateral) shape in a plan view. The plurality of low-concentration regions 13 may also be formed in a circular shape in a plan view.

[0114] The plurality of low-concentration regions 13 have upper ends on the first principal surface 3 side (the second layer 9 side) and lower ends on the second principal surface 4 side (the first layer 8 side). The upper ends are connected to corresponding second regions 12 in the second layer 9. In this embodiment, the lower ends cross the boundary between the first layer 8 and the second layer 9 and are connected to corresponding first regions 11 in the first layer 8.

[0115] As a result, the plurality of low concentration regions 13 electrically connect the corresponding first region 11 to the corresponding second region 12. When the first region 11 has an upper end located in the second layer 9, the lower end may be connected to the first region 11 within the second layer 9.

[0116] The low-concentration region 13 according to the fourth example may have the first to third layout examples shown in FIGS. 9A to 9C, similar to the low-concentration region 13 according to the third example.

[0117] The low-concentration region 13 may have the form shown in Fig. 11. Fig. 11 is a cross-sectional perspective view showing a main portion of the chip 2 together with a pillar region 10 according to a fifth example. The pillar region 10 according to the fifth example, like the pillar region 10 according to the first example, includes a plurality of low-concentration regions 13 interposed at the intersections of a plurality of first regions 11 and a plurality of second regions 12. In this form, the plurality of low-concentration regions 13 include a plurality of first low-concentration regions 13A and a plurality of second low-concentration regions 13B.

[0118] The plurality of first low-concentration regions 13A are respectively interposed at the intersections of the plurality of first regions 11 and the plurality of second regions 12. The plurality of first low-concentration regions 13A only need to be disposed at least at the intersections, and may extend to regions other than the intersections. The plurality of first low-concentration regions 13A are disposed in the first layer 8 at the intersections, and are formed at the intersections and regions other than the intersections.

[0119] The plurality of first low-concentration regions 13A are provided in a one-to-one correspondence with the plurality of first regions 11 in a region on the second layer 9 side relative to the plurality of first regions 11. The plurality of first low-concentration regions 13A each extend in a strip shape in the first direction X in a plan view and are formed at intervals in the second direction Y. The plurality of first low-concentration regions 13A extend in stripes in the first direction X and intersect (are perpendicular to) the plurality of second regions 12.

[0120] In this embodiment, the multiple first low-concentration regions 13A have a length in the first direction X that extends from the second side surface 5B to the fourth side surface 5D, and are exposed from both the second side surface 5B and the fourth side surface 5D. The multiple first low-concentration regions 13A may be formed at intervals inward from either or both of the second side surface 5B and the fourth side surface 5D. The multiple first low-concentration regions 13A may be formed in a one-to-many correspondence with the corresponding first regions 11, and may be formed at intervals in the first direction X following the extension direction of the corresponding first regions 11.

[0121] The plurality of first low-concentration regions 13A have upper ends on the first main surface 3 side (second layer 9 side) and lower ends on the second main surface 4 side (first layer 8 side). The upper ends may be disposed in the first layer 8 or the second layer 9. The lower ends are located within the first layer 8 and connected to corresponding first regions 11 within the first layer 8.

[0122] In this way, the plurality of first low-concentration regions 13A have a layout similar to that of the low-concentration region 13 according to the first example (see FIG. 3). The first low-concentration region 13A may have the first to third layout examples shown in FIGS. 5A to 5C. The plurality of first low-concentration regions 13A may have a layout similar to that of the low-concentration region 13 according to the third example (see FIG. 8).

[0123] The plurality of second low-concentration regions 13B are respectively interposed at intersections of the plurality of first low-concentration regions 13A (the plurality of first regions 11) and the plurality of second regions 12. The plurality of second low-concentration regions 13B only need to be disposed at least at the intersections, and may extend to regions other than the intersections. The plurality of second low-concentration regions 13B are disposed in the second layer 9 at the intersections, and are formed at the intersections and regions other than the intersections.

[0124] The second low-concentration regions 13B are provided in a one-to-one correspondence with the second regions 12 in a region on the first layer 8 side of the second regions 12. The second low-concentration regions 13B each extend in a strip shape in the second direction Y in a plan view and are formed at intervals in the first direction X. The second low-concentration regions 13B extend in stripes in the second direction Y and intersect (are perpendicular to) the first regions 11 and the first low-concentration regions 13A.

[0125] In this embodiment, the multiple second low-concentration regions 13B have a length in the second direction Y that extends from the first side surface 5A to the third side surface 5C, and are exposed from both the first side surface 5A and the third side surface 5C. The multiple second low-concentration regions 13B may be formed at intervals inward from either or both of the first side surface 5A and the third side surface 5C. The multiple second low-concentration regions 13B may be formed in a one-to-many correspondence with the corresponding second regions 12, and may be formed at intervals in the second direction Y following the extension direction of the corresponding second regions 12.

[0126] The second low-concentration regions 13B have upper ends on the first main surface 3 side (the second layer 9 side) and lower ends on the second main surface 4 side (the first layer 8 side). The upper ends are connected to corresponding second regions 12 in the second layer 9. In this embodiment, the lower ends cross the boundary between the first layer 8 and the second layer 9 and are connected to corresponding first low-concentration regions 13A in the first layer 8.

[0127] When the first low-concentration region 13A has an upper end located within the second layer 9, the lower end may be connected to the first low-concentration region 13A within the second layer 9. In this way, the plurality of low-concentration regions 13 electrically connects the plurality of first regions 11 to the plurality of second regions 12 via the plurality of first low-concentration regions 13A and the plurality of second low-concentration regions 13B.

[0128] In this way, the plurality of second low-concentration regions 13B have a layout similar to that of the low-concentration region 13 according to the second example (see FIG. 6). The second low-concentration region 13B may have the first to third layout examples shown in FIGS. 7A to 7C. The plurality of second low-concentration regions 13B may have a layout similar to that of the low-concentration region 13 according to the fourth example (see FIG. 10).

[0129] The pillar regions 10 according to the first to fifth examples may have the configurations shown in Fig. 12 and Fig. 13. Fig. 12 is a cross-sectional perspective view showing a first modified example applied to the pillar regions 10 according to the first to fifth examples. Fig. 13 is a cross-sectional perspective view showing a second modified example applied to the pillar regions 10 according to the first to fifth examples.

[0130] 12 (first modification), the plurality of first regions 11 may each include a plurality of p-type first impurity regions 16 arranged in a pillar shape in the thickness direction. The plurality of first impurity regions 16 are arranged so as to be connected to each other in the thickness direction. The number of first impurity regions 16 may be 2 or more and 10 or less. The number of first impurity regions 16 may be 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0131] Similarly, the multiple second regions 12 may each include multiple p-type second impurity regions 17 arranged in a pillar shape in the thickness direction. The multiple second impurity regions 17 are arranged so as to be connected to each other in the thickness direction. The number of second impurity regions 17 may be 2 or more and 10 or less. The number of second impurity regions 17 may be 2, 3, 4, 5, 6, 7, 8, 9, or 10. The number of second impurity regions 17 may be the same as or different from the number of first impurity regions 16.

[0132] In this embodiment, the plurality of low-concentration regions 13 are respectively interposed in regions between the plurality of first impurity regions 16 and the plurality of second impurity regions 17. Similar to the low-concentration regions 13 in the first example (see FIG. 3), the plurality of low-concentration regions 13 are arranged in the first layer 8 and are connected to the corresponding first impurity regions 16 and the corresponding second impurity regions 17, respectively.

[0133] In this case, the plurality of low-concentration regions 13 may have the first to third layout examples shown in Figures 5A to 5C. Of course, the plurality of low-concentration regions 13 may have a layout similar to that of the low-concentration region 13 according to the third example (see Figure 8).

[0134] The multiple low concentration regions 13 may be arranged in the second layer 9, similar to the low concentration regions 13 in the second example (see Figure 6), and may be connected to corresponding first impurity regions 16 and corresponding second impurity regions 17, respectively.

[0135] In this case, the plurality of low-concentration regions 13 may have the first to third layout examples shown in Figures 7A to 7C. Of course, the plurality of second low-concentration regions 13B may have the same layout as the low-concentration region 13 according to the fourth example (see Figure 10).

[0136] In this embodiment, an example has been shown in which the plurality of first regions 11 include a plurality of first impurity regions 16, and the plurality of second regions 12 include a plurality of second impurity regions 17. However, either the plurality of first regions 11 or the plurality of second regions 12 may be formed by a single impurity region.

[0137] 13 (second modified example), the semiconductor device 1A includes a plurality of first trench structures 20 formed in the semiconductor layer 7. The plurality of first trench structures 20 are structures that partition formation areas of a plurality of first regions 11. The plurality of first trench structures 20 are formed in the semiconductor layer 7 at intervals in the thickness direction from the first main surface 3. Specifically, the plurality of first trench structures 20 extend in strip shapes in the first direction X at the upper end of the first layer 8 and are formed at intervals in the second direction Y.

[0138] The multiple first trench structures 20 are formed at intervals in the thickness direction from the lower end (base layer 6) of the first layer 8, and face the base layer 6 across a part of the first layer 8. The multiple first trench structures 20 may cross the boundary between the base layer 6 and the first layer 8 and have a part located in the base layer 6. The spacing, width and depth of the multiple first trench structures 20 correspond to the spacing, width and depth of the multiple first regions 11 described above, respectively.

[0139] The plurality of first trench structures 20 include a first trench 21 and a non-insulating first filling material 22. The first trench 21 is dug from the upper end of the first layer 8 toward the lower end of the first layer 8, and has sidewalls and a bottom wall that expose the first layer 8. The bottom wall of the first trench 21 may be located within the base layer 6, exposing the base layer 6.

[0140] The first embedded object 22 includes either or both of a semiconductor single crystal and a semiconductor polycrystal. The first embedded object 22 may include at least one of a Si single crystal, a Si polycrystal, a SiC single crystal, and a SiC polycrystal. In this embodiment, the first embedded object 22 includes a SiC single crystal.

[0141] The first filling material 22 is buried directly in the first trench 21 and contacts the first layer 8 within the first trench 21. The first filling material 22 may have a flat upper end that forms a single flat surface together with the upper end of the first layer 8. When the first trench 21 exposes the base layer 6, the first filling material 22 contacts the base layer 6 and the first layer 8 within the first trench 21.

[0142] The first filling material 22 may be integrated with the first layer 8. The first filling material 22 may be an epitaxial layer grown on the first layer 8 starting from the wall surface of the first trench 21. The first filling material 22 may include a portion grown starting from the base layer 6.

[0143] The semiconductor device 1A includes a plurality of second trench structures 23 formed in the semiconductor layer 7. The plurality of trench structures are structures that partition formation areas of a plurality of second regions 12. The plurality of second trench structures 23 are formed in a region on the first main surface 3 side with respect to the plurality of first trench structures 20. Specifically, the plurality of second trench structures 23 extend in strip shapes in the second direction Y at the upper end portion (first main surface 3) of the second layer 9 and are formed at intervals in the first direction X.

[0144] The plurality of second trench structures 23 penetrate the second layer 9 to expose the first layer 8 and the plurality of first trench structures 20. The spacing, width, and depth of the plurality of second trench structures 23 correspond to the spacing, width, and depth of the plurality of second regions 12 described above, respectively.

[0145] The plurality of second trench structures 23 includes a second trench 24 and a non-insulating second filling material 25. The second trench 24 is dug down from the upper end (first main surface 3) of the second layer 9 toward the lower end of the second layer 9. The second trench 24 has sidewalls that expose the second layer 9 and a bottom wall that exposes the first layer 8 and the plurality of first trench structures 20.

[0146] The second buried material 25 includes either or both of a semiconductor single crystal and a semiconductor polycrystal. The second buried material 25 may include at least one of a Si single crystal, a Si polycrystal, a SiC single crystal, and a SiC polycrystal. In this embodiment, the second buried material 25 includes a SiC single crystal.

[0147] The second filling material 25 is buried directly in the second trench 24, contacts the second layer 9 on the sidewall of the second trench 24, and contacts the second layer 9 and the plurality of first trench structures 20 on the bottom wall of the second trench 24. The second filling material 25 may have a flat upper end portion that forms a single flat surface together with the upper end portion of the second layer 9.

[0148] The second filling material 25 may be integrated with the first layer 8 and the second layer 9. The second filling material 25 may be an epitaxial layer grown from the first layer 8 and the second layer 9, starting from the wall surface of the second trench 24. The second filling material 25 may include a portion grown from the first filling material 22.

[0149] In this embodiment, the plurality of first regions 11 are formed in the plurality of first trench structures 20, respectively. Specifically, the plurality of first regions 11 are formed in the plurality of first filled objects 22, respectively. That is, the plurality of first regions 11 are each formed from a region in which the first filled object 22 is imparted with p-type conductivity by a trivalent element. The plurality of first regions 11 may have a uniform p-type impurity concentration. The plurality of first regions 11 may have a concentration gradient that gradually decreases from the opening side of the first trench 21 toward the bottom wall side.

[0150] The plurality of first regions 11 form first pn junctions with the first layer 8 via the sidewalls and bottom walls of the corresponding first trenches 21. When the base layer 6 is exposed from the bottom walls of the first trenches 21, the plurality of first regions 11 may be electrically connected to the base layer 6 at the bottom walls of the corresponding first trenches 21. The plurality of first regions 11 are formed at intervals from the upper ends of the corresponding first filled objects 22 toward the bottom wall of the first trenches 21.

[0151] In this embodiment, the plurality of second regions 12 are formed in the plurality of second trench structures 23, respectively. Specifically, the plurality of second regions 12 are formed in the plurality of second filled objects 25, respectively. That is, the plurality of second regions 12 are each formed from a region in which the second filled object 25 is imparted with p-type conductivity by a trivalent element. The plurality of second regions 12 may have a uniform p-type impurity concentration. The plurality of second regions 12 may have a concentration gradient that gradually decreases from the opening side of the second trench 24 toward the bottom wall side.

[0152] The second regions 12 form second pn junctions with the first layer 8 and the second layer 9 via the sidewalls and bottom walls of the corresponding second trenches 24. The second regions 12 are electrically connected to the first filled objects 22 (the first regions 11) via the bottom walls of the corresponding second trenches 24. The second regions 12 may be formed over the entire area of ​​the second filled objects 25. The second regions 12 may be formed at intervals from the upper ends of the second filled objects 25 toward the bottom wall of the second trenches 24.

[0153] In this embodiment, the plurality of low concentration regions 13 are formed in the plurality of first trench structures 20, respectively. Specifically, the plurality of low concentration regions 13 are formed in the corresponding first buried objects 22, respectively. That is, the plurality of low concentration regions 13 are each made of a region in which the first buried object 22 is given p-type conductivity by a trivalent element.

[0154] The plurality of low-concentration regions 13 are formed in the upper end portions of the plurality of first buried objects 22. The plurality of low-concentration regions 13 may be formed at intervals from the depth position of the intermediate portion of the corresponding first trench 21 to the opening side of the corresponding first trench 21. The plurality of low-concentration regions 13 have upper ends on the first main surface 3 side and lower ends on the second main surface 4 side.

[0155] The upper ends are electrically connected to the second regions 12 within the first trenches 21. The lower ends are electrically connected to the first regions 11 within the first trenches 21. As a result, the multiple first regions 11 electrically connect the corresponding first regions 11 to the corresponding second regions 12 within the corresponding first trenches 21.

[0156] The plurality of low-concentration regions 13 may be formed in the plurality of second trench structures 23, respectively. That is, the plurality of low-concentration regions 13 may be formed in the corresponding second buried objects 25, respectively. In this case, the plurality of low-concentration regions 13 are each made of a region in which the second buried object 25 is imparted with p-type conductivity by a trivalent element.

[0157] The plurality of low-concentration regions 13 may be formed at the lower end of the corresponding second buried object 25. The plurality of low-concentration regions 13 may be formed at intervals from a depth position of the intermediate portion of the corresponding second trench 24 toward the bottom wall of the corresponding second trench 24. The plurality of low-concentration regions 13 may have an upper end on the first main surface 3 side and a lower end on the second main surface 4 side.

[0158] The upper ends may be electrically connected to the second regions 12 in the second trenches 24. The lower ends may be electrically connected to the first regions 11 in the second trenches 24. In this way, the plurality of low concentration regions 13 electrically connects the corresponding first regions 11 to the corresponding second regions 12 in the corresponding second trenches 24.

[0159] In this embodiment, an example has been shown in which a plurality of first regions 11 are formed in a plurality of first trench structures 20, and a plurality of second regions 12 are formed in a plurality of second trench structures 23. However, a configuration in which either a plurality of first trench structures 20 or a plurality of second trench structures 23 is not formed may also be employed.

[0160] That is, a plurality of first regions 11 may be formed in the first layer 8, while a plurality of second regions 12 may be formed in the second trench structures 23. Alternatively, a plurality of first regions 11 may be formed in the first trench structures 20, while a plurality of second regions 12 may be formed in the second layer 9.

[0161] The configuration in which a plurality of first regions 11 are formed in a plurality of first trench structures 20 can be combined with all of the configurations described above (see FIGS. 1 to 12). Also, the configuration in which a plurality of second regions 12 are formed in a plurality of second trench structures 23 can be combined with all of the configurations described above (see FIGS. 1 to 12).

[0162] As described above, the semiconductor device 1A may include an n-type semiconductor layer 7, a p-type first region 11, a p-type second region 12, and a p-type low-concentration region 13. The semiconductor layer 7 may have a first main surface 3. The first region 11 may extend in the semiconductor layer 7 in a first direction X along the first main surface 3. The second region 12 may be formed in a region of the semiconductor layer 7 on the first main surface 3 side relative to the first region 11.

[0163] The second region 12 may extend in the second direction Y along the first main surface 3 so as to intersect the first region 11 in a three-dimensional manner. The low concentration region 13 may be formed in the semiconductor layer 7 at least at the intersection of the first region 11 and the second region 12. The low concentration region 13 may have a concentration lower than both the maximum concentration value of the first region 11 and the maximum concentration value of the second region 12.

[0164] This configuration provides a novel semiconductor device 1A. For example, in this semiconductor device 1A, high concentration at the intersection of first region 11 and second region 12 is suppressed by low concentration region 13, and electric field concentration at the intersection is alleviated by low concentration region 13. This improves the breakdown voltage and thus electrical reliability.

[0165] The semiconductor layer 7 may contain SiC. This configuration provides the semiconductor device 1A as a novel SiC semiconductor device. The semiconductor device 1A appropriately improves electrical characteristics due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in a relatively high voltage environment, the electric field relaxation effect of the low concentration region 13 is effective in improving electrical characteristics.

[0166] The SiC may be a hexagonal crystal. The first direction X may be one of the a-axis direction and the m-axis direction of SiC. The second direction Y may be the other of the a-axis direction and the m-axis direction of SiC. The first direction X may be a direction intersecting both the a-axis direction and the m-axis direction. The second direction Y may be a direction intersecting both the a-axis direction and the m-axis direction. The semiconductor layer 7 may have an off-angle. The second direction Y may be perpendicular to the first direction X.

[0167] The concentration of the low-concentration region 13 may be lower than both the concentration at the intermediate depth position of the first region 11 and the concentration at the intermediate depth position of the second region 12. According to this configuration, the low-concentration region 13 appropriately suppresses high concentration at the intersection.

[0168] The low-concentration region 13 may form a first concentration transition portion 14 in which the concentration gradually decreases from the first region 11 at the intersection. With this configuration, the low-concentration region 13 appropriately suppresses the increase in concentration at the intersection due to the concentration of the first region 11. The low-concentration region 13 may form a second concentration transition portion 15 in which the concentration gradually increases toward the second region 12. With this configuration, the low-concentration region 13 appropriately suppresses the increase in concentration at the intersection due to the concentration of the second region 12.

[0169] The low-concentration regions 13 may also be formed in regions other than the intersections. With this configuration, the low-concentration regions 13 appropriately overlap the intersections. This provides the low-concentration regions 13 that are resistant to misalignment with respect to the intersections.

[0170] The low-concentration region 13 may have a portion extending in the first direction X following the first region 11. With this configuration, the low-concentration region 13 extending following the first region 11 appropriately suppresses an increase in concentration at the intersection. The low-concentration region 13 may have a portion extending in the second direction Y following the second region 12. With this configuration, the low-concentration region 13 extending following the second region 12 appropriately suppresses an increase in concentration at the intersection.

[0171] The first region 11 may extend vertically in the thickness direction of the semiconductor layer 7. The second region 12 may extend vertically in the thickness direction of the semiconductor layer 7. The first region 11 may have a width of 10 μm or less. The second region 12 may have a width of 10 μm or less.

[0172] The plurality of first regions 11 may be formed in stripes extending in the first direction X. The plurality of second regions 12 may be formed in stripes extending in the second direction Y so as to intersect with the plurality of first regions 11. The plurality of low concentration regions 13 may be formed at the plurality of intersections.

[0173] The plurality of first regions 11 may form a first superjunction structure SJ1 together with the semiconductor layer 7. In this case, electric field concentration on the first superjunction structure SJ1 is alleviated by the low concentration region 13. This improves the electrical characteristics of the first superjunction structure SJ1.

[0174] The plurality of second regions 12 may form a second superjunction structure SJ2 together with the semiconductor layer 7. In this case, electric field concentration on the second superjunction structure SJ2 is alleviated by the low concentration region 13. This improves the electrical characteristics of the second superjunction structure SJ2.

[0175] Fig. 14 is a plan view showing a semiconductor device 1B according to a second embodiment. Fig. 15 is a plan view showing an example layout of a first main surface 3. Fig. 16 is an enlarged plan view showing a main portion of an active region 30. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 16. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 16. Fig. 19 is a cross-sectional perspective view showing a main portion of the active region 30 together with pillar regions 10 according to a first example.

[0176] 14 to 19, a semiconductor device 1B is a semiconductor switching device having an insulated gate transistor structure as an example of a device structure (functional device). The transistor structure has a trench gate vertical structure.

[0177] The semiconductor device 1B has, as a basic configuration, the chip 2 and pillar region 10 according to the semiconductor device 1A. In this configuration, the semiconductor device 1B has the pillar region 10 according to the first embodiment example (see FIGS. 3 and 5A to 5C).

[0178] The semiconductor device 1B may have any one of the pillar regions 10 according to the second to fifth embodiments (see FIGS. 6 to 10). The semiconductor device 1B may also have the pillar region 10 according to the first modified example (see FIG. 11) or the pillar region 10 according to the second modified example (see FIG. 12).

[0179] The semiconductor device 1B includes an active region 30 set on the first main surface 3. The active region 30 includes a device structure (transistor structure) and is a region where an output current (drain current) is generated. The active region 30 is set in an inner portion of the first main surface 3 and spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active region 30 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0180] The ratio (area ratio) of the planar area of ​​the active region 30 to the planar area of ​​the first main surface 3 may be equal to or greater than 0.5 and less than 1. The area ratio may have a value belonging to at least one of the ranges of 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, 0.8 to 0.9, 0.9 to 0.95, and 0.95 to less than 1.

[0181] The semiconductor device 1B includes an outer region 31 set outside the active region 30 on the first main surface 3. The outer region 31 is a region that does not include a device structure (transistor structure). The outer region 31 is set in the peripheral portion of the first main surface 3. The outer region 31 is provided in a region between the peripheral edge of the first main surface 3 and the active region 30. The outer region 31 extends in a strip shape along the active region 30 in a planar view, and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 30.

[0182] The semiconductor device 1B includes a p-type body region 32 formed in a surface layer portion of the first main surface 3 in the active region 30. A source potential may be applied to the body region 32. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0183] The body region 32 may have a p-type impurity concentration higher than the p-type impurity concentration of the first region 11 (second region 12). The p-type impurity concentration of the body region 32 may be lower than the p-type impurity concentration of the first region 11 (second region 12).

[0184] The body region 32 is formed in the active region 30 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer region 31. In this embodiment, the body region 32 is formed throughout the active region 30. The body region 32 is formed in a surface layer portion of the second layer 9 and extends in a layered form along the first main surface 3. The body region 32 may be connected to a plurality of second regions 12. In this case, the p-type impurity concentration of the body region 32 is increased by the plurality of second regions 12.

[0185] The body region 32 is formed at a distance from the lower end (first layer 8) of the second layer 9 toward the first main surface 3, and has a portion facing the first layer 8 and the plurality of first regions 11 with part of the second layer 9 in between. The body region 32 is formed at a distance from the lower end of the second region 12 toward the first main surface 3. The body region 32 may be formed at a distance from a depth position of an intermediate portion of the second layer 9 toward the first main surface 3. The body region 32 may have a portion located on the first layer 8 side with respect to the depth position of the intermediate portion of the second layer 9.

[0186] The semiconductor device 1B includes a plurality of trench-type (trench electrode-type) gate structures 35 formed in an inner portion of the first main surface 3. The gate structures 35 may also be referred to as "first trench structures," "trench gate structures," etc. A gate potential (gate signal) is applied to the plurality of gate structures 35 as a control potential.

[0187] The multiple gate structures 35 are formed in the active region 30 at intervals from the periphery of the first main surface 3, and are not formed in the outer region 31. In this embodiment, the multiple gate structures 35 each extend in a strip shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. The multiple gate structures 35 are arranged in stripes extending in the first direction X.

[0188] In this embodiment, the plurality of gate structures 35 extend in the same direction as the plurality of first regions 11, but in a direction different from the direction in which the plurality of second regions 12 extend. The plurality of gate structures 35 intersect (specifically, orthogonally intersect) with the plurality of second regions 12. This layout is effective in relaxing the restrictions on the design rules for the plurality of gate structures 35 relative to the plurality of second regions 12.

[0189] In this embodiment, the plurality of gate structures 35 are arranged at intervals approximately equal to the intervals between the plurality of first regions 11, and overlap with the plurality of first regions 11 in a one-to-one correspondence in the stacking direction. The intervals between the plurality of gate structures 35 may be different from the intervals between the plurality of first regions 11.

[0190] In this case, the multiple gate structures 35 may include gate structures 35 that face the first regions 11 in the stacking direction and gate structures 35 that do not face the first regions 11 in the stacking direction. All of the gate structures 35 may face regions between the multiple first regions 11 in the stacking direction (i.e., first layers 8).

[0191] The spacing between the multiple gate structures 35 may be greater than 0 μm and less than or equal to 10 μm. The spacing between the gate structures 35 may be less than the width of the gate structures 35. The spacing between the gate structures 35 may be greater than the width of the gate. The spacing between the gate structures 35 may be approximately equal to the spacing between the second regions 12. The spacing between the gate structures 35 may be greater or smaller than the spacing between the second regions 12.

[0192] The spacing between the gate structures 35 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0193] The plurality of gate structures 35 penetrate the body region 32. Each of the plurality of gate structures 35 has a sidewall and a bottom wall connected to the plurality of second regions 12. The plurality of gate structures 35 are formed at intervals from the bottom of the second layer 9 toward the first main surface 3, and face the first layer 8 with portions of the second layer 9 interposed therebetween. The plurality of gate structures 35 are formed at intervals from the lower ends of the plurality of second regions 12 toward the first main surface 3, and face the first layer 8 with portions of the plurality of second regions 12 interposed therebetween.

[0194] The plurality of gate structures 35 are formed substantially perpendicular to the first main surface 3. The plurality of gate structures 35 may be formed in a tapered shape toward the bottom of the second layer 9. The side walls (long sides) of the plurality of gate structures 35 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the plurality of gate structures 35 may be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 35.

[0195] The side walls of the gate structures 35, together with the first main surface 3, define an open end curved in an arc (circular arc). The bottom walls of the gate structures 35 are formed by the c-plane (Si plane) of the SiC single crystal. The bottom walls of the gate structures 35 preferably extend substantially flat in the horizontal direction. The bottom walls of the gate structures 35 may be curved in an arc toward the second main surface 4.

[0196] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 35 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0197] The gate structure 35 may have a width greater than 0 μm and less than or equal to 10 μm. The width of the gate structure 35 may be less than the thickness of the second layer 9. The width of the gate structure 35 may be greater than the thickness of the second layer 9. The width of the gate structure 35 may be approximately equal to the width of the second region 12. The width of the gate structure 35 may be greater or smaller than the width of the second region 12. The width of the gate structure 35 may be approximately equal to the width of the first region 11. The width of the gate structure 35 may be greater or smaller than the width of the first region 11.

[0198] The width of the gate structure 35 may be in at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the gate structure 35 is preferably less than or equal to 5 μm.

[0199] The gate structure 35 may have a depth greater than 0 μm and less than or equal to 3 μm. The depth of the gate structure 35 is less than the thickness of the second layer 9. The depth of the gate structure 35 is less than the depth of the second region 12. The depth of the gate structure 35 is less than the depth of the first region 11. The depth of the gate structure 35 may be greater or less than the depth of the first region 11.

[0200] The depth of the gate structure 35 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, 2.25 μm to 2.5 μm, 2.5 μm to 2.75 μm, and 2.75 μm to 3 μm.

[0201] The gate structure 35 may have an aspect ratio of 1 to 3, inclusive. The aspect ratio of the gate structure 35 is the ratio of the depth of the gate structure 35 to the width of the gate structure 35. The aspect ratio may have a value belonging to at least one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3, inclusive.

[0202] Each of the plurality of gate structures 35 includes a gate trench 36, an insulating film 37, a buried electrode 38, and a buried insulator 39. The gate trench 36 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the gate structure 35.

[0203] The insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 37 may include a silicon oxide film containing an oxide of the chip 2 (second layer 9). The insulating film 37 may include a silicon oxide film containing an oxide other than the oxide of the chip 2.

[0204] The insulating film 37 covers the wall surface of the gate trench 36. In this embodiment, the insulating film 37 has an upper end located on the bottom wall side of the gate trench 36 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the gate trench 36.

[0205] The upper end of the insulating film 37 is preferably located closer to the opening of the gate trench 36 than the depth position of the intermediate portion of the gate trench 36. The thickness of the portion of the insulating film 37 covering the sidewall of the gate trench 36 may be greater than the thickness of the portion of the insulating film 37 covering the bottom wall of the gate trench 36.

[0206] The thickness of the insulating film 37 may be 10 nm or more and 250 nm or less. The thickness of the insulating film 37 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0207] The buried electrode 38 includes either or both of a metal and a non-metal conductor. The buried electrode 38 may include conductive polysilicon, which is an example of a non-metal conductor. In this case, the buried electrode 38 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 38 is preferably made of n-type conductive polysilicon.

[0208] The buried electrode 38 is buried in the gate trench 36 via the insulating film 37, and faces the second layer 9, the plurality of second regions 12, and the body region 32 via the insulating film 37. The buried electrode 38 has an electrode surface exposed from the gate trench 36. The electrode surface is formed at a distance from the height position of the first main surface 3 to the bottom wall side of the gate trench 36.

[0209] The electrode surface is located closer to the first main surface 3 than the depth position of the intermediate portion of the gate trench 36. The electrode surface may be located closer to the bottom wall of the gate trench 36 than the depth position of the intermediate portion of the gate trench 36. The electrode surface may have a recess recessed toward the bottom wall of the gate trench 36.

[0210] The buried insulator 39 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 39 may include an insulating material that is different from or the same as the insulating material of the insulating film 37. In this form, the buried insulator 39 includes a silicon oxide film having properties different from the properties of the insulating film 37.

[0211] The buried insulator 39 may have a single-layer structure or a multilayer structure including at least one of an NSG film (nondoped silicate glass film), a PSG film (phosphorus silicon glass film), and a BPSG film (boron phosphorus silicon glass film). The NSG film is a silicon oxide film without added impurities, the PSG film is a silicon oxide film containing phosphorus, and the BPSG film is a silicon oxide film containing both phosphorus and boron.

[0212] The buried insulator 39 preferably has a single-layer structure or a multilayer structure including at least an NSG film. The buried insulator 39 may have a multilayer structure including an NSG film and a PSG film stacked in this order from the chip 2 side. The buried insulator 39 may have a multilayer structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side. The buried insulator 39 may have a single-layer structure or a multilayer structure including a silicon oxide film containing an oxide of the buried electrode 38.

[0213] The buried insulator 39 covers the buried electrode 38 in the gate trench 36. In this embodiment, the buried insulator 39 is buried in the gate trench 36 via the insulating film 37, and is in contact with the insulating film 37 and the buried electrode 38 in the gate trench 36. In other words, the buried insulator 39 has a portion that faces the chip 2 in the horizontal direction with the insulating film 37 interposed therebetween.

[0214] The buried insulator 39 has an insulating surface exposed from the gate trench 36. The insulating surface is formed at a distance from the height position of the first main surface 3 to the bottom wall side of the gate trench 36, and exposes a part of the chip 2 from the opening end of the gate trench 36. The insulating surface is located on the opening side of the gate trench 36 with respect to the depth position of the intermediate portion of the gate trench 36. The insulating surface may also be located on the bottom wall side of the gate trench 36 with respect to the depth position of the intermediate portion of the gate trench 36.

[0215] The insulating surface exposes the upper end of the insulating film 37. In this embodiment, the insulating surface is flat and continuous with the upper end of the insulating film 37. That is, the insulating surface is formed flush with the upper end of the insulating film 37. The insulating surface may be located closer to the first main surface 3 or closer to the bottom wall of the gate trench 36 than the upper end of the insulating film 37.

[0216] The insulating surface may be formed flush with the first main surface 3, together with the upper end of the insulating film 37. The buried insulator 39 may cover the upper end of the insulating film 37 and be in direct contact with the chip 2 on the sidewall of the gate trench 36. In this form, the insulating surface has a recessed portion that sinks from the sidewall of the gate trench 36 toward the inside of the gate trench 36. The insulating surface may have a protruding portion that protrudes from the sidewall of the gate trench 36 toward the inside of the gate trench 36.

[0217] In this embodiment, the buried insulator 39 has a thickness greater than that of the insulating film 37. The thickness of the buried insulator 39 is preferably less than that of the buried electrode 38. The ratio of the thickness of the buried insulator 39 to the depth of the gate trench 36 may be greater than 0 and less than 0.5. The thickness ratio may have a value belonging to at least one of the ranges of greater than 0 and less than 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5.

[0218] The semiconductor device 1B includes a plurality of n-type source regions 40 formed in the surface layer portion of the first main surface 3 in the active region 30. The source regions 40 have a higher n-type impurity concentration than the n-type impurity concentration of the second layer 9 (first layer 8). The n-type impurity concentration of the source regions 40 is higher than the p-type impurity concentration of the body region 32.

[0219] The source regions 40 are formed in regions between the gate structures 35 in the surface layer portion of the body region 32. The source regions 40 are formed at intervals in the first direction X following the extension direction of the gate structures 35, and are adjacent to two gate structures 35 corresponding to each other in the second direction Y.

[0220] In this embodiment, the source regions 40 extend in strip shapes in the first direction X in accordance with the extension direction of the corresponding gate structures 35. The source regions 40 may intersect with one or more second regions 12. In the first direction X, the length of the source regions 40 is greater than the spacing between the gate structures 35.

[0221] With respect to the plurality of source regions 40 on one side and the other side formed on both sides of the plurality of gate structures 35, the plurality of source regions 40 on the other side face the plurality of source regions 40 on the one side in the second direction Y. The plurality of source regions 40 on the other side may face a region between the plurality of source regions 40 on the one side in the second direction Y.

[0222] The source regions 40 are formed at intervals from the bottom of the body region 32 toward the first main surface 3, and face the second layer 9 via a part of the body region 32. The source regions 40 are formed at intervals from the depth position of the intermediate portions of the gate structures 35 toward the first main surface 3. The source regions 40 may have portions located on the bottom wall side of the gate structures 35 relative to the depth position of the intermediate portions of the gate structures 35.

[0223] In this embodiment, the multiple source regions 40 have a portion located on the first main surface 3 side of the electrode surface of the buried electrode 38 and a portion located on the bottom wall side of the gate structure 35 with respect to the electrode surface of the buried electrode 38. The multiple source regions 40 have a portion located on the first main surface 3 side of the insulating surface of the buried insulator 39 and a portion located on the bottom wall side of the gate structure 35 with respect to the insulating surface of the buried insulator 39.

[0224] The plurality of source regions 40 have portions facing the corresponding buried electrodes 38 in the horizontal direction and portions facing the corresponding buried insulators 39. The plurality of source regions 40 face the corresponding buried electrodes 38 and the corresponding buried insulators 39 via the corresponding insulating films 37. In this embodiment, the plurality of source regions 40 have portions exposed from the opening ends of the gate trenches 36.

[0225] The plurality of source regions 40 has a thickness greater than the thickness between the bottom of the body region 32 and the bottom of the plurality of source regions 40. The depth of the plurality of source regions 40 may be less than the thickness between the bottom of the body region 32 and the bottom of the plurality of source regions 40.

[0226] The multiple source regions 40, together with the second layer 9, define a channel that serves as a current path in the region on the bottom side of the body region 32. The channel may have a channel length greater than 0 nm and not greater than 500 nm. The channel length is the distance between the bottom of the body region 32 and the bottom of the source region 40.

[0227] The channel length may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm. The channel length is preferably less than or equal to 300 nm.

[0228] The semiconductor device 1B includes a plurality of p-type contact regions 41 formed in the surface layer portion of the first main surface 3 in the active region 30. The contact regions 41 have a higher p-type impurity concentration than the p-type impurity concentration of the second region 12 (first region 11). The p-type impurity concentration of the contact regions 41 is higher than the p-type impurity concentration of the body region 32. The p-type impurity concentration of the contact regions 41 may be higher or lower than the n-type impurity concentration of the source region 40.

[0229] The plurality of contact regions 41 are formed in regions between the plurality of gate structures 35 in the surface layer portion of the body region 32, respectively, to increase the p-type impurity concentration of the body region 32. The plurality of contact regions 41 extend in layers along the first main surface 3. The plurality of contact regions 41 are formed at intervals in the first direction X following the extension direction of the plurality of gate structures 35, and are adjacent to two gate structures 35 corresponding to each other in the second direction Y. The plurality of contact regions 41 may intersect with one or more second regions 12.

[0230] The plurality of contact regions 41 are respectively interposed in regions between the plurality of source regions 40 in the first direction X. The plurality of contact regions 41 may be connected to the plurality of source regions 40 in the first direction X. The plurality of contact regions 41 may be formed at intervals from the plurality of source regions 40 in the first direction X and may face the plurality of source regions 40 with parts of the body region 32 interposed therebetween.

[0231] With respect to the plurality of contact regions 41 on one side and the other side formed on both sides of the plurality of gate structures 35, the plurality of contact regions 41 on the other side face the plurality of contact regions 41 on the one side in the second direction Y. The plurality of contact regions 41 on the other side may face a region (plurality of source regions 40) between the plurality of contact regions 41 on the one side in the second direction Y.

[0232] The plurality of contact regions 41 are formed at intervals from the bottom of the body region 32 toward the first main surface 3, and face the second layer 9 via a part of the body region 32. The plurality of contact regions 41 are formed at intervals from the depth position of the intermediate portions of the plurality of gate structures 35 toward the first main surface 3. The plurality of contact regions 41 may have portions located on the bottom wall side of the plurality of gate structures 35 relative to the depth position of the intermediate portions of the plurality of gate structures 35.

[0233] In this embodiment, the multiple contact regions 41 have a portion located on the first main surface 3 side of the electrode surface of the buried electrode 38 and a portion located on the bottom wall side of the gate structure 35 with respect to the electrode surface of the buried electrode 38. The multiple contact regions 41 have a portion located on the first main surface 3 side of the insulating surface of the buried insulator 39 and a portion located on the bottom wall side of the gate structure 35 with respect to the insulating surface of the buried insulator 39.

[0234] The plurality of contact regions 41 have portions facing the corresponding buried electrodes 38 in the horizontal direction and portions facing the corresponding buried insulators 39. The plurality of contact regions 41 face the corresponding buried electrodes 38 and the corresponding buried insulators 39 via the corresponding insulating films 37. In this embodiment, the plurality of contact regions 41 have portions exposed from the opening ends of the gate trenches 36.

[0235] The contact region 41 may have a depth greater than the depth of the source region 40. The depth of the contact region 41 may be less than the depth of the source region 40. The depth of the contact region 41 may be greater than the thickness between the bottom of the body region 32 and the bottom of the contact region 41. The depth of the contact region 41 may be less than the thickness between the bottom of the body region 32 and the bottom of the contact region 41.

[0236] The lengths of the contact regions 41 in the first direction X are adjusted according to the channel area to be formed. The channel area is the total planar area of ​​the source regions 40. That is, the channel area increases or decreases according to the ratio of the total planar area of ​​the contact regions 41. The total planar area of ​​the contact regions 41 is preferably less than the channel area.

[0237] The multiple contact regions 41 may extend in a strip shape in the first direction X in a plan view, following the extension direction of the multiple gate structures 35. The lengths of the multiple contact regions 41 in the first direction X may be equal to or different from one another. The length of the contact regions 41 may be greater or smaller than the width of the gate structure 35. The length of the contact regions 41 may be greater or smaller than the spacing between the multiple gate structures 35.

[0238] Fig. 20 is a cross-sectional view taken along line XX-XX in Fig. 14. Referring to Fig. 20, semiconductor device 1B includes a main surface insulating film 45 that selectively covers first main surface 3. The main surface insulating film 45 may also be referred to as a "surface insulating film," an "outer surface insulating film," or the like. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0239] The main surface insulating film 45 may include a silicon oxide film containing an oxide of the chip 2 (second layer 9). The main surface insulating film 45 may include a silicon oxide film containing an oxide other than the oxide of the chip 2. The main surface insulating film 45 may include the same type of insulator as the insulating film 37.

[0240] The main surface insulating film 45 selectively covers the first main surface 3 in the active region 30 and the outer region 31. The main surface insulating film 45 covers the first main surface 3 in the peripheral portion of the active region 30 in a film-like manner, exposing the multiple gate structures 35. Specifically, the main surface insulating film 45 is connected to the multiple insulating films 37, exposing the multiple buried insulators 39.

[0241] The main surface insulating film 45 covers the first main surface 3 (the plurality of second regions 12) in the outer region 31. The main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 45 may be formed spaced apart inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3. The main surface insulating film 45 may have a thickness substantially equal to that of the plurality of insulating films 37.

[0242] The thickness of the main surface insulating film 45 may be 10 nm or more and 250 nm or less. The thickness of the main surface insulating film 45 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0243] The semiconductor device 1B includes one or more gate wirings 46 (one in this embodiment) selectively routed on the first main surface 3 in the outer region 31. The gate wiring 46 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 46 preferably has the same conductive material as the buried electrode 38.

[0244] The gate wiring 46 is electrically connected to the plurality of gate structures 35 and applies a gate potential to the plurality of gate structures 35. The gate wiring 46 is disposed on the main surface insulating film 45 at a distance from the periphery of the first main surface 3 toward the active region 30, and faces the first main surface 3 with the main surface insulating film 45 interposed therebetween.

[0245] The gate wiring 46 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y, and intersects (specifically, orthogonally) with ends of the multiple gate structures 35. In this embodiment, the gate wiring 46 is formed in the shape of an endless polygonal ring (for example, a square ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 30 (the multiple gate structures 35).

[0246] The gate wiring 46 may be formed in a strip shape with ends. The gate wiring 46 may have an edge portion that connects the strip-like portion extending in the first direction X and the strip-like portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0247] The gate wiring 46 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 46 is mechanically and electrically connected to ends of the multiple gate structures 35. Specifically, the inner edge portion of the gate wiring 46 is mechanically and electrically connected to the multiple buried electrodes 38 in the multiple gate trenches 36. In this embodiment, the gate wiring 46 is formed integrally with the multiple buried electrodes 38 as an extension portion of the multiple buried electrodes 38.

[0248] The semiconductor device 1B includes an insulating interlayer film 47 covering the first main surface 3. The interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 may have a single-layer structure or a multilayer structure including at least one of an NSG film, a PSG film, and a BPSG film.

[0249] The interlayer film 47 preferably has a single-layer structure or a laminated structure including at least an NSG film. The interlayer film 47 may have a laminated structure including an NSG film and a PSG film laminated in this order from the chip 2 side. The interlayer film 47 may have a laminated structure including an NSG film, a PSG film, and a BPSG film laminated in this order from the chip 2 side. The interlayer film 47 may include the same type of insulator as the buried insulator 39.

[0250] The interlayer film 47 covers the main surface insulating film 45 in the active region 30 and the outer region 31. The interlayer film 47 covers the plurality of gate structures 35 in the peripheral portion of the active region 30. Specifically, the interlayer film 47 extends from above the main surface insulating film 45 into the plurality of gate trenches 36 and covers the plurality of buried electrodes 38 in the plurality of gate trenches 36.

[0251] The interlayer film 47 is connected to the plurality of buried insulators 39 in the gate trench 36. In this embodiment, the interlayer film 47 is integrally formed with the plurality of buried insulators 39. The connection portions of the interlayer film 47 to the plurality of buried insulators 39 may be regarded as part of the plurality of buried insulators 39 or as part of the interlayer film 47.

[0252] The interlayer film 47 covers the first main surface 3 (the plurality of second regions 12) in the outer region 31 via the main surface insulating film 45. The interlayer film 47 covers the gate wiring 46 in the outer region 31. The interlayer film 47 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge portion of the interlayer film 47 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and either or both of the peripheral edge portion of the first main surface 3 and the main surface insulating film 45 may be exposed.

[0253] The interlayer film 47 has a thickness greater than that of the main surface insulating film 45. The thickness of the interlayer film 47 may be 0.1 μm or more and 5 μm or less. The thickness of the interlayer film 47 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0254] The semiconductor device 1B includes a source opening 48 formed in the interlayer film 47 in the active region 30. The source opening 48 penetrates the main surface insulating film 45 and the interlayer film 47, exposing the plurality of gate structures 35. Specifically, the source opening 48 exposes the plurality of buried insulators 39, the body region 32, the plurality of source regions 40, and the plurality of contact regions 41.

[0255] The semiconductor device 1B includes one or more (multiple in this embodiment) gate openings 49 formed in an interlayer film 47. The multiple gate openings 49 penetrate the interlayer film 47 and selectively expose the gate wiring 46. In this embodiment, the multiple gate openings 49 extend in a strip shape following the extension direction of the gate wiring 46.

[0256] The multiple gate openings 49 may be formed at intervals along the extension direction of the gate wiring 46. The multiple gate openings 49 may each extend in a strip shape following the extension direction of the gate wiring 46. The multiple gate openings 49 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0257] The multiple gate openings 49 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view. The multiple gate openings 49 may be formed in a polygonal or circular shape in a plan view. For example, the multiple gate openings 49 may be formed in a quadrangular or hexagonal shape in a plan view. When one gate opening 49 is formed, the gate opening 49 may extend in a strip shape following the extension direction of the gate wiring 46.

[0258] The semiconductor device 1B includes a source electrode 50 disposed on the first main surface 3. The source electrode 50 may also be referred to as a "first main electrode," a "first terminal (electrode)," a "first pad (electrode)," a "source pad electrode," or the like. The source electrode 50 is disposed on the interlayer film 47.

[0259] In this embodiment, the source electrode 50 has a first pad portion 50a, a second pad portion 50b, and a third pad portion 50c. The first pad portion 50a has a relatively large planar area and forms the main body of the source electrode 50. In this embodiment, the first pad portion 50a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and is located closer to the third side surface 5C than the center of the first main surface 3.

[0260] The second pad portion 50b has a planar area smaller than that of the first pad portion 50a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 50a in the first direction X (the end on the second side surface 5B side) toward the first side surface 5A. The third pad portion 50c has a planar area smaller than that of the first pad portion 50a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 50a in the first direction X (the end on the fourth side surface 5D side) toward the first side surface 5A, and faces the second pad portion 50b in the first direction X.

[0261] The planar area of ​​the third pad portion 50c may be approximately equal to the planar area of ​​the second pad portion 50b. The planar area of ​​the third pad portion 50c may be larger or smaller than the planar area of ​​the second pad portion 50b. Either or both of the second pad portion 50b and the third pad portion 50c may be used as a terminal portion for monitoring a current.

[0262] The source electrode 50 does not necessarily have to have both the second pad portion 50b and the third pad portion 50c at the same time, and may have only one of the second pad portion 50b and the third pad portion 50c. The source electrode 50 may be composed of only the first pad portion 50a, and may not have both the second pad portion 50b and the third pad portion 50c.

[0263] In this embodiment, the source electrode 50 has a layered structure including a base electrode 51 and a main electrode 52. The base electrode 51 extends into the source opening 48 from above the interlayer film 47, and collectively covers the area within the source opening 48 in a film-like manner. The base electrode 51 has a portion that covers the interlayer film 47 in a film-like manner, a portion that covers the wall surface of the source opening 48 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner.

[0264] The base electrode 51 collectively covers the multiple gate structures 35 within the source opening 48. The base electrode 51 is mechanically and electrically connected to the body region 32, the multiple source regions 40, and the multiple contact regions 41 on the first main surface 3. The base electrode 51 covers insulating surfaces of the multiple buried insulators 39 within the multiple gate trenches 36, and is electrically isolated from the multiple buried electrodes 38.

[0265] The base electrode 51 has a peripheral portion that faces the ends of the multiple gate structures 35 via the interlayer film 47. The peripheral portion of the base electrode 51 is drawn from the active region 30 to the outer region 31 and faces a part of the gate wiring 46 via the interlayer film 47. The peripheral portion of the base electrode 51 is formed at a distance from the outer edge of the gate wiring 46 towards the inner edge of the gate wiring 46. The peripheral portion of the base electrode 51 may be located inward from the middle of the gate wiring 46.

[0266] The base electrode 51 may have a layered structure including multiple metal films or a single-layer structure including a single metal film. For example, the base electrode 51 may have a layered structure including a Ti film and a TiN film stacked in this order on the first main surface 3 side. For example, the base electrode 51 may have a single-layer structure including a Ti film or a TiN film.

[0267] The thickness of the base electrode 51 may be greater than 0 nm and less than or equal to 500 nm. The thickness of the base electrode 51 may have a value belonging to at least one of the ranges of 0 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0268] The main electrode 52 is made of a different conductor from the base electrode 51. In this embodiment, the main electrode 52 is made of an aluminum alloy. The aluminum alloy may include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0269] The main electrode 52 covers the base electrode 51 in a film-like manner and extends into the source opening 48 from above the interlayer film 47. The main electrode 52 has a portion that covers the interlayer film 47 in a film-like manner via the base electrode 51, a portion that covers the wall surface of the source opening 48 in a film-like manner via the base electrode 51, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 51.

[0270] The main electrode 52 collectively covers the plurality of gate structures 35 within the source opening 48 via the base electrode 51. The main electrode 52 is electrically connected to the body region 32, the plurality of source regions 40, and the plurality of contact regions 41 via the base electrode 51.

[0271] The main electrode 52 has a peripheral portion that faces the ends of the multiple gate structures 35 via the interlayer film 47. The peripheral portion of the main electrode 52 is drawn from the active region 30 to the outer region 31 and faces a part of the gate wiring 46 via the interlayer film 47. The peripheral portion of the main electrode 52 is formed at a distance from the outer edge of the gate wiring 46 towards the inner edge of the gate wiring 46. The peripheral portion of the main electrode 52 may be located inward from the middle of the gate wiring 46.

[0272] The main electrode 52 has a thickness greater than that of the base electrode 51. In this embodiment, the thickness of the main electrode 52 is greater than that of the interlayer film 47. The thickness of the main electrode 52 may be less than that of the interlayer film 47.

[0273] The thickness of the body electrode 52 may be greater than 0 μm and less than 5 μm. The thickness of the body electrode 52 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0274] The semiconductor device 1B includes a gate electrode 53 disposed on the first main surface 3. The gate electrode 53 may also be referred to as a "second main electrode," a "second terminal (electrode)," a "second pad (electrode)," a "gate pad electrode," or the like. The gate electrode 53 is disposed on the interlayer film 47 at a distance from the source electrode 50.

[0275] The gate electrode 53 is disposed in a region on the first side surface 5A side of the first pad portion 50a, and faces the center of the first side surface 5A and the first pad portion 50a in the second direction Y. The gate electrode 53 is interposed in a region between the second pad portion 50b and the third pad portion 50c, and faces both the second pad portion 50b and the third pad portion 50c in the first direction X.

[0276] The gate electrode 53 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 53 has a planar area smaller than that of the source electrode 50. The planar area of ​​the gate electrode 53 is smaller than that of the first pad portion 50a. The planar area of ​​the gate electrode 53 may be larger or smaller than that of the second pad portion 50b (third pad portion 50c).

[0277] In this embodiment, the gate electrode 53 does not have a direct electrical connection to the gate wiring 46. The gate electrode 53 may be mechanically and electrically connected to the gate wiring 46 via one or more gate openings 49. Although not shown, the gate electrode 53, like the source electrode 50, includes a base electrode 51 and a main electrode 52 stacked in this order from the interlayer film 47 side.

[0278] The semiconductor device 1B includes gate finger electrodes 54 extending from the gate electrode 53 onto the first main surface 3. The gate finger electrodes 54 may also be referred to as "gate wiring 46," "gate fingers," etc. The gate finger electrodes 54 transmit the gate potential applied to the gate electrode 53 to other regions.

[0279] The gate finger electrodes 54 are drawn out from the gate electrode 53 onto the interlayer film 47 and routed in a strip shape along the source electrode 50. The gate finger electrodes 54 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view. In this embodiment, the gate finger electrodes 54 are formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3 and surround the source electrode 50.

[0280] The gate finger electrodes 54 are arranged closer to the periphery of the first main surface 3 than both end portions of the multiple gate structures 35. The gate finger electrodes 54 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0281] The gate finger electrodes 54 extend into the plurality of gate openings 49 from above the interlayer film 47, and are mechanically and electrically connected to the gate wiring 46 within the plurality of gate openings 49. As a result, the gate potential applied to the gate electrode 53 is applied to the plurality of gate structures 35 via the gate wiring 46 and the gate finger electrodes 54.

[0282] The gate finger electrode 54 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 54 is formed at a distance from the ends of the multiple gate structures 35 toward the peripheral side of the first main surface 3, and faces the first main surface 3 in the stacking direction. In other words, the gate finger electrode 54 does not face the multiple gate structures 35 in the stacking direction.

[0283] The inner edge of the gate finger electrode 54 is disposed on the gate wiring 46. The inner edge of the gate finger electrode 54 faces the peripheral edge of the source electrode 50 in the horizontal direction above the gate wiring 46. The inner edge of the gate finger electrode 54 is located closer to the peripheral edge of the first main surface 3 than the middle part of the gate wiring 46. The outer edge of the gate finger electrode 54 is drawn out from above the gate wiring 46 to the peripheral edge of the first main surface 3, and faces the first main surface 3 in the stacking direction.

[0284] Like the gate electrode 53, the gate finger electrode 54 has a layered structure including a base electrode 51 and a main electrode 52 layered in this order from the first main surface 3 side. The base electrode 51 collectively covers the region of the interlayer film 47 where the multiple gate openings 49 are formed, and extends from above the interlayer film 47 into the multiple gate openings 49.

[0285] The base electrode 51 has a portion that covers the insulating surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surfaces of the plurality of gate openings 49 in a film-like manner, and a portion that covers the gate wiring 46 in the plurality of gate openings 49 in a film-like manner. The base electrode 51 is mechanically and electrically connected to the gate wiring 46 in the plurality of gate openings 49.

[0286] The main electrode 52 covers the region of the interlayer film 47 where the plurality of gate openings 49 are formed via the base electrode 51 in a film-like manner, and extends from above the interlayer film 47 into the plurality of gate openings 49 .

[0287] The main electrode 52 has a portion that covers the interlayer film 47 in a film form via the base electrode 51, a portion that covers the wall surfaces of the plurality of gate openings 49 in a film form via the base electrode 51, and a portion that covers the gate wiring 46 in a film form via the base electrode 51 within the plurality of gate openings 49. The main electrode 52 is electrically connected to the gate wiring 46 via the base electrode 51 within the plurality of gate openings 49.

[0288] The semiconductor device 1B includes a drain electrode 55 covering the second main surface 4. The drain electrode 55 may also be referred to as a "third main electrode," a "third terminal (electrode)," a "third pad (electrode)," a "drain pad electrode," or the like. The drain electrode 55 is mechanically and electrically connected to the base layer 6. The drain electrode 55 forms ohmic contact with the base layer 6.

[0289] The drain electrode 55 may cover the entire second main surface 4 and be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 55 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0290] A breakdown voltage that can be applied between source electrode 50 and drain electrode 55 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0291] Fig. 21 is a cross-sectional view showing a main part of the active region 30 of a semiconductor device 1C according to the third embodiment. Fig. 22 is a cross-sectional view showing another main part of the active region 30 of the semiconductor device 1C shown in Fig. 21. Fig. 23 is a cross-sectional perspective view showing a main part of the active region 30 together with the pillar region 10 according to the first example.

[0292] 21 to 23, semiconductor device 1C has, as a basic configuration, chip 2 and pillar region 10 according to semiconductor device 1A. In this configuration, semiconductor device 1C has pillar region 10 according to the first embodiment example (see FIGS. 3 and 5A to 5C).

[0293] The semiconductor device 1C may have any one of the pillar regions 10 according to the second to fifth embodiments (see FIGS. 6 to 10). The semiconductor device 1C may also have the pillar region 10 according to the first modified example (see FIG. 11) or the pillar region 10 according to the second modified example (see FIG. 12).

[0294] The semiconductor device 1C is a modified version of the semiconductor device 1B. Specifically, in this version, the gate structures 35 are arranged at intervals in a first direction X in a plan view and extend in a strip-like pattern in a second direction Y. The gate structures 35 are arranged in a strip-like pattern extending in the second direction Y in a plan view.

[0295] In this embodiment, the plurality of gate structures 35 extend in the same direction as the plurality of second regions 12, but in a direction different from the direction in which the plurality of first regions 11 extend. The plurality of gate structures 35 intersect (specifically, orthogonally intersect) the plurality of first regions 11. This layout is effective in increasing the channel area of ​​the active region 30.

[0296] In this embodiment, the multiple gate structures 35 are arranged at intervals approximately equal to the intervals between the multiple second regions 12, and overlap the multiple second regions 12 in a one-to-one correspondence in the stacking direction. The multiple gate structures 35 have bottom walls connected to the multiple second regions 12. The intervals between the multiple gate structures 35 may be approximately equal to the intervals between the multiple first regions 11. The intervals between the multiple gate structures 35 may be larger or smaller than the intervals between the multiple first regions 11.

[0297] In this embodiment, the source regions 40 are formed at intervals in the second direction Y following the extension direction of the gate structures 35, and are adjacent to two gate structures 35 corresponding to each other in the first direction X. In this embodiment, the source regions 40 extend in strip shapes in the second direction Y following the extension direction of the corresponding gate structures 35.

[0298] The multiple source regions 40 may intersect one or multiple second regions 12 in the stacking direction. Another explanation of the multiple source regions 40 can be obtained by replacing the "first direction X" with the "second direction Y" in the above explanation and simultaneously replacing the "second direction Y" with the "first direction X."

[0299] In this embodiment, the multiple contact regions 41 are formed at intervals in the second direction Y following the extension direction of the multiple gate structures 35, and are adjacent to two gate structures 35 corresponding to each other in the first direction X. In this embodiment, the multiple contact regions 41 extend in strip shapes in the second direction Y following the extension direction of the corresponding multiple gate structures 35.

[0300] The plurality of contact regions 41 may intersect one or more second regions 12 in the stacking direction. Another explanation of the plurality of contact regions 41 can be obtained by replacing the "first direction X" with the "second direction Y" in the above explanation and simultaneously replacing the "second direction Y" with the "first direction X."

[0301] Fig. 24 is an enlarged plan view showing the active region 30 of a semiconductor device 1D according to the fourth embodiment. Fig. 25 is a cross-sectional view taken along line XXV-XXV shown in Fig. 24. Fig. 26 is a cross-sectional perspective view showing a main part of the active region 30 together with the pillar region 10 according to the first example.

[0302] The semiconductor device 1D is a variation of the semiconductor device 1C. Specifically, the gate structures 35 are spaced apart from the second regions 12 and disposed in regions between the second regions 12.

[0303] In this embodiment, the plurality of gate structures 35 are respectively disposed in the middle of two adjacent second regions 12, and extend in a strip shape in the second direction Y following the extension direction of the second regions 12. The plurality of gate structures 35 each have a portion (bottom wall) that faces the plurality of second regions 12 in the horizontal direction, with part of the second layer 9 between them.

[0304] The multiple gate structures 35 are formed at intervals from the lower end of the second layer 9 toward the first main surface 3, and face the first layer 8 and the multiple first regions 11 across part of the second layer 9. This layout is effective in relaxing the restrictions on the design rule for the multiple gate structures 35 relative to the multiple second regions 12, compared to the configuration of the semiconductor device 1C. The other configurations are the same as those of the semiconductor device 1C.

[0305] Fig. 27 is an enlarged plan view showing the active region 30 of a semiconductor device 1E according to the fifth embodiment. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in Fig. 27. Fig. 29 is a cross-sectional view taken along line XXIX-XXIX shown in Fig. 27. Fig. 30 is a cross-sectional perspective view showing a main part of the active region 30 together with the pillar region 10 according to the first example. Fig. 31 is a cross-sectional view showing an outer region 31 of the semiconductor device 1E shown in Fig. 27.

[0306] 27 to 31, a semiconductor device 1E is a semiconductor switching device having an insulated gate transistor structure as an example of a device structure (functional device). The transistor structure has a planar gate vertical structure.

[0307] The semiconductor device 1E has, as a basic configuration, the chip 2 and pillar region 10 according to the semiconductor device 1A. In this configuration, the semiconductor device 1E has the pillar region 10 according to the first embodiment example (see FIGS. 3 and 5A to 5C).

[0308] The semiconductor device 1E may have any one of the pillar regions 10 according to the second to fifth embodiments (see FIGS. 6 to 10). The semiconductor device 1E may also have the pillar region 10 according to the first modified example (see FIG. 11) or the pillar region 10 according to the second modified example (see FIG. 12).

[0309] The semiconductor device 1E includes a plurality of p-type body regions 32 formed in the active region 30 in a surface layer portion of the first main surface 3. The plurality of body regions 32 are formed in the active region 30 at intervals from the periphery of the first main surface 3, and are not formed in the outer region 31. The plurality of body regions 32 are formed in a surface layer portion of the second layer 9, and extend in layers along the first main surface 3.

[0310] The body regions 32 each extend in a strip shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. The body regions 32 are arranged in stripes extending in the first direction X in a plan view. This layout is effective in relaxing the restrictions on the design rules for the body regions 32 relative to the second regions 12.

[0311] In this embodiment, the body regions 32 extend in the same direction as the first regions 11, but in a direction different from the direction in which the second regions 12 extend. The body regions 32 intersect (specifically, orthogonally intersect) the second regions 12. The body regions 32 are connected to the second regions 12. The p-type impurity concentrations of the body regions 32 are increased by the second regions 12.

[0312] In this embodiment, the body regions 32 are arranged at intervals substantially equal to the intervals between the first regions 11, and overlap with the first regions 11 in a one-to-one correspondence in the stacking direction. The intervals between the body regions 32 may be different from the intervals between the first regions 11.

[0313] In this case, the body regions 32 may include body regions 32 facing the first regions 11 in the stacking direction and body regions 32 not facing the first regions 11 in the stacking direction. All of the body regions 32 may face regions between the first regions 11 in the stacking direction.

[0314] The spacing between the body regions 32 may be greater than 0 μm and less than or equal to 10 μm. The spacing between the body regions 32 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0315] The semiconductor device 1E includes a plurality of n-type source regions 40 formed in the surface layer portions of the plurality of body regions 32. The plurality of source regions 40 are formed at intervals from both edges of the corresponding body region 32 toward the inner portions of the corresponding body region 32 in the second direction Y.

[0316] The source regions 40 each extend in a strip shape in the first direction X in a surface layer portion of the corresponding body region 32, and are formed at intervals in the second direction Y. The source regions 40 may be formed at intervals in the first direction X following the extension direction of the corresponding body region 32.

[0317] The plurality of source regions 40 are formed at intervals inward from both end portions of the corresponding body region 32 in the first direction X. The plurality of source regions 40 are formed at intervals from the bottom portions of the corresponding body regions 32 toward the first main surface 3, and face the second layer 9 with a part of the corresponding body region 32 interposed therebetween.

[0318] The semiconductor device 1E includes a plurality of p-type contact regions 41 formed in regions different from the plurality of source regions 40 in the surface layer portion of the corresponding body region 32. The plurality of contact regions 41 are interposed in regions between the plurality of source regions 40 in the surface layer portion of the corresponding body region 32, and are electrically connected to the body region 32.

[0319] The contact regions 41 extend in strip shapes in the first direction X following the extension direction of the corresponding body regions 32 (source regions 40). The contact regions 41 are formed at intervals inward from both end portions of the corresponding body regions 32 in the first direction X. The contact regions 41 are formed at intervals from the bottoms of the corresponding body regions 32 toward the first main surface 3, and face the second layer 9 with a part of the corresponding body region 32 sandwiched therebetween.

[0320] In this embodiment, the contact region 41 has a width that is less than the width of the plurality of source regions 40. The width of the contact region 41 may be greater than the width of the plurality of source regions 40. In this embodiment, the plurality of contact regions 41 have a thickness that is greater than the thickness of the plurality of source regions 40, and have bottoms that are located closer to the bottom of the body region 32 than the bottoms of the plurality of source regions 40.

[0321] The semiconductor device 1E includes a plurality of n-type surface drift regions 60 formed in a surface portion of the first main surface 3. In this embodiment, the plurality of surface drift regions 60 each comprises a portion of the second layer 9. The plurality of surface drift regions 60 may have an n-type impurity concentration higher than the n-type impurity concentration of the second layer 9, or may have an n-type impurity concentration lower than the n-type impurity concentration of the second layer 9.

[0322] The surface drift regions 60 are defined in regions between adjacent body regions 32 in the surface portion of the second layer 9. The surface drift regions 60 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. The surface drift regions 60 are formed in stripes extending in the first direction X.

[0323] The semiconductor device 1E includes a plurality of p-type channel regions 61 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 61 are partitioned into regions between the plurality of source regions 40 and the plurality of surface drift regions 60 (second layers 9) in the surface layer portions of the plurality of body regions 32, and extend in strip shapes in the first direction X. The plurality of channel regions 61 form a current path that extends horizontally along the first main surface 3.

[0324] The semiconductor device 1E includes a plurality of planar gate structures 65 (planar electrode type) arranged on the first main surface 3 in the active region 30. The plurality of gate structures 65 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. The plurality of gate structures 65 are arranged in stripes extending in the first direction X.

[0325] In this embodiment, the plurality of gate structures 65 extend in the same direction as the plurality of first regions 11, but in a direction different from the direction in which the plurality of second regions 12 extend. The plurality of gate structures 65 intersect (specifically, orthogonally intersect) with the plurality of second regions 12. This layout is effective in relaxing the restrictions on the design rules for the plurality of gate structures 65 relative to the plurality of second regions 12.

[0326] In this embodiment, the multiple gate structures 65 are arranged at intervals approximately equal to the intervals between the multiple first regions 11, and overlap with the regions between the multiple first regions 11 in a one-to-one correspondence in the stacking direction. The intervals between the multiple gate structures 65 may be approximately equal to the intervals between the multiple second regions 12. The intervals between the multiple gate structures 65 may be larger or smaller than the intervals between the multiple second regions 12.

[0327] The spacing between the multiple gate structures 65 may be different from the spacing between the multiple first regions 11. In this case, the multiple gate structures 65 may include gate structures 65 that face the first regions 11 in the stacking direction and gate structures 65 that do not face the first regions 11 in the stacking direction. All of the gate structures 65 may face the first regions 11 in the stacking direction.

[0328] The plurality of gate structures 65 are each disposed on at least one channel region 61 (periphery of the body region 32) and control inversion and non-inversion of the channel region 61. The plurality of gate structures 65 cover at least one peripheral portion of the body region 32, at least one source region 40, and one surface drift region 60, respectively.

[0329] In this embodiment, the multiple gate structures 65 extend across the peripheries of two adjacent body regions 32 and cover the multiple channel regions 61. Specifically, the multiple gate structures 65 extend across one and the other body regions 32 and cover the two source regions 40, one surface drift region 60, and two channel regions 61.

[0330] Each of the multiple gate structures 65 has a stacked structure including a planar insulating film 66 and a planar electrode 67. The planar insulating film 66 may be referred to as a "gate insulating film," and the planar electrode 67 may be referred to as a "gate electrode" or a "planar gate electrode."

[0331] The planar insulating film 66 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the planar insulating film 66 has a single-layer structure made of a silicon oxide film. The planar insulating film 66 preferably includes a silicon oxide film containing an oxide of the second layer 9.

[0332] The planar insulating film 66 covers the first main surface 3 in a film-like shape. The planar insulating film 66 extends in a strip shape in the first direction X. The planar insulating film 66 is disposed on at least one channel region 61 (periphery of the body region 32). The planar insulating film 66 covers the periphery of at least one body region 32, at least one source region 40, and one surface drift region 60.

[0333] In this embodiment, the planar insulating film 66 extends across the peripheries of two adjacent body regions 32. Specifically, the planar insulating film 66 extends across both body regions 32 and covers two source regions 40, one surface drift region 60, and two channel regions 61.

[0334] The planar electrode 67 is disposed on the planar insulating film 66. A gate potential is applied as a control potential to the planar electrode 67. The planar electrode 67 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0335] The planar electrode 67 covers the first main surface 3 in a film form via the planar insulating film 66, and faces at least one channel region 61 (peripheral portion of the body region 32). The planar electrode 67 extends in a strip shape in the first direction X. In this embodiment, the planar electrode 67 is formed inwardly from the peripheral edge of the planar insulating film 66 at a distance, exposing the peripheral edge of the planar insulating film 66.

[0336] The planar electrode 67 covers the periphery of at least one body region 32, at least one source region 40, and one surface drift region 60 via a planar insulating film 66. The planar electrode 67 spans the peripheries of two adjacent body regions 32. Specifically, the planar electrode 67 spans both body regions 32 and faces two source regions 40, one surface drift region 60, and two channel regions 61 via the planar insulating film 66.

[0337] Similar to the semiconductor device 1A, the semiconductor device 1E includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 selectively covers the first main surface 3 in the active region 30 and the outer region 31. The main surface insulating film 45 covers the first main surface 3 in the active region 30 in a film-like manner and is connected to a plurality of planar insulating films 66. The main surface insulating film 45 is formed integrally with the plurality of planar insulating films 66 and forms a single insulating film together with the plurality of planar insulating films 66.

[0338] The main surface insulating film 45 covers the first main surface 3 (the plurality of second regions 12) in the outer region 31. The main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D. The main surface insulating film 45 may be formed spaced apart inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3. The main surface insulating film 45 may have a thickness substantially equal to that of the plurality of insulating films 37.

[0339] Similar to the semiconductor device 1A, the semiconductor device 1E includes one or more (one in this embodiment) gate wirings 46 selectively routed on the first main surface 3 in the outer region 31. The gate wiring 46 applies a gate potential to the multiple gate structures 65.

[0340] The gate wiring 46 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 46 preferably has the same conductivity type as the planar electrode 67. The gate wiring 46 has a thickness approximately equal to that of the planar electrode 67. The thickness of the gate wiring 46 may be greater than or less than that of the planar electrode 67.

[0341] The gate wiring 46 is disposed on the main surface insulating film 45. The gate wiring 46 is selectively routed on the main surface insulating film 45 at intervals from the periphery of the first main surface 3 toward the plurality of gate structures 65. The gate wiring 46 extends in a strip shape along the plurality of gate structures 65. The gate wiring 46 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y.

[0342] In this embodiment, the gate wiring 46 is formed in an endless polygonal ring shape (for example, a square ring shape) having four sides parallel to the periphery of the first main surface 3, and surrounds the multiple gate structures 65 (active regions 30). The gate wiring 46 may be formed in a strip shape with ends. The gate wiring 46 may have an edge portion that connects the strip-like portion extending in the first direction X and the strip-like portion extending in the second direction Y in a planar view into an arc shape (preferably a quarter arc shape).

[0343] The gate wiring 46 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring 46 is mechanically and electrically connected to a plurality of planar electrodes 67 (gate structures 65) in a portion extending in the second direction Y. In this embodiment, the gate wiring 46 is formed integrally with the plurality of planar electrodes 67.

[0344] The gate line 46 has a width greater than that of the planar electrode 67. The width of the gate line 46 may be approximately equal to or less than the width of the planar electrode 67. The ratio of the width of the gate line 46 to the width of the planar electrode 67 may be 1 or more and 50 or less. The width ratio may have a value belonging to at least one of the ranges of 1 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less.

[0345] Similar to the semiconductor device 1A, the semiconductor device 1E includes an interlayer film 47 that selectively covers the first main surface 3 in the active region 30 and the outer region 31. The interlayer film 47 covers a plurality of gate structures 65 in the active region 30. Specifically, the interlayer film 47 covers a plurality of planar insulating films 66 and a plurality of planar electrodes 67, and electrically insulates the plurality of planar electrodes 67.

[0346] Similar to the semiconductor device 1A, the semiconductor device 1E includes a plurality of source openings 48 and a plurality of gate openings 49 formed in the interlayer film 47. The plurality of source openings 48 are formed in a one-to-one correspondence in regions between the plurality of planar electrodes 67, and each extends in a strip shape in the first direction X following the extension direction of the plurality of planar electrodes 67. The plurality of source openings 48 penetrate the planar insulating film 66 and the interlayer film 47, and expose the plurality of source regions 40 and the plurality of contact regions 41, respectively.

[0347] The source openings 48 may be formed in a one-to-many correspondence in the region between the planar electrodes 67. In this case, the source openings 48 may be formed at intervals along the extension direction of the planar electrodes 67. In this case, the source openings 48 may be formed in a quadrangular, rectangular (strip-like), circular, or other shape in plan view.

[0348] Similar to the semiconductor device 1A, the semiconductor device 1E includes a source electrode 50, a gate electrode 53, gate finger electrodes 54, and a drain electrode 55. In this embodiment, the source electrode 50 is disposed on the interlayer film 47 and extends from above the interlayer film 47 into the plurality of source openings 48. The source electrode 50 is electrically connected to the plurality of body regions 32, the plurality of source regions 40, and the plurality of contact regions 41 within the plurality of source openings 48.

[0349] In this embodiment, the gate electrode 53 is disposed on the interlayer film 47. The gate finger electrodes 54 are disposed on the interlayer film 47 and extend from above the interlayer film 47 into the plurality of gate openings 49. The gate finger electrodes 54 are electrically connected to the gate wiring 46 within the plurality of gate openings 49. The drain electrode 55 is mechanically and electrically connected to the first layer 8 on the second main surface 4.

[0350] 32 is a cross-sectional perspective view showing the active region 30 of a semiconductor device 1F according to the sixth embodiment together with the pillar region 10 according to the first example. The semiconductor device 1F has a modified form of the semiconductor device 1E. Specifically, the body regions 32 are arranged at intervals in the first direction X in a plan view and extend in a band-like manner in the second direction Y. The body regions 32 are arranged in a stripe pattern extending in the second direction Y in a plan view.

[0351] In this embodiment, the body regions 32 extend in the same direction as the second regions 12, but in a direction different from the direction in which the first regions 11 extend. The body regions 32 intersect (specifically, orthogonally intersect) the first regions 11. This layout is effective in increasing the channel area of ​​the active region 30.

[0352] The plurality of body structures are arranged at intervals approximately equal to the intervals between the plurality of second regions 12, and are connected to the plurality of second regions 12 in a one-to-one correspondence in the stacking direction. The p-type impurity concentrations of the plurality of body regions 32 are increased by the plurality of second regions 12. The intervals between the plurality of body regions 32 may be approximately equal to the intervals between the plurality of first regions 11. The intervals between the plurality of body regions 32 may be larger or smaller than the intervals between the plurality of first regions 11.

[0353] In this embodiment, the multiple source regions 40 are formed at intervals from both edges of the corresponding body region 32 toward the inner portion of the corresponding body region 32 in the first direction X. The multiple source regions 40 are formed at intervals in the first direction X in the surface layer portion of the corresponding body region 32, and each extends in a strip shape in the second direction Y.

[0354] The multiple source regions 40 may be formed at intervals in the second direction Y following the extension direction of the corresponding body regions 32. The multiple source regions 40 are formed at intervals inward from both end portions of the corresponding body regions 32 in the second direction Y. The multiple source regions 40 are formed at intervals from the bottoms of the corresponding body regions 32 toward the first main surface 3, and face the second layer 9 with a part of the corresponding body region 32 sandwiched therebetween.

[0355] The contact regions 41 extend in strip shapes in the second direction Y along the extension direction of the corresponding body regions 32 (source regions 40). The contact regions 41 are formed at intervals inward from both end portions of the corresponding body regions 32 in the second direction Y. The contact regions 41 are formed at intervals from the bottoms of the corresponding body regions 32 toward the first main surface 3, and face the second layer 9 with a part of the corresponding body region 32 sandwiched between them.

[0356] The surface drift regions 60 are partitioned into regions between the body regions 32, and extend in a strip shape in the second direction Y. The surface drift regions 60 are formed in regions between the second regions 12, and extend in a strip shape in the second direction Y following the extension direction of the second regions 12.

[0357] The channel regions 61 are defined in the surface portions of the body regions 32 between the source regions 40 and the surface drift regions 60 (second layers 9), and extend in the second direction Y in strip shapes.

[0358] The multiple gate structures 65 are arranged at intervals in a first direction X in a plan view, and extend in a strip-like pattern in a second direction Y. The multiple gate structures 65 are arranged in a strip-like pattern extending in the second direction Y in a plan view. This layout is effective in increasing the channel area of ​​the active region 30.

[0359] In this embodiment, the multiple gate structures 65 extend in the same direction as the multiple second regions 12, but in a direction different from the direction in which the multiple first regions 11 extend. The multiple gate structures 65 intersect (specifically, orthogonally intersect) the multiple first regions 11. The multiple gate structures 65 are arranged at intervals approximately equal to the intervals between the multiple second regions 12, and face the regions (surface drift regions 60) between the multiple second regions 12 in a one-to-one correspondence in the stacking direction.

[0360] The spacing between the multiple gate structures 65 may be approximately equal to the spacing between the multiple first regions 11. The spacing between the multiple gate structures 65 may be larger or smaller than the spacing between the multiple first regions 11. As in the case of the semiconductor device 1E, the multiple gate structures 65 are each disposed on at least one channel region 61 (periphery of the body region 32).

[0361] Additionally, the specific configuration of the semiconductor device 1E can be obtained by replacing the "first direction X" with the "second direction Y" in the configuration of the semiconductor device 1D and at the same time replacing the "second direction Y" with the "first direction X."

[0362] Fig. 33 is a plan view showing a semiconductor device 1G according to a seventh embodiment. Fig. 34 is a perspective view of the chip 2 shown in Fig. 33. Fig. 35 is a cross-sectional view taken along line XXXV-XXXV shown in Fig. 33. With reference to Figs. 33 to 35, the semiconductor device 1G is a semiconductor rectifier having a diode structure as an example of a device structure (functional device). The diode structure has a vertical structure.

[0363] The semiconductor device 1G has, as a basic configuration, the chip 2 and pillar region 10 according to the semiconductor device 1A. In this configuration, the semiconductor device 1G has the pillar region 10 according to the first embodiment example (see FIGS. 3 and 5A to 5C).

[0364] The semiconductor device 1G may have any one of the pillar regions 10 according to the second to fifth embodiments (see FIGS. 6 to 10). The semiconductor device 1G may also have the pillar region 10 according to the first modified example (see FIG. 11) or the pillar region 10 according to the second modified example (see FIG. 12).

[0365] The semiconductor device 1G includes the above-described active region 30 and outer region 31. In this embodiment, the active region 30 includes a device structure (diode structure) and is a region where an output current (forward current) is generated. In this embodiment, the outer region 31 is a region that does not include a device structure (diode structure).

[0366] The semiconductor device 1G includes a p-type guard region 70 formed in the outer region 31 within a surface layer portion of the first main surface 3. The guard region 70 may have a p-type impurity concentration higher than the n-type impurity concentration of the second layer 9. The p-type impurity concentration of the guard region 70 may be higher or lower than the p-type impurity concentration of the second region 12 (first region 11).

[0367] The guard region 70 is formed in the outer region 31 at a distance from the periphery of the first main surface 3. The guard region 70 extends in a strip shape along the active region 30. The guard region 70 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0368] In this embodiment, guard region 70 is formed in the shape of an endless polygonal ring (for example, a square ring) having four sides parallel to the periphery of first main surface 3, and surrounds the inner part of first main surface 3. Guard region 70 has portions connected to multiple second regions 12. The inner edge of guard region 70 defines the boundary between active region 30 and outer region 31.

[0369] The guard region 70 is formed at a distance from the lower end of the second layer 9 (first layer 8) toward the first main surface 3, and faces the first layer 8 across a part of the second layer 9. The guard region 70 is formed at a distance from the lower end of the second region 12 toward the first main surface 3. The guard region 70 may be formed at a distance from a depth position of the intermediate portion of the second layer 9 toward the first main surface 3. The guard region 70 may have a portion located on the first layer 8 side with respect to the depth position of the intermediate portion of the second layer 9.

[0370] The guard region 70 may be formed by utilizing the second region 12. That is, the guard region 70 may have a depth substantially equal to that of the second region 12 and a p-type impurity concentration substantially equal to that of the second region 12.

[0371] The semiconductor device 1G includes the aforementioned interlayer film 47 that selectively covers the first main surface 3. The interlayer film 47 selectively covers the first main surface 3 in the outer region 31. The interlayer film 47 covers the outer edge of the guard region 70 in the outer region 31, leaving the inner edge of the guard region 70 exposed. In this embodiment, the interlayer film 47 is continuous with the periphery of the first main surface 3. The interlayer film 47 may be formed at a distance from the periphery of the first main surface 3, leaving the second layer 9 exposed from the periphery of the first main surface 3.

[0372] The interlayer film 47 has a contact opening 71 that exposes the first main surface 3 in the active region 30. The contact opening 71 exposes the second layer 9 and the plurality of second regions 12. In this form, the contact opening 71 has an opening wall positioned on the guard region 70, exposing the inner edge of the guard region 70.

[0373] The semiconductor device 1G includes an anode electrode 72 disposed on the first main surface 3. The anode electrode 72 may also be referred to as a "first main surface 3 electrode," a "first terminal (electrode)," a "first pad (electrode)," or the like. The anode electrode 72 is disposed at a distance from the periphery of the first main surface 3. The anode electrode 72 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the first main surface 3 in a plan view.

[0374] The anode electrode 72 extends into the contact opening 71 from above the interlayer film 47 and is mechanically and electrically connected to the first main surface 3 within the contact opening 71. Specifically, the anode electrode 72 is mechanically and electrically connected to the second layer 9, the plurality of second regions 12, and the guard region 70. The anode electrode 72 forms a Schottky junction with the second layer 9 in a region between the plurality of second regions 12.

[0375] This forms a diode structure including the anode electrode 72 as an anode region and the second layer 9 as a cathode region. In this embodiment, the diode structure is a Schottky barrier diode structure. The second regions 12 may form a JBS structure (Junction Barrier Schottky structure) together with the second layer 9.

[0376] When multiple second regions 12 are formed at intervals in the thickness direction from the first main surface 3, the anode electrode 72 may be mechanically and electrically connected to the second layer 9 and the guard region 70 within the contact opening 71.

[0377] The semiconductor device 1G includes the aforementioned cathode electrode 73 disposed on the second main surface 4. In this embodiment, the cathode electrode 73 is formed as a cathode electrode 73. The cathode electrode 73 may also be referred to as a "second main surface 4 electrode," a "second terminal (electrode)," a "second pad (electrode)," or the like. The cathode electrode 73 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).

[0378] The cathode electrode 73 may cover an inner portion of the second main surface 4 at a distance from the periphery of the second main surface 4, leaving the periphery of the second main surface 4 exposed. The cathode electrode 73 is mechanically and electrically connected to the base layer 6. The cathode electrode 73 forms an ohmic contact with the base layer 6. The cathode electrode 73, together with the anode electrode 72, forms a current path through the chip 2.

[0379] The breakdown voltage that can be applied between the anode electrode 72 and the cathode electrode 73 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0380] Modifications applied to the second to sixth embodiments are shown below. Fig. 36 is a cross-sectional view showing a modification applied to any one of the semiconductor devices 1A to 1F according to the second to sixth embodiments. Referring to Fig. 36, the semiconductor devices 1A to 1F may include embedded insulators 39 protruding above the height position of the first main surface 3. The multiple embedded insulators 39 expose multiple source regions 40 and multiple contact regions 41 above the first main surface 3.

[0381] In this embodiment, the plurality of source openings 48 are defined in regions between the plurality of buried insulators 39 on the first main surface 3. The source electrodes 50 (base electrode 51 and body electrode 52) extend from above the interlayer film 47 into the plurality of source openings 48 and are electrically connected to the plurality of source regions 40 and the plurality of contact regions 41 within the plurality of source openings 48.

[0382] The above-described embodiments (including modifications) can be implemented in other forms. For example, the above-described first region 11 may extend in a direction intersecting both the a-axis and m-axis directions of the SiC single crystal. In this case, the second region 12 may be perpendicular to the first region 11. The second region 12 may extend in either the a-axis or m-axis direction of the SiC single crystal. The first region 11 may extend in either the a-axis or m-axis direction, and the second region 12 may extend in a direction intersecting both the a-axis and m-axis directions of the SiC single crystal.

[0383] The features of the semiconductor devices 1A to 1G according to the first to seventh embodiments can be combined as appropriate. Therefore, the semiconductor devices 1A to 1G may include any two, three, four, five, six, seven, eight, or nine of the features of the semiconductor devices 1A to 1G.

[0384] In each of the above-described embodiments, an example has been shown in which the trench type transistor structure, the planar type transistor structure, and the diode structure are formed on separate chips 2 (first main surface 3). However, the trench type transistor structure, the planar type transistor structure, and the diode structure may be fabricated on a common chip 2 (first main surface 3).

[0385] A structure including both a trench type transistor structure and a planar type transistor structure may be employed. A structure including both a trench type transistor structure and a diode structure may be employed. A structure including both a planar type transistor structure and a diode structure may be employed. A structure including all of a trench type transistor structure, a planar type transistor structure, and a diode structure may be employed.

[0386] In each of the above-described embodiments, a structure in which the conductivity type of the n-type semiconductor region is inverted to p-type and the conductivity type of the p-type semiconductor region is inverted to n-type may be adopted. A specific configuration in this case can be obtained by replacing n-type with p-type and p-type with n-type in the above description and accompanying drawings.

[0387] In each of the above-described embodiments, the base layer 6 is of n-type. However, the conductivity type of the base layer 6 may be p-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure.

[0388] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," etc., as necessary.

[0389] [A1] A semiconductor layer (7-9) of a first conductivity type (n-type / p-type) having a main surface (3), a first region (11) of a second conductivity type (p-type / n-type) extending in a first direction (X / Y) along the main surface (3) within the semiconductor layer (7-9), and a second region (11) of a second conductivity type (p-type / n-type) formed in a region on the main surface (3) side with respect to the first region (11) within the semiconductor layer (7-9) and extending in a second direction along the main surface (3) so as to intersect the first region (11) in a three-dimensional manner. A semiconductor device (1A to 1G) comprising: a second region (12) of a second conductivity type (p-type / n-type) extending in a direction (Y / X); and a low concentration region (13) of the second conductivity type (p-type / n-type) formed in the semiconductor layer (7 to 9) at least at an intersection of the first region (11) and the second region (12), and having a concentration lower than both the maximum concentration value of the first region (11) and the maximum concentration value of the second region (12).

[0390] [A2] The semiconductor device (1A to 1G) according to A1, wherein the semiconductor layers (7 to 9) contain SiC.

[0391] [A3] The semiconductor device (1A to 1G) according to A2, wherein the SiC is a hexagonal crystal.

[0392] [A4] The semiconductor device (1A to 1G) described in A3, wherein the first direction (X / Y) is one of the a-axis direction and the m-axis direction of the SiC, and the second direction (Y / X) is the other of the a-axis direction and the m-axis direction of the SiC.

[0393] [A5] The semiconductor device (1A to 1G) according to any one of A1 to A4, wherein the semiconductor layers (7 to 9) have an off-axis angle.

[0394] [A6] The semiconductor device (1A to 1G) according to any one of A1 to A5, wherein the second direction (Y / X) is orthogonal to the first direction (X / Y).

[0395] [A7] A semiconductor device (1A to 1G) according to any one of A1 to A6, wherein the concentration of the low concentration region (13) is lower than both the concentration of the middle part of the first region (11) and the concentration of the middle part of the second region (12).

[0396] [A8] A semiconductor device (1A to 1G) according to any one of A1 to A7, wherein the low concentration region (13) forms a first concentration transition portion (14) in which the concentration gradually decreases from the first region (11) at the intersection, and a second concentration transition portion (15) in which the concentration gradually increases toward the second region (12).

[0397] [A9] The semiconductor device (1A to 1G) according to any one of A1 to A8, wherein the low concentration region (13) is also formed in a region other than the intersection.

[0398] [A10] The semiconductor device (1A to 1G) according to any one of A1 to A9, wherein the low concentration region (13) has a portion extending in the first direction (X / Y) following the first region (11).

[0399] [A11] The semiconductor device (1A to 1G) according to any one of A1 to A10, wherein the low concentration region (13) has a portion extending in the second direction (Y / X) following the second region (12).

[0400] [A12] A semiconductor device (1A to 1G) according to any one of A1 to A11, wherein the first region (11) extends vertically in the thickness direction of the semiconductor layers (7 to 9), and the second region (12) extends vertically in the thickness direction of the semiconductor layers (7 to 9).

[0401] [A13] The semiconductor device (1A to 1G) according to any one of A1 to A12, wherein the first region (11) has a width of 10 μm or less, and the second region (12) has a width of 10 μm or less.

[0402] [A14] A semiconductor device (1A to 1G) according to any one of A1 to A13, wherein a plurality of the first regions (11) are formed in stripes extending in the first direction (X / Y), a plurality of the second regions (12) are formed in stripes extending in the second direction (Y / X) so as to intersect with a plurality of the first regions (11), and a plurality of the low concentration regions (13) are formed at a plurality of the intersections.

[0403] [A15] A semiconductor device (1A to 1G) according to A14, wherein the plurality of first regions (11) form a first super junction structure (SJ1) together with the semiconductor layers (7 to 9), and the plurality of second regions (12) form a second super junction structure (SJ2) together with the semiconductor layers (7 to 9).

[0404] [A16] The semiconductor device (1A to 1G) according to any one of A1 to A15, further including a field effect transistor structure formed on the main surface (3).

[0405] [A17] The semiconductor device (1A to 1G) according to A16, wherein the transistor structure includes a trench-type gate structure (35) formed on the main surface (3).

[0406] [A18] The semiconductor device (1A to 1G) according to A16, wherein the transistor structure includes a planar gate structure (65) formed on the main surface (3).

[0407] [A19] The semiconductor device (1A to 1G) according to any one of A1 to A18, further including a diode structure formed on the main surface (3).

[0408] [A20] The semiconductor device (1A to 1G) according to any one of A1 to A19, further comprising an electrode (50, 53, 54, 72) covering the main surface (3).

[0409] Although specific embodiments have been described in detail above, these are merely examples that clarify the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc. [Explanation of symbols]

[0410] 1A Semiconductor Device 1B Semiconductor Devices 1C Semiconductor Device 1D Semiconductor Device 1E Semiconductor Devices 1F Semiconductor equipment 1G Semiconductor Devices 2 chips 3 First main surface 7 Semiconductor layer 8. First layer (semiconductor layer) 9 Second layer (semiconductor layer) 11 First area 12 Second area 13 Low concentration area 14 1st concentration transition part 15 Second concentration transition part 35 Gate Structure 50 Source electrode 53 gate electrode 54 Gate finger electrode 65 Gate Structure 72 Anode electrode SJ1 First Superjunction Structure SJ2 Second Superjunction Structure

Claims

1. a first conductivity type semiconductor layer having a major surface; a first region of a second conductivity type extending in a first direction along the major surface within the semiconductor layer; a second region of a second conductivity type formed in a region on the main surface side of the semiconductor layer relative to the first region and extending in a second direction along the main surface so as to intersect the first region in a three-dimensional manner; a low concentration region of a second conductivity type formed in the semiconductor layer at least at an intersection of the first region and the second region, the low concentration region having a concentration lower than both the maximum concentration value of the first region and the maximum concentration value of the second region.

2. The semiconductor device according to claim 1 , wherein the semiconductor layer includes SiC.

3. The semiconductor device according to claim 2 , wherein the SiC is a hexagonal crystal.

4. the first direction is one of the a-axis direction and the m-axis direction of the SiC, The semiconductor device according to claim 3 , wherein the second direction is the other of the a-axis direction and the m-axis direction of the SiC.

5. The semiconductor device according to claim 1 , wherein the semiconductor layer has an off-axis angle.

6. The semiconductor device according to claim 1 , wherein the second direction is perpendicular to the first direction.

7. 2. The semiconductor device according to claim 1, wherein the concentration of said low concentration region is lower than both the concentration of an intermediate portion of said first region and the concentration of an intermediate portion of said second region.

8. 2. The semiconductor device according to claim 1, wherein the low concentration region forms a first concentration transition portion at the intersection where the concentration gradually decreases from the first region, and a second concentration transition portion at the intersection where the concentration gradually increases toward the second region.

9. 2. The semiconductor device according to claim 1, wherein said low concentration region is also formed in a region other than said intersection.

10. 2. The semiconductor device according to claim 1, wherein said low concentration region has a portion extending in said first direction along said first region.

11. 2. The semiconductor device according to claim 1, wherein said low concentration region has a portion extending in said second direction following said second region.

12. the first region extends longitudinally in the thickness direction of the semiconductor layer, The semiconductor device according to claim 1 , wherein said second region extends vertically in a thickness direction of said semiconductor layer.

13. the first region has a width of 10 μm or less; The semiconductor device according to claim 1 , wherein said second region has a width of 10 μm or less.

14. The first regions are formed in stripes extending in the first direction, a plurality of the second regions are formed in stripes extending in the second direction so as to intersect with a plurality of the first regions; 2. The semiconductor device according to claim 1, wherein a plurality of said low concentration regions are formed at a plurality of said intersections.

15. the plurality of first regions form a first superjunction structure with the semiconductor layer; The semiconductor device according to claim 14 , wherein the plurality of second regions form a second superjunction structure with the semiconductor layer.

16. 16. The semiconductor device according to claim 1, further comprising a field effect transistor structure formed on said main surface.

17. 17. The semiconductor device according to claim 16, wherein said transistor structure includes a trench-type gate structure formed in said main surface.

18. 17. The semiconductor device according to claim 16, wherein said transistor structure includes a planar gate structure formed on said main surface.

19. 16. The semiconductor device according to claim 1, further comprising a diode structure formed on the main surface.

20. 16. The semiconductor device according to claim 1, further comprising an electrode covering said main surface.

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