Liquid crystal display device and control method

Abstract

To provide technology that makes it possible to reduce power consumption in a liquid crystal display device.SOLUTION: A polarity switching control circuit 14 establishes electrical continuity to a first switch S1 intermittently for a prescribed unit period in a first period out of a vertical scanning period, establishes electrical continuity to a second switch S2 intermittently for a prescribed unit period in a second period following the first period, and intermittently flows a bias current to a first buffer circuit B1 and a second buffer circuit B2 in synchronism with electrical continuity to the first switch S1 and the second switch S2. In each of the first period and the second period, the bias current is made a reference value in some of a plurality of unit periods, and the bias current is reduced from the reference value in the remaining unit periods.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device and a control method. [Background technology]

[0002] Patent Document 1 discloses a liquid crystal display device that alternately applies a positive video signal held in a storage capacitor and a negative video signal held in another storage capacitor to pixel drive electrodes of a liquid crystal element by switching between these signals at a predetermined cycle shorter than the vertical scanning period. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-223289 Summary of the Invention [Problem to be solved by the invention]

[0004] In a liquid crystal display device that switches between a positive polarity video signal and a negative polarity video signal multiple times within a vertical scanning period, it is desirable to reduce power consumption.

[0005] The present invention has been made in view of the above circumstances, and its object is to provide a technique that can reduce power consumption in a liquid crystal display device. [Means for solving the problem]

[0006] In order to solve the above problem, a liquid crystal display device according to one embodiment of the present invention includes a plurality of pixels provided at intersections where a plurality of sets of data lines, each set consisting of two data lines, intersect with a plurality of gate lines; a plurality of sets of selection switches provided for each of the plurality of sets of data lines, the selection switches supplying a positive polarity video signal to one of the two data lines of a set and a negative polarity video signal to the other data line in sequence for the plurality of sets of data lines in set units; a horizontal drive circuit that sequentially drives the plurality of sets of selection switches in set units within a horizontal scanning period; a vertical drive circuit that sequentially drives the plurality of gate lines for each horizontal scanning period; and a polarity switching control circuit. Each of the plurality of pixels has a liquid crystal element in which a liquid crystal layer is sandwiched between opposing pixel drive electrodes and a common electrode, a first holding unit that samples and holds a positive video signal of a corresponding data line, a first buffer circuit that receives the positive video signal held in the first holding unit, a first switch that, when conductive, applies the positive video signal output from the first buffer circuit to the pixel drive electrode, a second holding unit that samples and holds a negative video signal of the corresponding data line, a second buffer circuit that receives the negative video signal held in the second holding unit, and a second switch that, when conductive, applies the negative video signal output from the second buffer circuit to the pixel drive electrode. The polarity switching control circuit intermittently turns on the first switch for each predetermined unit period during a first period of the vertical scanning period, and intermittently turns on the second switch for each unit period during a second period following the first period of the vertical scanning period, and intermittently passes a bias current through the first buffer circuit and the second buffer circuit in synchronization with the conduction of the first switch and the second switch, and in each of the first and second periods, sets the bias current to a reference value during some of the multiple unit periods, and reduces the bias current below the reference value during the remaining unit periods.

[0007] Another aspect of the present invention is a control method for a liquid crystal display device, the control method including: a plurality of pixels provided at intersections of a plurality of sets of data lines, each set consisting of two data lines, and a plurality of gate lines; a plurality of sets of selection switches provided for each of the plurality of sets of data lines, the selection switches supplying a positive polarity video signal to one of the two data lines of each set and a negative polarity video signal to the other data line in sequence for the plurality of sets of data lines; a horizontal drive circuit sequentially driving the plurality of sets of selection switches in sequence for each set within a horizontal scanning period; and a vertical drive circuit sequentially driving the plurality of gate lines in each horizontal scanning period. Each of the plurality of pixels includes a liquid crystal element having a liquid crystal layer sandwiched between opposing pixel drive electrodes and a common electrode, a first holding unit that samples and holds a positive video signal of a corresponding data line, a first buffer circuit that receives the positive video signal held in the first holding unit, a first switch that, when conductive, applies the positive video signal output from the first buffer circuit to the pixel drive electrode, a second holding unit that samples and holds a negative video signal of the corresponding data line, a second buffer circuit that receives the negative video signal held in the second holding unit, and a second switch that, when conductive, applies the negative video signal output from the second buffer circuit to the pixel drive electrode. The control method includes the steps of intermittently turning on the first switch every predetermined unit period during a first period of a vertical scanning period, intermittently turning on the second switch every unit period during a second period of the vertical scanning period following the first period of the vertical scanning period, and intermittently flowing a bias current through the first buffer circuit and the second buffer circuit in synchronization with the conduction of the first switch and the second switch. In each of the first period and the second period, the bias current is set to a reference value in some of the unit periods among the plurality of unit periods, and the bias current is reduced below the reference value in the remaining unit periods.

[0008] Any combination of the above components, and any transformation of the present invention into a method, device, system, recording medium, computer program, etc., are also valid aspects of the present invention. [Effects of the Invention]

[0009] According to the present invention, it is possible to reduce power consumption in a liquid crystal display device. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal display device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a first buffer circuit in FIG. [Figure 3] FIG. 10 is a timing chart for explaining the operation of a liquid crystal display device of a comparative example. [Figure 4] FIG. 2 is a timing chart for explaining the operation of the liquid crystal display device of FIG. [Figure 5] 2 is a diagram illustrating a functional configuration of the polarity switching control circuit of FIG. 1. FIG. [Figure 6] FIG. 10 is a timing chart for explaining the operation of the liquid crystal display device according to the second embodiment. [Figure 7] FIG. 10 is a diagram illustrating a functional configuration of a polarity switching control circuit according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and duplicate descriptions will be omitted as appropriate.

[0012] (First embodiment) FIG. 1 shows a schematic configuration of a liquid crystal display device 100 according to a first embodiment. The liquid crystal display device 100 includes a plurality of pixels P 11 ,P 12 ,P 21 ,P 22 ,···,P nm (n and m are natural numbers), multiple sets of selection switches S+1, S-1, S+2, S-2, . . ., S+ m ,S- m , a horizontal drive circuit 10 , a vertical drive circuit 12 , a polarity switching control circuit 14 , and a controller 16 .

[0013] Multiple pixels P 11 ,···,P nm are arranged in a matrix. "n" represents the number of pixels in the vertical direction (also called the column direction). "m" represents the number of pixels in the horizontal direction (also called the row direction). "n" and "m" are determined appropriately according to the resolution of the liquid crystal display device 100. For example, "n" may be 720 and "m" may be 1280. In FIG. 1, four pixels P 11 ,P 12 ,P 21 ,P 22 1 shows only the four pixels, and the other pixels are not shown. Also, the wiring etc. connected to the multiple pixels are shown only to the four pixels, and the other wiring etc. are not shown. Figure 1 also shows a schematic layout of the pixels and wiring.

[0014] The first row contains multiple pixels P 11 ,P 12 ,···,P 1m In the second row, a plurality of pixels P 21 ,P 22 ,···,P 2m In the i-th row (i is an integer from 1 to n), a plurality of pixels P i1 ,P i2 ,···,P im are placed.

[0015] Two data lines d+ j ,d- j (j is an integer from 1 to m) is a set of m data lines d+1, d-1, d+2, d-2, . . . , d+ m ,d- m extend in the column direction and are arranged in the row direction. n The pixels P extend in the row direction and are arranged in the column direction. 11 ,···,P nm is m sets of data lines d+1, d-1, . . . , d+ m ,d- m and n gate lines gat1, , gat n and are provided at the intersections where they intersect.

[0016] Two selection switches S+ j ,S- j m sets of selection switches S+1, S-1, . . . , S+ (j is an integer from 1 to m) m ,S- m is m sets of data lines d+1, d-1, . . . , d+ m ,d- m m sets of selection switches S+1, S-1, . . . , S+ m ,S- m supplies a positive video signal input to the positive signal line vs+ to one of a set of two data lines, and supplies a negative video signal input to the negative signal line vs- to the other data line, and this is done sequentially for m sets of data lines in units of sets.

[0017] The horizontal drive circuit 10 includes m sets of selection switches S+1, S-1, . . . , S+ m ,S- m The vertical direction driving circuit 12 sequentially drives and turns on the n gate lines gat1, . . . , gat n are sequentially driven for each horizontal scanning period.

[0018] The controller 16 generates various clock signals synchronized with the positive video signal input to the positive signal line vs+ and the negative video signal input to the negative signal line vs- and supplies them to the horizontal drive circuit 10, vertical drive circuit 12, and polarity switching control circuit 14 (paths not shown). The controller 16 drives the data lines and gate lines in synchronization with the positive video signal and negative video signal, respectively, thereby selecting pixels with horizontal and vertical scanning. Known techniques can be used to drive the data lines and gate lines, so further detailed explanation will be omitted.

[0019] Multiple pixels P 11 ,···,P nmEach of the pixels P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P40, P41, P42, P43, P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, P56, P57, P58, P59, P60, P61, P62, P63, P64, P65, P66, ij This article explains:

[0020] The liquid crystal element 20 has a configuration in which a liquid crystal layer LC is sandwiched between a pixel drive electrode (also called a reflective electrode) PE and a common electrode CE that face each other. A common voltage Vcom is supplied from the controller 16 to the common electrode CE.

[0021] The first holding unit A1 has a pixel selection transistor Q1 and a holding capacitor C1. The gate of the pixel selection transistor Q1 is connected to a corresponding gate line gat i The drain of the pixel selection transistor Q1 is connected to the corresponding data line d+ j One end of the storage capacitor C1 is connected to the source of the pixel selection transistor Q1, and the other end of the storage capacitor C1 is connected to the ground GND. i When activated, the pixel selection transistor Q1 conducts and the corresponding data line d+ j The positive polarity video signal is sampled and stored in the storage capacitor C1.

[0022] The input terminal "in" of the first buffer circuit B1 is connected to the connection node between the pixel selection transistor Q1 and the storage capacitor C1. The first buffer circuit B1 receives the positive polarity video signal held in the first storage unit A1, performs impedance conversion, and outputs the received positive polarity video signal. As will be described later, the first buffer circuit B1 has a corresponding bias line b i The bias current is controlled in response to the bias voltage received from the

[0023] One end of the first switch S1 is connected to the output terminal out of the first buffer circuit B1. The other end of the first switch S1 is connected to the pixel driving electrode PE. The first switch S1 is connected to the corresponding control signal line s+. iThe first switch S1 is turned on or off in response to a gate control signal received from the first buffer circuit B1. When turned on, the first switch S1 applies a positive video signal output from the first buffer circuit B1 to the pixel drive electrode PE. The first switch S1 can be configured with a transistor.

[0024] The second holding unit A2 has a pixel selection transistor Q2 and a holding capacitor C2. The gate of the pixel selection transistor Q2 is connected to the corresponding gate line gat i The drain of the pixel selection transistor Q2 is connected to the corresponding data line d- j One end of the storage capacitor C2 is connected to the source of the pixel selection transistor Q2, and the other end of the storage capacitor C2 is connected to the ground GND. i When the pixel select transistor Q2 is driven, the pixel select transistor Q2 is turned on and the corresponding data line d- j The negative video signal is sampled and stored in the storage capacitor C2.

[0025] The input terminal "in" of the second buffer circuit B2 is connected to the connection node between the pixel selection transistor Q2 and the storage capacitor C2. The second buffer circuit B2 receives the negative video signal held in the second storage unit A2, performs impedance conversion, and outputs the received negative video signal. As will be described later, the second buffer circuit B2 has a corresponding bias line b i The bias current is controlled in response to the bias voltage received from the

[0026] One end of the second switch S2 is connected to the output terminal out of the second buffer circuit B2, and the other end of the second switch S2 is connected to the pixel driving electrode PE. The second switch S2 is connected to the corresponding control signal line s- i The second switch S2 is turned on or off in response to a gate control signal received from the second buffer circuit B2. When turned on, the second switch S2 applies a negative video signal output from the second buffer circuit B2 to the pixel drive electrode PE. The second switch S2 can be configured with a transistor.

[0027] The storage capacitor C3 is connected between the common connection node of the other end of the first switch S1 and the other end of the second switch S2 and the ground GND. The storage capacitor C3 is a capacitor for driving the liquid crystal.

[0028] Fig. 2 is a circuit diagram of the first buffer circuit B1 in Fig. 1. The first buffer circuit B1 and the second buffer circuit B2 have the same circuit configuration. Here, the first buffer circuit B1 of the pixel in the i-th row will be described.

[0029] The first buffer circuit B1 includes a transistor Q3 and a transistor Q4. The transistors Q3 and Q4 form a source follower circuit for impedance conversion. The transistors Q3 and Q4 are PMOS transistors. The source follower circuit may also be formed of an NMOS transistor.

[0030] A signal input to the gate of the transistor Q3 is level-shifted and output from the source of the transistor Q3, the drain of which is connected to ground GND.

[0031] The transistor Q4 functions as a constant current source. The drain of the transistor Q4 is connected to the source of the transistor Q3, and the power supply voltage VDD is supplied to the source of the transistor Q4. The gate of the transistor Q4 is connected to the corresponding bias line b i Connected to bias line b i When the voltage on the bias line b is a predetermined bias voltage lower than the power supply voltage VDD, the transistor Q4 passes a predetermined constant current corresponding to the bias voltage as a bias current to the source follower circuit. i When the voltage at the output terminal of the transistor Q4 is the power supply voltage VDD, the transistor Q4 does not conduct bias current.

[0032] The input impedance of this source follower circuit is almost infinite, so the charges stored in the storage capacitors C1 and C2 are retained without leaking until a new signal is written one vertical scanning period later.

[0033] Next, we will explain the operation of the liquid crystal display device 100. A positive video signal is supplied to the positive signal line vs+ and a negative video signal is supplied to the negative signal line vs- from a video signal generation circuit (not shown) external to the liquid crystal display device 100. The positive video signal is a voltage on the positive side with respect to the common voltage Vcom, and the negative video signal is a voltage on the negative side with respect to the common voltage Vcom.

[0034] The vertical direction driving circuit 12 drives the gate line gat1 in the first horizontal scanning period of the current frame, and 11 ,···,P 1m The pixel selection transistors Q1 and Q2 are made conductive.

[0035] The horizontal driving circuit 10 turns on the selection switches S+1 and S-1 during the first horizontal scanning period, supplies a positive video signal from the positive signal line vs+ to the data line d+1, and supplies a negative video signal from the negative signal line vs- to the data line d-1.

[0036] As a result, the positive video signal supplied from the data line d+1 is 11 In parallel with this, a negative video signal supplied from the data line d-1 is written into the storage capacitor C1 through the pixel selection transistor Q1 at the pixel P 11 is written into the storage capacitor C2 via the pixel selection transistor Q2.

[0037] Subsequently, in the first horizontal scanning period, the remaining pixels P 12 ,···,P 1m Similarly, a positive video signal and a negative video signal are written sequentially into the respective holding capacitors C1 and C2.

[0038] Next, when the first horizontal scanning period ends, the vertical direction driving circuit 12 stops driving the gate line gat1, and the pixel P 11 ,···,P 1m This turns off the pixel selection transistors Q1 and Q2 of the first row of pixels P 11 ,···,P1m In each of the rows, the positive and negative video signals are held in the storage capacitors C1 and C2, respectively, until the video signals are written in the first horizontal scanning period of the next frame when the pixel selection transistors Q1 and Q2 are next turned on. Positive and negative video signals are written sequentially and held in the same manner for the plurality of pixels in the second and subsequent rows.

[0039] The positive video signal held in the holding capacitor C1 is read out via the first buffer circuit B1, selected by the first switch S1, and applied to the pixel drive electrode PE. Meanwhile, the negative video signal held in the holding capacitor C2 is read out via the second buffer circuit B2, selected by the second switch S2 exclusively from the selection by the first switch S1, and applied to the pixel drive electrode PE. This causes the drive voltage Vpe of the pixel drive electrode PE to be changed between positive and negative with respect to the common voltage Vcom, thereby AC-driving the liquid crystal element 20.

[0040] With this configuration, once a positive video signal and a negative video signal are written to the storage capacitors C1 and C2 in each pixel once per frame, the first switch S1 and the second switch S2 can be switched any number of times to AC-drive the liquid crystal element 20 during the period until the positive video signal and negative video signal of the next frame are written.

[0041] In other words, the liquid crystal element 20 can be AC-driven at a frequency higher than the vertical scanning frequency, independently of the video signal write cycle. This provides benefits such as preventing burn-in, improving reliability, and improving display quality. In addition, the common voltage Vcom of the liquid crystal element 20 can be changed in accordance with the polarity reversal of the drive voltage Vpe, allowing the voltage of the video signal to be reduced.

[0042] To reduce current consumption, pulse driving is performed, enabling the first buffer circuit B1, the second buffer circuit B2, the first switch S1, and the second switch S2 only for the period required for signal readout. A storage capacitor C3 is provided for this operation, and during the enable period, the video signal that passes through the conductive first switch S1 or the second switch S2 is written to the storage capacitor C3. When neither switch is conductive, the written video signal is held in the storage capacitor C3 while the liquid crystal element 20 is driven. This allows the liquid crystal element 20 to be AC-driven at a frequency higher than the vertical scanning frequency while suppressing a significant increase in power consumption.

[0043] Here, AC drive control of a liquid crystal display device of a comparative example recognized by the present inventors will be described. The liquid crystal display device of the comparative example has the same configuration as the liquid crystal display device 100 of Fig. 1, but the control is different.

[0044] 3 is a timing chart for explaining the operation of the liquid crystal display device of the comparative example. The following explanation will be given using the configuration of FIG. 1. 11 3 shows signal waveforms relating to the vertical synchronization signal, the bias voltage of the bias line b1, the gate control signal of the control signal line s+1, the gate control signal of the control signal line s-1, the drive voltage Vpe of the pixel drive electrode PE, and the common voltage Vcom.

[0045] The bias voltage of the bias line b1 drops in a pulsed manner for each horizontal scanning period indicated by "1H" in Figure 3. The horizontal scanning period is from time t1 to time t2. As a result, a pulsed constant current flows intermittently in the source follower circuits of the first buffer circuit B1 and the second buffer circuit B2 for each horizontal scanning period. Note that the width of each pulse is exaggerated in Figure 3 for clarity.

[0046] From time t1 to time t3, the gate control signal of the control signal line s+1 rises to a high level in pulses every horizontal scanning period in synchronization with the bias voltage pulse of the bias line b1, while the gate control signal of the control signal line s-1 remains at a low level, so that from time t1 to time t3, the drive voltage Vpe becomes the voltage of the positive polarity video signal.

[0047] From time t3 to time t4, the gate control signal of control signal line s+1 remains low, and the gate control signal of control signal line s-1 rises to a high level in pulses every horizontal scanning period in synchronization with the bias voltage pulse of bias line b1. As a result, from time t3 to time t4, the drive voltage Vpe becomes the voltage of the negative video signal. After time t4, the operation from time t1 to time t4 is repeated.

[0048] In the comparative example, a constant current flows intermittently in the source follower circuits of the first buffer circuit B1 and the second buffer circuit B2 for each horizontal scanning period. Therefore, the current consumption in the comparative example is relatively large. The inventors recognized that there is room for reducing the current consumption. Therefore, in the first embodiment, AC drive is used to reduce the current consumption, as described below.

[0049] 4 is a timing chart for explaining the operation of the liquid crystal display device 100 of FIG. 11 4 shows signal waveforms for the vertical synchronization signal, the bias voltage of the bias line b1, the gate control signal of the control signal line s+1, the gate control signal of the control signal line s-1, the drive voltage Vpe of the pixel drive electrode PE, and the common voltage Vcom, just like in FIG.

[0050] In FIG. 4, the bias voltage of the bias line b1 differs from that of the comparative example in FIG. 3. After time t1, time t3, and time t4, the bias voltage of the bias line b1 drops less from the power supply voltage VDD during the fifth through twelfth pulses than during the first through fourth pulses. Because the bias voltage drop is small, the current flowing through the transistor Q4 of the source follower circuit in FIG. 2 at these times is smaller than the reference value. The bias currents of the source follower circuits of multiple pixels account for a relatively large proportion of the total current consumption of the liquid crystal display device 100. Because the bias currents of the source follower circuits corresponding to the fifth and subsequent pulses are smaller than the reference value, the total current consumption of the liquid crystal display device 100 can be reduced.

[0051] When the bias current of the source follower circuit becomes small, the output voltages of the first buffer circuit B1 and the second buffer circuit B2 change, but this change is so slight that it does not affect the operation.

[0052] Furthermore, even if the bias current of the source follower circuit is reduced, the drive voltage Vpe can be kept approximately constant during each of the first period T1 and the second period T2 due to the storage capacitor C3.

[0053] The polarity switching control circuit 14 supplies a gate control signal of multiple pulses to the control signal line s+1 during a first period T1 of the vertical scanning period, thereby intermittently turning on the first switch S1 for each predetermined unit period. 11 ,···,P 1m In each of these, the first switch S1 is intermittently turned on at the same timing. Hereinafter, the unit period is, for example, a horizontal scanning period. Using the horizontal scanning period makes timing design easier. In the example of FIG. 4, the first period T1 is 12 times as long as the horizontal scanning period, but this is not limited to this. The pulse width of the gate control signal, the length of the first period T1, and the length of the unit period can be determined as appropriate through experiments or simulations.

[0054] During a second period T2 following a first period T1 of the vertical scanning period, the polarity switching control circuit 14 supplies a gate control signal of multiple pulses to the control signal line s-1 to intermittently turn on the second switch S2 for each unit period. 11 ,···,P 1m In each of the first and second periods T1 and T2, the second switch S2 is intermittently turned on at the same timing. The second period T2 has the same length as the first period T1. The vertical scanning period includes a plurality of first periods T1 and a plurality of second periods T2. The first periods T1 and the second periods T2 are alternately arranged.

[0055] The polarity switching control circuit 14 supplies a bias voltage that drops in a pulsed manner to the bias line b1 in synchronization with the conduction of the first switch S1 or the second switch S2, and causes a pulsed bias current to flow intermittently through the first buffer circuit B1 and the second buffer circuit B2. 11 ,···,P 1m In each of the first period T1 and the second period T2, the bias current flows intermittently at the same timing. In some of the unit periods in each of the first period T1 and the second period T2, the polarity switching control circuit 14 sets the bias current of the first buffer circuit B1 and the second buffer circuit B2 to a reference value, and reduces the bias current below the reference value in the remaining unit periods.

[0056] The partial unit periods in the first period T1 are two or more consecutive unit periods from the first unit period in the first period T1, i.e., four unit periods in the example of FIG. 4 . The partial unit periods in the second period T2 are two or more consecutive unit periods from the first unit period in the second period T2, i.e., four unit periods in the example of FIG. 4 . The number of partial unit periods can be determined appropriately through experiments or simulations. That is, at the beginning of the first period T1, a positive video signal is applied to the pixel drive electrode PE multiple times in succession while the driving capability of the first buffer circuit B1 is relatively high, and at the beginning of the second period T2, a negative video signal is applied to the pixel drive electrode PE multiple times in succession while the driving capability of the second buffer circuit B2 is relatively high. This allows the storage capacitor C3 to be appropriately charged.

[0057] Although not shown in the figure, the polarity switching control circuit 14 may supply a pulsed gate control signal to the control signal line s+2 so that the pulse rises immediately after the fall of the pulse of the control signal line s+1 in each unit period of the first period T1, and the plurality of pixels P 21 ,···,P 2m For each of the pixels in the nth row, the first switch S1 may be intermittently turned on for each unit period. That is, the turn-on period of the first switch S1 in the second row may begin immediately after the end of the turn-on period of the first switch S1 in the first row. Similarly, in each unit period of the second period T2, the turn-on period of the second switch S2 in the second row may begin immediately after the end of the turn-on period of the second switch S2 in the first row. Similarly, in each unit period of the first period T1 and the second period T2, the period in which bias current flows in the second row may begin immediately after the end of the period in which bias current flows in the first buffer circuit B1 and the second buffer circuit B2 in the first row. Similar control may be performed for multiple pixels in the third row and beyond. For example, in the horizontal scanning period from time t1 to time t2, the time when the turn-on period of the first switch S1 in the nth row ends and the period in which bias current flows in the nth row ends may be before time t2, for example, approximately 1 / 2 to 1 / 3 of the horizontal scanning period. Other horizontal scanning periods may also be controlled in a similar manner.

[0058] Therefore, in each unit period of the first period T1, the conduction period of the first switch S1 may differ for each row, and the first switches S1 in different rows may not be conductive at the same time. In each unit period of the second period T2, the conduction period of the second switch S2 may differ for each row, and the second switches S2 in different rows may not be conductive at the same time. In each unit period of the first period T1 and the second period T2, the period during which bias current flows in the first buffer circuit B1 and the second buffer circuit B2 may differ for each row, and the bias current may not flow simultaneously in the first buffer circuit B1 and the second buffer circuit B2 in different rows. In this case, it is possible to prevent the consumption current from increasing unevenly over time.

[0059] According to the embodiment, the current consumption of each pixel can be reduced compared to the comparative example, and therefore the current consumption of the liquid crystal display device 100 can be reduced.

[0060] Fig. 5 shows the functional configuration of the polarity switching control circuit 14 of Fig. 1. The polarity switching control circuit 14 has a start pulse generating section 30, a shift register 32, an output section 34, a switching signal generating section 36, a counter 38, and a control section 40.

[0061] The following description will also refer to FIG. 4 as appropriate. The start pulse generation unit 30 generates a start pulse P for each unit period, and also generates a clock CLK with a predetermined cycle that is significantly shorter than the unit period. The multiple start pulses P are signals in which the multiple pulses of the control signal line s+1 in FIG. 4 are repeated. The start pulse generation unit 30 supplies the generated start pulse P and clock CLK to a shift register 32.

[0062] The shift register 32 shifts the received start pulse P for each clock CLK and outputs the shifted pulse. The shift register 32 also shifts the received start pulse P the same number of times as the number of gate lines, i.e., n times, and then outputs an output pulse Po. The shift register 32 supplies the shifted pulse to an output unit 34, and supplies the output pulse Po to a clock terminal of a counter 38.

[0063] The output unit 34 has control signal lines s+1, . . . , s+ n , control signal lines s-1,···,s- n , and bias lines b1, ,b nare connected. The output unit 34 outputs a control signal for the first switch S1 of each of the plurality of pixels, a control signal for the second switch S2, and a control signal for the bias current of the first buffer circuit B1 and the second buffer circuit B2, based on the shifted pulse output from the shift register 32 for each clock CLK. The output unit 34 outputs a pulse of a gate control signal to the control signal line s+1 and a pulse of a bias voltage to the bias line b1 in synchronization with the pulse output from the shift register 32 at the first clock CLK in response to the first start pulse P output at time t1 in FIG. 4. These pulses correspond to the first pulse immediately after time t1 in FIG. 4. Similarly, in synchronization with the pulse output from the shift register 32 at the ith clock CLK, i The gate control signal pulse is output to the bias line b i As mentioned above, the nth row control signal line s+ n and bias wire b n The timing at which the output unit 34 outputs a pulse is before time t2. After this, the output unit 34 does not output a pulse until time t2. Subsequently, at time t2 in FIG. 4, a second start pulse P is output, and the output unit 34 outputs a pulse in the same manner as for the first start pulse P.

[0064] The counter 38 counts the number of output pulses Po of the shift register 32 supplied to the clock terminal, and when the counted number reaches the number of the part of the unit period described above, outputs a control signal Cs to the control unit 40. In other words, n When pulses equal in number to the number of partial unit periods are output in the counter 38, the control signal Cs is output in synchronization with the next clock CLK. In the example of FIG. 4, the number of partial unit periods is "4," and the control signal Cs is output at time t2a, for example. The number of partial unit periods may be changeable by changing the setting of the counter 38 from outside the liquid crystal display device 100. This makes it possible to change the current consumption and display quality according to the situation.

[0065] When the control unit 40 receives the control signal Cs, it outputs an instruction signal to the output unit 34 to decrease the bias current. When the output unit 34 receives the instruction signal from the control unit 40, it outputs a pulse of the bias voltage, the decrease amount of which is decreased, to the bias line b in synchronization with the pulse output from the shift register 32 at the i-th clock CLK in the next unit period or later, so that the bias current decreases below the reference value. i Output to.

[0066] In this way, the counter 38 counts the output pulses Po of the shift register 32. This ensures a sufficient time operating margin for the circuit. That is, in the example of FIG. 4, after time t1, there is a period of time from time t2a, when the fourth output pulse Po is output in response to the fourth start pulse P, to time t2a, when the fifth start pulse P is output. During this period, the output unit 34 can complete control to reduce the amount of reduction in the bias voltage pulse in response to the instruction signal received from the control unit 40, ensuring a sufficient time operating margin. That is, in FIG. 4, immediately after time t2b, when the fifth start pulse P is output, a bias voltage pulse with a reduced amount of reduction can be output to the bias line b1.

[0067] In contrast, consider another comparative example in which the counter 38 counts the number of start pulses P. In this case, when the fifth start pulse P is output at time t2b, the count reaches 5, a control signal Cs is output, and an instruction signal to reduce the bias current is sent to the output unit 34. When the instruction signal is sent, the bias voltage pulse for the bias line b1 immediately after time t2b has already been output. Therefore, the amount of reduction in the pulse for the bias line b1 cannot be reduced, and the bias current for the first buffer circuit B1, etc. in the first row does not decrease. Furthermore, it is possible that control to reduce the amount of reduction in the bias voltage pulses for some of the subsequent bias lines b2, etc., may not be able to be completed in time. In the embodiment, this type of operation can be avoided. Image quality can be maintained while further reducing current consumption.

[0068] The switching signal generator 36 generates a switching signal between positive and negative polarity and supplies it to the reset terminal of the counter 38. At time t3, when a first period T1 has elapsed since time t1 in FIG. 4, the switching signal is supplied to the counter 38. This resets the control signal Cs output from the counter 38. When the control signal Cs is reset, the controller 40 stops outputting the instruction signal for reducing the bias current. When the controller 40 stops supplying the instruction signal, the output unit 34 restores the amount of reduction in the bias voltage pulse so that the bias current returns to the reference value.

[0069] Furthermore, the output unit 34 outputs a gate control signal pulse to the control signal line s-1 and a bias voltage pulse to the bias line b1 in synchronization with the pulse output from the shift register 32 at the first clock CLK in response to the first start pulse P of the second period T2 output at time t3 in FIG. 4. These pulses correspond to the first pulse immediately after time t3 in FIG. 4. Pulses are similarly output after time t3. Furthermore, the switching signal generation unit 36 ​​outputs a switching signal to the counter 38 at time t4. Subsequent operations are similar.

[0070] (Second embodiment) The second embodiment differs from the first embodiment in that no bias current flows through the first buffer circuit and the second buffer circuit during the remaining unit period. The following mainly describes the differences from the first embodiment.

[0071] The configuration of the liquid crystal display device 100 is the same as that of Fig. 1. The control by the polarity switching control circuit 14 differs from that of the first embodiment.

[0072] 6 is a timing chart for explaining the operation of the liquid crystal display device 100 according to the second embodiment, which shows signals corresponding to those in FIG.

[0073] In FIG. 6, the bias voltage of bias line b1, the gate control signal of control signal line s+1, and the gate control signal of control signal line s-1 are different from those in FIG. 4. After time t1, after time t3, and after time t4, the first to fourth pulses are the same as those in FIG. 4, but the difference from FIG. 4 is that there are no pulses from the fifth onward. After the fourth pulse, the bias voltage of bias line b1 remains at the power supply voltage VDD, so no current flows through transistor Q4 of the source follower circuit in FIG. 2. This allows for a reduction in current consumption compared to the first embodiment.

[0074] Even if the bias current of the source follower circuit is stopped, the drive voltage Vpe can be kept approximately constant during each of the first period T1 and the second period T2 by the storage capacitor C3.

[0075] During the first period T1, the polarity switching control circuit 14 supplies a gate control signal of multiple pulses to the control signal line s+1 during some of the multiple unit periods, intermittently turning on the first switch S1 for each unit period, and during the remaining unit periods, does not supply a pulsed gate control signal to the control signal line s+1, turning off the first switch S1.

[0076] In a second period T2 following the first period T1, the polarity switching control circuit 14 supplies a gate control signal of multiple pulses to the control signal line s-1 during some of the multiple unit periods, thereby intermittently turning on the second switch S2 for each unit period, and does not supply a pulsed gate control signal to the control signal line s-1 during the remaining unit periods, thereby turning off the second switch S2.

[0077] In each of the first period T1 and the second period T2, the polarity switching control circuit 14 sets the bias currents of the first buffer circuit B1 and the second buffer circuit B2 to a reference value during some of the multiple unit periods, and does not flow bias currents to the first buffer circuit B1 and the second buffer circuit B2 during the remaining unit periods.

[0078] During each partial unit period of the first period T1, the conduction period of the first switch S1 may differ for each row, and the first switches S1 of different rows may not be conductive at the same time. During each partial unit period of the first period T1, the period during which a bias current flows may differ for each row in the first buffer circuit B1 and the second buffer circuit B2, and the bias current may not flow simultaneously through the first buffer circuit B1 and the second buffer circuit B2 of different rows. During each partial unit period of the second period T2, the conduction period of the second switch S2 may differ for each row, and the second switches S2 of different rows may not be conductive at the same time. During each partial unit period of the second period T2, the period during which a bias current flows may differ for each row in the first buffer circuit B1 and the second buffer circuit B2, and the bias current may not flow simultaneously through the first buffer circuit B1 and the second buffer circuit B2 of different rows.

[0079] 7 shows the functional configuration of the polarity switching control circuit 14 of the second embodiment. In this polarity switching control circuit 14, the functions of the control unit 40 and the start pulse generating unit 30 differ from those of the first embodiment.

[0080] When the control unit 40 receives the control signal Cs because the number of output pulses Po counted by the counter 38 has reached the number of the partial unit periods described above, it outputs a pulse stop instruction signal to the start pulse generating unit 30. As in the first embodiment, the number of the partial unit periods may be changeable by externally changing the settings of the counter 38. This allows the current consumption and the like to be changed according to the situation.

[0081] When the start pulse generating unit 30 receives the instruction signal from the control unit 40, it stops generating and outputting the start pulse P and the clock CLK. As a result, the output unit 34 subsequently outputs the control signal lines s+1, . . . , s+ n , control signal lines s-1,···,s- n , and bias lines b1, ,b n Stops output of pulses to the

[0082] At time t3, when the first period T1 has elapsed since time t1 in FIG. 6, a switching signal is supplied to the counter 38, as in the first embodiment. This resets the control signal Cs output from the counter 38. When the control signal Cs is reset, the control unit 40 stops outputting the instruction signal to stop the pulse. When the supply of the instruction signal from the control unit 40 stops, the start pulse generation unit 30 resumes generating and outputting the start pulse P and the clock CLK.

[0083] The polarity switching control circuit 14 may have a reception unit that receives a user's operational input, and may be able to select either the control mode of the first embodiment or the control mode of the second embodiment in response to the received operational input. In this case, when the control unit 40 receives the control signal Cs in response to the operational input received by the reception unit, the control unit 40 outputs an instruction signal to the output unit 34 to decrease the bias current, or outputs an instruction signal to stop the pulses to the start pulse generation unit 30. This allows the optimum control mode to be selected depending on the situation. The user may switch the control mode, check the display quality of the liquid crystal display device 100, and then decide which control mode to select.

[0084] The present invention has been described above based on the embodiments. These embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the components and treatment processes, and that such modifications are also within the scope of the present invention. [Explanation of symbols]

[0085] 10... horizontal direction drive circuit, 12... vertical direction drive circuit, 14... polarity switching control circuit, 20... liquid crystal element, 30... start pulse generation unit, 32... shift register, 34... output unit, 36... switching signal generation unit, 38... counter, 40... control unit, 100... liquid crystal display device, A1... first holding unit, A2... second holding unit, B1... first buffer circuit, B2... second buffer circuit, C1, C2, C3... holding capacitance, P 11 ,···,P nm …pixels, S+1, S-1,..., S+ m ,S-m …Selection switch, d+1, d-1, . . ., d+ m ,d- m …data lines, gat1,..., gat n ...gate line, Q1, Q2...pixel selection transistor, Q3, Q4...transistor, S1...first switch, S2...second switch.

Claims

1. a plurality of pixels provided at intersections where a plurality of sets of data lines, each set consisting of two data lines, intersect with a plurality of gate lines; a plurality of sets of selection switches provided for the plurality of sets of data lines, each set of selection switches supplying a positive video signal to one of the two data lines of a set and a negative video signal to the other data line, sequentially for each set of data lines; a horizontal direction drive circuit that sequentially drives the plurality of sets of selection switches in units of sets within a horizontal scanning period; a vertical direction drive circuit that sequentially drives the plurality of gate lines for each horizontal scanning period; a polarity switching control circuit; Each of the plurality of pixels is a liquid crystal element in which a liquid crystal layer is sandwiched between a pixel drive electrode and a common electrode facing each other; a first holding unit that samples and holds the positive polarity video signal of the corresponding data line; a first buffer circuit that receives the positive video signal held in the first holding unit; a first switch that, when conductive, applies a positive video signal output from the first buffer circuit to the pixel drive electrode; a second holding unit that samples and holds the negative video signal of the corresponding data line; a second buffer circuit that receives the negative video signal held in the second holding unit; a second switch that, when conductive, applies a negative video signal output from the second buffer circuit to the pixel drive electrode; The polarity switching control circuit during a first period of a vertical scanning period, the first switch is intermittently turned on for each predetermined unit period; In a second period following the first period of the vertical scanning period, the second switch is intermittently turned on for each unit period; intermittently supplying a bias current to the first buffer circuit and the second buffer circuit in synchronization with the conduction of the first switch and the second switch; In each of the first period and the second period, the bias current is set to a reference value during some of the plurality of unit periods, and the bias current is reduced below the reference value during the remaining unit periods. A liquid crystal display device characterized by:

2. The polarity switching control circuit In the first period, the first switch is intermittently turned on for some of the unit periods among the plurality of unit periods, and the first switch is turned off for the remaining unit periods; In the second period, the second switch is intermittently turned on for some of the unit periods among the plurality of unit periods, and the second switch is turned off for the remaining unit periods; In each of the first period and the second period, the bias current is not passed through the first buffer circuit and the second buffer circuit during the remaining unit period.

2. The liquid crystal display device according to claim 1.

3. the unit period is the horizontal scanning period, 3. The liquid crystal display device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

4. the part of unit periods in the first period is two or more consecutive unit periods from a first unit period in the first period, the part of unit periods in the second period is two or more consecutive unit periods from a first unit period in the second period; 3. The liquid crystal display device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. the first buffer circuit and the second buffer circuit are each a source follower circuit; The bias current is a constant current flowing in the source follower circuit.

3. The liquid crystal display device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. The polarity switching control circuit a start pulse generating unit that generates a start pulse for each unit period; a shift register that shifts the start pulse for each clock and outputs a pulse after the shift, and outputs an output pulse when the start pulse is shifted the same number of times as the number of the gate lines; an output unit that outputs a control signal for the first switch, a control signal for the second switch, and a control signal for the bias current of the first buffer circuit and the second buffer circuit for each of the plurality of pixels, based on a shifted pulse output from the shift register for each clock; a counter that counts the number of output pulses output from the shift register, when the number counted by the counter reaches the number of the partial unit period, the output unit outputs a control signal for the bias current so as to reduce the bias current below the reference value.

2. The liquid crystal display device according to claim 1.

7. The polarity switching control circuit a start pulse generating unit that generates a start pulse for each unit period; a shift register that shifts the start pulse for each clock and outputs a pulse after the shift, and outputs an output pulse when the start pulse is shifted the same number of times as the number of the gate lines; an output unit that outputs a control signal for the first switch, a control signal for the second switch, and a control signal for the bias current of the first buffer circuit and the second buffer circuit for each of the plurality of pixels, based on a shifted pulse output from the shift register for each clock; a counter that counts the number of output pulses output from the shift register, the start pulse generating unit stops generating the start pulse when the number counted by the counter reaches the number of the part of the unit periods.

3. The liquid crystal display device according to claim 2.

8. A control method for a liquid crystal display device, comprising: The liquid crystal display device comprises: a plurality of pixels provided at intersections where a plurality of sets of data lines, each set consisting of two data lines, intersect with a plurality of gate lines; a plurality of sets of selection switches provided for the plurality of sets of data lines, each set of selection switches supplying a positive video signal to one of the two data lines of a set and a negative video signal to the other data line, sequentially for each set of data lines; a horizontal direction drive circuit that sequentially drives the plurality of sets of selection switches in units of sets within a horizontal scanning period; a vertical direction drive circuit that sequentially drives the plurality of gate lines for each horizontal scanning period; Each of the plurality of pixels is a liquid crystal element in which a liquid crystal layer is sandwiched between a pixel drive electrode and a common electrode facing each other; a first holding unit that samples and holds the positive polarity video signal of the corresponding data line; a first buffer circuit that receives the positive video signal held in the first holding unit; a first switch that, when conductive, applies a positive video signal output from the first buffer circuit to the pixel drive electrode; a second holding unit that samples and holds the negative video signal of the corresponding data line; a second buffer circuit that receives the negative video signal held in the second holding unit; a second switch that, when conductive, applies a negative video signal output from the second buffer circuit to the pixel drive electrode; The control method includes: intermittently conducting the first switch for each predetermined unit period during a first period of a vertical scanning period; intermittently conducting the second switch for each unit period during a second period following the first period of the vertical scanning period; intermittently supplying a bias current to the first buffer circuit and the second buffer circuit in synchronization with the conduction of the first switch and the second switch; In each of the first period and the second period, the bias current is set to a reference value during some of the plurality of unit periods, and the bias current is reduced below the reference value during the remaining unit periods. A control method comprising:

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