Semiconductor device
The semiconductor device's innovative mesa and trench structure design, featuring wider termination trenches, addresses the challenge of high breakdown voltage by enhancing electric field dispersion and reducing leakage currents, leading to improved electrical performance.
Patent Information
- Application Number
- JP2024058971
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-04-01
- Publication Date
- 2025-10-14
AI Technical Summary
Existing semiconductor devices face challenges in achieving high breakdown voltage due to limitations in trench gate structures.
The semiconductor device incorporates a design with mesa portions and trench structures, including wider termination trenches adjacent to mesa portions, where the termination trenches have a greater width than gate trenches, and are positioned to facilitate better depletion layer extension and hole discharge, reducing peak electric field strength.
This design enhances breakdown voltage by dispersing electric fields and reducing leakage currents, thereby improving the device's electrical characteristics and reliability.
Smart Images
Figure 2025155255000001_ABST
Abstract
Description
[Technical Field]
[0001] The embodiments relate to a semiconductor device. [Background technology]
[0002] Trench gate structures are widely used in vertical power devices. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Patent No. 6208612 [Patent Document 2] Patent No. 6127069 Summary of the Invention [Problem to be solved by the invention]
[0004] The embodiments provide a semiconductor device that can improve the breakdown voltage. [Means for solving the problem]
[0005] According to an embodiment, a semiconductor device includes an upper electrode, a lower electrode, a semiconductor layer located between the upper electrode and the lower electrode, the semiconductor layer having a plurality of mesa portions aligned in a first direction and extending in a second direction perpendicular to the first direction, and a plurality of trench structures adjacent to the mesa portions in the first direction and extending in the second direction. The plurality of mesa portions include a plurality of cell mesa portions each having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, having a higher first conductivity type impurity concentration than the first semiconductor layer, and in contact with the upper electrode, and a termination mesa portion located at an end of the plurality of mesa portions in the first direction, the termination mesa portion having the first semiconductor layer and a fourth semiconductor layer of the second conductivity type provided on the first semiconductor layer and in contact with the upper electrode, but not having the third semiconductor layer. The plurality of trench structures include a plurality of gate trenches adjacent to the cell mesa in the first direction, each having a gate electrode and a first insulating film provided between the gate electrode and the cell mesa, and a first termination trench located at an end of the plurality of trench structures in the first direction, adjacent to the termination mesa, and having a conductive member and a second insulating film provided between the conductive member and the termination mesa. The width of the first termination trench in the first direction is greater than the width of the gate trench. The lower end of the first termination trench is located below the lower end of the gate trench. [Brief explanation of the drawings]
[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional perspective view taken along line AA in FIG. [Figure 3] FIG. 10 is a schematic plan view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional perspective view taken along line BB in FIG. 3. [Figure 5] 10(a) and 10(b) are graphs showing the simulation results. [Figure 6] 10 is a graph showing a simulation result. [Figure 7] 10(a) and 10(b) are graphs showing the simulation results. DETAILED DESCRIPTION OF THE INVENTION
[0007] Hereinafter, embodiments will be described with reference to the drawings, in which the same components are denoted by the same reference numerals.
[0008] [First embodiment] A semiconductor device 1 according to a first embodiment will be described with reference to Figures 1 and 2. The semiconductor device 1 includes an upper electrode 31, a lower electrode 32, a semiconductor layer 10, and a plurality of trench structures 40, 50A. In Figure 2, the upper electrode 31 is represented by a two-dot chain line to make it easier to see the configuration of the portion covered by the upper electrode 31.
[0009] The semiconductor device 1 has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. The upper electrode 31 is the source electrode of the MOSFET, and the lower electrode 32 is the drain electrode of the MOSFET. For example, a positive potential is applied to the lower electrode 32, and a ground potential is applied to the upper electrode 31. In an on-state in which the gate voltage of the gate electrode 41 (described later) is made higher than a threshold voltage, a current flows vertically (in a third direction Z) between the upper electrode 31 and the lower electrode 32 through the semiconductor layer 10. In the third direction Z, the direction from the lower electrode 32 to the upper electrode 31 is defined as "up" or "upward," and the direction from the upper electrode 31 to the lower electrode 32 is defined as "down" or "downward." In this specification, a "width in a certain direction" refers to the maximum width in that certain direction.
[0010] The semiconductor layer 10 is located between the upper electrode 31 and the lower electrode 32 in the third direction Z. The semiconductor layer 10 has a plurality of mesa portions 21, 22 aligned in the first direction X and extending in the second direction Y. The first direction X and the second direction Y are orthogonal to each other in a plane perpendicular to the third direction Z. The semiconductor layer 10 is, for example, a silicon layer. The semiconductor layer 10 may be a silicon carbide layer or a gallium nitride layer. In this specification, the first conductivity type is described as n-type and the second conductivity type is described as p-type in terms of the conductivity type of the semiconductor layer 10, but the first conductivity type may be described as p-type and the second conductivity type may be described as n-type.
[0011] The semiconductor layer 10 includes an n-type first semiconductor layer 11, a p-type second semiconductor layer 12 provided on the first semiconductor layer 11, and an n-type third semiconductor layer 13 provided on the second semiconductor layer 12. The n-type impurity concentration of the third semiconductor layer 13 is higher than the n-type impurity concentration of the first semiconductor layer 11. The third semiconductor layer 13 is in contact with an upper electrode 31 and is electrically connected to the upper electrode 31. The semiconductor layer 10 also includes an n-type fifth semiconductor layer 15 provided between a lower electrode 32 and the first semiconductor layer 11. The n-type impurity concentration of the fifth semiconductor layer 15 is higher than the n-type impurity concentration of the first semiconductor layer 11. The fifth semiconductor layer 15 is in contact with the lower electrode 32 and is electrically connected to the lower electrode 32.
[0012] The first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 are the drift layer, the base layer, the source layer, and the drain layer, respectively, of the MOSFET.
[0013] 1 is a schematic plan view showing an example of the arrangement of multiple mesas 21, 22 and multiple trench structures 40, 50A. The semiconductor device 1 has a cell region 101 and a termination region 102. The multiple mesas 21, 22 and multiple trench structures 40, 50A are arranged in the cell region 101. The termination region 102 continuously surrounds the cell region 101. The termination region 102 does not have a trench structure.
[0014] The plurality of mesas include a plurality of cell mesas 21 and a termination mesa 22 .
[0015] Each of the multiple cell mesa portions 21 has a portion of a first semiconductor layer 11 (drift layer), a second semiconductor layer 12 (base layer) provided on a portion of the first semiconductor layer 11, and a third semiconductor layer 13 (source layer) provided on the second semiconductor layer 12.
[0016] 2, the third semiconductor layer 13 is not provided on the upper portion 12A of the second semiconductor layer 12 in the cell mesa portion 21, and the upper portion 12A of the second semiconductor layer 12 is in contact with the upper electrode 31. The p-type impurity concentration of the upper portion 12A is higher than the p-type impurity concentration of a portion of the second semiconductor layer 12 located below the upper portion 12A. Holes can be discharged to the upper electrode 31 via the upper portion 12A of the second semiconductor layer 12. For example, the third semiconductor layer 13 and the upper portions 12A of the second semiconductor layer 12 are arranged alternately in the third direction Y.
[0017] As shown in FIG. 1 , termination mesa 22 is located at both ends of the multiple mesas in first direction X. Multiple cell mesas 21 are arranged between two termination mesas 22 located at both ends in first direction X. Termination mesa 22 has a part of first semiconductor layer 11 and a p-type fourth semiconductor layer 14 provided on part of first semiconductor layer 11. Termination mesa 22 does not have third semiconductor layer 13, and the top of fourth semiconductor layer 14 is in contact with upper electrode 31. Holes can be discharged to upper electrode 31 via fourth semiconductor layer 14.
[0018] The semiconductor layer 10 further includes a p-type sixth semiconductor layer 16 provided on the first semiconductor layer 11 in the termination region 102. The sixth semiconductor layer 16 extends in the first direction X and the second direction Y, and continuously surrounds the cell region 101. An upper portion of the sixth semiconductor layer 16 contacts the upper electrode 31. Holes can be discharged to the upper electrode 31 via the sixth semiconductor layer 16.
[0019] The trench structures include gate trenches 40 and a first termination trench 50 A. The gate trenches 40 and the first termination trench 50 A are adjacent to the mesa in the first direction X and extend in the second direction Y.
[0020] Each of the multiple gate trench portions 40 is adjacent to a cell mesa portion 21 in the first direction X. The cell mesa portion 21 is located between the gate trench portions 40 adjacent to each other in the first direction X.
[0021] Each of the multiple gate trench portions 40 has a gate electrode 41 and a first insulating film 42 provided between the gate electrode 41 and the cell mesa portion 21. A side surface of the gate electrode 41 faces the second semiconductor layer 12 in the first direction X, with the first insulating film 42 interposed therebetween.
[0022] The lower end of the gate electrode 41 is located below the junction (pn junction) between the second semiconductor layer 12 and the first semiconductor layer 11. The first insulating film 42 is also provided between the lower end of the gate electrode 41 and the first semiconductor layer 11. In this specification, the "lower end" refers to the end of the member that is closest to the lower electrode 32 in the third direction Z.
[0023] The gate trench portion 40 further includes an insulating layer 43 provided between the gate electrode 41 and the upper electrode 31 in the third direction Z.
[0024] When a gate voltage higher than the threshold voltage is applied to the gate electrode 41, an n-channel (inversion layer) is formed in the region of the second semiconductor layer 12 facing the gate electrode 41, and the semiconductor device 1 is turned on.
[0025] When a gate voltage lower than the threshold voltage is applied to the gate electrode 41, the semiconductor device 1 turns off, and a depletion layer extends from the junction (pn junction) between the second semiconductor layer 12 and the first semiconductor layer 11 and from the boundary between the first insulating film 42 in the gate trench portion 40 and the first semiconductor layer 11, thereby maintaining the breakdown voltage.
[0026] 1, the first termination trenches 50A are located at both ends of the multiple trench structures in the first direction X. Multiple gate trenches 40 are arranged between the two first termination trenches 50A located at both ends in the first direction X. The first termination trenches 50A are adjacent to the termination mesa 22 in the first direction X. The first termination trenches 50A are located between the termination mesa 22 and the sixth semiconductor layer 16 in the first direction X.
[0027] The first termination trench 50A has a conductive member 44 and a second insulating film 45 provided between the conductive member 44 and the termination mesa 22. The gate electrode 41 and the conductive member 44 are formed, for example, simultaneously in the same process and made of the same material. The gate electrode 41 and the conductive member 44 may be made of, for example, polycrystalline silicon containing impurities. The second insulating film 45 is also provided between the lower end of the conductive member 44 and the first semiconductor layer 11, and between the side surface of the conductive member 44 and the sixth semiconductor layer 16.
[0028] The first termination trench portion 50A further has an insulating layer 43 provided between the conductive member 44 and the upper electrode 31 in the third direction Z. In the off state, depletion layers extend from the junction (p-n junction) between the fourth semiconductor layer 14 and the first semiconductor layer 11, the boundary between the second insulating film 45 in the first termination trench portion 50A and the first semiconductor layer 11, and the junction (p-n junction) between the sixth semiconductor layer 16 and the first semiconductor layer 11, thereby maintaining the breakdown voltage.
[0029] The trench structure is formed in a trench formed in the semiconductor layer 10 by, for example, an RIE (Reactive Ion Etching) method. When a plurality of trenches aligned in the first direction X are formed in the semiconductor layer 10, the shape of the termination trench located at the end in the first direction X tends to be different from the shapes of other trenches located more inward than the termination trench.
[0030] According to this embodiment, the first termination trench 50A located at the end in the first direction X is adjacent to the termination mesa 22 that does not have the third semiconductor layer 13 (source layer). The first termination trench 50A and the termination mesa 22 are not switched on or off by controlling the gate electrode. This makes it possible to suppress the impact on the electrical characteristics of the semiconductor device 1 even if the shape of the first termination trench 50A deteriorates.
[0031] The lower end of the first termination trench 50A is located lower than the lower end of the gate trench 40. The lower end of the conductive member 44 is located lower than the lower end of the gate electrode 41. The lower end of the first termination trench 50A is the boundary between the first semiconductor layer 11 and the second insulating film 45 located between the lower end of the conductive member 44 and the first semiconductor layer 11. The lower end of the gate trench 40 is the boundary between the first semiconductor layer 11 and the first insulating film 42 located between the lower end of the gate electrode 41 and the first semiconductor layer 11.
[0032] The inventors used simulations (Technology Computer Aided Design (TCAD)) to calculate the electric field generated at the bottom end of the first termination trench 50A for Model 1 and Model 2. In Model 1, the bottom end of the first termination trench 50A is located lower than the bottom end of the gate trench 40. In Model 2, the position (position in the third direction Z) of the bottom end of the first termination trench 50A is the same as the position (position in the third direction Z) of the gate trench 40. As a result of this simulation, Model 1 had a higher peak electric field strength at the bottom end of the first termination trench 50A than Model 2. When the electric field strength at the bottom end of the first termination trench 50A is high, it becomes more difficult for a depletion layer to extend from the bottom end of the first termination trench 50A into the first semiconductor layer 11 in the off state, and the breakdown voltage is more likely to decrease.
[0033] 2, the width in the first direction X of the first termination trench 50A is greater than the width in the first direction X of the gate trench 40. Furthermore, the width in the first direction X of the conductive member 44 in the first termination trench 50A is greater than the width in the first direction X of the gate electrode 41 in the gate trench 40. According to this embodiment, as will be described below with reference to FIGS. 5(a) and 5(b), it is possible to reduce the peak of the electric field strength at the bottom end of the first termination trench 50A.
[0034] FIG. 5(a) shows the results of a simulation in which the electric field at the position X1-X1' along the first direction X shown in FIG. 2 was calculated. The calculation was performed for three models a to c. In all three models a to c, the bottom end of the first termination trench 50A is located lower than the bottom end of the gate trench 40. The bottom end of the first termination trench 50A in the three models a to c is located at the same position (position in the third direction Z). Models a to c differ from each other in the width (width in the first direction X) of the first termination trench 50A.
[0035] The width of the first termination trench portion 50A of model a is the same as the width of the gate trench portion 40, which is 0.15 μm. The width of the first termination trench portion 50A of model b is 0.2 μm, which is larger than the width of the first termination trench portion 50A of model a. The width of the first termination trench portion 50A of model c is 0.3 μm, which is larger than the width of the first termination trench portion 50A of model b.
[0036] 5(b) shows the results of calculating the Idss-Vdss characteristics by simulation for the above models a to c, where Idss represents the drain current and Vdss represents the drain-source voltage.
[0037] The results in FIG. 5(a) show that in models b and c, in which the width of the first termination trench 50A is made larger than the width of the gate trench 40, the peak electric field strength at the bottom end of the first termination trench 50A can be reduced more than in model a. By reducing the peak electric field strength at the bottom end of the first termination trench 50A, the depletion layer is more likely to extend from the bottom end of the first termination trench 50A into the first semiconductor layer 11. As a result, as shown in FIG. 5(b), models b and c can improve the breakdown voltage more than model a.
[0038] 5(a), as the width of the first termination trench 50A increases, the peak of the electric field intensity shifts to the right, i.e., toward the sixth semiconductor layer 16. This makes it easier to discharge holes generated by impact ionization at the bottom end of the first termination trench 50A to the upper electrode 31 via the fourth semiconductor layer 14 and the sixth semiconductor layer 16 of the termination mesa 22. Holes generated by impact ionization are less likely to flow along the interface between the cell mesa 21 and the first insulating film 42, making it less likely for holes to be trapped at that interface or in the first insulating film 42. This reduces the likelihood of leakage current, a decrease in breakdown voltage, and element breakdown.
[0039] If the width of the first termination trench 50A is made too wide, the embedding ability of the conductive member 44 and the insulating layer 43 into the trench will decrease, and voids may occur in the first termination trench 50A. Therefore, the width of the first termination trench 50A is preferably greater than the width of the gate trench 40 and is no more than 2.7 times the width of the gate trench 40. This improves the breakdown voltage while making it less likely for voids to occur in the first termination trench 50A.
[0040] 1, the semiconductor device 1 further includes a second termination trench 50B that is continuous with the first termination trench 50A and extends in the second direction Y. The first termination trench 50A and the second termination trench 50B continuously surround the cell mesa 21, the termination mesa 22, and the gate trench 40.
[0041] The second termination trench portion 50B has a conductive member 44 and a second insulating film 45 provided between the conductive member 44 and the semiconductor layer 10, similar to the first termination trench portion 50A.
[0042] The width of the second termination trench portion 50B in the second direction Y is greater than the width of the gate trench portion 40 in the first direction X. The bottom end of the second termination trench portion 50B is located lower than the bottom end of the gate trench portion 40.
[0043] The gate trench for forming the gate trench portion 40, the first termination trench for forming the first termination trench portion 50A, and the second termination trench for forming the second termination trench portion 50B are simultaneously formed by RIE. During this process, locally deep portions (sub-trenches) tend to form in the second termination trench, which extends in a direction perpendicular to the gate trench and the first termination trench. The sub-trench is prone to forming acute angles and portions with large curvatures, which can easily result in locally thin portions in the insulating film (silicon oxide film) formed within the trench by, for example, thermal oxidation. Electric fields tend to concentrate in locally thin portions of the insulating film within the trench, which can cause leakage current.
[0044] By making the width in the second direction Y of second termination trench portion 50B larger than the width in the first direction X of gate trench portion 40, etching gas is more likely to accumulate in the second termination trench when forming the second termination trench, facilitating etching. This makes it less likely that acute angles or portions with large curvatures will be formed in the second termination trench, reducing the electric field applied to second insulating film 45 in second termination trench portion 50B and suppressing leakage current.
[0045] [Second embodiment] A semiconductor device 2 according to the second embodiment will be described with reference to Figures 3 and 4. The semiconductor device 2 according to the second embodiment will be described mainly with respect to the configuration that differs from the semiconductor device 1 according to the first embodiment.
[0046] 4, in the semiconductor device 2, the lower end of the first termination trench 50A is located higher than the lower end of the gate trench 40 and lower than the junction (p-n junction) between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the termination mesa 22. The lower end of the conductive member 44 is located higher than the lower end of the gate electrode 41 and lower than the p-n junction between the fourth semiconductor layer 14 and the first semiconductor layer 11. The lower end of the first termination trench 50A and the lower end of the conductive member 44 are located lower than the p-n junction between the sixth semiconductor layer 16 and the first semiconductor layer 11.
[0047] The width in the first direction X of the first termination trench portion 50A is equal to or less than the width in the first direction X of the gate trench portion 40. For example, the width of the first termination trench portion 50A is the same as the width of the gate trench portion 40. Alternatively, the width of the first termination trench portion 50A may be smaller than the width of the gate trench portion 40.
[0048] FIG. 6 shows the results of a simulation of carrier generation due to impact ionization at position X2-X2' along the first direction X shown in FIG. 4. The calculation was performed for four models a to d. In all four models a to d, the width in the first direction X of the first termination trench portion 50A is set to the same width in the first direction X as the width in the first direction X of the gate trench portion 40 (0.15 μm). Models a to d differ from one another in the position of the bottom end of the first termination trench portion 50A (position in the third direction Z).
[0049] The bottom end of the first termination trench 50A of model a is located higher than the bottom end of the gate trench 40, and is also located higher than the pn junction between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the termination mesa 22. The bottom end of the first termination trench 50A of model a is located 0.2 μm higher than the bottom end of the gate trench 40.
[0050] The bottom end of the first termination trench 50A in model b is located higher than the bottom end of the gate trench 40 and lower than the pn junction between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the termination mesa 22. The bottom end of the first termination trench 50A in model b is located 0.05 μm higher than the bottom end of the gate trench 40.
[0051] The position of the bottom end of the first termination trench 50A in model c is the same as the position of the bottom end of the gate trench 40, and is located below the pn junction between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the termination mesa 22.
[0052] The bottom end of the first termination trench 50A in model d is located lower than the bottom end of the gate trench 40, and is also located lower than the pn junction between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the termination mesa 22. For model d, in which the bottom end of the first termination trench 50A is located lower than the bottom end of the gate trench 40, impact ionization was calculated for the position X1-X1' shown in Figure 2. The bottom end of the first termination trench 50A in model d is located 0.1 μm lower than the bottom end of the gate trench 40.
[0053] 6, in models a and b in which the bottom end of the first termination trench 50A is located above the bottom end of the gate trench 40, the impact ionization peak is located at the gate trench 40 adjacent to the first termination trench 50A. In model c in which the bottom end of the first termination trench 50A is located at the same position as the bottom end of the gate trench 40, and in model d in which the bottom end of the first termination trench 50A is located below the bottom end of the gate trench 40, the impact ionization peak is located at the first termination trench 50A.
[0054] 7(a) shows the results of calculations of the depletion layer widths by simulation for the above models a to d. For models a and b, the widths represent the depletion layer widths extending downward from the bottom end of the gate trench 40 adjacent to the first termination trench 50A. For models c and d, the widths represent the depletion layer widths extending downward from the bottom end of the first termination trench 50A.
[0055] FIG. 7(b) shows the results of calculating Vdss by simulation for the above models a to d.
[0056] 6, model b, in which the bottom end of first termination trench 50A is located higher than the bottom end of gate trench 40 and lower than the pn junction between fourth semiconductor layer 14 and first semiconductor layer 11 in termination mesa 22, has the lowest impact ionization peak. When impact ionization decreases, the amount of generated thermal carriers (thermal electrons and thermal holes) decreases, thereby suppressing fluctuations in the characteristics of semiconductor device 2. Furthermore, as shown in FIG. 7(a), model b has the widest depletion layer, and as a result, model b has the highest breakdown voltage, as shown in FIG. 7(b).
[0057] Furthermore, by positioning the lower end of the first termination trench 50A above the lower end of the gate trench 40 by a distance of 2% to 10% of the distance in the third direction Z from the upper surface of the semiconductor layer 10 to the lower end of the gate trench 40, it was confirmed by simulation that thermions flow to the upper electrode 31 while being dispersed to the second semiconductor layer 12 of the cell mesa 21 and the fourth semiconductor layer 14 of the termination mesa 22. This disperses hot spots caused by current concentration, enabling the breakdown voltage to be maintained at a high level.
[0058] In the semiconductor device 2, the width in the second direction Y of the second termination trench portion 50B can be made the same as the width in the first direction X of the first termination trench portion 50A.
[0059] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]
[0060] 1, 2... semiconductor device, 10... semiconductor layer, 11... first semiconductor layer, 12... second semiconductor layer, 13... third semiconductor layer, 14... fourth semiconductor layer, 15... fifth semiconductor layer, 16... sixth semiconductor layer, 21... cell mesa portion, 22... termination mesa portion, 31... upper electrode, 32... lower electrode, 41... gate electrode, 42... first insulating film, 43... insulating layer, 44... conductive member, 45... second insulating film, 50A... first termination trench portion, 50B... second termination trench portion, 101... cell region, 102... termination region
Claims
1. an upper electrode; A lower electrode; a semiconductor layer located between the upper electrode and the lower electrode, the semiconductor layer having a plurality of mesa portions aligned in a first direction and extending in a second direction perpendicular to the first direction; a plurality of trench structures adjacent to the mesa portion in the first direction and extending in the second direction; Equipped with The plurality of mesa portions are a plurality of cell mesa portions each having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, having a higher first conductivity type impurity concentration than the first semiconductor layer, and in contact with the upper electrode; a terminal mesa portion located at an end of the plurality of mesa portions in the first direction, the terminal mesa portion including the first semiconductor layer and a fourth semiconductor layer of a second conductivity type provided on the first semiconductor layer and in contact with the upper electrode, and not including the third semiconductor layer; and The plurality of trench structures include: a plurality of gate trench portions adjacent to the cell mesa portion in the first direction, each having a gate electrode and a first insulating film provided between the gate electrode and the cell mesa portion; a first termination trench portion located at an end of the plurality of trench structures in the first direction and adjacent to the termination mesa portion, the first termination trench portion including a conductive member and a second insulating film provided between the conductive member and the termination mesa portion; and a width of the first termination trench portion in the first direction is greater than a width of the gate trench portion in the first direction; a lower end of the first termination trench portion located lower than a lower end of the gate trench portion.
2. a width of the conductive member in the first direction is larger than a width of the gate electrode in the first direction; 2. The semiconductor device according to claim 1, wherein a lower end of said conductive member is located lower than a lower end of said gate electrode.
3. a second termination trench portion extending in the second direction and continuous with the first termination trench portion; a width of the second termination trench portion in the second direction is greater than a width of the gate trench portion in the first direction; The semiconductor device according to claim 1 , wherein a lower end of the second termination trench portion is located lower than the lower end of the gate trench portion.
4. an upper electrode; A lower electrode; a semiconductor layer located between the upper electrode and the lower electrode, the semiconductor layer having a plurality of mesa portions aligned in a first direction and extending in a second direction perpendicular to the first direction; a plurality of trench structures adjacent to the mesa portion in the first direction and extending in the second direction; Equipped with The plurality of mesa portions are a plurality of cell mesa portions each having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, having a higher first conductivity type impurity concentration than the first semiconductor layer, and in contact with the upper electrode; a terminal mesa portion located at an end of the plurality of mesa portions in the first direction, the terminal mesa portion including the first semiconductor layer and a fourth semiconductor layer of a second conductivity type provided on the first semiconductor layer and in contact with the upper electrode, and not including the third semiconductor layer; and The plurality of trench structures include: a plurality of gate trench portions adjacent to the cell mesa portion in the first direction, each having a gate electrode and a first insulating film provided between the gate electrode and the cell mesa portion; a first termination trench portion located at an end of the plurality of trench structures in the first direction and adjacent to the termination mesa portion, the first termination trench portion including a conductive member and a second insulating film provided between the conductive member and the termination mesa portion; and a lower end of the first termination trench portion located higher than a lower end of the gate trench portion and lower than a junction between the fourth semiconductor layer and the first semiconductor layer in the termination mesa portion.
5. 5. The semiconductor device according to claim 4, wherein a lower end of the conductive member is located above a lower end of the gate electrode and below the junction between the fourth semiconductor layer and the first semiconductor layer.
6. The semiconductor device according to claim 4 , wherein the width of the first termination trench portion in the first direction is equal to or smaller than the width of the gate trench portion in the first direction.
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