Semiconductor device and manufacturing method thereof

Abstract

To improve the performance of a semiconductor device.SOLUTION: A region DR1 of a die pad DP included in a semiconductor device PKG1 includes a region DR3 having a surface facing a surface CPb of a semiconductor chip CP with a die bond material DB interposed therebetween, and a region DR4 having a surface facing the surface CPb of the semiconductor chip CP without the die bond material DB interposed therebetween. The die pad DP is provided in the region DR3, and includes a projection CV projecting from a plane including an upper surface DPt toward the semiconductor chip CP. A sealing body MR contains a plurality of filler particles MRf. Some of the filler particles MRf are interposed between the surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP located in the region DR4 of the die pad DP.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] There is a technology for mounting a semiconductor chip on a die pad via a die bond material (JP 2019-145625 A). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-145625 Summary of the Invention [Problem to be solved by the invention]

[0004] When a semiconductor chip is mounted on a die pad via a die bond material, a space may be formed between the semiconductor chip and the die pad without the die bond material interposed between them. If the thickness of this space is thin, it becomes difficult for filler particles contained in the encapsulant that encapsulates the semiconductor chip and the die pad to be supplied into the space, which may cause peeling between the encapsulant and the die pad.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a die pad having a first surface including a first region and a second region surrounding the first region, a semiconductor chip having a second surface opposite the first surface and mounted on the first region of the die pad via a die bond material, multiple wires, and a sealing body that seals the semiconductor chip, the multiple wires, and the first surface of the die pad. The multiple wires include a first wire connected to the second region of the die pad. The first region of the die pad includes a third region having a surface facing the second surface of the semiconductor chip via the die bond material, and a fourth region having a surface facing the second surface of the semiconductor chip via the sealing body. The die pad is provided in the third region and includes a first protrusion that protrudes toward the semiconductor chip from a plane including the first surface. The sealing body includes multiple filler particles. Some of the filler particles are interposed between the second surface of the semiconductor chip and the first surface of the die pad located in the fourth region of the die pad.

[0007] A semiconductor device according to another embodiment includes a die pad, a semiconductor chip, multiple wires, and a sealing body. The die pad includes a first surface, multiple through holes, a central portion including the center of the first surface, a peripheral portion along the periphery of the first surface, and multiple connecting portions disposed between the multiple through holes in a plan view and extending to connect the central portion and the peripheral portion. The semiconductor chip includes a second surface facing the first surface, a third surface positioned opposite the second surface, and multiple electrodes arranged on the third surface. The semiconductor chip is mounted in a chip mounting area of ​​the first surface of the die pad via a die bond material. The sealing body seals the semiconductor chip, the multiple wires, and the first surface of the die pad. The multiple wires include a first wire connected to the peripheral portion of the die pad. The die pad includes grooves formed in each of the multiple connecting portions. The groove includes a first portion exposed from the die-bonding material and facing the second surface of the semiconductor chip via the encapsulant, and a second portion positioned so as not to overlap the semiconductor chip. A first distance from a bottom surface of the first portion of the groove to the second surface of the semiconductor chip is longer than a second distance from a plane including the first surface of the central portion to the second surface of the semiconductor chip. The encapsulant includes a plurality of filler particles. Some of the filler particles are interposed between the second surface of the semiconductor chip and the first portion of the groove of the die pad.

[0008] A method for manufacturing a semiconductor device according to another embodiment includes the steps of: (a) preparing a lead frame having a die pad with a first surface including a first region and a second region surrounding the first region in a plan view; and a plurality of leads arranged around the die pad in a plan view. The method for manufacturing a semiconductor device includes the steps of: (b) preparing a semiconductor chip with a second surface, a third surface opposite the second surface, and a plurality of electrodes arranged on the third surface; and mounting the semiconductor chip on the first region of the die pad via a die bond material so that the second surface faces the first surface. The method for manufacturing a semiconductor device includes the steps of: (c) connecting a first wire to the second region of the die pad; and (d) forming a sealing body that encapsulates the semiconductor chip, the first wire, and the die pad using a resin containing a plurality of filler particles. In the step (b), the first region of the die pad includes a third region having a surface facing the second surface of the semiconductor chip via the die bond material, and a fourth region having a surface facing the second surface of the semiconductor chip without the die bond material. The die pad of the lead frame prepared in the step (a) is provided in the third region and has a first protrusion protruding upward from a plane including the first surface. In the step (d), some of the plurality of filler particles are supplied between the second surface of the semiconductor chip and the first surface of the die pad located in the fourth region of the die pad. [Effects of the Invention]

[0009] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a transparent plan view of FIG. [Figure 4] 4 is a plan view showing the semiconductor chip and the plurality of wires shown in FIG. 3 removed. [Figure 5] FIG. 4 is an enlarged plan view of the die pad shown in FIG. [Figure 6] FIG. 4 is an enlarged plan view of the die pad shown in FIG. [Figure 7] 6 is an enlarged cross-sectional view of the semiconductor device shown in FIG. 3 taken along line BB in FIG. 5. [Figure 8] 8 is an enlarged cross-sectional view showing a semiconductor device that is a study example of FIG. 7. [Figure 9] 6 is an enlarged plan view of a die pad which is a modified example of the die pad shown in FIG. 5. [Figure 10] 7 is an enlarged plan view of a die pad which is a modified example of the die pad shown in FIG. 6. FIG. [Figure 11] 10 is an enlarged cross-sectional view of the semiconductor device taken along line CC in FIG. 9. [Figure 12] 6 is an enlarged plan view of a die pad which is another modified example of the die pad shown in FIG. 5. FIG. [Figure 13] 7 is an enlarged plan view of a die pad which is another modified example of the die pad shown in FIG. 6. FIG. [Figure 14] FIG. 14 is an enlarged cross-sectional view of the semiconductor device taken along line DD in FIG. 13. [Figure 15] 14 is an enlarged cross-sectional view of the semiconductor device taken along line EE in FIG. 13. [Figure 16] 10 is an enlarged plan view showing a modified example of the die pad shown in FIG. [Figure 17] 11 is an enlarged plan view showing a modified example of the die pad shown in FIG. [Figure 18] FIG. 18 is an explanatory diagram showing the flow of an assembly process for any of the semiconductor devices described with reference to FIGS. 1 to 17. [Figure 19] 19 is an enlarged plan view showing a lead frame prepared in the base material preparing step shown in FIG. 18. FIG. [Figure 20] 20 is an enlarged cross-sectional view showing a state in which a semiconductor chip is mounted on a die pad of the lead frame shown in FIG. 19. [Figure 21] FIG. 10 is an enlarged plan view showing a state in which a paste-like die bonding material is applied onto a die pad in a die bonding process. [Figure 22] FIG. 22 is an enlarged cross-sectional view taken along the line FF in FIG. 21. [Figure 23] 23 is an enlarged cross-sectional view showing a state in which a semiconductor chip is pressed against the die pad shown in FIG. 22 and a paste-like die bonding material is spread. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Explanation of the description format, basic terms and usage in this application) In this application, the description of the embodiments will be divided into multiple sections, etc., for convenience, as necessary. However, unless otherwise expressly stated, these are not mutually independent and separate, and regardless of the order of description, they are each part of a single example, one being a partial detail of the other, or a partial or complete modification, etc. Furthermore, as a general rule, repeated explanations of similar parts will be omitted. Furthermore, each component in the embodiments is not essential unless otherwise expressly stated, there is a theoretical limit to the number, or it is clearly not essential from the context.

[0012] Similarly, in the description of embodiments, when a material, composition, etc. is described as "X consisting of A," this does not exclude elements other than A, unless otherwise expressly stated or clearly indicated by the context. For example, when referring to a component, it means "X containing A as its primary component." For example, a "silicon component" does not necessarily refer to pure silicon, but also includes SiGe (silicon-germanium) alloys and other multi-component alloys containing silicon as the primary component, as well as components containing other additives. Furthermore, unless otherwise expressly stated, gold plating, Cu layer, nickel plating, etc., include not only pure components but also components containing gold, Cu, nickel, etc. as their primary components.

[0013] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, unless it is theoretically limited to that number, or unless it is clearly not the case from the context, the number may be greater than that specific number or less than that specific number.

[0014] In each drawing of the embodiments described below, the same or similar parts are indicated by the same or similar symbols or reference numerals, and descriptions thereof will not be repeated as a general rule.

[0015] In the accompanying drawings, hatching may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the description, etc. Furthermore, hatching or dot patterns may be added even in cases where the drawing is not a cross section to clearly indicate that the hole is not a void or to clearly indicate the boundary of the area.

[0016] In the following description, directions such as the X direction, the Y direction, and the Z direction may be used. For example, the X direction and the Y direction are shown in FIG. 1, which will be described later. The X direction and the Y direction intersect with each other. In the example described below, the X direction is orthogonal to the Y direction. In the following description, the XY plane including the X direction and the Y direction is assumed to be a plane parallel to the main surface of the semiconductor device and the main surface of the mounting substrate.

[0017] A surface that intersects the XY plane (for example, a surface parallel to the XZ plane including the X and Z directions, and a surface parallel to the YZ plane including the Y and Z directions) is called a side surface. In the following description, unless otherwise specified, "planar view" means a view of a surface parallel to the XY plane. Furthermore, the normal direction to the XY plane will be referred to as the "Z direction" or thickness direction. Unless otherwise specified, "thickness" and "height" refer to the length in the "Z direction." The X, Y, and Z directions are directions that intersect with each other, and more specifically, are directions that are perpendicular to each other.

[0018] <Semiconductor device> First, an outline of the configuration of the semiconductor device PKG1 of this embodiment will be described with reference to Figs. 1 to 4. Fig. 1 is a top view of the semiconductor device of this embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 3 is a transparent plan view showing the internal structure of the semiconductor device in a state where the sealing body shown in Fig. 1 is seen through. Fig. 4 is a plan view showing a state where the semiconductor chip and multiple wires shown in Fig. 3 are removed.

[0019] As shown in FIGS. 1 to 4, the semiconductor device PKG1 has a die pad DP (see FIGS. 2 and 3), a semiconductor chip CP (see FIGS. 2 and 3), multiple leads LD, and multiple wires BW (see FIG. 2). The semiconductor chip CP, multiple wires BW, and die pad DP are sealed in a sealing body MR. The sealing body MR seals at least the upper surface DPt of the die pad DP. In the example shown in FIG. 2, the upper surface DPt and the lower surface DPb of the die pad DP, both of which are flat surfaces, are sealed in the sealing body. Although not shown, as a modified example, the lower surface DPb of the die pad DP may be exposed from the sealing body MR. The inner lead portions ILD (see FIG. 2) of each of the multiple leads LD are sealed in the sealing body MR, and the outer lead portions OLD of each of the multiple leads LD are exposed from the sealing body MR.

[0020] As shown in Fig. 1, the planar shape of the sealing body MR included in the semiconductor device PKG1 is a rectangle (quadrilateral). The sealing body MR has an upper surface MRt, a lower surface (back surface, mounted surface) MRb (see Fig. 2) located opposite the upper surface MRt, and side surfaces located between the upper surface MRt and the lower surface MRb. As shown in Fig. 7, which will be described later, the sealing body MR is made of an insulating material containing filler particles MRf and a resin component MRr.

[0021] 1 and 3, the sealing body MR has a side (main side) MRs1 extending (extending) along the X direction in a plan view, and a side (main side) MRs2 extending along the Y direction intersecting the X direction (orthogonal to the X direction in FIG. 1). The sealing body MR has a side MRs3 located opposite the side MRs1 and extending along the X direction, and a side MRs4 located opposite the side MRs2 and extending along the Y direction. As shown in FIG. 1, the four side surfaces of the sealing body MR are arranged along the respective sides of the sealing body MR.

[0022] The corner portion MRc of the sealing body MR includes a peripheral region of a corner that is the intersection point of any two intersecting sides (two main sides) of the four sides (four main sides) of the sealing body MR. Strictly speaking, as shown in Figures 1 and 3, the corner portion MRc of the sealing body MR has a tapered shape that does not include the intersection point of the four main sides, and therefore the intersection point of the main sides is located outside the corner portion MRc of the sealing body MR. However, because the size of the corner portion MRc is sufficiently small compared to the length of the main sides, the present application will describe the corner of the sealing body MR by regarding the center of the corner portion MRc as the corner of the sealing body MR.

[0023] The semiconductor device PKG1 has a plurality of leads LD arranged along each side (each main side) of the sealing body MR having a rectangular planar shape. Each of the leads LD is made of a metal material, and in this embodiment, is a metal member made of, for example, copper or a copper alloy.

[0024] As shown in FIG. 2, the outer lead portions OLD of the leads LD protrude from the inside to the outside of the sealing body MR on the side surfaces of the sealing body MR. Furthermore, a metal film (external plating film) MC is formed on the exposed surfaces of the outer lead portions OLD of the leads LD, for example, on the surface of a base material mainly composed of copper. The metal film MC is made of a metal material, such as solder, that has better wettability with solder than the base copper, and is a metal coating that covers the surface of the copper material, which is the base copper. By forming the metal film MC made of solder or the like on each of the outer lead portions OLD of the leads LD, which are external terminals of the semiconductor device PKG1, the wettability of the solder material, which is a conductive connecting material, can be improved when the semiconductor device PKG1 is mounted on a mounting substrate. This increases the bonding area between the leads LD and the solder material, thereby improving the bonding strength between the leads LD and the terminals on the mounting substrate.

[0025] The metal film MC is, for example, a solder material made of Sn-Pb solder material containing lead (Pb), or a solder material made of so-called lead-free solder that does not substantially contain Pb. Examples of lead-free solder include tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), and tin-copper (Sn-Cu). Here, lead-free solder means solder containing 0.1 weight percent or less of lead (Pb), which is specified as a standard by the RoHS (Restriction of Hazardous Substances) Directive.

[0026] As shown in FIG. 2, the semiconductor chip CP is sealed in a sealing body MR. As shown in FIG. 3, the semiconductor chip CP is rectangular in plan view, and a plurality of electrode pads (electrodes) PD (see FIG. 2) are provided on the surface CPt along each of the four sides constituting the outer edge of the surface CPt. The semiconductor chip CP (more specifically, the semiconductor substrate provided in the semiconductor chip CP) is made of, for example, silicon (Si). Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (more specifically, the semiconductor element formation region on the upper surface of the semiconductor substrate provided in the semiconductor chip CP). The plurality of electrode pads PD are electrically connected to the semiconductor elements via wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip CP (more specifically, between the surface CPt and the semiconductor element formation region, not shown). In other words, the plurality of electrode pads PD are electrically connected to the circuits formed in the semiconductor chip CP.

[0027] The semiconductor chip CP has a surface (main surface, back surface, bottom surface) CPb and a surface (main surface, front surface, top surface) CPt opposite to the surface CPb. A plurality of electrode pads PD are arranged on the surface CPt of the semiconductor chip CP.

[0028] More specifically, an insulating film covering the substrate and wiring of the semiconductor chip CP is formed on the surface CPt of the semiconductor chip CP, and the surfaces of each of the multiple electrode pads PD (see FIG. 2) are exposed from the insulating film at openings formed in the insulating film. The electrode pads PD are made of metal, and in this embodiment, are made of aluminum (Al), for example. In this specification, the phrase "electrode pads PD arranged on the surface CPt of the semiconductor chip CP" may be used, but strictly speaking, this means the following: "each of the multiple electrode pads PD is exposed from the insulating film at any of multiple openings formed in the insulating film having the surface CPt of the semiconductor chip CP."

[0029] As shown in Fig. 3, a plurality of leads LD are arranged around the die pad DP. Each of the plurality of leads LD is spaced apart from the die pad DP. The electrode pads PD (see Fig. 2) arranged on the surface CPt of the semiconductor chip CP are electrically connected to inner lead portions ILD of the leads LD located inside the sealing body MR via wires (conductive members) BW. The wires BW are made of, for example, gold (Au) or copper (Cu), and a part of the wires BW (for example, one end) is bonded to the electrode pad PD, and the other part (for example, the other end) is bonded to a wire bonding region at the tip of the inner lead portion ILD.

[0030] Furthermore, a metal film (plated film, plated metal film) MF1 (see FIG. 2) is formed in the wire bonding region at the tip of the inner lead portion ILD. As shown in FIG. 2, the metal film MF1 is partially formed on a portion of the inner lead portion ILD (the upper surface (front surface) LDt of the tip portion closest to the die pad DP). The metal film MF1 is made of a material mainly containing silver (Ag), for example. By forming the metal film MF1 made of a material mainly containing silver in the portion of the inner lead portion ILD to which the wire BW is connected, the bonding strength with the wire BW made of gold or copper can be improved.

[0031] In the case of the semiconductor device PKG1 shown in Figures 1 to 3, some of the multiple wires BW have one end connected to the die pad DP and the other end connected to the electrode pad PD (see Figure 2) of the semiconductor chip CP. Another portion of the multiple wires BW have one end connected to the die pad DP and the other end connected to the lead LD. Furthermore, still another portion of the multiple wires BW have one end connected to the electrode pad PD (see Figure 2) of the semiconductor chip CP and the other end connected to the lead LD.

[0032] In other words, the wires BW include wires BWD connected to the die pad DP and wires BWC connected to the semiconductor chip CP and leads LD without going through the die pad DP.

[0033] When some of the wires BW are connected to the die pad DP, as in the semiconductor device PKG1, the die pad DP can be used as a transmission path. The die pad DP has a larger cross-sectional area of ​​the transmission path than the wires BW. Therefore, the potential transmitted via the die pad DP is less likely to change due to factors such as noise. For example, when the die pad DP is a supply path for a reference potential (e.g., a ground potential), the reference potential can be stabilized (made less likely to change due to the influence of noise, etc.).

[0034] As shown in Figure 2, the semiconductor chip CP is mounted on a die pad DP, which is a chip mounting portion. The die pad DP has an upper surface (main surface, chip mounting surface) DPt and a lower surface (main surface, back surface) DPb opposite the upper surface DPt. The semiconductor chip CP is mounted on the upper surface DPt of the die pad DP. The semiconductor chip CP is mounted in a chip mounting region (chip mounting region, die bonding region) DBR (see Figure 4) of the upper surface DPt of the die pad DP. The chip mounting region DBR is a region that includes the center of the upper surface DPt of the die pad DP. The outline of the chip mounting region DBR coincides with the outer edge of the semiconductor chip CP in a planar view.

[0035] 3 and 4, the outer edge of the upper surface DPt of the die pad DP forms an octagon. The die pad DP is a support member that supports the semiconductor chip CP, and there are various modifications of the shape and size in addition to the example shown in Fig. 4. For example, the planar shape of the die pad DP may be a polygon with more sides than a square.

[0036] As shown in Figure 4, a metal film (plated film, plated metal film) MF2 is formed on the periphery of the die pad DP. The metal film MF2 is made of a material whose main component is, for example, silver (Ag) or gold (Au). The metal film MF2 is made of the same metal material as the metal film MF1 formed on the upper surface of each of the tips of the multiple leads LD, and is formed by plating.

[0037] As described above, in this embodiment, some of the wires BW are connected to the die pad DP. From the viewpoint of improving the connection reliability of the wires BW connected to the die pad DP, it is preferable that a metal film MF2 be formed at the location where the wires BW are connected to the die pad DP.

[0038] In this embodiment, a metal film MF2 is formed on the upper surface DPt of the die pad DP in a wire bonding region WBR where a wire BW (see FIG. 3) may be connected, among the upper surface DPt of the die pad DP. In other words, in the die pad DP shown in FIG. 4, the location where the metal film MF2 is formed is a region where a wire BW may be connected. The wire bonding region WBR is a planned region where a wire BW may be bonded depending on the product specifications. Therefore, depending on the product, a wire BW may not be bonded to the wire bonding region WBR.

[0039] The metal film MF2, made of a metal material primarily containing silver or gold, has a lower adhesive strength with the sealing body MR shown in FIG. 2 than the die pad DP, made of copper. When the semiconductor device PKG1 is subjected to a thermal load, such as a reflow process during mounting or a temperature cycle load, stress occurs at the adhesive interface between the die pad DP and the sealing body MR due to the difference in the linear expansion coefficients of the sealing body MR and the die pad DP. In the case of a large-area metal pattern such as the die pad DP, the stress caused by this thermal load is greatest at the periphery of the die pad DP. Therefore, when stress caused by the thermal load occurs, peeling between the die pad DP and the sealing body MR may occur at the periphery of the die pad DP. In particular, when the metal film MF2 and the sealing body MR are bonded at the periphery of the die pad DP, the adhesive interface between the metal film MF2 and the sealing body MR is more susceptible to peeling than the adhesive interface between the die pad DP and the sealing body MR.

[0040] Therefore, in this embodiment, a through hole DTH1 is formed at a position overlapping with the metal film MF2 or around the metal film MF2. The through hole DTH1 is an opening that penetrates the die pad DP in the thickness direction. A sealing body MR is embedded in the through hole DTH1. In this case, even if there is a large difference in the linear expansion coefficient between the sealing body MR and the die pad DP when a thermal load is applied, a portion of the sealing body MR embedded in the through hole DTH1 functions as an anchor that suppresses excessive expansion or contraction of the sealing body MR. This makes it possible to suppress peeling or the progression of peeling between the metal film MF2 and the sealing body MR.

[0041] 4, the die pad DP has a plurality of through holes DTH2 penetrating the die pad DP in the thickness direction (Z direction shown in FIG. 2). As shown in FIG. 2, the surface CPb of the semiconductor chip CP is in contact with the sealing body MR at the positions where the plurality of through holes DTH2 (see FIG. 4) are formed. The adhesive strength at the interface between the surface CPb of the semiconductor chip CP and the sealing body MR is higher than the adhesive strength at the interface between the die pad DP and the sealing body MR. Therefore, when a portion of the surface CPb of the semiconductor chip CP is bonded to the sealing body MR as in this embodiment, peeling of the sealing body MR from the semiconductor chip CP or the die pad DP can be suppressed compared to when the entire surface CPb of the semiconductor chip CP is not in contact with the sealing body MR.

[0042] In the example shown in FIG. 4, the planar shape of each of the multiple through holes DTH2 is a triangle. However, the planar shape of the through holes DTH2 is not limited to a triangle, and there are various modified examples. For example, in the case of the die pad DP4 shown in FIGS. 16 and 17 described later, the shape of the through holes DTH2 is a rectangle. Note that, as in the example shown in FIG. 4 and the example shown in FIG. 16 described later, some or all of the multiple vertices of a triangle or rectangle may be rounded (rounded). In this specification, even when the vertices are rounded in this way, the rounded parts will be described as vertices.

[0043] 2, the semiconductor chip CP is mounted on the die pad DP via a die bond material (adhesive) DB, with its surface CPb facing the upper surface DPt of the die pad DP. That is, the semiconductor chip CP is mounted by a so-called face-up mounting method, in which the surface CPb opposite the surface CPt on which the multiple electrode pads PD are formed faces the chip mounting surface (upper surface DPt). This die bond material DB is an adhesive used when die-bonding the semiconductor chip CP, and is, for example, a resin adhesive made of an epoxy-based thermosetting resin containing metal particles made of silver or the like, or a metal bonding material such as solder.

[0044] 4, a plurality of suspension leads HL are arranged around the die pad DP, extending from the peripheral edge of the die pad DP toward the peripheral edge of the sealing body MR. The suspension leads HL are members that support the die pad DP on the supporting portion (frame portion) of the lead frame in the manufacturing process of the semiconductor device PKG1, and one end of each suspension lead HL is connected to the outer edge of the die pad DP.

[0045] 4, four suspension leads HL1, HL2, HL3, and HL4 are connected to the die pad DP, each extending from a portion of the die pad DP toward one of four corners MRc of the sealing body MR. The suspension lead HL2 is disposed on the opposite side of the die pad DP from the suspension lead HL1. The suspension lead HL4 is disposed on the opposite side of the die pad DP from the suspension lead HL3. Lead groups each including a plurality of leads LD are disposed between the suspension leads HL1 and HL3, between the suspension leads HL1 and HL4, between the suspension leads HL2 and HL3, and between the suspension leads HL2 and HL4.

[0046] One end of each of the plurality of suspension leads HL is connected to a corner of the die pad DP, and the other end of each of the plurality of suspension leads HL extends toward a corner MRc of the sealing body MR, branches into two in the vicinity of the corner MRc, and is exposed from the sealing body MR (see FIG. 1) at the side surface of the sealing body MR.

[0047] 2, the upper surface DPt of the die pad DP and the upper surfaces of the inner lead portions ILD of the leads LD are disposed at different heights. Specifically, for example, assuming that the lower surface MRb of the sealing body MR is a reference plane, the height from the reference plane to the upper surface DPt of the die pad DP is lower than the height from the reference plane to the upper surface LDt of the inner lead portions ILD. Therefore, each of the plurality of suspension leads HL shown in FIG. 3 is provided with an offset portion (a bent portion, a downset portion in this embodiment) that is bent so that the height of the upper surface DPt of the die pad DP is different from the height of the upper surfaces LDt of the inner lead portions ILD of the leads LD (see FIG. 2).

[0048] 2, the semiconductor chip CP, die pad DP, multiple wires BW, and multiple leads LD are each sealed with a sealing body MR. More specifically, the semiconductor chip CP, die pad DP, and multiple wires BW are entirely sealed with the sealing body MR. Also, a portion (inner lead portion ILD) of each of the multiple leads LD is sealed with the sealing body MR, and the other portion (outer lead portion OLD) is exposed from the sealing body MR.

[0049] As will be described in detail later, the sealing body MR includes a resin and a plurality of filler particles MRf (see FIG. 7 described later) mixed into the resin. The filler particles MRf are made of, for example, silica (an inorganic material whose main component is silicon dioxide). By mixing the filler particles MRf into the sealing body MR, it is possible to reduce the difference between the linear expansion coefficient of the semiconductor chip CP and the linear expansion coefficient of the sealing body MR.

[0050] <Details of the die pad area> Next, the peripheral structure of the die pad DP shown in Figures 2 to 4 will be described in detail. Figures 5 and 6 are each an enlarged plan view of the die pad shown in Figure 3. Although Figure 5 is a plan view, each region is hatched to clearly indicate the range of the region provided on the upper surface DPt of the die pad DP. Similarly, Figure 6 is a plan view, but each portion is hatched to clearly indicate the range of the portion provided on the die pad DP. Figure 7 is an enlarged cross-sectional view of the semiconductor device shown in Figure 3 when cut along line BB in Figure 5.

[0051] 5, the upper surface DPt of the die pad DP includes a region DR1 and a region DR2 that surrounds the region DR1 in a plan view. The region DR1 is a region of the chip mounting region DBR, which is a region where the semiconductor chip CP (see FIG. 3) is mounted, excluding a portion that overlaps with any of the plurality of through holes DTH2.

[0052] The region DR2 is a frame-shaped region that continuously surrounds the periphery of the chip mounting region DBR. The region DR2 is the region of the top surface DPt of the die pad DP excluding the portions that overlap with the region DR1, any of the multiple through holes DTH1, and any of the multiple through holes DTH2. Each of the multiple wire bonding regions WBR is disposed within the region DR2. The region DR2 includes the outer edge of the top surface DPt of the die pad DP.

[0053] Furthermore, region DR1 includes regions DR3 and DR4. As shown in FIG. 7, region DR3 is a region of the top surface DPt that has a surface facing the surface CPb of the semiconductor chip CP with the die bond material DB interposed therebetween. Region DR4 has a surface facing the surface CPb of the semiconductor chip CP with the sealing body MR interposed therebetween, and in the example shown in FIG. 5, is a region located closer to region DR2 than region DR3. Note that in FIG. 7, region DR4 faces the semiconductor chip CP without the die bond material DB interposed therebetween. However, resin components of the die bond material DB may seep out of a portion of region DR4.

[0054] As shown in Figures 5 to 7, the die pad DP is provided in the region DR3 and has a protrusion CV that protrudes from a plane (reference plane) including the top surface DPt toward the semiconductor chip CP. As shown in Figure 7, the top surface CVt of the protrusion CV is located at a different height from the top surface DPt of the die pad DP. Therefore, the top surface CVt of the protrusion CV is not included in the top surface DPt of the die pad DP. Therefore, to be precise, the protrusion CV is located at a position surrounded by the region DR3. The sealing body MR includes a plurality of filler particles MRf. Some of the plurality of filler particles MRf are interposed between the surface CPb of the semiconductor chip CP and the region DR4 of the die pad DP.

[0055] The die pad DP of this embodiment can be expressed as follows using FIG. 6. As shown in FIG. 6, the die pad DP includes a central portion DCP including a center DPc of the top surface DPt, a peripheral portion DPP, and a plurality of coupling portions CNP that are arranged between the plurality of through holes DTH2 in a plan view and extend to couple the central portion DCP and the peripheral portion DPP. The plurality of coupling portions CNP include a coupling portion CNP1 that extends from the central portion DCP toward the peripheral portion DPP and a coupling portion CNP2 that is arranged on the opposite side of the coupling portion CNP1 across the central portion DCP. The plurality of coupling portions CNP also include a coupling portion CNP3 that extends from the central portion DCP toward the peripheral portion DPP and a coupling portion CNP4 that is arranged on the opposite side of the coupling portion CNP3 across the central portion DCP. The coupling portion CNP1 is adjacent to the coupling portion CNP3 and the coupling portion CNP4, respectively, via the through hole DTH2. The connecting portion CNP2 is adjacent to the connecting portion CNP3 and the connecting portion CNP4 via the through-hole DTH2.

[0056] Next, the reason why the region DR1 on the upper surface DPt of the die pad DP includes the regions DR3 and DR4 will be explained. Considering the mounting strength of the semiconductor chip CP, it is preferable that the die bond material DB (see FIG. 7) is interposed over the entire surface between the surface CPb of the semiconductor chip CP and the die pad DP.

[0057] However, in the case of a structure in which a wire BW (see Figure 3) is connected to a wire bonding area WBR located in the peripheral area of ​​the die pad DP, as in this embodiment, it is necessary to prevent the die bonding material DB from spreading too far toward the periphery of the top surface DPt and reaching the wire bonding area WBR.

[0058] Furthermore, as in this embodiment, when the planar area of ​​the semiconductor chip CP (the area of ​​the surface CPt shown in Figure 3) is relatively large compared to the area of ​​the upper surface DPt of the die pad DP, the distance from the outer edge of the chip mounting area DBR to the wire bonding area WBR may be short, as shown in Figure 4.

[0059] In this case, to prevent the die bond material DB from reaching the wire bonding region WBR, it is preferable to limit the amount of die bond material DB applied so that the die bond material DB does not reach the outside of the chip mounting region DBR as far as the wire bonding region WBR. Since it is difficult to stop the die bond material DB at the boundary between the chip mounting region DBR and region R2, when considering margins, the die bond material DB is designed to stop expanding within the chip mounting region DBR. As a result, region DR1 of the die pad DP includes region DR3 covered with die bond material DB and region DR4 exposed from the die bond material DB.

[0060] Alternatively, when the die pad DP has a plurality of through holes DTH2 as in this embodiment, it is necessary to limit the amount of die bond material DB (see FIG. 7) applied for the following reasons.

[0061] The die bond material DB is applied to the chip mounting region DBR (more specifically, the central portion DCP and the connecting portion CNP) shown in FIG. 6, and then spreads to the periphery by pressing the semiconductor chip CP against it.

[0062] At this time, if the amount of die bond material DB (see Figure 7) applied is large, the die bond material DB may wrap around the side surface of the through hole DTH2. If the die bond material DB wraps around the side surface of the through hole DTH2, it becomes difficult to control the separation distance (gap) between the semiconductor chip CP and the die pad DP. For this reason, it is necessary to prevent the die bond material DB from wrapping around the side surface of the through hole DTH2. For this reason, the amount of die bond material DB applied is limited. As a result, the region DR1 of the die pad DP includes a region DR3 covered with the die bond material DB and a region DR4 exposed from the die bond material DB.

[0063] As described above, in the case of the semiconductor device PKG1 having a structure in which some of the wires BW are bonded to the die pad DP, the chip mounting region DBR may include the region DR4 exposed from the die bond material DB, regardless of whether the die pad DP has the through hole DTH2. Furthermore, in the case of the semiconductor device PKG1 having the through hole DTH2 at a position overlapping with the chip mounting region DBR as in this embodiment, the region DR1 of the die pad DP is likely to include the region DR4 exposed from the die bond material DB.

[0064] As shown in Fig. 7, a sealing body MR is embedded between the region DR4 and the surface CPb of the semiconductor chip CP. However, as shown as an example in Fig. 8, it has been found that the following problem occurs in the case of a die pad having a structure in which the convex portion CV is not provided. Fig. 8 is an enlarged cross-sectional view showing a semiconductor device that is an example of the semiconductor device shown in Fig. 7.

[0065] The semiconductor device PKG2 shown in Fig. 8 differs from the semiconductor device PKG1 shown in Fig. 7 in that the protrusion CV shown in Fig. 7 is not formed. When the protrusion CV is not formed, the distance between the semiconductor chip CP and the die pad DPZ can be reduced in the process of mounting the semiconductor chip CP on the die pad DP, and therefore the value of the distance DCD from the upper surface DPt of the die pad DP in the region DR4 to the surface CPb of the semiconductor chip CP is small.

[0066] In the example shown in FIG. 8, the value of the distance DCD is smaller than the average value of the particle diameters DMRf of the plurality of filler particles MRf contained in the encapsulant MR. Hereinafter, the average value of the particle diameters DMRf of the plurality of filler particles MRf contained in the encapsulant MR may be referred to as the average particle diameter DMRf. For example, the average particle diameter DMRf of the plurality of filler particles MRf is greater than 25 μm and less than 30 μm. The distance DCD between the upper surface DPt of the die pad DPZ in the region DR4 and the surface CPb of the semiconductor chip CP is, for example, less than 5 μm. In this case, the amount of die bond material DB applied can be reduced, which has been considered preferable.

[0067] <About peeling between the sealing body and the die pad> However, according to the study by the inventors of the present application, it has been found that in the semiconductor device PKG2 shown in FIG. 8, a cavity may occur between the sealing body MR and the die pad DPZ in the region DR4. It has also been found that this cavity is the starting point for the development of peeling between the sealing body MR and the die pad DPZ. An oxide film (e.g., a copper oxide film) is formed on the upper surface DPt of the die pad DPZ, but in the region DR2, the oxide film and the sealing body MR are firmly bonded. Therefore, it has been found that peeling develops between the oxide film of the die pad DPZ and the base material in the region DR2.

[0068] As already explained, in this embodiment, a wire bonding region WBR (see FIG. 4) to which a wire BW (see FIG. 3) is bonded is provided at the periphery of the die pad DP shown in FIG. 7. Therefore, if the above-mentioned peeling progresses and reaches the wire bonding region WBR, it will cause a decrease in the reliability of the electrical connection between the wire BW and the die pad DPZ (see FIG. 8).

[0069] The cause of the peeling described above is believed to be as follows. Specifically, in the process of forming the sealing body MR shown in FIG. 8, the sealing body MR is embedded between the region DR4 of the die pad DPZ and the semiconductor chip CP. At this time, because the distance DCD between the semiconductor chip CP and the die pad DPZ is small, the filler particles MRf contained in the sealing body MR are unlikely to enter between the semiconductor chip CP and the die pad DPZ. As a result, the sealing body MR embedded between the semiconductor chip CP and the region DR4 of the die pad DPZ has a higher concentration of the resin component MRr than the sealing body MR in other regions. In other words, the density of the filler particles MRf between the semiconductor chip CP and the region DR4 of the die pad DPZ is lower than the density of the filler particles MRf in other regions. Therefore, the shrinkage rate of the sealing body MR between the semiconductor chip CP and the die pad DPZ is higher than the shrinkage rate of the sealing body MR in other portions.

[0070] When the sealing body MR is cured in this state (in other words, the thermosetting resin component is cured by cure baking), the above-mentioned cavities (shrinkage cavities or casting cavities) occur in areas where the adhesive strength with the sealing body MR is relatively weak and in areas where particularly strong stress due to temperature changes is applied.

[0071] In this embodiment, since the adhesive strength between the semiconductor chip CP and the sealing body MR is strong, a cavity occurs at the interface between the die pad DPZ and the sealing body MR. Furthermore, since a particularly strong stress is applied near the boundary between the regions DR2 and DR4, a cavity occurs near the boundary between the regions DR2 and DR4.

[0072] The adhesive strength between the upper surface DPt of the die pad DP and the sealing body MR can be improved by forming a copper oxide film on the upper surface DPt of the die pad DP or by roughening the upper surface DPt. However, if the resin component of the die bond material DB seeps into the region DR4 of the die pad DPZ as described above, the sealing body MR will adhere to the die pad DPZ via this seeped resin component. The adhesive strength between the sealing body MR and the seeped resin component is relatively weak compared to the adhesive strength between the sealing body MR and the semiconductor chip CP. Therefore, even if an oxide film is formed on the upper surface DPt of the die pad DP, the above-mentioned voids will occur at the interface between the seeped resin and the sealing body MR when the sealing body MR is cured.

[0073] Based on the above-mentioned study results, the inventors of the present application have studied a technique for preventing the occurrence of voids between the semiconductor chip CP and the die pad DPZ. As a result of the study, it has been found that the occurrence of voids can be suppressed if filler particles MRf are interposed between the semiconductor chip CP and the die pad DP, as shown in Figure 7.

[0074] Specifically, when filler particles MRf are interposed between the semiconductor chip CP and the die pad DP, the sealing body MR filled between the semiconductor chip CP and the die pad DP can be prevented from shrinking at an extremely high rate during the sealing process. Filler particles MRf are inorganic particles, such as silica, and have a smaller linear expansion coefficient than the resin component MRr containing a thermosetting resin. Therefore, when the sealing body MR disposed between the semiconductor chip CP and the die pad DP contains filler particles MRf at a density similar to that of the sealing body MR in other parts, the shrinkage rate of the sealing body MR disposed between the semiconductor chip CP and the die pad DP can be reduced. Since the principle behind the formation of voids (shrinkage cavities or casting cavities) is as described above, reducing the shrinkage rate of the sealing body MR disposed between the semiconductor chip CP and the die pad DP can prevent or suppress the formation of voids.

[0075] Although FIGS. 7 and 8 only show filler particles MRf close to the average particle size DMRf, the multiple filler particles MRf may contain particles (hereinafter referred to as fine particles) that are significantly smaller than the average particle size DMRf. Fine particles include, for example, crushed particles of the multiple filler particles MRf, and their particle size is 20 percent or less of the average particle size DMRf of the multiple filler particles. When the filler particles MRf are pre-classified purchased products, the particle size specified in the purchased product specifications can be used as the average particle size DMRf of the multiple filler particles MRf. Furthermore, when the average particle size DMRf of the multiple filler particles MRf is determined by measurement, all filler particles MRf contained in a unit volume can be extracted, and the average particle size of the filler particles MRf excluding fine particles (e.g., particles with a particle size less than 5 μm) can be defined as the average particle size DMRf.

[0076] If only microparticles (e.g., particles with a particle size of less than 5 μm) are present between the semiconductor chip CP and the die pad DP, the effect of reducing the shrinkage rate of the sealing body MR is small. It is difficult to fill the gap between the semiconductor chip CP and the die pad DP with only microparticles at a high density (a density similar to the density of the filler particles MRf in the sealing body MR in other parts). For this reason, if the filler particles MRf interposed between the semiconductor chip CP and the die pad DP are only microparticles, the proportion of the resin component MRr in the sealing body MR will be high.

[0077] Therefore, it is more preferable that filler particles MRf having a relatively large particle size, more specifically, multiple filler particles MRf containing filler particles of an average particle size or larger, are interposed between the semiconductor chip CP and the die pad DP. From this perspective, it is preferable that the distance DCD from the upper surface DPt of the die pad DP to the surface CPb of the semiconductor chip CP in the region DR4 shown in FIG. 7 be larger than the average particle size DMRf of the multiple filler particles MRf. For example, in the example shown in FIG. 7, the average particle size DMRf of the multiple filler particles MRf is larger than 25 μm and smaller than 30 μm. In contrast, it is preferable that the distance DCD from the upper surface DPt of the die pad DP to the surface CPb of the semiconductor chip CP in the region DR4 be 30 μm or larger.

[0078] 7, in the present embodiment, since a convex portion is formed in region DR3 of the die pad DP, no matter how hard the semiconductor chip CP is pressed in the process of mounting the semiconductor chip CP on the die pad DP, the distance DCD from the upper surface DPt of the die pad DP in region DR4 to the surface CPb of the semiconductor chip CP is the same as or greater than the protrusion height HCV of the convex portion CV. Note that the protrusion height HCV of the convex portion CV is defined as the difference in height between the top surface CVt of the convex portion CV and the reference plane, which is the height of the upper surface DPt of the die pad DP in region DR3.

[0079] The protrusion height HCV of the convex portions CV is preferably greater than the average particle size DMRf of the plurality of filler particles MRf. For example, in the example shown in Fig. 7, the protrusion height HCV of the convex portions CV is preferably 30 µm or more.

[0080] In the example shown in Fig. 7, the surface CPb of the semiconductor chip CP and the top surface CVt of the convex portion CV are in contact with each other. Although not shown, as a modification of Fig. 7, a die bond material DB may be interposed between the surface CPb of the semiconductor chip CP and the top surface CVt of the convex portion CV. However, from the viewpoint of reducing variations in the separation distance (gap) between the semiconductor chip CP and the die pad DP, even if the die bond material DB is interposed between the semiconductor chip CP and the convex portion CV, it is preferable that the thickness of the die bond material DB disposed between the semiconductor chip CP and the convex portion CV is thin enough to be practically negligible.

[0081] Furthermore, from the viewpoint of reducing variations in the separation distance (gap) between the semiconductor chip CP and the die pad DP, it is particularly preferable that the surface CPb of the semiconductor chip CP and the top surface CVt of the convex portion CV are in contact with each other. The top surface CVt is preferably a flat surface parallel to the upper surface DPt of the die pad DP. This makes it easy to arrange the surface CPb and the top surface CVt of the convex portion CV in parallel.

[0082] In this embodiment, the die pad DP has one protrusion CV. When there is one protrusion CV, it is preferable that the protrusion CV is arranged so as to include the center DPc of the die pad, taking into consideration the balance when mounting the semiconductor chip CP. Therefore, as shown in Figure 7, the protrusion CV faces the center CPbc of the surface CPb of the semiconductor chip CP.

[0083] In order to reduce variations in the distance (spacing) between the semiconductor chip CP and the die pad DP, a modification in which a plurality of convex portions CV are provided on the die pad DP can be considered. This modification will be described later.

[0084] 5 and 6, the top surface CVt of the convex portion CV is circular. However, the shape of the top surface CVt is not limited to a circle, and may be, for example, a triangle or a polygon with more sides than a square.

[0085] The protrusion CV is formed by, for example, press molding using a mold, and therefore, a recess DEP is formed on the underside DPb of the die pad DP opposite to the protrusion CV, as shown in FIG.

[0086] <Modification of the layout of the convex portions> Next, modifications of the layout of the protrusions described with reference to FIGS. 5 to 7 will be described. FIG. 9 is an enlarged plan view of a die pad which is a modification of FIG. 5. FIG. 10 is an enlarged plan view of a die pad which is a modification of FIG. 6. FIG. 11 is an enlarged cross-sectional view of a semiconductor device when cut along line CC in FIG. 9. Note that the structures of the multiple protrusions CV shown in FIGS. 9 and 10 are similar. For this reason, FIG. 11 shows protrusion CV1 arranged on line CC in FIG. 9 as a representative example, but also includes the symbols for protrusions CV2, CV3, and CV4.

[0087] The semiconductor device PKG3 shown in FIG. 11 differs from the semiconductor device PKG1 shown in FIG. 7 in that it includes a die pad DP2 (see FIG. 11) instead of the die pad DP that the semiconductor device PKG1 has.

[0088] The die pad DP2 shown in Figures 9 to 11 differs from the die pad DP described with reference to Figures 5 to 7 in the number of protrusions CV and the layout of the protrusions CV. As shown in Figure 10, the die pad DP2 includes a central portion DCP including a center DPc of the top surface DPt, a peripheral portion DPP including a region DR2 (see Figure 9), and a plurality of coupling portions CNP that are arranged between the plurality of through holes DTH2 in a plan view and extend to couple the central portion DCP and the peripheral portion DPP. The plurality of coupling portions CNP include a coupling portion CNP1 extending from the central portion DCP toward the peripheral portion DPP, a coupling portion CNP2 arranged on the opposite side of the coupling portion CNP1 across the central portion DCP, a coupling portion CNP3 extending from the central portion DCP toward the peripheral portion DPP, and a coupling portion CNP4 arranged on the opposite side of the coupling portion CNP3 across the central portion DCP. This is similar to the die pad DP described with reference to Figures 5 to 7.

[0089] The die pad DP2 of this modified example has a convex portion CV1 provided in a region DR3 of the connecting portion CNP1 and protruding from a plane (reference plane) including the top surface DPt toward the semiconductor chip CP (see Figure 11), and a convex portion CV2 provided in a region DR3 of the connecting portion CNP2 and protruding from the plane (reference plane) including the top surface DPt toward the semiconductor chip CP (see Figure 11) with the same protrusion height HCV (see Figure 11) as the convex portion CV1.

[0090] Furthermore, the die pad DP2 has a convex portion CV3 that is provided in the region DR3 of the connecting portion CNP3 and that protrudes from a plane (reference plane) including the top surface DPt toward the semiconductor chip CP (see Figure 11) at the same protrusion height HCV (see Figure 11) as the convex portion CV1, and a convex portion CV4 that is provided in the region DR3 of the connecting portion CNP4 and that protrudes from a plane (reference plane) including the top surface DPt toward the semiconductor chip CP (see Figure 11) at the same protrusion height HCV (see Figure 11) as the convex portion CV1.

[0091] 11, the top surfaces CVt of the protrusions CV1, CV2, CV3, and CV4 are located at a different height from the upper surface DPt of the die pad DP. Therefore, the top surfaces CVt of the multiple protrusions CV are not included in the upper surface DPt of the die pad DP. Therefore, to be precise, each of the multiple protrusions CV is located at a position surrounded by the region DR3.

[0092] In this modified example, the semiconductor chip CP can be supported by multiple convex portions CV. Therefore, the surface CPb of the semiconductor chip CP is unlikely to be inclined relative to the upper surface DPt of the die pad DP. In other words, in this modified example, the semiconductor chip CP is easily mounted so that the surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP are parallel to each other. As a result, the value of the distance DCD between the surface CPb and the upper surface DPt in the region DR4 shown in FIG. 11 is unlikely to vary and is approximately the same value as the protrusion height HCV of each of the multiple convex portions CV. Therefore, filler particles MRf (more specifically, filler particles MRf having a particle size close to the average particle size DMRf) are easily supplied between the region DR4 of the die pad DP and the semiconductor chip CP.

[0093] Therefore, according to this modification, compared to the die pad DP shown in FIGS. 5 to 7, the occurrence of voids and the occurrence of peeling due to voids can be more stably suppressed.

[0094] Incidentally, from the viewpoint of stably supporting the semiconductor chip CP compared to the die pad DP shown in Figures 5 to 7, it is sufficient that at least the set of convex portions CV1 and CV2, or the set of convex portions CV3 and CV4, of the four convex portions CV shown in Figures 9 and 10, is present.

[0095] For example, if at least the set of convex portions CV1 and CV2 is formed among the four convex portions CV shown in Figure 9, it is possible to prevent the semiconductor chip CP from tilting relative to the die pad DP in the direction along the line CC in Figure 9.

[0096] As described above, the die pad DP is connected to a plurality of suspension leads HL that support the die pad DP. The coupling portions CNP1 and CNP2 shown in FIG. 10 are each disposed on an extension of the suspension lead HL1 (and on an extension of the suspension lead HL2) among the plurality of leads LD. Between the coupling portion CNP1 and the suspension lead HL1 is a wire bonding region WBR to which a wire BWD (see FIG. 3) is connected. If only the set of protrusions CV1 and CV2 shown in FIG. 9 is provided, as described above, tilting of the semiconductor chip CP in the direction along the line CC in FIG. 9 can be suppressed. Therefore, a cavity that could cause peeling is unlikely to occur between the protrusion CV1 and the wire bonding region WBR, and therefore, peeling can be prevented from progressing to the wire bonding region WBR.

[0097] 9 and 10, when four protrusions CV are formed, tilting of the semiconductor chip CP with respect to the die pad DP can be prevented not only in the direction along the line CC shown in FIG. 9 but also in the direction perpendicular to the line CC. Therefore, it is possible to prevent the occurrence of cavities that cause peeling between each of the multiple protrusions CV and the chip mounting region DBR and the outer edge. In this respect, it is particularly preferable that four protrusions CV are formed as shown in FIG. 9 and 10.

[0098] 10 is disposed on an extension of the suspension lead HL3 (and on an extension of the suspension lead HL4) among the multiple leads LD. Between the suspension lead CNP3 and the suspension lead HL3 is a wire bonding region WBR to which a wire BWD (see FIG. 3) is connected. As described above, in this modified example, cavities that could cause peeling are unlikely to occur between each of the multiple protrusions CV and the wire bonding region WBR, and therefore, peeling can be prevented from progressing to the wire bonding region WBR.

[0099] 9 and 10 show an example in which four protrusions CV are provided, but as a further modification, the number of protrusions CV may be five or more. For example, in addition to the four protrusions CV shown in Fig. 9 and 10, a fifth protrusion CV may be arranged at a position overlapping with the center DPc of the top surface DPt, as shown in Fig. 5 and 6.

[0100] 7 already explained, in the example shown in Fig. 11, the surface CPb of the semiconductor chip CP and the top surfaces CVt of the plurality of convex portions CV are in contact with each other. Although not shown, as a modification of Fig. 11, a die bond material DB may be interposed between the surface CPb of the semiconductor chip CP and the top surfaces CVt of the convex portions CV. However, from the viewpoint of reducing variations in the separation distance (spacing) between the semiconductor chip CP and the die pad DP, even if the die bond material DB is interposed between the semiconductor chip CP and the convex portions CV, it is preferable that the thickness of the die bond material DB disposed between the semiconductor chip CP and the convex portions CV is thin enough to be practically negligible.

[0101] 11 is the same as the top surface CVt of the protrusion CV described with reference to FIGS. 5 to 7. Each of the four protrusions CV in this modification is formed by, for example, press molding using a mold. Therefore, as shown in FIG. 11, recesses DEP are formed on the underside DPb of the die pad DP on the opposite side of each of the plurality of protrusions CV.

[0102] Except for the differences described above, the die pad DP2 and the semiconductor device PKG3 (see FIG. 11) shown in Figures 9 to 11 are similar to the die pad DP and the semiconductor device PKG1 described with reference to Figures 1 to 7. Therefore, redundant description will be omitted.

[0103] <Modified peeling prevention measures> Next, as modified examples of measures against peeling, measures different from the protrusions CV described with reference to Figs. 5 to 11 will be described. Fig. 12 is an enlarged plan view of a die pad which is another modified example of Fig. 5. Fig. 13 is an enlarged plan view of a die pad which is another modified example of Fig. 6. Fig. 14 is an enlarged cross-sectional view of the semiconductor device taken along line DD in Fig. 13. Fig. 15 is an enlarged cross-sectional view of the semiconductor device taken along line EE in Fig. 13.

[0104] The structures of the multiple linking portions CNP shown in Figures 12 and 13 are similar. For this reason, Figure 14 illustrates linking portion CNP1, which is located on line D-D in Figure 13, as a representative example, but also lists the reference numerals for linking portions CNP2, CNP3, and CNP4. Similarly, Figure 14 illustrates groove portion TR1, which is located on line D-D in Figure 13, as a representative example, but also lists the reference numerals for groove portion TR2, TR3, and TR4. Similarly, Figure 15 illustrates groove portion TR4, which is located on line E-E in Figure 13, as a representative example, but also lists the reference numerals for groove portion TR1, TR2, and TR3.

[0105] 12 and 13, the hatching shown in FIGS. 5 and 6 is omitted to make it easier to see the positions and shapes of the multiple groove portions TR. However, the range of each region on the upper surface DPt of the die pad DP and the range of each part on the die pad DP are the same as those in FIGS. 5 and 6.

[0106] The semiconductor device PKG4 shown in Fig. 14 differs from the semiconductor device PKG1 in that it includes a die pad DP3 instead of the die pad DP included in the semiconductor device PKG1 shown in Fig. 7. The semiconductor device PKG4 has a structure that suppresses the occurrence of the above-mentioned peeling by providing a plurality of groove portions TR instead of one or a plurality of convex portions CV described using Figs.

[0107] 12 to 15 includes a top surface DPt, a plurality of through holes DTH2 penetrating the die pad DP3 in the thickness direction, a central portion DCP including a center DPc of the top surface DPt, a peripheral portion DPP on the periphery of the die pad DP, and a plurality of connecting portions CNP arranged between the plurality of through holes DTH2 in plan view and extending to connect the central portion DCP and the peripheral portion DPP, similar to the die pad DP shown in FIGS.

[0108] 12 and 13, the die pad DP3 includes grooves TR formed in each of the multiple coupling portions CNP. As shown in FIG. 14, each of the multiple grooves TR includes a portion P1 exposed from the die bond material DB and facing the surface CPb of the semiconductor chip CP via the sealing body MR, and a portion P2 disposed in a position not overlapping the semiconductor chip CP. A distance DCD1 from the bottom surface TRb of the portion P1 of the groove TR to the surface CPb of the semiconductor chip CP is longer than a distance DCD2 from the top surface DPt of the center portion DCP to the surface CPb of the semiconductor chip CP. Some of the multiple filler particles MRf are interposed between the surface CPb of the semiconductor chip CP and the portion P1 of the groove TR of the die pad DP.

[0109] In this modified example, since there is no convex portion CV, the value of the distance DCD2 shown in Fig. 14 may be smaller than the value of the average particle diameter DMRf of the filler particles MRf. Therefore, in the process of forming the sealing body MR, measures are needed to make it easier to supply the filler particles MRf (especially filler particles MRf with a size close to the average particle diameter DMRf) to the region DR4 shown in Fig. 12.

[0110] Therefore, in this modification, the value of the distance DCD1 shown in FIG. 14 is increased by providing a groove TR in the region DR4 shown in FIG. 12. The value of the distance DCD1 is, for example, larger than the value of the average particle size DMRf of the plurality of filler particles MRf contained in the sealing body MR. In this modification, the bottom surface TRb of the groove TR (see FIG. 14) and the top surface DPt of the die pad DP at a position where the groove TR is not provided are different in height. In this modification, the bottom surface TRb and side surface TRs of the groove TR are part of the top surface DPt of the die pad DP. In other words, the bottom surface TRb and side surface TRs of the groove TR are included in the top surface DPt of the die pad DP.

[0111] 14, the trench TR includes a portion P1 arranged at a position overlapping the semiconductor chip CP (i.e., a portion having a surface facing the surface CPb of the semiconductor chip CP) and a portion P2 arranged at a position not overlapping the semiconductor chip CP. In the example shown in FIG. 14, the portion P2 is located closer to the peripheral portion DPP than the portion P1. In other words, as shown in FIGS. 12 and 13, each of the multiple trenches TR is arranged so as to straddle the outer edge of the chip mounting region DBR in a plan view. Therefore, in the process of forming the sealing body MR, the filler particles MRf are easily supplied from the gap between the semiconductor chip CP and the trench TR.

[0112] Here, for each of the multiple connecting portions CNP, the direction away from the center of the die pad is defined as the extension direction, and the direction perpendicular to the extension direction is defined as the direction perpendicular to the extension direction. In this modification, each of the grooves TR shown in FIG. 13 is arranged to penetrate the connecting portion CNP in the width direction. Specifically, as shown in FIG. 15, the connecting portion CNP has one side surface CNPs1 and a side surface CNPs2 opposite to the side surface CNPs1. One end of the groove TR intersects with the side surface CNPs1 of the connecting portion CNP. The other end of the groove TR intersects with the side surface CNPs2 of the connecting portion CNP. In this case, as shown in FIG. 15, an opening through which multiple filler particles MRf can be supplied is formed between the semiconductor chip CP and the die pad DP3 in the region DR4 of the die pad DP (see FIG. 12). This allows the filler particles MRf to be reliably supplied between the semiconductor chip CP and the die pad DP3.

[0113] As a further modification of this modification, the groove portion TR may terminate midway along the connecting portion CNP without reaching either or both of the side surface CNPs1 and the side surface CNPs2 of the connecting portion CNP. In other words, the groove portion TR may have a recessed shape surrounded by a wall. Even in this case, since an opening is formed between the semiconductor chip CP and the portion P2 of the groove portion TR in the cross section shown in FIG. 14, it is possible to supply filler particles MRf between the semiconductor chip CP and the groove portion TR.

[0114] Conversely, as another modification of this modification, when each of the trenches TR shown in FIG. 13 is arranged to penetrate the connecting portion CNP in the width direction as described with reference to FIG. 15, the portion P2 shown in FIG. 14 may not be present. In this case, the trench terminates at a portion corresponding to the portion P1 in FIG. 14, making it difficult to supply filler particles MRf (see FIG. 14) from the direction perpendicular to the EE line shown in FIG. 13 (the extension direction of the connecting portion CNP). However, since the cross-sectional structure shown in FIG. 15 is present, it is possible to supply filler particles MRf between the trenches TR and the semiconductor chip CP.

[0115] Incidentally, the depth of the groove portion TR, which is defined as the difference between the intervals DCD2 and DCD1 shown in FIG. 14, is preferably as follows: If the depth of the groove portion TR is equal to or greater than the average particle size DMRf of the plurality of filler particles MRf, this is preferable because it ensures space for arranging the filler particles MRf even when, for example, the value of the interval DCD2 is close to zero. However, in reality, it is unlikely that the value of the interval DCD2 will be zero, and a space of several microns will be ensured. Therefore, it is preferable that the depth of the groove portion TR is greater than the value of the interval DCD1 shown in FIG. 14, which is the average particle size DMRf of the plurality of filler particles MRf. Even when the value of the interval DCD1 is greater than the value of the average particle size DMRf of the plurality of filler particles MRf, the depth of the groove portion TR may be smaller than the value of the average particle size DMRf of the plurality of filler particles MRf.

[0116] For example, when the average particle size DMRf of the plurality of filler particles MRf is 30 μm, the depth of the groove portion TR is preferably 25 μm or more, and particularly preferably 30 μm or more.

[0117] 14, in this modification, the groove portion TR further includes a portion P3 that is located between the portion P1 and the central portion DCP and is covered with the die bond material DB. In other words, a part of the groove portion TR is covered with the die bond material DB.

[0118] Although not shown in the figures, if the die bond material DB terminates at a position that does not reach the groove portion TR, there is a possibility that an area will be created between the die bond material DB and the groove portion TR where the distance between the semiconductor chip CP and the die pad DP is the distance DCD2 shown in Fig. 14 and the die pad DP and the semiconductor chip CP face each other without the die bond material DB in between. In this area, filler particles MRf will not be supplied, and there is a possibility that a cavity will occur that will cause the above-mentioned peeling.

[0119] 14, when the groove portion TR has a portion P3 covered with the die bond material DB, the region that causes the above-mentioned voids does not occur. Therefore, from the viewpoint of reducing the possibility of voids occurring, it is preferable that the groove portion TR has the portion P3 as in this modification.

[0120] 13 , the multiple coupling portions CNP of this modification include a coupling portion CNP1 extending from the central portion DCP toward the peripheral portion DPP and a coupling portion CNP2 disposed on the opposite side of the coupling portion CNP1 across the central portion DCP. The die pad DP3 includes a groove TR1 provided in the coupling portion CNP1 and a groove TR2 provided in the coupling portion CNP2. The depths of the grooves TR1 and TR2 are equal to each other. Furthermore, the multiple coupling portions CNP further include a coupling portion CNP3 extending from the central portion DCP toward the peripheral portion DPP and a coupling portion CNP4 disposed on the opposite side of the coupling portion CNP3 across the central portion DCP. The die pad DP3 includes a groove TR3 provided in the coupling portion CNP3 and a groove TR4 provided in the coupling portion CNP4.

[0121] 12 and 13, each of coupling portions CNP1, CNP2, CNP3, and CNP4 overlaps with region DR4 of die pad DP. Therefore, by providing grooves TR in the portions of coupling portions CNP1, CNP2, CNP3, and CNP4 that overlap with region DR4, it is possible to prevent cavities that cause peeling from occurring in any of coupling portions CNP1, CNP2, CNP3, and CNP4.

[0122] As shown in Fig. 13, among the multiple connecting portions CNP, a wire bonding region WBR to which a wire BWD (see Fig. 3) is connected is located on an extension line of connecting portion CNP1. As shown in Fig. 14, a groove TR1 is provided in connecting portion CNP1, which can suppress the occurrence of cavities that cause peeling in the groove TR. This prevents peeling from starting from the cavities and progressing toward the wire bonding region WBR.

[0123] Similarly, on the extension lines of each of the connecting portions CNP2, CNP3, and CNP4, there is a wire bonding region WBR to which the wire BWD (see FIG. 3) is connected. As described above, the groove portion TR is provided in the portion of each of the connecting portions CNP2, CNP3, and CNP4 that overlaps with the region DR4, so that the peeling can be prevented from progressing toward any of the plurality of wire bonding regions WBR.

[0124] Except for the differences described above, the die pad DP3 and the semiconductor device PKG4 (see FIG. 14) shown in Figures 12 to 15 are similar to the die pad DP and the semiconductor device PKG1 described with reference to Figures 1 to 7. Therefore, redundant description will be omitted.

[0125] <Modifications of the die pad shape> Next, modified examples of the shape of the die pad (particularly the planar shape of the through hole DTH2) will be described. Figures 16 and 17 are enlarged plan views showing modified examples of the die pads shown in Figures 9 and 10, respectively.

[0126] 10, the coupling portions CNP1 and CNP2 are arranged along the extending direction of the suspension leads HL1 and HL2, and the coupling portions CNP3 and CNP4 are arranged along the extending direction of the suspension leads HL3 and HL4.

[0127] 17, the connecting portions CNP1 and CNP2 are arranged along the X direction, and the connecting portions CNP3 and CNP4 are arranged along the Y direction.

[0128] Furthermore, in the die pad DP4, the planar shape of the plurality of through holes DTH2 is rectangular. In this case, compared to the die pad DP2 shown in FIG. 10, the area of ​​the chip mounting region DBR that overlaps with any of the plurality of through holes DTH2 is larger. In other words, when the die pad DP4 is used, the area of ​​the surface CPb of the semiconductor chip CP shown in FIG. 2 that is in close contact with the sealing body MR is larger than that of the die pad DP. The value of the adhesion strength between the sealing body MR and the semiconductor chip CP is greater than the value of the adhesion strength between the sealing body MR and the die pad DP and the value of the adhesion strength between the sealing body MR and the die bond material DB. Therefore, from the viewpoint of improving the adhesion between the semiconductor chip CP and the sealing body MR, the die pad DP4 of this modified example is preferable.

[0129] Even in the case where multiple connecting portions CNP are arranged along the X direction or Y direction inclined at 45 degrees with respect to the extending direction of the hanging lead HL, as in this modified example, the technology relating to the convex portion CV described using FIGS. 5 to 11 and the technology relating to the groove portion TR described using FIGS. 12 to 15 can be applied.

[0130] That is, although Figures 16 and 17 have been described as a modified example of Figures 9 and 10 as a representative example, they can also be applied in combination with the layout of multiple connecting portions CNP shown in Figure 17 and the layout of convex portions CV shown in Figure 6.

[0131] 16 and 17 are similar to the die pad DP2 and semiconductor device PKG3 (see FIG. 11) described with reference to FIGS. 9 to 11, except for the differences described above. Therefore, a duplicated description will be omitted.

[0132] <Method of manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device described with reference to Figures 1 to 17 will be described. Below, a method for manufacturing the semiconductor device PKG1 shown in Figure 7 will be taken up as a representative example, and only differences from the representative examples will be described for the methods for manufacturing the semiconductor device PKG3 shown in Figure 11 and the semiconductor device PKG4 shown in Figure 14. Note that the method for manufacturing the semiconductor device using the die pad DP4 shown in Figures 16 and 17 is the same as the methods for manufacturing the semiconductor devices described above, and therefore description thereof will be omitted.

[0133] FIG. 18 is an explanatory diagram showing the flow of an assembly process for any of the plurality of semiconductor devices described with reference to FIGS. 1 to 17. FIG. 18 shows the main steps of the manufacturing process for the semiconductor device PKG1 shown in FIG. 1, but various modified examples can be applied in addition to the assembly flow shown in FIG. 18. For example, FIG. 18 does not show a marking process for forming a product identification mark on the sealing body MR (see FIG. 1), but this can also be added between the sealing process and the plating process. Furthermore, for example, FIG. 18 does not show an inspection process, but there are cases where an inspection process is added, for example, after the singulation process.

[0134] <Base material preparation process> In the base material preparing step shown in Fig. 18, a lead frame LF shown in Fig. 19 is prepared. Fig. 19 is an enlarged plan view showing the lead frame prepared in the base material preparing step shown in Fig. 18.

[0135] The lead frame LF prepared in this step has a plurality of device forming portions LFd inside a frame portion LFf. The lead frame LF is a substrate having a plurality of device forming portions LFd, but for ease of viewing, only one of the plurality of device forming portions LFd is shown enlarged in FIG. 19. The lead frame LF is made of metal, and in this embodiment, is made of, for example, copper (Cu) or a copper alloy.

[0136] 19, a die pad DP, which is a chip mounting portion, is formed in the center of the device forming portion LFd. A plurality of suspension leads HL are connected to the die pad DP and are arranged to extend toward the corners of the device forming portion LFd. That is, the die pad DP is supported by the suspension leads HL and is also supported by the frame portion LFf of the lead frame LF via these suspension leads HL.

[0137] Moreover, a plurality of leads LD are formed between the plurality of suspension leads HL around the die pad DP, and the plurality of leads LD are connected to the frame portion LFf, respectively.

[0138] The leads LD are connected to one another via tie bars TB. The tie bars TB function as connecting members that connect the leads LD, and also as dam members that suppress resin leakage in the sealing process shown in FIG. 18. The tie bars TB are connected to the leads LD and the frame portion LFf of the lead frame LF. One end of each of the leads LD is connected to the frame portion LFf of the lead frame LF. Therefore, until the lead cutting process shown in FIG. 18, each of the leads LD is supported by the frame portion LFf of the lead frame LF.

[0139] The lead frame LF prepared in this step has the structure of the die pad DP described using Figures 4 to 7, the structure of the die pad DP2 described using Figures 9 to 11, the structure of the die pad DP3 described using Figures 12 to 15, or the structure of the die pad DP4 described using Figures 16 and 17. In the example shown in Figure 19, the lead frame LF has the structure of the die pad DP described using Figures 4 to 7.

[0140] That is, the die pad DP has an upper surface DPt, and the upper surface DPt includes a region DR1 and a region DR2 surrounding the periphery of the region DR1 in a plan view. As shown in Fig. 7, in the die bonding process shown in Fig. 18, the region DR1 includes a region DR3 having a surface facing the surface CPb of the semiconductor chip CP via the die bond material DB, and a region DR4 having a surface facing the surface CPb of the semiconductor chip CP via the sealing body MR without the die bond material DB. The die pad DP is provided in the region DR3 and has a protrusion CV protruding upward from a plane (reference plane) including the upper surface DPt.

[0141] 19, the die pad DP has wire bonding regions WBR at eight locations, each of which is covered with a metal film MF2. In the example shown in FIG. 19, the die pad DP has wire bonding regions WBR at eight locations, each of which is covered with a metal film MF2. In each of the wire bonding regions WBR, a plurality of through holes DTH1 are formed. In the example shown in FIG. 19, the die pad DP has wire bonding regions WBR at eight locations, each of which is covered with a metal film MF2. In each of the wire bonding regions WBR, a plurality of through holes DTH1 are formed. In addition, the die pad DP has a plurality of through holes DTH2 that penetrate the die pad DP in its thickness direction (the Z direction shown in FIG. 2). Each of the plurality of through holes DTH2 is disposed in a position that overlaps a portion of a chip mounting region DBR, which is a region where a semiconductor chip is to be mounted in the die bonding process shown in FIG. 18.

[0142] The lead frame shown in Fig. 19 is manufactured, for example, as follows. In the base material preparation step, first, a metal plate that will be the base of the lead frame LF is prepared (metal plate preparation step). The metal plate is made of a metal whose main component is copper. The metal plate is formed by rolling a metal material.

[0143] Next, the substrate preparation process includes a pattern formation process in which, after the metal plate preparation process, the metal plate is processed to form a metal pattern as shown in FIG. 19. In this pattern formation process, a cutting process is performed to cut multiple leads LD, die pads DP, etc. into the shape shown in FIG. 19. In addition, in the pattern formation process, a drilling process is performed to form multiple through holes DTH1 in the die pad DP. For example, the cutting process can be performed by pressing a die between a punch and a die, or by removing unnecessary portions by etching. In addition, the drilling process to form the through holes DTH1 and DTH2 can also be performed by cutting a metal plate using a drill, in addition to the above-mentioned die pressing method and etching.

[0144] 19 is formed by, for example, press working using a mold. In this case, as described with reference to FIG. 7, a recess DEP is formed on the lower surface DPb of the die pad DP on the opposite side to the protrusion CV.

[0145] 12 to 15, a plurality of grooves TR are formed in the pattern forming process by removing a portion of the lead frame LF (see FIG. 19) by, for example, etching or laser irradiation.

[0146] The base material preparation step also includes a metal film formation step of forming a metal film MF2 on the upper surface DPt of the die pad DP after the pattern formation step. In the metal film formation step, in addition to the multiple metal films MF2 shown in FIG. 19, a metal film MF1 is also formed.

[0147] The substrate preparation step also includes a bending step in which a part (offset portion) of the suspension lead is bent to offset the position of the die pad DP. This bending step can be performed after the pattern formation step or the metal film formation step.

[0148] <Die bonding process> Next, in the die bonding step (semiconductor chip mounting step) shown in Fig. 18, a semiconductor chip CP is mounted on a die pad DP as shown in Fig. 20. Fig. 20 is an enlarged cross-sectional view showing a state in which a semiconductor chip is mounted on the die pad of the lead frame shown in Fig. 19. Fig. 21 is an enlarged plan view showing a state in which a paste-like die bonding material DBP is applied to the die pad in the die bonding step. Fig. 22 is an enlarged cross-sectional view taken along line FF in Fig. 21. Fig. 23 is an enlarged cross-sectional view showing a state in which the semiconductor chip is pressed against the die pad shown in Fig. 22 to spread the paste-like die bonding material.

[0149] As shown in Figure 20, the die bonding process includes a chip preparation process for preparing a semiconductor chip CP having a surface CPb, a surface CPt located opposite to the surface CPb, and a plurality of electrode pads PD arranged on the surface CPt. The die bonding process also includes a chip mounting process for mounting the semiconductor chip CP on a region DR1 (see Figure 21) of the die pad DP via a die bond material DB so that the surface CPb of the semiconductor chip CP faces the upper surface DPt of the die pad DP. The chip preparation process is a process for transporting the semiconductor chip CP to be mounted in the chip mounting process to a location where the chip mounting process will be performed. The process for manufacturing the semiconductor chip CP is performed in advance before the die bonding process is performed.

[0150] For example, as explained using Figures 5 to 7, the upper surface DPt of the die pad DP after the die bonding process includes a region DR3 having a surface facing the surface CPb of the semiconductor chip CP via the die bonding material DB, and a region DR4 having a surface facing the surface CPb of the semiconductor chip CP without the die bonding material DB.

[0151] The die bonding process includes a die bonding material application process of applying a die bonding material DBP to multiple locations in a region DR3 (see FIG. 21) of the die pad DP, as shown in FIG. 21 and FIG. 22. The die bonding material DBP shown in FIG. 21 and FIG. 22 is a paste-like material before hardening.

[0152] 2 is an adhesive used when die-bonding a semiconductor chip CP, and is, for example, a resin adhesive made of an epoxy-based thermosetting resin containing metal particles made of silver or the like, or a metal bonding material such as a solder material. The die-bonding material DBP is, for example, a conductive paste (so-called silver paste) containing an epoxy resin before hardening and a plurality of silver particles. Alternatively, the die-bonding material DBP is a conductive paste (so-called solder paste) containing a solvent and a solder component dissolved in the solvent.

[0153] 21 and 22, in the die bond material application step, the die bond material DBP is applied to the region DR1 (specifically, the region DR3). The die bond material DBP is not applied onto the protrusion CV, but is applied around the protrusion CV. Considering the ease of spreading the die bond material DBP in the die bond material expansion step described later, it is preferable that the die bond material DBP be applied at least to both sides of the protrusion CV in the die bond material application step.

[0154] 9 and 11, it is preferable that the die bond material DBP be applied to both sides of each of the plurality of convex portions CV. Furthermore, when the die pad DP2 is used, in addition to both sides of each of the plurality of convex portions CV, the die bond material DBP (see FIG. 21) may be applied to the center DPc of the top surface DPt of the die pad DP2 shown in FIG.

[0155] 12 and 13 is used, in the die bond material application step, the die bond material DBP is applied to any multiple locations in the region DR3 shown in Fig. 12. For example, the die bond material DBP is applied to a total of five locations, including the center DPc shown in Fig. 12 and four locations around the center DPc.

[0156] In order to prevent the die bonding material DBP from spreading to the wire bonding region WBR, the die bonding material DBP is not applied to the region DR4 in this process. This also applies to the case where the die pad DP2 shown in Fig. 9 is used, the case where the die pad DP3 shown in Fig. 12 is used, and the case where the die pad DP4 shown in Fig. 16 is used.

[0157] As a modification of this embodiment, there is a method of applying a die bond material DBP onto the protrusion CV in the die bond material application process. However, if the die bond material DBP is applied onto the protrusion CV, a gap may occur between the side surface of the protrusion CV and the die bond material DBP in the die bond material expansion process. Therefore, from the viewpoint of preventing the occurrence of a gap, it is preferable to apply the die bond material DBP to a location other than the protrusion. In the example shown in FIG. 21, a protrusion CV is formed at the center DPc of the upper surface DPt of the die pad DP, so the die bond material DBP is not applied to the center DPc.

[0158] As shown in Fig. 22, the height HDB of the applied die bond material DBP is preferably higher than the protruding height HCV of the convex portion CV. The height HDB is determined by the distance (shortest distance) from the apex of the die bond material DBP to the reference plane when the position of the upper surface DPt of the die pad DP in region DR3 is taken as the reference plane. As shown in Fig. 22, by making the height HDB of the applied die bond material DBP higher than the protruding height HCV of the convex portion CV, the surface CPb of the semiconductor chip CP can come into contact with the die bond material DBP before coming into contact with the convex portion CV in the die bond material expanding step shown in Fig. 23.

[0159] The die bonding step includes a die bonding material expanding step of pressing the semiconductor chip CP against the die pad DP to expand the die bonding material DBP within the region DR3, as shown in FIG.

[0160] In the die bond material expanding step, as shown by the outline arrows in Fig. 23, a pressing force F1 is applied to the die bond material DBP while the surface CPb of the semiconductor chip CP is in contact with the die bond material DBP. Since each of the die bond materials DBP is sandwiched between the semiconductor chip CP and the die pad DP, it is expanded in the expanding direction D1.

[0161] When the semiconductor chip CP is further pressed toward the die pad DP from the state shown in Fig. 23, the surface CPb of the semiconductor chip CP and the top surface CVt of the convex portion CV come into contact with each other as shown in Fig. 20. Therefore, when the die bond material expanding step is completed, the distance between the surface CPb of the semiconductor chip CP and the top surface DPt of the die pad DP in the region DR3 (i.e., the thickness of the die bond material DBP) is determined by the protrusion height HCV of the convex portion CV (see Fig. 20).

[0162] In the die bond material expanding process, if a portion of the die bond material DBP rises onto the top surface CVt of the convex portion CV (see FIG. 20), there is a possibility that a portion of the die bond material DBP will remain on the convex portion CV and the semiconductor chip CP. However, even if a portion of the die bond material DBP rises onto the top surface CVt of the convex portion CV, most of the risen portion will be pushed out to the periphery of the convex portion CV by the pressing force F1 shown in FIG.

[0163] Therefore, when this step is completed, it can be considered that the surface CPb of the semiconductor chip CP and the top surface CVt of the convex portion CV are substantially in contact with each other, as shown in FIG.

[0164] Although not shown in the drawings, the die bonding process includes a die bonding material hardening process in which the die bonding material DBP is hardened after the die bonding material expanding process. When the die bonding material hardening process is completed, a hardened die bonding material DB is obtained as shown in FIG.

[0165] If the die bond material DBP is a resin adhesive made of epoxy-based thermosetting resin containing metal particles such as silver, the die bond material DBP (see Figure 22) is heated (cure baked) to a temperature above the curing temperature of the thermosetting resin in the die bond material curing process. If the die bond material DBP is a solder paste, the die bond material DBP (see Figure 22) is heated to a temperature above the melting point of the solder components to volatilize the solvent, and then cooled. This process is called reflow processing.

[0166] 9 to 11, in the manufacturing method of a semiconductor device using the die pad DP2, in the die bonding process, the surface CPb of the semiconductor chip CP shown in FIG. 11 comes into contact with the top surfaces CVt of the plurality of convex portions CV. As already explained, the value of the protrusion height HCV of the convex portion CV1 shown in FIG. 11 is the same as the value of the protrusion height HCV of the convex portion CV2, the protrusion height HCV of the convex portion CV3, and the protrusion height HCV of the convex portion CV4. Therefore, by pressing the semiconductor chip CP until the surface CPb of the semiconductor chip CP also comes into contact with each of the plurality of convex portions CV, the surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP can be made parallel to each other.

[0167] When the surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP are parallel to each other, the value of the distance DCD in the region DR4 shown in Fig. 11 can be made close to the design value (in other words, the value defined by the protrusion height HCV of each of the multiple convex portions CV). As a result, it is possible to suppress the occurrence of cavities, which are the cause of peeling as already explained, in any location in the region DR4 shown in Fig. 9.

[0168] In the manufacturing method of a semiconductor device using the die pad DP3 described with reference to Figures 12 to 15, the convex portion CV shown in Figures 20 to 23 does not exist. Therefore, in the die bonding process, it is necessary to control the end position of the die bonding material expanding process in which the semiconductor chip CP is pressed against the die pad DP (the value of the distance DCD2 shown in Figure 14 when the die bonding material expanding process is completed). In addition, it is necessary to control so that the surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP are parallel to each other when the die bonding material expanding process is completed.

[0169] However, as already described, the die pad DP3 has groove portions TR formed in each of the multiple coupling portions CNP. Therefore, for example, even if the value of the distance DCD2 is smaller than the value of the average particle size DMRf of the filler particles MRf shown in FIG. 14, the value of the distance DCD1 can be set to a value larger than the value of the average particle size DMRf of the filler particles MRf.

[0170] <Wire bonding process> Next, in the wire bonding process shown in Figure 18, as shown in Figures 2 and 3, multiple electrode pads PD formed on the surface CPt of the semiconductor chip CP are electrically connected to the die pad DP or multiple leads LD, respectively, via multiple wires (conductive members) BW.

[0171] The multiple wires BW shown in Fig. 3 include wires BWC that electrically connect the electrode pads PD of the semiconductor chip CP and the multiple leads LD. One end of the wire BWC is bonded to the electrode pads PD of the semiconductor chip CP, and the other end is bonded to a wire bonding region (a portion covered with the metal film MF1 shown in Fig. 4) at the tip of the lead LD. The multiple wires BW also include wires BWD that electrically connect the electrode pads PD of the semiconductor chip CP and the die pad DP, or the die pad DP and the lead LD. At least one end of the wire BWD is bonded to a wire bonding region WBR of the die pad DP (a portion covered with the metal film MF2 shown in Fig. 4).

[0172] In other words, the wire bonding process includes a step of connecting the wire BWD to the region DR2 of the die pad DP shown in Fig. 5. Although redundant explanations will be omitted, the same applies to the die pad DP2 shown in Fig. 9, the die pad DP3 shown in Fig. 12, or the die pad DP4 shown in Fig. 16.

[0173] There are various variations in the bonding method of the wire BW, but for example, a bonding method is used in which a bonding tool (e.g., a capillary) is used to apply heat and ultrasound to the bonding portion of the wire BW to press it against the bonded portion (electrode pad PD, metal film MF1, or metal film MF2).

[0174] <Sealing process> Next, in the sealing process shown in Fig. 18, the semiconductor chip CP, the plurality of wires BW, and the die pad DP shown in Fig. 2 are sealed with resin to form a sealing body MR. The sealing body MR shown in Fig. 7, 11, or 14 is an insulating material containing a plurality of filler particles MRf and a resin component MRr.

[0175] In this process, for example, with the lead frame LF placed in a molding die having a cavity (not shown), resin is supplied into the space formed by the cavity, and then the resin is hardened to form the sealing body (sealing portion) MR. This method of forming the sealing body MR is called the transfer molding method.

[0176] The cavities that cause peeling, as already explained, occur when there is variation in the shrinkage rate of the sealing body MR in the heating step (cure bake step) for hardening the sealing body MR in the sealing step.

[0177] In the case of this embodiment, as described above, in the sealing step, some of the plurality of filler particles MRf are supplied between the surface CPb of the semiconductor chip CP and the region DR4 of the die pad DP.

[0178] This makes it possible to suppress variations in the shrinkage rate within the sealing body MR, which can cause voids to form. By suppressing variations in the shrinkage rate within the sealing body MR, the formation of voids can be suppressed, and as a result, the progression of the peeling described above can be suppressed.

[0179] <Plating process> Next, in the plating process shown in Fig. 18, a metal film MC is formed by plating on the exposed surfaces of the plurality of leads LD shown in Fig. 2. The metal film MC formed in this process is formed to improve the wettability of the solder material used as a bonding material when the semiconductor device PKG1 is mounted on a mounting board (not shown).

[0180] In this process, it is preferable to form a metal film MC made of solder on the exposed surface of the lead LD. Furthermore, electroplating, which deposits ionized metal ions on the exposed surface of the lead LD, can be used as a method for forming the metal film MC. The electroplating method is preferable because the film quality of the metal film MC can be easily controlled by controlling the current during the formation of the metal film MC. Furthermore, electroplating is preferable because it can shorten the time required to form the metal film MC.

[0181] <Lead cutting process> Next, in a lead cutting step shown in FIG. 18, the outer lead portions OLD of each of the leads LD shown in FIG. 3 are cut, and each of the leads LD is separated from the lead frame LF shown in FIG.

[0182] In this embodiment, after the leads LD are cut, they are bent as shown in FIG. 2 to form a plurality of leads LD.

[0183] In this process, the tie bars TB (see FIG. 19) connecting the leads LD shown in FIG. 19 are cut. Furthermore, each of the leads LD is separated from the frame portion LFf. As a result, the leads LD become separate, independent members. Furthermore, after the leads LD are separated, the sealing body MR and the leads LD are supported by the frame portion LFf via the suspension leads HL (see FIG. 19).

[0184] The leads LD and tie bars TB are cut by press working using a cutting die, and the cut leads LD can be shaped, for example, as shown in FIG. 2, by bending the outer lead portions OLD of the leads LD using press working with a molding die (not shown).

[0185] <Singulation process> Next, in the singulation step shown in FIG. 18, the plurality of suspension leads HL shown in FIG. 19 are cut to separate the semiconductor packages in each device formation portion LFd.

[0186] 19 are cut to obtain a semiconductor package (more specifically, an object to be inspected before the inspection process). The cutting method can be, for example, similar to the lead forming process described above, by cutting by press working using a cutting die (not shown).

[0187] After this process, necessary inspections and tests such as visual inspection and electrical test are performed, and those that pass become the finished semiconductor device PKG1 shown in FIG. 1, the semiconductor device PKG3 shown in FIG. 11, or the semiconductor device PKG4 shown in FIG. 14.

[0188] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0189] BW, BWC, BWD Wire (conductive material) CNP,CNP1,CNP2,CNP3,CNP4 connection part CNPs1, CNPs2 side CP semiconductor chip CPb,CPt plane CPbc,DPc center CV, CV1, CV2, CV3, CV4 convex part CVt top surface D1 Extension direction DB, DBP die bond material (adhesive) DBR chip mounting area DCD, DCD1, DCD2 interval DCP center DMRf average particle size DP, DP2, DP3, DP4, DPZ die pads DPb bottom surface (main surface, back surface) DPP periphery DPt top surface (main surface, chip mounting surface) DR1,DR2,DR3,DR4 area DTH1,DTH2 through hole F1 Pressing force HL, HL1, HL2, HL3, HL4 Hanging lead ILD inner lead part LD lead LDt top surface LF lead frame LFd Device Formation Department LFf frame MC,MF1,MF2 Metal film MR sealing body (sealing part) MRb bottom surface (back surface, mounted surface) MRc Corner MRf filler particles MRr resin component MRs1,MRs2,MRs3,MRs4 sides (main sides) MRt Top surface (surface) OLD outer lead part P1,P2,P3 part PD electrode pads (electrodes) PKG1, PKG2, PKG3, PKG4 Semiconductor device TB Tie Bar TR,TR1,TR2,TR3,TR4 Groove TRb bottom WBR Wire Bonding Area

Claims

1. a die pad having a first surface including a first region and a second region surrounding the periphery of the first region in a plan view; a semiconductor chip including a second surface facing the first surface, a third surface located on the opposite side of the second surface, and a plurality of electrodes arranged on the third surface, the semiconductor chip being mounted on the first region of the die pad via a die bond material; a plurality of leads arranged around the die pad in a plan view; A plurality of wires; an encapsulant that encapsulates the semiconductor chip, the plurality of wires, and the first surface of the die pad; Including, the plurality of wires includes a first wire connected to the second region of the die pad; The first region of the die pad is a third region having a surface facing the second surface of the semiconductor chip via the die bond material; a fourth region having a surface facing the second surface of the semiconductor chip with the sealing body interposed therebetween; Including, the die pad is provided in the third region and includes a first protrusion protruding from a plane including the first surface toward the semiconductor chip; the encapsulant includes a plurality of filler particles; A semiconductor device, wherein some of the plurality of filler particles are interposed between the second surface of the semiconductor chip and the first surface of the die pad located in the fourth region of the die pad.

2. In claim 1, the die pad has a plurality of through holes penetrating the die pad in a thickness direction, The semiconductor device, wherein the second surface of the semiconductor chip is in contact with the sealing body at positions where the plurality of through holes are formed.

3. In claim 2, The semiconductor device, wherein the first protrusion faces the center of the second surface of the semiconductor chip.

4. In claim 2, The die pad is a central portion including a center of the first surface; a peripheral portion including the second region; a plurality of connecting portions that are arranged between the plurality of through holes in a plan view and extend to connect the central portion and the peripheral portion; Equipped with The plurality of connecting portions are a first connecting portion extending from the central portion toward the peripheral portion; a second connecting portion disposed on the opposite side of the first connecting portion with the central portion interposed therebetween; Including, The die pad is the first protrusion provided in the third region of the first connection portion and protruding from a plane including the first surface toward the semiconductor chip; a second protrusion provided in the third region of the second connecting portion and protruding from a plane including the first surface toward the semiconductor chip at the same protrusion height as the first protrusion; The semiconductor device comprises:

5. In claim 4, The plurality of connecting portions are a third connecting portion extending from the central portion toward the peripheral portion; a fourth connecting portion disposed on the opposite side of the third connecting portion with the central portion interposed therebetween; Further comprising: The die pad is a third protrusion provided in the third region of the third connecting portion and protruding from a plane including the first surface toward the semiconductor chip at the same protrusion height as the first protrusion; a fourth protrusion provided in the third region of the fourth connection portion and protruding from a plane including the first surface toward the semiconductor chip at the same protrusion height as the first protrusion; The semiconductor device further comprises:

6. In claim 4, a plurality of suspension leads for supporting the die pad are connected to the die pad; each of the first connecting portion and the second connecting portion is disposed on an extension line of a first hanging lead among the plurality of hanging leads; A semiconductor device, wherein a first wire bonding region to which the first wire is connected is located between the first connecting portion and the first suspension lead.

7. In claim 1, a distance between the first surface of the die pad and the second surface of the semiconductor chip in the fourth region that is greater than an average particle size of each of the plurality of filler particles;

8. a die pad including a first surface, a plurality of through holes, a central portion including a center of the first surface, a peripheral portion on the periphery of the first surface, and a plurality of connecting portions that are arranged between the plurality of through holes in a plan view and extend to connect the central portion and the peripheral portion; a semiconductor chip including a second surface facing the first surface, a third surface located on the opposite side of the second surface, and a plurality of electrodes arranged on the third surface, the semiconductor chip being mounted in a chip mounting area on the first surface of the die pad via a die bond material; a plurality of leads arranged around the die pad in a plan view; A plurality of wires; an encapsulant that encapsulates the semiconductor chip, the plurality of wires, and the first surface of the die pad; Including, the plurality of wires includes a first wire connected to the peripheral portion of the die pad; the die pad includes a groove formed in each of the plurality of connecting portions, The groove portion is a first portion exposed from the die bond material and facing the second surface of the semiconductor chip via the sealing body; a second portion disposed at a position not overlapping the semiconductor chip; Including, a first distance from a bottom surface of the first portion of the groove to the second surface of the semiconductor chip is longer than a second distance from a plane including the first surface of the central portion to the second surface of the semiconductor chip; the encapsulant includes a plurality of filler particles; a semiconductor device, wherein some of the plurality of filler particles are interposed between the second surface of the semiconductor chip and the first portion of the groove of the die pad;

9. In claim 8, Each of the plurality of coupling portions has a first side surface and a second side surface opposite the first side surface, one end of the groove intersects with the first side surface, The other end of the groove intersects with the second side surface.

10. In claim 9, The plurality of connecting portions are a first connecting portion extending from the central portion toward the peripheral portion; a second connecting portion disposed on the opposite side of the first connecting portion with the central portion interposed therebetween; a third connecting portion extending from the central portion toward the peripheral edge portion; a fourth connecting portion disposed on the opposite side of the third connecting portion with the central portion interposed therebetween; Further comprising: The die pad is a first groove portion provided in the first connecting portion; a second groove portion provided in the second connecting portion; a third groove portion provided in the third connecting portion; a fourth groove portion provided in the fourth connecting portion; The semiconductor device further comprises:

11. In claim 8, A semiconductor device, wherein a first wire bonding region to which the first wire is connected is located on an extension line of a first connecting portion among the plurality of connecting portions.

12. In claim 8, The semiconductor device, wherein the groove portion further includes a third portion located between the first portion and the central portion and covered with the die bond material.

13. In claim 8, The semiconductor device, wherein the first interval is greater than an average particle size of each of the plurality of filler particles.

14. (a) preparing a lead frame having a die pad with a first surface including a first region and a second region surrounding the periphery of the first region in a plan view, and a plurality of leads arranged around the periphery of the die pad in a plan view; (b) preparing a semiconductor chip having a second surface, a third surface located opposite to the second surface, and a plurality of electrodes arranged on the third surface, and mounting the semiconductor chip on the first region of the die pad via a die bond material so that the second surface faces the first surface; (c) connecting a first wire to the second region of the die pad; (d) forming a sealing body that seals the semiconductor chip, the first wires, and the die pad with a resin containing a plurality of filler particles; Including, In the step (b), the first region of the die pad is a third region having a surface facing the second surface of the semiconductor chip via the die bond material; a fourth region having a surface facing the second surface of the semiconductor chip without the die bond material therebetween; Including, the die pad of the lead frame prepared in the step (a) is provided in the third region and includes a first protrusion protruding upward from a plane including the first surface; A method for manufacturing a semiconductor device, wherein in the step (d), some of the plurality of filler particles are supplied between the second surface of the semiconductor chip and the fourth region of the die pad.

15. In claim 14, the die pad has a plurality of through holes penetrating the die pad in a thickness direction, In the step (d), a sealing body is formed so that the second surface of the semiconductor chip contacts the sealing body at a position where the plurality of through holes of the die pad and the semiconductor chip overlap.

16. In claim 15, The step (b) comprises: (b1) applying the die bond material to a plurality of locations in the third region of the die pad; (b2) pressing the semiconductor chip against the die pad to spread the die bond material within the third region; Including, In the step (b2), a distance between the second surface of the semiconductor chip and the first surface of the die pad is determined by a protrusion height of the first convex portion.

17. In claim 16, In the step (b1), the die bond material is applied to at least both sides of the first convex portion.

18. In claim 16, The die pad is a central portion including a center of the first surface; a peripheral portion including the second region; a plurality of connecting portions that are arranged between the plurality of through holes in a plan view and extend to connect the central portion and the peripheral portion; Equipped with The plurality of connecting portions are a first connecting portion extending from the central portion toward the peripheral portion; a second connecting portion disposed on the opposite side of the first connecting portion with the central portion interposed therebetween; Including, The die pad is the first protrusion provided in the third region of the first connection portion and protruding from a plane including the first surface toward the semiconductor chip; a second protrusion provided in the third region of the second connecting portion and protruding from a plane including the first surface toward the semiconductor chip at the same protrusion height as the first protrusion; A method for manufacturing a semiconductor device, comprising:

19. In claim 18, The plurality of connecting portions are a third connecting portion extending from the central portion toward the peripheral portion; a fourth connecting portion disposed on the opposite side of the third connecting portion with the central portion interposed therebetween; Further comprising: The die pad is a third protrusion provided in the third region of the third connecting portion and protruding from a plane including the first surface toward the semiconductor chip at the same protrusion height as the first protrusion; a fourth protrusion provided in the third region of the fourth connection portion and protruding from a plane including the first surface toward the semiconductor chip at the same protrusion height as the first protrusion; The method for manufacturing a semiconductor device further comprises:

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