Voltage regulator and semiconductor device

Abstract

To provide a voltage regulator that can avoid gain peaking.SOLUTION: A voltage regulator 1 comprises: a differential amplifier circuit AMP that amplifies and outputs the difference between a reference voltage Vref and a divided voltage obtained by dividing the voltage output by an output transistor MP1 to control a gate of the output transistor MP1; and a phase compensation circuit PCC. The phase compensation circuit PCC comprises: a first transistor MN1 whose drain is connected to the output terminal of the differential amplifier circuit AMP; a second transistor MN2 whose drain is connected to a gate of the first transistor MN1 and whose gate is connected to the gate of the first transistor MN1 via at least a first resistor R3 and to a drain of the output transistor MP1 via a first capacitor C1; and a second capacitor C2 connected in parallel to a first resistor R3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a voltage regulator and a semiconductor device. [Background technology]

[0002] Conventionally, voltage regulators capable of outputting a constant voltage lower than the input voltage have been widely used as integrated circuits (ICs) for power supplies of electronic devices. Such voltage regulators have a phase compensation function capable of suppressing oscillation. Non-Patent Document 1, for example, is known as a document disclosing a voltage regulator with a phase compensation function. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS: REGULAR PAPERS, VOL. 54, NO. 9 SEPTEMBER 2007 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional circuits such as those described in Non-Patent Document 1 include a boost circuit to improve transient characteristics. Under heavy loads, the poles of the VOUT terminal and the DRVG terminal approach each other, which can cause a deterioration in the phase margin.

[0005] First, problems associated with the prior art will be described with reference to FIGS.

[0006] FIG. 7 is a circuit diagram showing a voltage regulator according to the prior art. First, a voltage regulator 90 according to the prior art will be described with reference to the same figure. The voltage regulator 90 generates a constant output voltage vout lower than an input voltage vin applied between a ground terminal and a power supply terminal, and outputs the output voltage vout to an output terminal. A predetermined load resistance and load capacitance (not shown) are connected to the output terminal.

[0007] Specifically, the voltage regulator 90 includes an output transistor MP1, a differential amplifier circuit 92, a phase compensation circuit 99, resistors R1 and R2, and an N-channel transistor MN2, an N-channel transistor MN1, a resistor R3, and a capacitor C1.

[0008] The differential amplifier circuit 92 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The differential amplifier circuit 92 also has a positive power supply terminal and a negative power supply terminal (not shown). The inverting input terminal is connected to a reference voltage circuit, and a predetermined reference voltage vref is applied to it. The non-inverting input terminal is connected to the connection point of resistors R1 and R2. The output terminal is connected to the gate terminal of the output transistor MP1. The differential amplifier circuit 92 amplifies and outputs the difference between the reference voltage vref and a divided voltage (i.e., the voltage at the connection point of resistors R1 and R2) obtained by dividing the voltage output by the output transistor MP1, thereby controlling the gate of the output transistor MP1.

[0009] The drain of the transistor MN2 is connected to the output terminal of the differential amplifier circuit 92, the source is connected to the ground terminal, and the gate is connected to one end of the resistor R3 and the drain of the transistor MN1. The drain of the transistor MN1 is connected to the gate of the transistor MN2, the source is connected to the ground terminal, and the gate is connected to the other end of the resistor R3 and one end of the capacitor C1. The other end of the capacitor C1 is connected to the output terminal and the drain of the output transistor MP1.

[0010] A predetermined current control circuit is connected to the drain of the transistor MN2 and the drain of the transistor MN1.

[0011] FIG. 8 is a circuit diagram showing a small-signal equivalent circuit of a voltage regulator according to the prior art. This figure shows the small-signal equivalent circuit of the voltage regulator 90 shown in FIG. 7. Capacitance Cd1 represents the drain-source capacitance of transistor MN1, and resistance rd1 represents the drain-source resistance of transistor MN1. Furthermore, transfer conductance gm1 and transfer conductance gm2 represent the transfer conductances of transistors MN1 and MN2.

[0012] Here, the relationship between the voltage at node N92 connected to the gate of transistor MN2 and the output voltage vout at the drain of output transistor MP1 (in other words, the transfer function when the output terminal is the input and node N92 is the output) can be expressed by the following equation (1):

[0013]

number

[0014] 9 is a graph showing the gain-frequency characteristics of a voltage regulator according to the prior art. The horizontal axis of the graph represents frequency [Hz], and the vertical axis represents gain [dB]. The first pole frequency fp1 shown in the graph is the frequency of the first pole generated by the load capacitance connected to the output terminal. The second pole frequency fp2 and the third pole frequency fp3 are the frequencies of the second pole and the third pole at node N92.

[0015] FIG. 9(A) shows the frequency characteristics of the gain under normal load. The frequency fp1 of the first pole and the pole occurring at node N91 are sufficiently separated. Therefore, under normal load, phase compensation is sufficiently possible. Here, the frequency fp2 of the second pole and the frequency fp3 of the third pole are located at ω 2It is calculated from the term, the term ω, and the integer term. Under heavy load, the frequency fp1 of the first pole moves into the high frequency region and approaches the pole generated at node N91. In other words, under heavy load, phase compensation can become difficult.

[0016] Figure 9(B) shows the gain-frequency characteristics when the capacitance C1 is increased and the transfer conductance gm1 of transistor MN1 is also increased as an improvement measure under heavy loads. In this case, phase compensation at node N92 is effective starting from the low-frequency range, improving the phase. However, in this case, the attenuation coefficient becomes small, which can cause gain peaking.

[0017] The present invention has been made in view of the above circumstances, and has an object to provide a voltage regulator and a semiconductor device that are capable of avoiding gain peaking. [Means for solving the problem]

[0018] A voltage regulator according to one embodiment of the present invention is a voltage regulator comprising: a differential amplifier circuit that amplifies and outputs the difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor, and controls the gate of the output transistor; and a phase compensation circuit, wherein the phase compensation circuit comprises: a first transistor having a drain connected to the output terminal of the differential amplifier circuit; a second transistor having a drain connected to the gate of the first transistor, a gate connected to the gate of the first transistor via at least a first resistor, and connected to the drain of the output transistor via a first capacitor; and a second capacitor connected in parallel with the first resistor. [Effects of the Invention]

[0019] According to the present invention, it is possible to provide a voltage regulator and a semiconductor device that are capable of avoiding gain peaking. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a circuit diagram illustrating a voltage regulator according to a first embodiment. [Figure 2] 1 is a circuit diagram showing a small signal equivalent circuit of a voltage regulator according to a first embodiment. [Figure 3] 4 is a graph showing frequency characteristics of gain in the voltage regulator according to the first embodiment. [Figure 4] FIG. 10 is a circuit diagram illustrating a voltage regulator according to a second embodiment. [Figure 5] FIG. 10 is a circuit diagram showing a small signal equivalent circuit of a voltage regulator according to a second embodiment. [Figure 6] 10 is a graph showing frequency characteristics of gain in a voltage regulator according to a second embodiment. [Figure 7] FIG. 1 is a circuit diagram showing a voltage regulator according to a conventional technique. [Figure 8] FIG. 1 is a circuit diagram showing a small signal equivalent circuit of a voltage regulator according to a conventional technique. [Figure 9] 1 is a graph showing frequency characteristics of gain in a voltage regulator according to a conventional technique. DETAILED DESCRIPTION OF THE INVENTION

[0021] [Embodiment] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A voltage regulator according to an aspect of the present invention will be described in detail below with reference to preferred embodiments and the accompanying drawings.

[0022] [First embodiment] FIG. 1 is a circuit diagram showing a voltage regulator according to a first embodiment. First, the circuit configuration of the voltage regulator 1 according to the first embodiment will be described with reference to the same figure. The voltage regulator 1 generates a constant output voltage vout that is lower than an input voltage vin applied between a ground terminal and a power supply terminal, and outputs the output voltage vout to an output terminal. A predetermined load resistance and load capacitance (not shown) are connected to the output terminal.

[0023] Specifically, voltage regulator 1 includes an output transistor MP1, a differential amplifier circuit AMP, a phase compensation circuit PCC, resistors R1 and R2. Phase compensation circuit PCC includes N-channel transistors MN1 and MN2, resistors R3, and capacitors C1 and C2. That is, voltage regulator 1 differs from voltage regulator 90 according to the prior art described above in that it further includes capacitor C2 connected in parallel with resistor R3.

[0024] In the following description, the transistor MN1 may be referred to as a first transistor, the transistor MN2 as a second transistor, the capacitor C1 as a first capacitor, the capacitor C2 as a second capacitor, and the resistor R3 as a first resistor.

[0025] The differential amplifier circuit AMP has an inverting input terminal, a non-inverting input terminal, and an output terminal. The differential amplifier circuit AMP also has a positive power supply terminal and a negative power supply terminal (not shown). The inverting input terminal is connected to a reference voltage circuit, to which a predetermined reference voltage vref is applied. The non-inverting input terminal is connected to the connection point of resistors R1 and R2. The output terminal is connected to the gate terminal of the output transistor MP1. The differential amplifier circuit AMP amplifies and outputs the difference between the reference voltage vref and a divided voltage (i.e., the voltage at the connection point of resistors R1 and R2) obtained by dividing the voltage output by the output transistor MP1, thereby controlling the gate of the output transistor MP1.

[0026] The transistor MN2 has a drain connected to the output terminal of the differential amplifier circuit AMP, a source connected to the ground terminal, and a gate connected to one end of the resistor R3, one end of the capacitor C2, and the drain of the transistor MN1. The transistor MN1 has a drain connected to the gate of the transistor MN2, a source connected to the ground terminal, and a gate connected to the other end of the resistor R3, the other end of the capacitor C2, and one end of the capacitor C1. The other end of the capacitor C1 is connected to the output terminal and the drain of the output transistor MP1.

[0027] A predetermined current control circuit is connected to the drains of transistor MN1 and transistor MN2.

[0028] FIG. 2 is a circuit diagram showing a small-signal equivalent circuit of the voltage regulator according to the first embodiment. Capacitance Cd1 represents the drain-source capacitance of transistor MN1, and resistance rd1 represents the drain-source resistance of transistor MN1. Also, transconductances gm1 and gm2 represent the transconductances of transistor MN1 and transistor MN2.

[0029] Here, the relationship between the voltage Vg at the gate of transistor MN2 and the output voltage vout at the drain of output transistor MP1 (in other words, the transfer function when the output terminal is taken as the input and the gate of transistor MN2 is taken as the output) can be expressed by the following equation (2).

[0030]

Equation

[0031] Note that in equation (2), it is approximated that Cd1 << C1 and Cd1 << C2.

[0032] FIG. 3 is a graph showing the frequency characteristics of the gain in the voltage regulator according to the first embodiment. The horizontal axis of the figure indicates the frequency [Hz], and the vertical axis indicates the gain [dB]. The frequency fp1 of the first pole shown in the figure is the frequency of the first pole generated by the output capacitance connected to the output terminal. The frequencies fp4 and fp5 of the fourth and fifth poles are obtained from the terms of ω and the integer terms existing in the denominator of equation (2). The frequency fp6 of the sixth pole is a zero point obtained from the terms of ω and the integer terms existing in the numerator of equation (2). 2 The terms of ω and the integer terms existing in the denominator of equation (2). The frequency fp6 of the sixth pole is a zero point obtained from the terms of ω and the integer terms existing in the numerator of equation (2).

[0033] According to this embodiment, the attenuation coefficient of the transfer function shown in equation (2) is increased by adding a capacitor C2 in parallel with the resistor R3. The increased attenuation coefficient suppresses gain peaking. The capacitance ratio between the capacitors C1 and C2 is preferably about 1:1 to 4:1.

[0034] [Second embodiment] FIG. 4 is a circuit diagram showing a voltage regulator according to a second embodiment. First, the circuit configuration of a voltage regulator 1A according to the second embodiment will be described with reference to the same figure. In the description of the voltage regulator 1A, components similar to those of the voltage regulator 1 will be denoted by the same reference numerals and description thereof may be omitted. The voltage regulator 1A differs from the voltage regulator 1 in that it further includes a resistor R4. In the following description, the resistor R4 may be referred to as a second resistor.

[0035] Resistor R4 is connected between the gate of transistor MN2 and resistor R3. In other words, one end of resistor R4 is connected to the gate of transistor MN2 and the drain of transistor MN1, and the other end is connected to the gate of transistor MN1 via resistor R3. Note that in voltage regulator 1A, as in voltage regulator 1, capacitor C2 is connected in parallel with resistor R3.

[0036] 5 is a circuit diagram showing a small-signal equivalent circuit of a voltage regulator according to a second embodiment. This figure shows the small-signal equivalent circuit of the voltage regulator 1A shown in FIG. 4. Capacitance Cd1 represents the drain-source capacitance of transistor MN1, and resistance rd1 represents the drain-source resistance of transistor MN1. Furthermore, transfer conductance gm1 and transfer conductance gm2 represent the transfer conductances of transistors MN1 and MN2.

[0037] Here, the relationship between the voltage Vg at the gate of transistor MN2 and the output voltage vout at the drain of the output transistor MP1 (in other words, the transfer function when the output terminal is the input and the gate of transistor MN2 is the output) can be expressed by the following equation (3):

[0038]

number

[0039] FIG. 6 is a graph showing the frequency characteristics of gain in the voltage regulator according to the second embodiment. The horizontal axis of the graph indicates frequency [Hz], and the vertical axis indicates gain [dB]. As in FIG. 3, the frequency fp1 of the first pole shown in the graph is the frequency of the first pole generated by the output capacitance connected to the output terminal. The frequency fp4 of the fourth pole and the frequency fp5 of the fifth pole are determined by the ω 2 The frequency fp6 of the sixth pole is determined by the ω term and the integer term in the numerator of equation (2).

[0040] Here, in equation (3), g m1 If R4>1 is satisfied, when A+jbω (A is the real part and bω is the imaginary part), the imaginary part of the zero point becomes positive, improving the phase. Note that the resistance ratio between resistors R3 and R4 is preferably between 1:1 and 4:1.

[0041] According to this embodiment, gain peaking can be avoided and the phase margin can be secured by making the imaginary part of the zero point positive, thereby realizing a voltage regulator with excellent AC characteristics even if the output capacitance is small.

[0042] The voltage regulator 1 or 1A according to this embodiment can be realized as a predetermined semiconductor device. The semiconductor device needs to include at least the voltage regulator 1 or 1A. In addition to the voltage regulator 1 or 1A, the semiconductor device may also include a predetermined control circuit, peripheral circuits, etc.

[0043] Although the embodiments have been described above as modes for carrying out the present invention, the specific aspects of the present invention are not limited to these embodiments, and various modifications, substitutions, design changes, etc. can be made without departing from the spirit of the present invention. For example, the same effect can be obtained by swapping all NMOS transistors and PMOS transistors and reversing the circuit configuration.

[0044] Furthermore, it is also possible to combine the above-described embodiments and the configurations described in the embodiments. [Explanation of symbols]

[0045] 1...Voltage regulator MP1: Output transistor AMP...differential amplifier circuit PCC…Phase compensation circuit MN1, MN2...Transistors R1, R2, R3, R4...Resistance C1, C2…capacity

Claims

1. a differential amplifier circuit that amplifies and outputs a difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor, and controls a gate of the output transistor; a phase compensation circuit; A voltage regulator comprising: The phase compensation circuit a first transistor whose drain is connected to an output terminal of the differential amplifier circuit; a second transistor having a drain connected to the gate of the first transistor, a gate connected to the gate of the first transistor via at least a first resistor, and a drain of the output transistor via a first capacitor; a second capacitor connected in parallel with the first resistor; A voltage regulator comprising:

2. a capacitance ratio of the first capacitance to the second capacitance is between 1:1 and 4:1; 2. The voltage regulator according to claim 1.

3. a second resistor having one end connected to the gate of the first transistor and the other end connected to the gate of the second transistor via the first resistor; 2. The voltage regulator according to claim 1.

4. a resistance ratio between the first resistor and the second resistor is between 1:1 and 4:1; 4. The voltage regulator according to claim 3.

5. A semiconductor device comprising the voltage regulator according to claim 1 .

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