Current compensation circuit and semiconductor device

Abstract

To provide a current compensation circuit, etc., capable of maintaining a constant collector current of a bipolar transistor (hereinafter, "Tr") regardless of a magnitude of a current amplification factor when an emitter is grounded.SOLUTION: A current compensation circuit 100 includes: a constant current source 16; a drain (hereinafter, "D") connected to one end of the constant current source 16; a PMOSTr 12 including a source (hereinafter, "S") connected to a VDD terminal 1; a TrQ2 whose collector (hereinafter, "C") and base (hereinafter, "B") are connected to a GND terminal 2; a TrQ1 configured with the same process variations as the TrQ2 and whose C is connected to the GND terminal 2; PMOSTr 11 and 13 which constitute a current mirror circuit with the PMOSTr 12 and supply current to emitters (hereinafter, "E") of the TrQ1 and Q2, respectively; and a NMOSTr 14 and a NMOSTr 15 which constitute a current mirror circuit that replicates the base current of the TrQ1 and adds it to a connection point between the constant current source 16 and the PMOSTr 12.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a current compensation circuit and a semiconductor device. [Background technology]

[0002] The voltage Vbe of the base-emitter diode of the parasitic bipolar transistor formed in the CMOS process is expressed by the following equation (1) using Boltzmann's constant k, absolute temperature T, electron charge q, collector current Ic, reverse saturation current Is, and natural logarithm ln. Vbe=(kT / q)×ln(Ic / Is) ---(1) The voltage Vbe is used as information for conversion into absolute temperature T, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-44297 Summary of the Invention [Problem to be solved by the invention]

[0004] As shown in the above equation (1), the voltage Vbe is a function of the collector current Ic, so in order to reduce process variations in the voltage Vbe, it is necessary to keep the collector current Ic constant. However, since the collector terminal of a parasitic bipolar transistor is the substrate, it is not possible to directly pass a constant current from the collector terminal to the parasitic bipolar transistor. Therefore, as an alternative, a constant current is directly passed from the emitter terminal to the parasitic bipolar transistor.

[0005] h is the current amplification factor when the emitter is grounded FEWhen is sufficiently large, the emitter current Ie is approximately equal to the collector current Ic (Ie ≒ Ic), so keeping the emitter current Ie constant can reduce the effect of process variations in the voltage Vbe even if keeping the collector current Ic constant.

[0006] However, in the case of a parasitic bipolar transistor, h FE is relatively small, so h FE Unlike when h is sufficiently large, the magnitude of the base current Ib that flows from the emitter terminal to the base terminal cannot be ignored. In other words, for the voltage Vbe of the base-emitter diode of the parasitic bipolar transistor, keeping the emitter current Ie constant cannot be substituted for keeping the collector current Ic constant. Therefore, in the case of a parasitic bipolar transistor, FE For the base-emitter diode voltage Vbe of a bipolar transistor with a small capacitance, a new technique is required to replace the constant emitter current Ie.

[0007] SUMMARY OF THE INVENTION In consideration of the above circumstances, an object of the present invention is to provide a current compensation circuit and a semiconductor device that can keep the collector current of a bipolar transistor constant regardless of the magnitude of the current amplification factor when the emitter is grounded. [Means for solving the problem]

[0008] A current compensation circuit according to the present invention is a circuit for supplying a current to the emitter of a first bipolar transistor, the first bipolar transistor including a collector connected to a first power supply terminal, a base connected to the first power supply terminal, and an emitter, the current compensation circuit comprising: a second bipolar transistor including a collector connected to the first power supply terminal, a base, and an emitter, and configured to have the same process variation as the first bipolar transistor; a first transistor including a drain connected to the emitter of the second bipolar transistor, a gate, and a source connected to a second power supply terminal; a second transistor including a gate connected to the gate of the first transistor, a drain connected to its own gate, and a source connected to the second power supply terminal; a third transistor having a drain connected to the emitter of the second bipolar transistor, a gate connected to a connection point between the drain of the second transistor, the gate of the second transistor, and the gate of the first transistor, and a source connected to the second power supply terminal; a constant current source having a first end connected to the connection point and a second end connected to the first power supply terminal; a fourth transistor having a drain connected to the base of the second bipolar transistor, a source connected to the first power supply terminal, and a gate connected to its own drain; and a fifth transistor having a drain connected to the first end of the constant current source, a gate connected to the gate and the drain of the fourth transistor, and a source connected to the first power supply terminal.

[0009] The semiconductor device of the present invention is a semiconductor device having an integrated circuit formed on a semiconductor substrate, characterized in that it comprises a first bipolar transistor including a collector connected to a first power supply terminal, a base connected to the first power supply terminal, and an emitter, and the current compensation circuit. [Effects of the Invention]

[0010] According to the present invention, the collector current of the bipolar transistor can be kept constant regardless of the magnitude of the current amplification factor when the emitter is grounded. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a circuit diagram showing a configuration example of a current compensation circuit and a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 6 is a circuit diagram showing a configuration example of a current compensation circuit and a semiconductor device according to a second embodiment of the present invention. [Figure 3] 10 is a circuit diagram showing a first configuration example of a current compensation circuit and a voltage reduction circuit in a semiconductor device according to a second embodiment. FIG. [Figure 4] 10 is a circuit diagram showing a first configuration example of a current compensation circuit and a current adjustment circuit in a voltage reduction circuit of a semiconductor device according to a second embodiment. FIG. [Figure 5] FIG. 10 is a circuit diagram showing a second configuration example of a current compensation circuit and a voltage reduction circuit in a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a circuit diagram showing a second configuration example of a current compensation circuit and a current adjustment circuit in a voltage reduction circuit of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, a current compensation circuit and a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0013] [First embodiment] FIG. 1 is a circuit diagram of a current compensation circuit 100 and a semiconductor device 10, which are examples of a current compensation circuit and a semiconductor device according to a first embodiment of the present invention.

[0014] The semiconductor device 10 is configured to include an integrated circuit (IC) integrated on a semiconductor substrate, and includes, for example, a transistor Q2 which is a parasitic bipolar transistor formed in a CMOS process, a current compensation circuit 100 which supplies a compensated current to the emitter E of the transistor Q2, and an output terminal To which is connected to the emitter E of the transistor Q2. The collector C and base B of the transistor Q2 which is a first bipolar transistor are each connected to a GND terminal 2 which is a power supply terminal that supplies a ground voltage.

[0015] The current compensation circuit 100 includes, for example, PMOS transistors 11, 12, and 13, NMOS transistors 14 and 15, a constant current source 16, a switch 17, and a transistor Q1 as a second bipolar transistor. The transistor Q1 is a bipolar transistor configured to have the same process variation as the transistor Q2.

[0016] The PMOS transistor 11, serving as a first transistor, has a drain connected to the emitter E of the transistor Q1, a gate, and a source connected to a VDD terminal 1 serving as a power supply terminal that supplies a power supply voltage different from the ground voltage. The PMOS transistor 12, serving as a second transistor, has a gate connected to the gate of the PMOS transistor 11, a drain connected to the gate of the PMOS transistor 12, and a source connected to the VDD terminal 1. The PMOS transistor 13, serving as a third transistor, has a drain connected to the emitter E of the transistor Q2, a gate connected to a junction P1 between the gate of the PMOS transistor 11 and the gate and drain of the PMOS transistor 12, and a source connected to the VDD terminal 1. In other words, the PMOS transistors 11, 12, and 13 form a current mirror circuit that replicates the drain current of the PMOS transistor 12 and supplies the drain current from the PMOS transistor 11 and the PMOS transistor 13.

[0017] An NMOS transistor 14 serving as a fourth transistor has a drain connected to the base B of the transistor Q1, a source connected to the GND terminal 2, and a gate connected to its own drain. An NMOS transistor 15 serving as a fifth transistor has a drain connected to a connection point P1 via a switch 17, a gate connected to the gate and drain of the NMOS transistor 14, and a source connected to the GND terminal 2. A constant current source 16 has a first end connected to the connection point P1 and a second end connected to the GND terminal 2. The switch 17 connects between the connection point P1 and the drain of the NMOS transistor 15 in a manner that allows it to be switched between a conductive state and an open state, i.e., to be opened and closed.

[0018] Next, the operations of the current compensation circuit 100 and the semiconductor device 10 will be described. In the current compensation circuit 100 and semiconductor device 10 configured as described above, the transistor Q1 is configured to have the same process variations as the transistor Q2, and therefore functions as a dummy transistor simulating the transistor Q2. Therefore, a compensation current that compensates for the base current shunted from the base B of the transistor Q2 is generated based on the base current shunted from the base B of the transistor Q1.

[0019] The generated compensation current is added to the constant current sunk by the constant current source 16 at the node of the connection point P1 via NMOS transistors 14 and 15, which form a current mirror circuit, and switch 17. The current obtained by adding the constant current and the compensation current is supplied to the emitter E of transistor Q2 via PMOS transistors 12 and 13.

[0020] In the current compensation circuit 100 and semiconductor device 10 that operate in this manner, the current supplied to the emitter E of transistor Q2 is the sum of the compensation current and the constant current of constant current source 16, and therefore the collector current Ic flowing through the collector C of transistor Q2 is determined by the current value of constant current source 16, regardless of whether the magnitude of the collector current Ic is negligible compared to the base current shunted from the base B of transistor Q2. Therefore, if the current value of constant current source 16 can be determined accurately, a highly accurate collector current Ic can be obtained.

[0021] The accuracy of the current value of the constant current source 16 can be ensured by trimming, for example, during pre-shipment inspection. During trimming, compensation current is not required, so the switch 17 is opened. That is, the drain of the NMOS transistor 15 is electrically disconnected from the connection point P1. On the other hand, after trimming is completed, the switch 17 is short-circuited, and the drain of the NMOS transistor 15 and the connection point P1 are electrically connected.

[0022] According to the current compensation circuit 100 and the semiconductor device 10, the h FE Even if there are process variations in h FE Therefore, the current compensation circuit 100 and the semiconductor device 10 can keep the collector current Ic constant regardless of the magnitude of the emitter current Ie. FE Without causing variations in the base-emitter diode voltage Vbe due to FE The current compensation circuit 100 and the semiconductor device 10 are suitable for application to, for example, a temperature sensor or BGR circuit that obtains a highly accurate temperature (absolute temperature T) based on the base-emitter diode voltage Vbe obtained from the above-mentioned equation (1).

[0023] [Second embodiment] FIG. 2 is a circuit diagram of a current compensation circuit 200 and a semiconductor device 20, which are examples of a current compensation circuit and a semiconductor device according to a second embodiment of the present invention.

[0024] The semiconductor device 20 differs from the semiconductor device 10 in that it includes a current compensation circuit 200 instead of the current compensation circuit 100, but is otherwise substantially the same. The current compensation circuit 200 differs from the current compensation circuit 100 in that it further includes a voltage reduction circuit 30, but is otherwise substantially the same. Therefore, in this embodiment, components that differ from the semiconductor device 10 and the current compensation circuit 100 will be mainly described, and components that are not substantially different from the components described in the above embodiments will be assigned the same reference numerals, and duplicated description will be omitted.

[0025] The current compensation circuit 200 further includes a voltage reduction circuit 30 that reduces the potential of the base of the transistor Q1 compared to the current compensation circuit 100. The voltage reduction circuit 30 has a first terminal 38 connected to the gate of the NMOS transistor 14 and a second terminal 39 connected to the base B of the transistor Q1 and the drain of the NMOS transistor 14.

[0026] FIG. 3 is a circuit diagram showing an example of the configuration of a voltage reduction circuit 30, which is an example of a voltage reduction circuit in a current compensation circuit and a semiconductor device according to the second embodiment. The voltage reduction circuit 30 includes a depletion-type NMOS transistor (hereinafter referred to as "DNMOS transistor") 31 and a current adjustment circuit 32. The DNMOS transistor 31 includes a drain connected to the VDD terminal 1, a gate connected to a second terminal 39 of the voltage reduction circuit 30, and a source connected to a first terminal 38 of the voltage reduction circuit 30. Here, the connection point between the source of the DNMOS transistor 31 and the first terminal 38 of the voltage reduction circuit 30 is referred to as connection point P2.

[0027] The current adjustment circuit 32 includes a first terminal 32a connected to the connection point between the source of the DNMOS transistor 31 and the first terminal 38 of the voltage reduction circuit 30, i.e., connection point P2, and a second terminal 32b connected to the GND terminal 2, and is configured as a variable current source that can adjust the current value of the current flowing through connection point P2.

[0028] 4 and 5 are circuit diagrams showing a first configuration example and a second configuration example of the current adjustment circuit 32, respectively.

[0029] The current adjustment circuit 32 of the first configuration example (FIG. 4) has a DNMOS transistor 321 whose gate and source are connected to the GND terminal 2, and a current mirror circuit 320 including a first terminal connected to the drain of the DNMOS transistor 321 and a second terminal connected to a connection point P2. The DNMOS transistor 321 as the second depletion type transistor is configured to have the same process variation as the DNMOS transistor 31 as the first depletion type transistor.

[0030] The current mirror circuit 320 has a PMOS transistor 322 and a PMOS transistor 323 that form a first current mirror circuit, and an NMOS transistor 324 and an NMOS transistor 325 that form a second current mirror circuit. The first current mirror circuit and the second current mirror circuit are connected by connecting the drain of the PMOS transistor 323 and the drain of the NMOS transistor 324.

[0031] The current mirror circuit 320 is configured to be able to adjust the overall mirror ratio k (k is a positive number) by including at least one transistor, such as a PMOS transistor 323, among the PMOS transistor 322, the PMOS transistor 323, the NMOS transistor 324, and the NMOS transistor 325 that constitute the current mirror circuit 320, whose drain current is adjustable.

[0032] In the first current mirror circuit, the PMOS transistor 322 includes a drain connected to the drain of the DNMOS transistor 321, a gate connected to the drain of the PMOS transistor 322, and a source connected to the VDD terminal 1. The PMOS transistor 323 includes a source connected to the VDD terminal 1, a gate connected to the drain and gate of the DNMOS transistor 322, and a drain.

[0033] In the second current mirror circuit, the NMOS transistor 324 includes a drain connected to the drain of the PMOS transistor 323, a gate connected to the drain of the NMOS transistor 324, and a source connected to the GND terminal 2. The NMOS transistor 325 includes a drain connected to the connection point P2, a gate connected to the drain and gate of the NMOS transistor 324, and a source connected to the GND terminal 2.

[0034] Here, in the current mirror circuit 320, a connection point P3 between the gate and drain of the PMOS transistor 322 and the drain of the DNMOS transistor 321 corresponds to a first terminal of the current mirror circuit 320. The drain of the NMOS transistor 325, i.e., connection point P2, corresponds to a second terminal of the current mirror circuit 320. In the current adjustment circuit 32 of the first configuration example (FIG. 4), the node identical to the drain of the NMOS transistor 325 connected to connection point P2 corresponds to the first terminal 32a, and the node identical to connection point P4, which is the connection point between the gate and source of the DNMOS transistor 321, corresponds to the second terminal 32b.

[0035] The current adjustment circuit 32 of the second configuration example (FIG. 5) is configured with a DNMOS transistor 326 whose gate and source are connected and whose drain current is adjustable. In the current adjustment circuit 32 of the second configuration example (FIG. 5), the node identical to the drain of the DNMOS transistor 326 connected to connection point P2 corresponds to the first end 32a, and the node identical to connection point P4, which is the connection point between the gate and source of the DNMOS transistor 326, corresponds to the second end 32b.

[0036] Next, the operations of the current compensation circuit 200 and the semiconductor device 20 will be described with reference to FIGS.

[0037] The current compensation circuit 200 and semiconductor device 20 configured as described above generate a compensation current that compensates for the base current shunted from the base B of transistor Q2, based on the base current shunted from the base B of transistor Q1, similar to the current compensation circuit 100 and semiconductor device 10. However, in the current compensation circuit 200, by adjusting the current value of the current adjustment circuit 32, it is possible to adjust the gate-source voltage Vgs31 of the DNMOS transistor 31 to zero or less (Vgs31≦0) while operating the NMOS transistors 14 and 15 as a current mirror circuit.

[0038] Therefore, the current value of the current adjustment circuit 32 is adjusted so that the gate-source voltage Vgs31 of the DNMOS transistor 31 becomes negative (Vgs31<0). The current value of the current adjustment circuit 32 is adjusted, for example, by generating a reference current using the DNMOS transistor 321 operating as a constant current source, multiplying the generated reference current by a constant (1 / k times in the example of FIG. 4) via the current mirror circuit 320, and outputting the resultant current to the drain of the NMOS transistor 325, i.e., the connection point P2.

[0039] By adjusting the current value of the current adjustment circuit 32, the voltage reduction circuit 30 supplies a voltage to the second terminal 39, which is the same node as the gate of the DNMOS transistor 31, that is lower than the voltage of the first terminal 38, which is the same node as the source of the DNMOS transistor 31. Note that when k is other than 1 (k≠1), that is, when the current value of the drain current of the PMOS transistor 322 is different from the current value of the drain current of the PMOS transistor 323, the DNMOS transistor 31 has slight process dependency and temperature dependency, but as long as the slight process dependency and temperature dependency of the DNMOS transistor 31 are within a range that is allowable in design, the influence of this can be ignored.

[0040] According to the current compensation circuit 200 and the semiconductor device 20, similarly to the current compensation circuit 100 and the semiconductor device 10, the h FE Even if there are process variations in h FE Therefore, the collector current Ic can be kept constant regardless of the magnitude of h FE Without causing variations in the base-emitter diode voltage Vbe due to FE This cancels out the variations in the base-emitter diode voltage Vbe caused by the

[0041] Furthermore, according to the current compensation circuit 200 and the semiconductor device 20, the gate-source voltage Vgs31 of the DNMOS transistor 31 is adjusted to be negative, thereby making it possible to lower the base potential of the transistor Q1 in the current compensation circuit 200 and the semiconductor device 20 compared to before the adjustment. That is, according to the current compensation circuit 200 and the semiconductor device 20, it is possible to lower the operating point of the transistor Q1 compared to the operating point of the transistor Q1 in the current compensation circuit 100 and the semiconductor device 10 that do not include the voltage reduction circuit 30.

[0042] If the operating point of the transistor Q1 can be lowered, the voltage of the terminal connected to the source of the PMOS transistor 11, i.e., the voltage of the VDD terminal 1, can be lowered. Therefore, the current compensation circuit 200 and the semiconductor device 20 can be operated at a lower power supply voltage than the conventional circuit or the current compensation circuit 100 and the semiconductor device 10 that do not include the voltage reduction circuit 30. In many cases, this benefit outweighs the disadvantage of the DNMOS transistor 31 having slight process dependency and temperature dependency, and is beneficial overall.

[0043] The present invention is not limited to the above-described embodiments, and various other embodiments may be implemented in the implementation stage, and various omissions, additions, substitutions, or modifications may be made without departing from the spirit of the invention. For example, switch 17 may be omitted when it is not necessary to separate the drain current of NMOS transistor 15 from the drain current of PMOS transistor 13, for example, because trimming of the current value of constant current source 16 has been completed or the collector current Ic is sufficiently accurate so that trimming is not necessary.

[0044] Furthermore, an example of a configuration in which the current value of the current flowing through the connection point P2 can be adjusted is not limited to the voltage reduction circuit 30 having the current adjustment circuit 32 in which the current value of the current flowing through the connection point P2 can be adjusted. Another configuration in which the current value of the current flowing through the connection point P2 can be adjusted, for example, a voltage reduction circuit 30A (see FIG. 6) in which the DNMOS transistor 31 included in the voltage reduction circuit 30 is replaced with a DNMOS transistor 33 configured as a transistor in which the drain current can be adjusted to adjust the current flowing through the connection point P2.

[0045] FIG. 6 is a circuit diagram showing an example of the configuration of a voltage reduction circuit 30A, which is another example of a voltage reduction circuit in a current compensation circuit and a semiconductor device according to the second embodiment.

[0046] The voltage reduction circuit 30A illustrated in FIG. 6 is configured such that, in place of the DNMOS transistor 31 in the voltage reduction circuit 30, a DNMOS transistor 33 capable of adjusting the current flowing through the connection point P2 is provided, and in place of the current adjustment circuit 32, a constant current source 34 is provided.

[0047] The voltage reduction circuit described above only needs to be configured to be able to adjust the current flowing through the connection point P2, and may be configured to include the DNMOS transistor 33 and the current adjustment circuit 32. In a voltage reduction circuit having the DNMOS transistor 33 and the current adjustment circuit 32, if one of the DNMOS transistor 33 and the current adjustment circuit 32 is configured to be able to adjust the current in the increasing direction and the other in the decreasing direction, it becomes possible to easily adjust the increase or decrease of the current flowing through the connection point P2.

[0048] Furthermore, if one of the DNMOS transistor 33 and the current adjustment circuit 32 is configured to be able to adjust the current value more finely than the other, one can be used for fine adjustment and the other for coarse adjustment. When one of the DNMOS transistor 33 and the current adjustment circuit 32 is configured to be able to be finely adjusted and the other to be able to be coarsely adjusted, the range of size ratio required for the elements to add the current value adjustment function can be reduced, and as a result, the increase in the area of ​​the current compensation circuit 200 and the semiconductor device 20 can be minimized.

[0049] These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0050] 10,20 Semiconductor device 100,200 current compensation circuit Q1 Bipolar transistor (second bipolar transistor) Q2 Bipolar transistor (first bipolar transistor) 11 PMOS transistor (first transistor) 12 PMOS transistor (second transistor) 13 PMOS transistor (third transistor) 14 NMOS transistor (fourth transistor) 15 NMOS transistor (fifth transistor) 16 constant current source 17 Switch 30,30A low voltage circuit 31, 33 Depletion-type NMOS transistor (first depletion-type transistor) 32 Variable current source (current adjustment circuit) 34 Constant current source 320 Current mirror circuit 321 Depletion-type NMOS transistor (second depletion-type transistor)

Claims

1. A circuit for supplying a current to an emitter of a first bipolar transistor including a collector connected to a first power supply terminal, a base connected to the first power supply terminal, and an emitter, the circuit comprising: a second bipolar transistor including a collector connected to the first power supply terminal, a base, and an emitter, the second bipolar transistor having the same process variation as the first bipolar transistor; a first transistor including a drain connected to the emitter of the second bipolar transistor, a gate, and a source connected to a second power supply terminal; a second transistor including a gate connected to the gate of the first transistor, a drain connected to its own gate, and a source connected to the second power supply terminal; a third transistor including a drain connected to the emitter of the first bipolar transistor, a gate connected to a connection point of the drain of the second transistor, the gate of the second transistor, and the gate of the first transistor, and a source connected to the second power supply terminal; a constant current source including a first end connected to the connection point and a second end connected to the first power supply terminal; a fourth transistor having a drain connected to the base of the second bipolar transistor, a source connected to the first power supply terminal, and a gate connected to its drain; a fifth transistor including a drain connected to the first end of the constant current source, a gate connected to the gate of the fourth transistor, and a source connected to the first power supply terminal; A current compensation circuit comprising:

2. 2. The current compensation circuit according to claim 1, further comprising a voltage reduction circuit having a first terminal connected to the gate of the fourth transistor and a second terminal connected to the drain of the fourth transistor, the voltage of the second terminal being adjusted to be equal to or lower than the voltage of the gate of the fourth transistor.

3. The voltage reduction circuit includes: a first depletion type transistor including a drain connected to the second power supply terminal, a gate connected to a second end of the first depletion type transistor, and a source connected to a first end of the voltage reduction circuit and a back gate of the first depletion type transistor; a current adjusting circuit including a first terminal connected to a second connection point that connects the back gate and source of the first depletion type transistor and a first terminal of the voltage reduction circuit, and a second terminal connected to the first power supply terminal, the current adjusting circuit being configured to be able to adjust a value of a current flowing through the second connection point; 3. The current compensation circuit of claim 2, comprising:

4. The voltage reduction circuit includes: a first depletion type transistor having a drain connected to the second power supply terminal, a gate connected to a second end of the first depletion type transistor, and a source connected to the first end of the voltage reduction circuit and a back gate of the first depletion type transistor, the first depletion type transistor having an adjustable drain current; a current adjusting circuit including a first terminal connected to a second connection point that connects the back gate and source of the first depletion type transistor and a first terminal of the voltage reduction circuit, and a second terminal connected to the first power supply terminal, and configured to be able to adjust the current value of the current flowing through the second connection point; 3. The current compensation circuit of claim 2, comprising:

5. The voltage reduction circuit includes: a first depletion type transistor having a drain connected to the second power supply terminal, a gate connected to a second end of the first depletion type transistor, and a source connected to the first end of the voltage reduction circuit and a back gate of the first depletion type transistor, the first depletion type transistor having an adjustable drain current; a constant current source that supplies a constant current, the constant current source including a first terminal connected to a second connection point that connects the back gate and source of the first depletion type transistor and a first terminal of the voltage reduction circuit, and a second terminal connected to the first power supply terminal; 3. The current compensation circuit of claim 2, comprising:

6. 6. The current compensation circuit according to claim 1, further comprising a switch that opens and closes the first terminal of the constant current source and the drain of the fifth transistor.

7. A semiconductor device including an integrated circuit formed on a semiconductor substrate, A current compensation circuit according to any one of claims 1 to 5 or claim 6 which cites claim 1; the first bipolar transistor; A semiconductor device comprising:

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