Semiconductor apparatus, photoelectric conversion system, and method of manufacturing semiconductor apparatus

Abstract

To provide a semiconductor device in which the degradation of a function of a semiconductor layer included in a chip due to the intrusion of moisture or the like can be reduced.SOLUTION: A semiconductor apparatus includes a first substrate including a first wiring structure and a first semiconductor layer, a second substrate including a second wiring structure and a second semiconductor layer, and a pad to be connected to an external terminal. A first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are bonded together to electrically connect the first semiconductor layer and the second semiconductor layer to each other. In a plan view seen from a side of the first semiconductor layer, the second semiconductor layer is larger than the first semiconductor layer. In the plan view, the pad is located outside of the first semiconductor layer. A first protection film is arranged to extend to at least a part of a side surface of the first semiconductor layer and at least a part of a side surface of the first wiring structure, the first protection film including nitrogen.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a photoelectric conversion system, and a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, semiconductor devices have become known in which semiconductor layers of different sizes, each having a semiconductor element formed thereon, are stacked together. Patent Document 1 proposes a chip-on-wafer (CoW) technology in which a chip including a semiconductor layer and a wiring structure is bonded to a wafer including a semiconductor layer and a wiring structure using Cu-Cu bonding of metal patterns included in each wiring structure. In the Cu-Cu bonding, a metal pattern included in the wiring layer of the chip is directly bonded to a metal pattern included in the wiring layer of the wafer. Patent Document 1 also discloses that after bonding the chip and wafer, they are attached to a support substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-89275 A Summary of the Invention [Problem to be solved by the invention]

[0004] The technology disclosed in Patent Document 1 may allow moisture and other substances to penetrate into the semiconductor layer contained in the chip, resulting in a deterioration in the functionality of the semiconductor device. Furthermore, the technology disclosed in Patent Document 1 may cause defects in bonding to the substrate.

[0005] The semiconductor device of the present invention aims to reduce the deterioration of the function of the semiconductor layer included in the chip due to the penetration of moisture, etc. Also, the method for manufacturing the semiconductor device of the present invention aims to reduce defects in bonding to the substrate. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention comprises a first substrate including a first wiring structure and a first semiconductor layer, a second substrate including a second wiring structure and a second semiconductor layer, and a pad connected to an external terminal, wherein a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, the second semiconductor layer is larger than the first semiconductor layer in a planar view seen from the first semiconductor layer side, the pad is arranged outside the first semiconductor layer in a planar view, a first protective film is arranged extending over at least a portion of a side surface of the first semiconductor layer and at least a portion of a side surface of the first wiring structure, and the first protective film contains nitrogen.

[0007] A semiconductor device according to one embodiment of the present invention comprises a first substrate including a first wiring structure and a first semiconductor layer having a photoelectric conversion element, and a second substrate including a second wiring structure and a second semiconductor layer, wherein a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, and in a planar view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, and a first protective film is arranged extending over at least a portion of a side surface of the first semiconductor layer and at least a portion of a side surface of the first wiring structure, and the first protective film contains nitrogen.

[0008] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes the steps of: preparing a bonded body in which a first substrate including a first wiring structure and a first semiconductor layer having a photoelectric conversion element, and a second substrate including a second wiring structure and a second semiconductor layer are stacked; forming a protective film on an upper surface and a side surface of the bonded body, the protective film being a first protective film containing nitrogen and a second protective film arranged in that order; and removing a portion of the protective film so as to expose at least a portion of the first protective film, wherein in the step of preparing the bonded body, a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are bonded to each other so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, and the second semiconductor layer is larger than the first semiconductor layer in a plan view viewed from the first semiconductor layer side. [Effects of the Invention]

[0009] According to the present invention, it is possible to reduce the deterioration of the function of the semiconductor device due to the penetration of moisture etc. Also, according to the manufacturing method of the present invention, it is possible to reduce defects in bonding with the substrate. [Brief explanation of the drawings]

[0010] [Figure 1] 1A and 1B are a schematic plan view and a schematic cross-sectional view of a semiconductor device according to a first embodiment; [Figure 2] 1 is a schematic cross-sectional view of a bonding portion of a semiconductor device according to a first embodiment; [Figure 3] 1 is a schematic cross-sectional view of a bonding portion of a semiconductor device according to a first embodiment; [Figure 4] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 5] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 8] 1A and 1B are a schematic plan view and a schematic cross-sectional view of a semiconductor device according to a second embodiment; [Figure 9]10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a third embodiment. [Figure 12] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a third embodiment. [Figure 13] 10A and 10B are a schematic plan view and a schematic cross-sectional view of a semiconductor device according to a fourth embodiment; [Figure 14] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 15] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 16] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 17] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 18] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 19] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 20] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 21] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 22] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 23] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a sixth embodiment. [Figure 24] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to a sixth embodiment. [Figure 25] FIG. 13 is a diagram showing the configuration of a photoelectric conversion system according to a seventh embodiment. [Figure 26] 13A and 13B are diagrams showing the configuration and operation of a moving body according to an eighth embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0012] In the following embodiments, a photoelectric conversion device will be mainly described as an example of a semiconductor device. However, in each embodiment, the semiconductor device can be used for a light emitting device or the like in addition to a photoelectric conversion device. Furthermore, in the following, an imaging device will be described as an example of a photoelectric conversion device, but the photoelectric conversion device is not limited to this. For example, the semiconductor device can also be applied to photoelectric conversion devices such as a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) and a photometric device (a device for measuring the amount of incident light).

[0013] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0014] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals.

[0015] In the following, a wafer refers to a substrate on which multiple semiconductor elements are formed by a semiconductor process before dicing, and a chip refers to an individual semiconductor element after dicing the wafer. For example, multiple imaging elements and multiple circuit units may be formed on the wafer.

[0016] (First embodiment) A semiconductor device 100 (photoelectric conversion device) according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.

[0017] The schematic configuration of the semiconductor device 100 will be described with reference to FIG. 1. FIG. 1(a) is a schematic plan view of the semiconductor device 100, and FIG. 1(b) is a schematic cross-sectional view of plane AB of FIG. 1(a). In this specification, a plane refers to a plane viewed from the semiconductor layer 201 side (first semiconductor layer side) in a stacked structure of a semiconductor layer 201 (first semiconductor layer) and a semiconductor layer 301 (second semiconductor layer), which will be described later. A cross section refers to a plane viewed from a direction perpendicular to the stacking direction of the semiconductor layer 201 and the semiconductor layer 301, that is, a plane passing through the semiconductor layer 201 and the semiconductor layer 301. A planar view refers to a view taken from the above-mentioned plane, and a cross-sectional view refers to a view taken from a cross section passing through the semiconductor layer 201 and the semiconductor layer 301. For example, a planar view refers to a view taken from a direction perpendicular to a plane on which a plurality of pixels are arranged in a two-dimensional array.

[0018] As shown in FIG. 1, the semiconductor device 100 includes a substrate 200 (first substrate) having a semiconductor layer 201 and an interconnect structure 260 (first interconnect structure), and a substrate 300 (second substrate) having a semiconductor layer 301 and an interconnect structure 360 ​​(second interconnect structure). The interconnect structure 260 includes multiple interconnect layers 203 and interconnect interlayer films 202 disposed between the interconnect layers. Each interconnect layer has multiple metal patterns, and the interconnect interlayer films 202 are also disposed between the metal patterns. In addition, the metal pattern of one interconnect layer may be electrically connected to the metal pattern of an adjacent interconnect layer via a via plug. Similarly, the interconnect structure 360 ​​includes multiple interconnect layers 303 and interconnect interlayer films 302 disposed between the interconnect layers. Each interconnect layer has multiple metal patterns, and the interconnect interlayer films 302 are also disposed between the metal patterns.

[0019] The semiconductor layer 201 includes a first semiconductor element, and the semiconductor layer 301 includes a second semiconductor element. In the following, an example will be described in which the substrate 200 constitutes an imaging element and the substrate 300 constitutes a circuit section. In the following example, in the substrate 200, the semiconductor layer 201 includes a photodiode, which is a photoelectric conversion element, as the first semiconductor element. In addition, in the substrate 300, the semiconductor layer includes a signal processing circuit, which processes a signal from the photoelectric conversion element, as the second semiconductor element. Note that the first semiconductor element does not have to be a photoelectric conversion element, and may be an element such as a transistor, or a light-emitting element. When the first semiconductor element is a light-emitting element, the second semiconductor element may be, for example, a circuit that controls the light emission of the light-emitting element.

[0020] The semiconductor layer 201 has a plurality of pixels arranged therein, each pixel including a photoelectric conversion element, a transfer transistor, an amplification transistor, and a reset transistor. A configuration including at least one photoelectric conversion element is referred to as a pixel. In the following, a case where one pixel includes a photoelectric conversion element, a transfer transistor, an amplification transistor, and a reset transistor is described. The source of the transfer transistor is connected to the photoelectric conversion element, and the drain of the transfer transistor is connected to the gate electrode of the amplification transistor. The node that is the same as the gate electrode of the amplification transistor is referred to as a floating diffusion (FD). The reset transistor is connected to the FD, and sets the potential of the FD to an arbitrary potential (for example, a reset potential). Here, the amplification transistor is part of a source follower circuit, and outputs a signal corresponding to the potential of the FD to a signal line.

[0021] The arrangement of the amplifying transistor and the reset transistor is not limited to this. For example, the amplifying transistor and the reset transistor may be arranged in the semiconductor layer 301. This allows the area of ​​the photoelectric conversion element to be increased compared to when all components of the pixel are arranged in the semiconductor layer 201, thereby improving sensitivity. Furthermore, even if the area of ​​the photoelectric conversion element is not increased, it is possible to provide a large number of photoelectric conversion elements, thereby enabling a large number of pixels.

[0022] The semiconductor layer 301 is provided with peripheral circuits including a readout circuit and a control circuit. The peripheral circuits include a vertical scanning circuit, which is a control circuit for supplying control signals to the gate electrodes of the pixel transistors. The peripheral circuits also include a readout circuit that holds signals output from the pixels and performs signal processing such as amplification, addition, and AD conversion. The peripheral circuits also include a horizontal scanning circuit, which is a control circuit that controls the timing of sequentially outputting signals from the readout circuit.

[0023] The first semiconductor element may be an avalanche photodiode, in which case the semiconductor layer 201 does not need to include a transistor.

[0024] The semiconductor device 100 is constructed by bonding a substrate 200 and a substrate 300 together. The wiring layer located on the surface of the substrate 200 of the wiring structure 260 facing the second substrate has a metal pattern 204 (first metal pattern). Furthermore, the wiring layer located on the surface of the substrate 300 of the wiring structure 360 ​​facing the substrate 200 has a metal pattern 304 (second metal pattern). The substrates 200 and 300 are electrically connected by bonding the metal patterns included in each substrate. For example, the metal pattern 204 and the metal pattern 304 can each be made of a material mainly composed of Cu, and electrically connected by Cu-Cu bonding.

[0025] The substrate 300 has a guard structure 305 on the outer side of the substrate 200 in a planar view. Specifically, the substrate 300 has the guard structure 305 on the outer side of the edge (end) of the substrate 200 in a planar view. The guard structure 305 is provided to prevent the second semiconductor element of the substrate 300 from being affected by dicing when the semiconductor device 100 is diced into individual pieces. The guard structure 305 is preferably connected to the semiconductor layer 301, and a metal layer is preferably formed continuously up to the surface of the substrate 300 (the surface that will be bonded to the substrate 200). For example, as shown in FIG. 1(b), the guard structure 305 is preferably formed by continuously connecting metal with a plurality of contact plugs, metal patterns, and via plugs arranged from the surface of the semiconductor layer 301 to the upper surface of the substrate 300. This makes it less susceptible to the effects of dicing.

[0026] Guard structure 305 has a metal pattern (third metal pattern) 317 that forms part of the bonding surface of substrate 300. Metal pattern 317 is disposed at the same height as metal pattern 304. Metal pattern 317 is located outside semiconductor layer 201 in plan view. By forming at least a part of guard structure 305 outside substrate 200 in plan view, it is possible to expand the area of ​​substrate 300 that can be effectively used.

[0027] In this embodiment, in a plan view, a contact portion between the metal pattern 317 and the protective film (first protective film) 401 that contacts the metal pattern 317 is located outside the semiconductor layer 201. In other words, in a plan view, the contact portion is located outside the edge (end portion) of the semiconductor layer 201. By the protective film 401 contacting the metal pattern 317, it is possible to suppress the metal elements of the metal pattern 317 from diffusing into the semiconductor layer 201 via the protective film (second protective film) 402.

[0028] The metal pattern 317 is electrically connected to the semiconductor layer 301. For example, a fixed potential can be supplied to the metal pattern 317. This can prevent problems that may occur when the metal pattern 317 becomes floating.

[0029] The guard structure 305 may be, for example, ring-shaped in plan view. If metal elements contained in the metal pattern 317 of the guard structure 305 diffuse into the semiconductor layer 201, the characteristics of the substrate 200 may deteriorate. In other words, the protective performance for the semiconductor device may be reduced. Therefore, in this embodiment, to prevent the diffusion of metal elements, a protective film 401 containing nitrogen is provided so as to be in contact with the metal pattern 317 of the guard structure 305. It is desirable that the protective film 401 is disposed so as to cover the top of the guard structure 305 in cross-sectional view. For example, as shown in FIG. 1( a), the guard structure may be disposed in a ring-shaped manner in plan view. Furthermore, a guard structure may also be disposed in the wiring structure 260 of the substrate 200.

[0030] When the protective film 401 covers the side surface of the wiring structure 260, it is not essential that the protective film 401 contacts the metal pattern 317. In this case, the diffusion prevention film disposed near the metal pattern 204 or the like can suppress the diffusion of metal elements into the semiconductor layer 201 via the wiring structure 360.

[0031] The guard structure 305 does not have to be made entirely of metal, but may be made of an insulating material different from the wiring interlayer film 302, instead of a metal via plug, between metal patterns, as long as it is resistant to the effects of dicing.

[0032] The protective film 401 is disposed so as to extend over at least a part of the side surface of the semiconductor layer 201 and at least a part of the side surface of the wiring structure 260. As shown in FIG. 1(b), the protective film 401 is preferably disposed over the entire side surface of the semiconductor layer 201 and the entire surface of the wiring structure 260. This can improve moisture resistance.

[0033] As shown in Fig. 1(a), a plurality of pads 600 are arranged inside the guard structure 305. The pads 600 have the function of outputting signals (image signals) based on charges generated in the photoelectric conversion elements to the substrates 200 and 300, and the function of inputting voltages for driving peripheral circuits supplied from the outside. Fig. 1(a) shows an example in which the pads are arranged on the substrate 300, but the pads 600 may also be arranged on the substrate 200.

[0034] On the surface of the substrate 200 of the semiconductor device 100 opposite to the circuit board that will become the substrate 300, optical structures such as a color filter 404 and a microlens 405 may be arranged.

[0035] As described above, the semiconductor device according to this embodiment is a back-illuminated stacked sensor using Chip On Wafer (CoW) technology.

[0036] 2(a), 2(b), 3(a), and 3(b) are examples showing enlarged views of metal patterns 204, 304, and 317 on the bonding surfaces of substrates 200 and 300. Any of these examples may be used in this embodiment.

[0037] As shown in FIGS. 2 and 3, the metal patterns 204, 304, and 317 may each include a conductor 204a, 304a, or 317a and a conductive film 204b, 304b, or 317b made of a material different from the conductor. The conductors 204a, 304a, and 317a may be made of different materials, but preferably the same material. The conductive films 204b, 304b, and 317b function as a film that prevents the diffusion of metal elements from the conductor. The conductive films 204b, 304b, and 317b may be made of different materials, but preferably the same material. The side surfaces of the conductor and the surface opposite to the surface that contacts another conductor are preferably covered with a conductive film. This ensures that the conductor remains covered with the conductive film even after bonding, thereby suppressing the generation of dark current and leakage current. For example, Cu can be used as the conductor.

[0038] In the following description, the conductors 204a, 304a, and 317a are made of the same material, and the conductive films 204b, 304b, and 317b are made of the same material. In the following description, a single damascene structure interconnect is formed by a single damascene method, in which a groove that becomes the interconnect is formed in an interconnect interlayer film and then filled with a conductive film or a conductor such as copper that functions as a barrier metal, and has the interconnect embedded in the interconnect interlayer film. A dual damascene structure interconnect is formed so that the interconnect and via are integrated, and has the interconnect and via embedded in the interconnect interlayer film. It is formed by a dual damascene method, in which a groove that becomes the interconnect and via is formed in an interconnect interlayer film and then filled with a conductive film or a conductor such as copper that functions as a barrier metal, and has the interconnect embedded in the interconnect interlayer film.

[0039] In FIG. 2(a), the conductor 204a of the metal pattern 204 and the conductor 304a of the metal pattern 304 are in contact with each other. A conductive film 204b is arranged in contact with the conductor 204a so as to cover the conductor 204a except for the contact surface with the conductor 304a. The conductive film 204b is arranged in contact with the metal pattern 206 of the adjacent wiring layer. The metal pattern 206 has a conductor 206a and a conductive film 206b. The conductor 206a is mainly composed of, for example, Cu, and the conductive film 206b is mainly composed of, for example, a material that prevents the diffusion of Cu. The conductive film 206b may also be arranged on the side opposite the metal pattern 204. The conductive film 204b penetrates a portion of the conductive film 206b and is in contact with the conductor 206a.

[0040] The conductor 317a of the metal pattern 317 is in contact with the protective film 401. This makes it possible to prevent the conductor 317a from diffusing.

[0041] As shown in FIG. 2(b), the metal patterns 204 and 304 may be misaligned at the bonding surface. In this case, the conductor 203a comes into contact with both the conductor 304a and the conductive film 304b. Furthermore, if the metal patterns 204 and 304 are misaligned at the time of bonding, the metal elements of the conductors of each metal pattern may diffuse into the inter-wiring layer film. Therefore, diffusion barrier films 410a and 410b are provided to prevent metal diffusion between the metal patterns 204 and 304. As described below, the diffusion barrier films 410a and 410b are provided before bonding the substrates 200 and 300, and can prevent the diffusion of metal elements of the metal patterns 204 and 304. On the other hand, since the chip-shaped substrate 200 is bonded to the wafer-shaped substrate 300, it is difficult to leave only the diffusion barrier film for the metal pattern 317. Therefore, the diffusion barrier film 410a and the protective film 401 may be provided in different processes.

[0042] The diffusion prevention film 410a and the protective film 401 may be made of different materials or the same material. For example, the diffusion prevention film 410a may be made of silicon nitride or the like. As shown in Figures 2(a) and 2(b), the protective film 401 is preferably thicker than the diffusion prevention film 410a. However, the protective film 401 and the diffusion prevention film 410a may have the same thickness.

[0043] The thickness of the protective film 401 is preferably, for example, in the range of 50 nm to 500 nm, and more preferably in the range of 100 nm to 300 nm. The thickness of the protective film 401 is preferably, for example, in the range of 1 / 4 to 1 / 2 times the thickness of the metal pattern 317. In FIG. 3(a), the shapes of the metal patterns 204, 304, and 317 are different from those in FIG. 2(b). The metal pattern 206 may be composed of a conductor and a conductive film.

[0044] An insulating film may be interposed between the protective film 401 and the semiconductor layer 201. From the viewpoint of protective function, it is preferable that the thickness of the insulating film between the protective film 401 and the semiconductor layer 201 is, for example, 300 nm or less. In other words, it is preferable that the shortest distance between the side surface of the semiconductor layer 201 and the protective film 401 is 300 nm or less. The insulating film may contain, for example, silicon oxide (SiO). This makes it possible to relieve stress between the protective film 401 containing SiN and the semiconductor layer 201 containing Si.

[0045] 3(b), the diffusion prevention films 410a and 410b may be disposed at positions away from the bonding surface, which still prevents diffusion of metal elements from the metal patterns 204 and 304 into the adjacent wiring layers.

[0046] Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 4 to 7. Figures 4 to 7 are cross-sectional views showing the steps in the method for manufacturing a semiconductor device according to this embodiment.

[0047] In FIG. 4 , a bonded assembly is prepared by stacking and bonding a substrate 200 including a chip-shaped imaging element on a wafer-like substrate 300 including multiple circuit units. Metal patterns 304 and 204, primarily made of, for example, Cu, are arranged on the substrates 300 and 200, respectively, and the bonding can be achieved by Cu-Cu metal bonding and covalent bonding between the wiring interlayer film 202 and the wiring interlayer film 302. In this case, a diffusion barrier film containing, for example, silicon nitride (SiN) can be formed on a portion of the wiring interlayer film 202 and the wiring interlayer film 302 to suppress diffusion of metal elements contained in the metal patterns 304 and 204 of the wiring layer. In this case, the guard structure 305 exposes the wiring layer on the same layer as the wiring layer on which the metal pattern 304 is arranged. Furthermore, a metal layer that forms a pad 600 is formed on the wiring structure 360. In this embodiment, the pad 600 is formed in the wiring structure 360, but the pad 600 may also be formed in the wiring structure 260 on the chip-shaped substrate 200 side. When the pad 600 is formed outside the substrate 200 in a plan view, an opening can be formed so that the pad 600 is exposed without penetrating the semiconductor layer 201.

[0048] Next, as shown in Figure 5, for example, a silicon nitride film is deposited and a nitrogen-containing protective film 401 is formed using photolithography and etching techniques. The protective film 401 is formed on the top and side surfaces of the bonded body. The first protective film preferably contains silicon nitride (SiN) or silicon oxynitride (SiON). This makes it easier to ensure the reliability of the semiconductor device.

[0049] When forming the protective film 401, a film similar to the protective film may remain on the side surface of the substrate 200, in which case it is possible to improve the moisture resistance of the substrate 200. Furthermore, by removing the protective film 401 from the surface of the semiconductor device 100 that will be diced, it is possible to avoid problems such as film peeling during dicing.

[0050] 6, for example, silicon oxide is deposited and planarized to form a protective film 402. The thickness of the substrate 200 is, for example, 10 μm to 30 μm, and the thickness of the deposited protective film 402 needs to be greater than the height of the substrate 200. For example, the thickness of the protective film 402 is preferably 10 times or more the thickness of the protective film 401. The protective film 402 preferably contains silicon oxide (SiO).

[0051] Next, a portion of the protective film 402 is removed so as to expose at least a portion of the protective film 401. In the step of removing a portion of the protective film 402, it is preferable to flatten the protective film 402 by a CMP method, which can reduce defects in bonding with the substrate in the subsequent step.

[0052] By disposing the nitrogen-containing protective film 401 between the protective film 402 and the semiconductor layer 201, it is possible to improve the flatness within the wafer surface due to differences in polishing rate depending on the material by performing the CMP method until the protective film 401 is exposed.

[0053] In this embodiment, CMP is performed until the protective film 401 is exposed, and then a step of removing the protective film 401 by, for example, etching is performed. Next, the semiconductor layer 201 is thinned by wet etching. At this time, it is preferable to previously add impurities to the semiconductor layer 201 to provide a first region doped with the impurity and a second region not doped with the impurity. This makes it possible to control the etching rate of the semiconductor layer 201 between the first and second regions, thereby enabling processing to a specific thickness. To prevent lateral etching during wet etching of the semiconductor layer 201, it is preferable that an insulating film including the protective film 401 protects the sidewalls of the semiconductor layer 201. At this time, it is preferable that the insulating film including the protective film 401 remains at a position higher than the height of the semiconductor layer 201 after wet etching. Thereafter, a portion of the protective film 401 is removed by etching so that the upper end of the protective film 401 is lower than the upper end of the semiconductor layer 201. Subsequently, CMP is performed to thin the semiconductor layer 201 to a thickness of, for example, 1 μm to 5 μm. At this time, a part of the protective film 401 and a part of the protective film 402 are simultaneously removed. As shown in Fig. 7, the protective film 401 is disposed so as to cover the side surface of the substrate 200 and the upper surface of the substrate 300. If the protective film 401 is higher than the semiconductor layer 201 when performing CMP, the narrow protective film 401 may bend during polishing, causing physical scratches on the semiconductor layer 201. Therefore, it is desirable to etch the protective film 401 before CMP.

[0054] Next, as shown in FIG. 7, optical structures such as color filters 404 and microlenses 405 are formed on the semiconductor layer 201, and openings are formed so that the pads 600 are exposed. The semiconductor device shown in FIG. 1 is obtained by dicing the semiconductor device into individual pieces.

[0055] A bonding layer 403 may be formed between the step of thinning the semiconductor layer 201 and the step of forming the optical structure. The bonding layer 403 may contain, for example, silicon oxide or silicon oxynitride. This allows the optical structure and the semiconductor layer 201 to be bonded together. Note that an oxide film or a metal wiring layer with a light-shielding function may be disposed between the bonding layer 403 and the semiconductor layer 201, and a part of the bonding layer 403 may have an intralayer lens shape.

[0056] According to the semiconductor device of this embodiment, the protective film 401 extends from at least a part of the side surface of the semiconductor layer 201 to at least a part of the side surface of the wiring structure 260, which makes it easier to reduce the penetration of moisture and the like into the semiconductor layer 201 and ensure the reliability of the semiconductor device. Furthermore, according to the manufacturing method of the semiconductor device of this embodiment, it is possible to reduce defects in bonding with the substrate.

[0057] (Second embodiment) A semiconductor device according to a second embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 8 to 10. FIGS. 8 to 10 are cross-sectional views illustrating the steps of manufacturing the semiconductor device of this embodiment. This embodiment differs from the first embodiment in that, in the step of forming a bonded body between a wafer-state substrate 300 and a chip-shaped substrate 200, a metal layer that becomes a pad 600 is not formed on the wiring structure 360. Other than this point and the points described below, the configuration is substantially the same as that of the first embodiment, and therefore, description thereof may be omitted.

[0058] 8, a bonded body is formed by stacking and bonding a chip-shaped substrate 200 on a wafer-state substrate 300. A semiconductor layer 201 of the substrate 200 includes a photoelectric conversion element.

[0059] 9, silicon oxide is deposited and etched to form protective structures 406 on the side surfaces of the semiconductor layer 201. Subsequently, a metal film mainly made of aluminum is deposited, and a metal layer of a pad 600 containing nitrogen is formed using photolithography and etching techniques. At this time, the pad 600 comes into contact with the metal pattern 304, thereby being electrically connected.

[0060] 10, similarly to the first embodiment, protective films 401 and 402 are formed, and the semiconductor layer 201 is thinned to form an optical structure. Then, the bonding layer 403, protective films 402 and 401 are etched to form openings so that the pads 600 are exposed, and the semiconductor device shown in FIG. 10 is obtained by dicing the semiconductor device.

[0061] The metal layer of the pad 600 is thicker than the other metal layers, which can cause deterioration in flatness during formation. In this embodiment, by forming the pad 600 after bonding the chip-shaped substrate 200 to the wafer-state substrate 300, it is possible to reduce bonding defects when bonding the substrates 300 and 200, and to reduce electrical connection defects between the metal pattern 204 and the metal pattern 304.

[0062] (Third embodiment) A semiconductor device according to a third embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 11 and 12. FIGS. 11 and 12 are cross-sectional views illustrating steps in a manufacturing method for a semiconductor device according to this embodiment. This embodiment differs from the first embodiment in that, when the bonding layer 403 has been formed, no metal layer serving as the pad 600 is formed in the wiring structures 260 and 360, and the pad 600 is formed above the upper surface of the wiring structure 260. Other than this point and the points described below, the configuration is substantially the same as that of the first embodiment, and therefore, a description thereof may be omitted.

[0063] 11, a bonded structure is formed by stacking and bonding a chip-shaped substrate 200 on a wafer-state substrate 300. A semiconductor layer 201 of the substrate 200 includes a photoelectric conversion element. Then, similar to the first embodiment, protective films 401 and 402 are formed, the semiconductor layer 201 is thinned, and a bonding layer 403 included in the optical structure is formed.

[0064] 12, via-shaped openings are formed in the bonding layer 403, the protective film 402, and the protective film 401, and a metal mainly made of tungsten is embedded in the openings to form plugs 407. Furthermore, pads 600 mainly made of aluminum are formed so as to be in contact with the plugs 407. Thereafter, color filters, microlenses, etc. included in the optical structure are formed, thereby obtaining the semiconductor device shown in FIG.

[0065] In this embodiment, plug 407 is connected to metal pattern 304, but may be connected to any metal layer of wiring layer 303. In this embodiment, by forming pad 600 after bonding chip-shaped substrate 200 to substrate 300, bonding defects when bonding substrate 300 and substrate 200 can be reduced, and electrical connection defects between metal pattern 204 and metal pattern 304 can be reduced.

[0066] (Fourth embodiment) A semiconductor device and a method for manufacturing the same according to a fourth embodiment of the present invention will be described with reference to FIGS.

[0067] The schematic configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 13. Fig. 13(a) is a schematic plan view of the semiconductor device according to this embodiment, and Fig. 13(b) is a schematic cross-sectional view of the AB plane of Fig. 13(a).

[0068] The fourth embodiment differs from the first embodiment in that a circuit portion, which is a chip-shaped substrate 300 (first substrate), is bonded to a wafer-state substrate 200 (second substrate), and the substrate 200 includes a guard structure 205. In addition, the substrate 300 is bonded to a single imaging element included in the substrate 200 as separate chips, a memory circuit 300a and a logic circuit 300b. Other than these points and points described below, the configuration is substantially the same as the first embodiment, and therefore, description may be omitted.

[0069] In this embodiment, the semiconductor layer 201 of the substrate 200 is larger than the semiconductor layer 301 of the substrate 300 in plan view.

[0070] The substrate 200 includes a guard structure 205. The guard structure 205 is similar to the guard structure 305 described in the first embodiment, and the guard structure 205 includes a metal pattern on the bonding surface with the substrate 300. The metal pattern of the guard structure 205 is covered with a protective film 401. This prevents metal elements of the metal pattern of the guard structure 205 from diffusing into the semiconductor layer 301. Furthermore, at least a portion of the guard structure 205 is formed outside the memory circuit 300a and the logic circuit 300b in a plan view.

[0071] A support substrate 500 is disposed on the side of the substrate 300 opposite to the substrate 200. Furthermore, similar to the first embodiment, optical structures such as a bonding layer 403, a color filter 404, and a microlens 405 are disposed on the surface of the substrate 200 opposite to the substrate 300.

[0072] The protective film 401 is disposed not only on the guard structure 205 but also on the side surfaces of the substrate 300 and the surface opposite to the bonding surface. As shown in Fig. 13(b), the protective film 401 preferably continuously covers the surfaces other than the bonding surface with the substrate 200. In Fig. 13(b), the protective film 401 covers the side surfaces of the memory circuit 300a and the logic circuit 300b and the surface opposite to the bonding surface with the substrate 200.

[0073] Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to Figures 14 to 18. Figures 14 to 18 are cross-sectional views showing the steps in the method for manufacturing the semiconductor device according to this embodiment.

[0074] In FIG. 14 , a substrate 300 including a chip-shaped memory circuit 300a and a logic circuit 300b is bonded to a wafer-like substrate 200 having multiple imaging elements arranged thereon. In this embodiment, two circuit chips are bonded to one imaging element, but the number of bonded circuit chips may be one or more. The memory circuit 300a and the logic circuit 300b are bonded by Cu-Cu metal bonding and covalent bonding between the wiring interlayer film 202 and the wiring interlayer film 302, as in the first embodiment. After bonding the chips, a process of thinning the semiconductor layer 301 may be performed. At least a portion of the guard structure 205 is formed outside the memory circuit 300a and the logic circuit 300b in a plan view. A metal layer that becomes the pad 600 is formed in the wiring interlayer film 202 on the substrate 200 side.

[0075] 15, silicon nitride (SiN) is deposited as a protective film 401. As in the first embodiment, in order to improve moisture resistance, it is desirable to use a material such as silicon oxynitride (SiON) in addition to silicon nitride as the protective film 401. In this embodiment, by leaving the protective film 401 on the side and top surfaces of the memory circuit 300a and the logic circuit 300b, it is possible to improve the moisture resistance of the memory circuit 300a and the logic circuit 300b.

[0076] As in the first embodiment, a step of removing a portion of the silicon nitride that will become the protective film 401 may be performed. When performing the removal step, for example, by removing the protective film 401 from the dicing surface, problems such as film peeling during dicing can be avoided.

[0077] Next, as shown in FIG. 16 , an insulating film containing, for example, silicon oxide is deposited by CVD and planarized by CMP to form a protective film 402. The substrate 300 has a thickness of, for example, 10 μm to 30 μm, and the protective film 402 must be deposited to a thickness greater than the height of the substrate 300. The insulating film for the protective film 402 may be formed by a coating method such as a spin-on glass method, which can improve flatness. Furthermore, after depositing an insulating film by the spin-on glass method, another insulating film may be deposited using CVD and then planarized by CMP. When planarizing the protective film 402, CMP may be performed until the portion of the protective film 401 formed on the substrate 300 is exposed. This allows for improved flatness within the wafer surface due to differences in polishing rates depending on the material. It is not necessary to expose the protective film 401 during the planarization process; the protective film 402 may remain on the entire surface. Alternatively, an underfill material may be formed by, for example, spin coating before depositing the protective film 402, and then a protective film made of silicon oxide may be deposited and the protective film 402 may be planarized. The introduction of underfill material can improve the planarity after CMP.

[0078] 17, bonding is performed to a support substrate 500 via a bonding surface 501. A bonding layer made of silicon nitride or silicon oxynitride is formed on the support substrate 500. Then, the bonding layers made of silicon nitride or silicon oxynitride are bonded to each other at the bonding surface 501.

[0079] 18, a step of thinning the semiconductor layer 201 is carried out to form optical structures such as color filters 404 and microlenses 405. Subsequently, openings are formed to expose the pads 600. According to the method for manufacturing a semiconductor device of this embodiment, defects in bonding to a support substrate or the like can be reduced.

[0080] (Fifth embodiment) A semiconductor device according to a fifth embodiment of the present invention and a manufacturing method thereof will be described with reference to Figures 19 to 22. Figures 19 to 22 are cross-sectional views illustrating the steps of manufacturing the semiconductor device of this embodiment. This embodiment differs from the fourth embodiment in that, in the step of forming a bonded body between a wafer-state substrate 200 and a chip-shaped substrate 300, a metal layer that becomes a pad 600 is not formed on the wiring structure 260. Other than this point and the points described below, the configuration is substantially the same as that of the fourth embodiment, and therefore, description thereof may be omitted.

[0081] 19, a bonded body is formed by bonding a circuit portion, which is a chip-shaped substrate 300 (first substrate), to a wafer-state substrate 200. No metal layer that will become a pad 600 is formed in the wiring interlayer film 202.

[0082] 20, silicon oxide is deposited and etched to form a protective structure 406 on the side surface of the semiconductor layer 301. Subsequently, a metal film mainly made of aluminum is deposited, and a metal layer of the pad 600 containing nitrogen is formed using photolithography and etching techniques. At this time, the metal layer of the pad 600 is electrically connected by contacting with the metal pattern 204. In this embodiment, the pad 600 is connected to the metal pattern 204, but it may also be connected to the wiring layer 203 through a via or the like.

[0083] Next, the semiconductor layer 301 is thinned by a back grinding device, and protective films 401 and 402 are formed as shown in FIG. 21, and then the semiconductor layer 301 is bonded to a support substrate 500 via a bonding surface 501 .

[0084] 22, a step of thinning the semiconductor layer 201 is carried out to form optical structures such as a color filter 404 and a microlens 405. Subsequently, an opening is formed so that the pad 600 is exposed, thereby obtaining the semiconductor device shown in FIG.

[0085] In this embodiment, by forming pads 600 after bonding chip-shaped substrate 300 to wafer-shaped substrate 200, it is possible to reduce bonding failures when bonding substrates 300 and 200 together, and to reduce electrical connection failures between metal pattern 204 and metal pattern 304.

[0086] (Sixth embodiment) A semiconductor device and a manufacturing method thereof according to a sixth embodiment of the present invention will be described with reference to Figures 23 and 24. Figures 23 and 24 are cross-sectional views illustrating steps in the manufacturing method of the semiconductor device of this embodiment. This embodiment differs from the fourth embodiment in that, in the step of bonding a wafer-state substrate 200 to a chip-shaped substrate 300 and then bonding a support substrate 500, a metal layer that becomes pads 600 is not formed on the wiring structure 260. Other than this point and the points described below, the configuration is substantially the same as that of the fourth embodiment, and therefore, description thereof may be omitted.

[0087] 23 shows a state in which a circuit portion, which is a chip-shaped substrate 300 (first substrate), is bonded to a wafer-state substrate 200, and is further bonded to a support substrate 500. As shown in FIG. 23, in this embodiment, a metal layer that becomes a pad 600 is not formed in the wiring interlayer film 202 of the wiring structure 260.

[0088] 24 , in this embodiment, a step of thinning the semiconductor layer 201 is carried out, a part of the bonding layer 403 is formed, and then a via 408 penetrating the semiconductor layer 201 is formed. The via 408 is bonded to the via 207 formed in the wiring layer 203. Next, a metal pattern of the pad 600 is formed, the remaining part of the bonding layer 403 is formed, and an opening for the pad 600 is formed.

[0089] In this embodiment, via 408 is bonded to via 207, but it may also be bonded to wiring layer 203. Next, optical structures such as color filter 404 and microlens 405 are formed, and pad 600 is formed. In this way, the semiconductor device shown in FIG. 24 is obtained.

[0090] In this embodiment, by forming pads 600 after bonding chip-shaped substrate 300 to wafer-shaped substrate 200, it is possible to reduce bonding failures when bonding substrate 300 and substrate 200, and to reduce electrical connection failures between metal pattern 204 and metal pattern 304.

[0091] (Seventh embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 25. Fig. 25 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0092] The semiconductor devices (imaging devices) described in the first to sixth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system. Figure 25 shows a block diagram of a digital still camera as an example of such systems.

[0093] 25 includes an imaging device 1004, which is an example of a semiconductor device, and a lens 1002 that forms an optical image of a subject on the imaging device 1004. The imaging device 1004 further includes an aperture 1003 that adjusts the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the imaging device 1004. The imaging device 1004 is a semiconductor device (imaging device) according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0094] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as necessary to output image data. The signal processing unit 1007 may be formed on the same semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004. Alternatively, the imaging device 1004 and the signal processing unit 1007 may be formed on the same semiconductor substrate.

[0095] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0096] The photoelectric conversion system further includes an overall control and calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0097] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0098] As described above, according to this embodiment, it is possible to realize a photoelectric conversion system to which the semiconductor device (imaging device) according to any one of the above embodiments is applied.

[0099] (Eighth embodiment) The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 26. Fig. 26 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0100] FIG. 26(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 1300 includes an imaging device 1310. The imaging device 1310 is the semiconductor device (imaging device) described in any of the above embodiments. The photoelectric conversion system 1300 includes an image processing unit 1312 that performs image processing on multiple pieces of image data acquired by the imaging device 1310. The photoelectric conversion system 1300 also includes a parallax acquisition unit 1314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 1300. The photoelectric conversion system 1300 also includes a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 1318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0101] The photoelectric conversion system 1300 is connected to a vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1300 is also connected to a control ECU 1330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 1318. The photoelectric conversion system 1300 is also connected to an alarm device 1340 that issues an alarm to the driver based on the determination result of the collision determination unit 1318. For example, if the determination result of the collision determination unit 1318 indicates a high collision possibility, the control ECU 1330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0102] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 1300. Fig. 26(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 1350). A vehicle information acquisition device 1320 sends instructions to the photoelectric conversion system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0103] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the subject vehicle, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, a propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0104] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0105] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present invention.

[0106] Furthermore, the photoelectric conversion systems shown in the seventh and eighth embodiments are examples of photoelectric conversion systems to which the semiconductor device can be applied, and the photoelectric conversion systems to which the semiconductor device of the present invention can be applied are not limited to the configurations shown in Figures 25 and 26.

[0107] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0108] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then even if the statement that "A is not B" (A≠B) is omitted, this specification is deemed to disclose or suggest that "A is not B." This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0109] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0110] The present invention also includes the following configurations.

[0111] (Configuration 1) 1. A semiconductor device comprising: a first substrate including a first wiring structure and a first semiconductor layer; a second substrate including a second wiring structure and a second semiconductor layer; and a pad connected to an external terminal, wherein a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other; in a planar view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer; the pad is arranged outside the first semiconductor layer in a planar view; and a first protective film is arranged extending over at least a portion of a side surface of the first semiconductor layer and at least a portion of a side surface of the first wiring structure, and the first protective film contains nitrogen.

[0112] (Configuration 2) 2. The semiconductor device according to configuration 1, wherein the first semiconductor layer includes a photoelectric conversion element.

[0113] (Configuration 3) 2. The semiconductor device according to configuration 1, wherein the second semiconductor layer includes a photoelectric conversion element.

[0114] (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein the pad is disposed at the same height as the first wiring structure.

[0115] (Configuration 5) 4. The semiconductor device according to claim 1, wherein the pad is disposed at a height higher than that at which the first semiconductor layer is disposed.

[0116] (Configuration 6) a first substrate including a first wiring structure and a first semiconductor layer having a photoelectric conversion element; a second substrate including a second wiring structure and a second semiconductor layer; a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined together, and the first semiconductor layer and the second semiconductor layer are electrically connected to each other; In a plan view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, a first protective film is disposed so as to extend over at least a portion of a side surface of the first semiconductor layer and at least a portion of a side surface of the first wiring structure; 1. A semiconductor device, wherein the first protective film contains nitrogen.

[0117] (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, wherein the first protective film contains SiN or SiON.

[0118] (Configuration 8) 8. The semiconductor device according to any one of configurations 1 to 7, wherein the first protective film is disposed on the entire side surface of the first semiconductor layer.

[0119] (Configuration 9) 9. The semiconductor device according to any one of structures 1 to 8, wherein, in the plan view, the first protective film overlaps the second wiring structure located outside the first semiconductor layer.

[0120] (Configuration 10) The semiconductor device described in any one of structures 1 to 9, characterized in that the second wiring structure includes a guard structure having a third metal pattern arranged at the same height as the second metal pattern, and in the planar view, the first protective film is characterized in that the contact portion between the third metal pattern and the first protective film is located outside the first semiconductor layer.

[0121] (Configuration 11) 11. The semiconductor device according to claim 10, wherein the contact portion is located outside an edge of the first semiconductor layer in the plan view.

[0122] (Configuration 12) 11. The semiconductor device according to any one of configurations 1 to 10, wherein the third metal pattern is made of a material containing Cu as a main component.

[0123] (Configuration 13) 13. The semiconductor device according to any one of structures 1 to 12, wherein the first protective film extends to a surface of the first semiconductor layer opposite to the second semiconductor layer.

[0124] (Configuration 14) 14. The semiconductor device according to any one of structures 1 to 13, wherein an insulating film is disposed between the side surface of the first semiconductor layer and the first protective film.

[0125] (Configuration 15) 15. The semiconductor device according to any one of structures 1 to 14, wherein the shortest distance between the side surface of the first semiconductor layer and the first protective film is 300 nm or less.

[0126] (Configuration 16) 16. The semiconductor device according to any one of configurations 1 to 15, further comprising a support substrate, the first substrate and the second substrate being stacked on the support substrate.

[0127] (Configuration 17) 17. A photoelectric conversion system comprising: the semiconductor device according to any one of configurations 1 to 16; and a signal processing unit that generates an image using a signal output by the semiconductor device.

[0128] (Configuration 18) 17. A moving body comprising the semiconductor device according to any one of configurations 1 to 16, characterized in that the moving body has a control unit that controls movement of the moving body using a signal output by the semiconductor device.

[0129] (Configuration 19) 1. A method for manufacturing a semiconductor device, comprising: preparing a bonded body in which a first substrate including a first wiring structure and a first semiconductor layer and a second substrate including a second wiring structure and a second semiconductor layer are stacked; forming a protective film on an upper surface and a side surface of the bonded body, the protective film being a first protective film containing nitrogen and a second protective film arranged in that order; and removing a portion of the protective film so that at least a portion of the first protective film is exposed, wherein in the step of preparing the bonded body, a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are bonded to each other so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, and the second semiconductor layer is larger than the first semiconductor layer in a plan view seen from the first semiconductor layer side.

[0130] (Configuration 20) 20. The method for manufacturing a semiconductor device according to claim 19, further comprising the step of bonding a support substrate after the step of removing a portion of the protective film.

[0131] (Configuration 21) 21. The method for manufacturing a semiconductor device according to Structure 19 or 20, wherein the first protective film contains SiN or SiON, and the second protective film contains SiO.

[0132] (Configuration 22) 22. The method for manufacturing a semiconductor device according to any one of claims 19 to 21, wherein the step of removing a portion of the protective film includes planarizing an upper surface of the protective film by a CMP method.

[0133] (Configuration 23) 23. The method for manufacturing a semiconductor device according to any one of configurations 19 to 22, wherein the thickness of the second protective film is at least 10 times the thickness of the first protective film.

[0134] (Configuration 24) 24. The method for manufacturing a semiconductor device according to any one of Structures 19 to 23, wherein an insulating film is formed on a side surface of the first semiconductor layer before the step of forming the protective film.

[0135] (Configuration 25) In the step of preparing the junction body, the first semiconductor layer has a first region to which an impurity is added and a second region to which the impurity is not added, the insulating film is formed on a sidewall of the first region, 25. The method of manufacturing a semiconductor device according to claim 24, wherein in the step of removing a portion of the protective film, a portion of the first semiconductor layer is removed.

[0136] (Configuration 26) 26. A method for manufacturing a semiconductor device according to any one of structures 19 to 25, characterized in that in the step of removing a portion of the protective film, the portion of the first semiconductor layer is removed so that the height of the first semiconductor layer is lower than the height of the protective film. [Explanation of symbols]

[0137] 100 Semiconductor device 200 boards 201 Semiconductor layer 202 Interlayer film 203 Wiring layer 204 Metal Pattern 205 Guard Structure 300 boards 301 Semiconductor layer 302 Interlayer film 303 Wiring layer 304 Metal Pattern 305 Guard Structure 401 Protective film (1st protective film) 402 Protective film (secondary protective film) 600 pads

Claims

1. a first substrate including a first wiring structure and a first semiconductor layer; a second substrate including a second wiring structure and a second semiconductor layer; a pad to be connected to an external terminal, a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined together, and the first semiconductor layer and the second semiconductor layer are electrically connected to each other; In a plan view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, the pad is disposed outside the first semiconductor layer in a plan view, a first protective film is disposed so as to extend over at least a portion of a side surface of the first semiconductor layer and at least a portion of a side surface of the first wiring structure; The semiconductor device is characterized in that the first protective film contains nitrogen.

2. 2. The semiconductor device according to claim 1, wherein the first protective film contains SiN or SiON.

3. The semiconductor device according to claim 2 , wherein the first protective film is disposed on the entire side surface of the first semiconductor layer.

4. 4. The semiconductor device according to claim 3, wherein, in the plan view, the first protective film overlaps the second wiring structure located outside the first semiconductor layer.

5. the second wiring structure includes a guard structure having a third metal pattern disposed at the same height as the second metal pattern; 2. The semiconductor device according to claim 1, wherein, in the plan view, a contact portion between the third metal pattern and the first protective film is located outside the first semiconductor layer.

6. The semiconductor device according to claim 5 , wherein the contact portion is located outside an edge of the first semiconductor layer in the plan view.

7. 7. The semiconductor device according to claim 6, wherein the third metal pattern is made of a material containing Cu as a main component.

8. 2. The semiconductor device according to claim 1, wherein the first protective film extends to a surface of the first semiconductor layer opposite to the second semiconductor layer.

9. 2. The semiconductor device according to claim 1, wherein an insulating film is disposed between the side surface of the first semiconductor layer and the first protective film.

10. 2. The semiconductor device according to claim 1, wherein the shortest distance between the side surface of the first semiconductor layer and the first protective film is 300 nm or less.

11. a support substrate; The semiconductor device according to claim 1 , wherein the first substrate and the second substrate are stacked on the support substrate.

12. The semiconductor device according to claim 1 , wherein the first semiconductor layer includes a photoelectric conversion element.

13. The semiconductor device according to claim 1 , wherein the second semiconductor layer includes a photoelectric conversion element.

14. 2. The semiconductor device according to claim 1, wherein the pad is disposed at the same height as that at which the first wiring structure is disposed.

15. 2. The semiconductor device according to claim 1, wherein the pad is disposed above a height at which the first semiconductor layer is disposed.

16. a first substrate including a first wiring structure and a first semiconductor layer having a photoelectric conversion element; a second substrate including a second wiring structure and a second semiconductor layer; a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined together, and the first semiconductor layer and the second semiconductor layer are electrically connected to each other; In a plan view seen from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer, a first protective film is disposed so as to extend over at least a portion of a side surface of the first semiconductor layer and at least a portion of a side surface of the first wiring structure; The semiconductor device is characterized in that the first protective film contains nitrogen.

17. 17. The semiconductor device according to claim 16, wherein the first protective film contains SiN or SiON.

18. The semiconductor device according to claim 17 , wherein the first protective film is disposed on the entire side surface of the first semiconductor layer.

19. 19. The semiconductor device according to claim 18, wherein, in the plan view, the first protective film overlaps the second wiring structure located outside the first semiconductor layer.

20. the second wiring structure includes a guard structure having a third metal pattern disposed at the same height as the second metal pattern; 17. The semiconductor device according to claim 16, wherein, in the plan view, a contact portion between the third metal pattern and the first protective film is located outside the first semiconductor layer.

21. 21. The semiconductor device according to claim 20, wherein the contact portion is located outside an edge of the first semiconductor layer in the plan view.

22. 22. The semiconductor device according to claim 21, wherein the third metal pattern is made of a material containing Cu as a main component.

23. 17. The semiconductor device according to claim 16, wherein the first protective film extends to a surface of the first semiconductor layer opposite to the second semiconductor layer.

24. 17. The semiconductor device according to claim 16, wherein an insulating film is disposed between the side surface of the first semiconductor layer and the first protective film.

25. 17. The semiconductor device according to claim 16, wherein the shortest distance between the side surface of the first semiconductor layer and the first protective film is 300 nm or less.

26. a support substrate; The semiconductor device according to claim 16 , wherein the first substrate and the second substrate are stacked on the support substrate.

27. A semiconductor device according to any one of claims 1 to 26; a signal processing unit that generates an image using a signal output from the semiconductor device.

28. A moving object comprising the semiconductor device according to any one of claims 1 to 26, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the semiconductor device.

29. a step of preparing a bonded body in which a first substrate including a first wiring structure and a first semiconductor layer and a second substrate including a second wiring structure and a second semiconductor layer are stacked; forming a protective film on the upper surface and side surface of the bonded body, the protective film being a first protective film containing nitrogen and a second protective film disposed in this order; removing a portion of the protective film so that at least a portion of the first protective film is exposed; A method for manufacturing a semiconductor device, characterized in that in the step of preparing the junction, a junction is prepared in which a first metal pattern included in the first wiring structure and a second metal pattern included in the second wiring structure are joined so that the first semiconductor layer and the second semiconductor layer are electrically connected to each other, and in a planar view viewed from the first semiconductor layer side, the second semiconductor layer is larger than the first semiconductor layer.

30. 30. The method for manufacturing a semiconductor device according to claim 29, further comprising the step of bonding a support substrate after the step of removing a portion of the protective film.

31. 30. The method of claim 29, wherein the first protective film contains SiN or SiON, and the second protective film contains SiO.

32. 32. The method for manufacturing a semiconductor device according to claim 31, wherein the step of removing a portion of the protective film includes planarizing an upper surface of the protective film by a CMP method.

33. 30. The method for manufacturing a semiconductor device according to claim 29, wherein the thickness of the second protective film is at least 10 times the thickness of the first protective film.

34. 30. The method for manufacturing a semiconductor device according to claim 29, wherein an insulating film is formed on a side surface of the first semiconductor layer before the step of forming the protective film.

35. In the step of preparing the junction body, the first semiconductor layer has a first region to which an impurity is added and a second region to which the impurity is not added, the insulating film is formed on a sidewall of the first region, 35. The method for manufacturing a semiconductor device according to claim 34, wherein in the step of removing a portion of the protective film, a portion of the first semiconductor layer is removed.

36. 30. The method for manufacturing a semiconductor device according to claim 29, wherein in the step of removing a portion of the protective film, the portion of the first semiconductor layer is removed so that the height of the first semiconductor layer is lower than the height of the protective film.

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