Semiconductor device

Abstract

To provide a semiconductor device which provides stable performance and improved reliability in a diode having a structure similar to that of a nanosheet field effect transistor.SOLUTION: A semiconductor device 10 includes: a first well region NW and a second well region PW disposed along a first horizontal direction X in a substrate 101 between element isolation films STI, and coming into contact with each other; nanosheets NS and sacrificial dielectric patterns 111 alternately stacked in a vertical direction; a pair of inactive gate structures GS surrounding both ends of the nanosheets and the sacrificial dielectric patterns, respectively; a first impurity conductive part NC penetrating through the nanosheets and the sacrificial dielectric patterns 101 in the vertical direction to be connected to the first well region NW; a second impurity conductive part PC penetrating through the nanosheets and the sacrificial dielectric patterns in the vertical direction to be connected to the second well region PW; a first contact CT connected to the top of the first impurity conductive part; and a second contact CT connected to the top of the second impurity conductive part.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including field effect transistors and diodes. [Background technology]

[0002] As the size of semiconductor devices continues to shrink, there is a need to increase the integration density of field-effect transistors on a substrate, which has led to the development of nanosheet field-effect transistors (NSFETs), which contain multiple nanosheets stacked on the same layout area. Recently, as the integration density of semiconductor devices continues to increase and the size of semiconductor devices continues to shrink, there is a need to develop new structures that can improve the reliability of nanosheet field-effect transistors and diodes with similar structures. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide a semiconductor device that can provide stable performance and improved reliability in a diode having a structure similar to that of a nanosheet field effect transistor.

[0004] The problems that the technical idea of ​​the present invention aims to solve are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] a first well region and a second well region arranged along a first horizontal direction in the substrate between the pair of device isolation layers and contacting each other; a nanosheet and a sacrificial insulating pattern alternately stacked vertically on the first well region and the second well region; a pair of inactive gate structures extending from both ends of the nanosheet and the sacrificial insulating pattern in a second horizontal direction perpendicular to the first horizontal direction and surrounding both ends of the nanosheet and the sacrificial insulating pattern; a first impurity conductive portion penetrating the nanosheet and the sacrificial insulating pattern in the vertical direction on the first well region and connected to the first well region; a second impurity conductive portion penetrating the nanosheet and the sacrificial insulating pattern in the vertical direction on the second well region and connected to the second well region; a first contact connected to an upper portion of the first impurity conductive portion; and a second contact connected to an upper portion of the second impurity conductive portion.

[0006] A semiconductor device according to the technical idea of ​​the present invention includes a substrate having a first surface and a second surface facing each other, a pair of isolation films penetrating the substrate and spaced apart in a first horizontal direction, a nanosheet and a sacrificial insulating pattern alternately stacked in a vertical direction on the substrate between the pair of isolation films, a pair of inactive gate structures extending from both ends of the nanosheet and the sacrificial insulating pattern in a second horizontal direction perpendicular to the first horizontal direction and surrounding both ends of the nanosheet and the sacrificial insulating pattern, a first impurity region penetrating the substrate, the nanosheet, and the sacrificial insulating pattern in the vertical direction, a second impurity region penetrating the substrate, the nanosheet, and the sacrificial insulating pattern in the vertical direction and contacting the first impurity region, a first contact connected to an upper portion of the first impurity region, and a second contact connected to an upper portion of the second impurity region.

[0007] A semiconductor device according to the technical idea of ​​the present invention includes a substrate having a first surface and a second surface facing each other and a pair of isolation films penetrating the substrate; a first well region and a second well region arranged along a first horizontal direction in the substrate between the pair of isolation films and contacting each other; a nanosheet and a sacrificial insulating pattern alternately stacked vertically on the first well region and the second well region; a first impurity conductive portion penetrating the nanosheet and the sacrificial insulating pattern in the vertical direction on the first well region and connected to the first well region; a second impurity conductive portion penetrating the nanosheet and the sacrificial insulating pattern in the vertical direction on the second well region and connected to the second well region; a first contact connected to an upper portion of the first impurity conductive portion; a second contact connected to an upper portion of the second impurity conductive portion; and a backside power distribution network arranged below the second surface of the substrate. [Effects of the Invention]

[0008] The semiconductor device according to the technical concept of the present invention can provide stable performance and improved reliability by including a side PN junction diode in which there is no inactive gate structure on the interface of the junction diode in a diode having a structure similar to that of a nanosheet field effect transistor. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a schematic plan view illustrating components of a semiconductor device in accordance with one embodiment of the inventive concept. [Figure 1B] FIG. 1B is a cross-sectional view taken along line BB' in FIG. 1A. [Figure 2A] 1 is a schematic plan view illustrating components of a semiconductor device in accordance with another embodiment of the inventive concept. [Figure 2B] FIG. 2B is a cross-sectional view taken along line BB' in FIG. 2A. [Figure 3A] 1 is a schematic plan view of a semiconductor device according to yet another embodiment of the inventive concept. [Figure 3B] 1 is a schematic plan view of a semiconductor device according to yet another embodiment of the inventive concept. [Figure 4] 1 is a schematic plan view of a semiconductor device according to yet another embodiment of the inventive concept. [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 16]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 24] 1 is a block diagram illustrating a system including a semiconductor device according to an embodiment of the inventive concept; DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0011] Figure 1A is a schematic plan view of components of a semiconductor device according to one embodiment of the inventive concept, and Figure 1B is a cross-sectional view taken along line BB' of Figure 1A.

[0012] Referring to both FIGS. 1A and 1B, the semiconductor device 10 of the present invention includes a lateral diode formed on a substrate 101, and the lateral diode may have a structure similar to a nanosheet field effect transistor or a multi-bridge channel FET (MBCFET) (hereinafter referred to as a nanosheet field effect transistor).

[0013] The substrate 101 may be a wafer containing silicon (Si). In some embodiments, the substrate 101 may be a wafer containing a semiconductor element such as germanium (GE), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Alternatively, the substrate 101 may have a silicon-on-insulator (SOI) structure.

[0014] A pair of isolation layers STI defining a region where the lateral diode is to be formed may be disposed on the substrate 101. The isolation layer STI may also be a shallow trench isolation extending through the substrate 101. The isolation layer STI may have a double-layer structure including an interface layer (not shown) and a buried insulating layer (not shown).

[0015] The substrate 101 may also include a first well region NW and a second well region C that are disposed along a first horizontal direction (X direction) between a pair of isolation films STI and are in contact with each other. The first well region NW and the second well region PW may each be formed using a doping process. For example, the first well region NW is a region doped with impurities having a first conductivity type, and the second well region PW is a region doped with impurities having a second conductivity type different from the first conductivity type. Here, the first conductivity type may be n-type, and the second conductivity type may be p-type, but is not limited thereto. Therefore, the first well region NW is also referred to as an n-type well, and the second well region PW is also referred to as a p-type well.

[0016] In the semiconductor device 10 of the present invention, a lateral PN junction diode can be formed at the interface where the first well region NW and the second well region PW contact each other, and a gate structure GS (described later) is not formed on the contact interface.

[0017] In some embodiments, through the process of reducing the thickness of the substrate 101, the vertical level of the top surfaces of the first well region NW and the second well region PW is substantially the same as the upper surface of the substrate 101, and the vertical level of the bottom surfaces of the first well region NW and the second well region PW is also substantially the same as the bottom surface of the substrate 101.

[0018] Nanosheets NS and sacrificial insulating patterns 110S may be stacked and arranged alternately in the vertical direction (Z direction) on the first well region NW and the second well region PW.

[0019] Specifically, the nanosheets NS may be spaced apart in the vertical direction (Z direction), and each nanosheet NS may include a semiconductor element such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiC, GaAs, InAs, or InP.

[0020] The nanosheets NS are also semiconductor patterns having a relatively wide width in a first horizontal direction (X-direction) and a relatively thin thickness in a vertical direction (Z-direction). For example, but not limited to, each nanosheet NS may have a width along the first horizontal direction (X-direction) in the range of about 5 nm to 100 nm and a thickness along the vertical direction (Z-direction) in the range of about 1 nm to 10 nm. In some embodiments, at least one of the nanosheets NS also has a different thickness along the vertical direction (Z-direction) than the remaining nanosheets NS.

[0021] In some embodiments, the nanosheets NS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 spaced apart in the vertical direction (Z direction). Of course, the number of nanosheets NS is not limited thereto. In the semiconductor device 10 of the present invention, the nanosheets NS shown in the drawings may also be one component constituting a lateral diode. Meanwhile, the nanosheets NS not shown may function as a channel region from a nanosheet field-effect transistor.

[0022] In the semiconductor device 10 of the present invention, a sacrificial insulating pattern 110S may be disposed between the nanosheets NS. The sacrificial insulating pattern 110S shown in the drawings is also one component constituting a lateral diode. Meanwhile, in a nanosheet field effect transistor, the sacrificial insulating pattern 110S may be removed, and a gate dielectric layer (not shown) and a gate line (not shown) may be formed in the location where the sacrificial insulating pattern 110S was removed.

[0023] In some embodiments, the length of the nanosheet NS along the first horizontal direction (X direction) and the length of the sacrificial insulating pattern 110S along the first horizontal direction (X direction) may be substantially the same. In some embodiments, both ends of the nanosheet NS along the first horizontal direction (X direction) and each end of the pair of element isolation films STI may be aligned in the vertical direction (Z direction).

[0024] In the semiconductor device 10 of the present invention, a pair of gate structures GS may be disposed, extending from both ends of the nanosheet NS and the sacrificial insulating pattern 110S in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction) and surrounding both ends of the nanosheet NS and the sacrificial insulating pattern 110S. The gate structures GS illustrated in the drawings are also referred to as inactive gate structures or dummy gate structures. In other words, they may be understood as dummy structures that are not involved in the operation of the semiconductor device 10. Meanwhile, in a nanosheet field effect transistor, the gate structure GS is also an active gate structure that constitutes a transistor.

[0025] The gate structure GS may include a gate spacer 120 and a gate electrode 130 surrounded by the gate spacer 120. In some embodiments, the gate spacer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof. In some embodiments, the gate electrode 130 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the gate electrode 130 may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof.

[0026] The semiconductor device 10 of the present invention may include a first impurity conductive portion NC that penetrates the nanosheet NS and the sacrificial insulating pattern 110S in the vertical direction (Z direction) on the first well region NW and is electrically connected to the first well region NW, and a second impurity conductive portion PC that penetrates the nanosheet NS and the sacrificial insulating pattern 110S in the vertical direction (Z direction) on the second well region PW and is electrically connected to the second well region PW. The first impurity conductive portion NC and the second impurity conductive portion PC shown in the drawings are also one component constituting a lateral diode. On the other hand, the first impurity conductive portion NC and the second impurity conductive portion PC do not exist in a nanosheet field effect transistor.

[0027] The first impurity conductive portion NC and the second impurity conductive portion PC may serve to electrically connect the first well region NW and the second well region PW to the contact CT. Therefore, the first impurity conductive portion NC may contain impurities of the same conductivity type (e.g., n-type impurities) as the first well region NW, and the second impurity conductive portion PC may contain impurities of the same conductivity type (e.g., p-type impurities) as the second well region PW. As will be described below, the first impurity conductive portion NC and the second impurity conductive portion PC may be formed to a predetermined conductivity type and a predetermined depth through an ion implantation process (IIP, see FIG. 9 ) and a heat treatment process.

[0028] In some embodiments, the vertical level of the top surfaces of the first impurity conductive portion NC and the second impurity conductive portion PC may be substantially the same as the vertical level of the top surface of the third nanosheet N3, and the vertical level of the bottom surfaces of the first impurity conductive portion NC and the second impurity conductive portion PC may be located inside the substrate 101.

[0029] An inter-gate insulating layer 140 may be disposed to cover the pair of gate structures GS and the nanosheet NS. The inter-gate insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

[0030] A contact CT may be disposed to penetrate the inter-gate insulating layer 140 and extend to the third nanosheet N3 and a portion of the sacrificial insulating pattern 110S. The contact CT may include a first contact electrically connected to the first impurity conductive portion NC and a second contact electrically connected to the second impurity conductive portion PC. Here, the contact CT may be disposed between a pair of gate structures GS in a first horizontal direction (X direction).

[0031] In some embodiments, each contact CT may be formed in a double-layer structure including a metal buried layer 154 and a metal barrier film 152 surrounding the side and bottom surfaces of the metal buried layer 154. That is, the metal barrier film 152 may be first disposed so as to contact the third nanosheet N3 and a portion of the sacrificial insulating pattern 110S, and then the metal buried layer 154 may be disposed so as to cover the metal barrier film 152. In other embodiments, the metal barrier film 152 may be omitted, and the contact CT may be formed as a layered structure of the metal buried layer 154.

[0032] In some embodiments, the metal barrier film 152 may include, for example, titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, and the metal buried layer 154 may include, for example, but is not limited to, at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), a suicide thereof, or an alloy thereof.

[0033] Although not shown, a back-end-of-line (BEOL) structure may be disposed on the inter-gate insulating layer 140 and the contact CT. The BEOL structure may include a via connected to the contact CT and a metal wiring connected to the via.

[0034] Advances in electronics technology have led to rapid downscaling of semiconductor devices. Since highly downscaled semiconductor devices require not only high operating speeds but also high operational accuracy, it is necessary to provide a stable and optimized wiring structure within a relatively small area. To this end, a semiconductor device 10 including a backside power delivery network (BSPDN) has been developed.

[0035] In the semiconductor device 10 of the present invention, a backside power wiring structure BSPDN may be further formed on the lower surface of the substrate 101, and a connection structure such as a via contact for connecting the backside power wiring structure BSPDN to a lateral diode and / or a nanosheet field effect transistor may be further formed.

[0036] As the size of semiconductor devices 10 gradually decreases, it has become necessary to increase the integration density of field effect transistors on a substrate 101, and thus nanosheet field effect transistors, which include nanosheets NS stacked on the same layout area, have been developed. Recently, as the integration density of semiconductor devices 10 has further increased and the size of semiconductor devices 10 has further decreased, it has become necessary to develop a structure that can improve the reliability of nanosheet field effect transistors and lateral diodes having similar structures.

[0037] Generally, a passive gate structure may be formed on the junction interface of a diode. However, due to the presence of the passive gate structure, a band-to-band tunneling effect occurs due to the gate electrode (metal material) of the passive gate structure, which induces leakage current.

[0038] The semiconductor device 10 according to the technical idea of ​​the present invention has an advantage that it can provide stable performance and improved reliability by using a first impurity conductive portion NC and a second impurity conductive portion PC instead of forming a gate structure GS on the junction interface of the diode in a lateral PN junction diode having a structure similar to that of a nanosheet field effect transistor.

[0039] Figure 2A is a schematic plan view of components of a semiconductor device according to another embodiment of the inventive concept, and Figure 2B is a cross-sectional view taken along line BB' of Figure 2A.

[0040] Most of the components and materials constituting the semiconductor device 20 described below are substantially the same as or similar to those described above with reference to Figures 1A and 1B. Therefore, for the sake of convenience, the following description will focus on the differences from the semiconductor device 10 described above.

[0041] 2A and 2B, the semiconductor device 20 of the present invention may include a lateral diode formed in the first impurity region NC2 and the second impurity region PC2.

[0042] The semiconductor device 20 of this embodiment does not include a first well region NW and a second well region PW. That is, instead of the first well region NW and the second well region PW, the semiconductor device 20 of this embodiment may include a first impurity region NC2 and a second impurity region PC2 that penetrate the substrate 101, the nanosheet NS, and the sacrificial insulating pattern 110S in the vertical direction (Z direction) and contact each other.

[0043] The first impurity region NC2 and the second impurity region PC2 are regions doped with impurities of different conductivity types. In some embodiments, the first impurity region NC2 may contain n-type impurities, and the second impurity region PC2 may contain p-type impurities. As will be described later, the first impurity region NC2 and the second impurity region PC2 may be formed to a predetermined conductivity type and a predetermined depth through an ion implantation process (IIP, see FIG. 18) and a heat treatment process.

[0044] As a result, a lateral PN junction diode can be formed at the interface where the first impurity region NC2 and the second impurity region PC2 contact each other. The contact interface can be formed across the substrate 101, the nanosheet NS, and the sacrificial insulating pattern 110S. Furthermore, no gate structure GS is formed on the contact interface.

[0045] In some embodiments, the first impurity region NC2 may include a first conductivity type impurity (e.g., n-type impurity), and the second impurity region PC2 may include a second conductivity type impurity (e.g., p-type impurity). As will be described later, the first impurity region NC2 and the second impurity region PC2 may be formed to a predetermined conductivity type and a predetermined depth through an ion implantation process (IIP, see FIG. 18) and a heat treatment process.

[0046] The vertical level of the top surfaces of the first impurity region NC2 and the second impurity region PC2 is also substantially the same as the vertical level of the top surface of the third nanosheet N3. In some embodiments, the vertical level of the bottom surfaces of the first impurity region NC2 and the second impurity region PC2 is also substantially the same as the bottom surface of the substrate 101 through the process of reducing the thickness of the substrate 101.

[0047] A contact CT may be disposed to penetrate the inter-gate insulating layer 140 and extend to the third nanosheet N3 and a portion of the sacrificial insulating pattern 110S. The contact CT may include a first contact electrically connected to the first impurity region NC2 and a second contact electrically connected to the second impurity region PC2. Here, the contact CT may be disposed between a pair of gate structures GS in the first horizontal direction (X direction).

[0048] The semiconductor device 20 according to the technical concept of the present invention has a lateral PN junction diode having a structure similar to that of a nanosheet field effect transistor, and does not form a gate structure GS on the junction interface of the diode, but instead uses a first impurity region NC2 and a second impurity region PC2, thereby providing stable performance and improved reliability.

[0049] 3A, 3B, and 4 are schematic plan views of a semiconductor device according to still another embodiment of the inventive concept.

[0050] Most of the components and materials constituting the semiconductor devices 30, 40, and 50 described below are substantially the same as or similar to those described above with reference to Figures 1A and 1B. Therefore, for the sake of convenience, the following description will focus on the differences from the semiconductor device 10 described above.

[0051] Referring to FIG. 3A, in the semiconductor device 30 of the present invention, each nanosheet NS formed on the substrate 101 may be formed in multiple numbers, spaced apart from each other along a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction).

[0052] In the semiconductor element 30 of this embodiment, each nanosheet NS is not a plate-shaped planar type extending in the second horizontal direction (Y direction), but may be formed as a multi-fin type in which multiple nanosheets are spaced apart from each other in the second horizontal direction (Y direction).

[0053] Although the drawings exemplarily illustrate three nanosheets NS along the second horizontal direction (Y direction), the number of nanosheets NS along the second horizontal direction (Y direction) is not limited thereto, and the number of nanosheets NS along the second horizontal direction (Y direction) may be two or four or more.

[0054] Referring to FIG. 3B, in the semiconductor device 40 of the present invention, a plurality of contacts CT may be formed on the substrate 101 in each of the first impurity conductive portion NC and the second impurity conductive portion PC.

[0055] In the semiconductor device 40 of this embodiment, the contacts CT may include a plurality of first contacts electrically connected to the first impurity conductive portion NC and a plurality of second contacts electrically connected to the second impurity conductive portion PC.

[0056] Although the drawings exemplarily illustrate three first contacts and three second contacts, the present invention is not limited thereto. That is, the number of first contacts and the number of second contacts may be two or more than four. Here, a contact CT may be disposed between a pair of gate structures GS in a first horizontal direction (X direction).

[0057] Referring to FIG. 4, in the semiconductor device 50 of the present invention, an inter-gate insulating layer 140 may be disposed on both ends of the nanosheet NS and the sacrificial insulating pattern 110S.

[0058] In the semiconductor device 50 of this embodiment, no inactive gate structures (or dummy gate structures) are formed on both ends of the nanosheet NS and the sacrificial insulating pattern 110S. Therefore, both ends of the nanosheet NS and the sacrificial insulating pattern 110S can be arranged to contact the inter-gate insulating layer 140.

[0059] 5 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0060] Referring to FIG. 5, a substrate 101 having a first surface and a second surface facing each other can be prepared.

[0061] The substrate 101 may have a first surface corresponding to the top surface (or active surface) and a second surface corresponding to the bottom surface (or non-active surface).

[0062] Then, a first well region NW and a second well region PW that are in contact with each other may be formed inside the substrate 101. Each of the first well region NW and the second well region PW may be formed using a doping process.

[0063] For example, the first well region NW is a region doped with a first conductivity type impurity, and the second well region PW is a region doped with a second conductivity type impurity, where the first conductivity type is n-type and the second conductivity type is p-type, but is not limited thereto.

[0064] Referring to FIG. 6, nanosheets NS and sacrificial insulating patterns 110S may be alternately stacked on the upper surface of a substrate 101 in a vertical direction (Z direction).

[0065] Each nanosheet NS may also be a semiconductor pattern. In some embodiments, the nanosheets NS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 spaced apart in the vertical direction (Z direction).

[0066] A sacrificial insulating pattern 110S may be formed between the nanosheets NS. In some embodiments, the length of the nanosheets NS along the first horizontal direction (X direction) and the length of the sacrificial insulating pattern 110S along the first horizontal direction (X direction) may be formed to be substantially the same.

[0067] Referring to FIG. 7, the nanosheet NS and a portion of the sacrificial insulating pattern 110S may be etched to form a pair of isolation layers STI on the exposed upper surface of the substrate 101.

[0068] The isolation film STI is also a shallow isolation film extending from the top surface of the substrate 101 to the inside of the first well region NW and the second well region PW. The isolation film STI may be formed to have a double-layer structure of an interface layer (not shown) and a buried insulating layer (not shown).

[0069] Referring to FIG. 8, a sacrificial material layer 130S surrounding both ends of the nanosheet NS and the sacrificial insulating pattern 110S, and a gate spacer 120 surrounding the sacrificial material layer 130S may be formed.

[0070] In some embodiments, the sacrificial material film 130S may be formed of, but is not limited to, polysilicon, and in some embodiments, the gate spacer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

[0071] Referring to FIG. 9, impurities of different conductivity types can be implanted into the nanosheet NS and the sacrificial insulating pattern 110S through two ion implantation processes IIP.

[0072] First, the nanosheet NS, the sacrificial insulating pattern 110S, and the first well region NW may be implanted with impurities of the same conductivity type as the first well region NW (e.g., n-type impurities), and then the nanosheet NS, the sacrificial insulating pattern 110S, and the second well region PW may be implanted with impurities of the same conductivity type as the second well region PW (e.g., p-type impurities).

[0073] The photomask (not shown) process for the ion implantation process IIP is obvious to those skilled in the art, so a detailed description thereof will be omitted here.

[0074] Referring to FIG. 10, the first impurity conductive portion NC and the second impurity conductive portion PC may be formed by a heat treatment process using the implanted impurities of different conductivity types.

[0075] Accordingly, the first impurity conductive portion NC and the second impurity conductive portion PC may serve to electrically connect the first well region NW and the second well region PW to the contact CT.

[0076] In some embodiments, the vertical level of the top surfaces of the first impurity conductive portion NC and the second impurity conductive portion PC may be substantially the same as the vertical level of the top surface of the third nanosheet N3, and the vertical level of the bottom surfaces of the first impurity conductive portion NC and the second impurity conductive portion PC may be located inside the substrate 101.

[0077] The sacrificial material film 130S (see FIG. 9) may then be removed, and the gate electrode 130 may be formed in the location where the sacrificial material film 130S (see FIG. 9) was removed. In some embodiments, the gate electrode 130 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof.

[0078] This allows the formation of a pair of gate structures GS that surround both ends of the nanosheet NS and the sacrificial insulating pattern 110S, respectively.

[0079] Referring to FIG. 11, an inter-gate insulating layer 140 may be formed to cover the pair of gate structures GS and nanosheets NS.

[0080] In some embodiments, the inter-gate insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

[0081] Referring to FIG. 12, contact holes 140H may be formed to expose the first impurity conductive portion NC and the second impurity conductive portion PC.

[0082] In some embodiments, a contact hole 140H may be formed by etching a portion of the uppermost layer of the inter-gate insulating layer 140, the third nanosheet N3, and the sacrificial insulating pattern 110S through a photolithography and etching process.

[0083] In another embodiment, the contact hole 140H may be formed by etching a portion of the inter-gate insulating layer 140 and the third nanosheet N3 through a photolithography and etching process. That is, unlike the illustrated example, the bottom surface of the contact hole 140H may be located inside the third nanosheet N3.

[0084] Referring to FIG. 13, a contact CT may be formed to fill the contact hole 140H (see FIG. 12).

[0085] The contact CT may include a first contact electrically connected to the first impurity conductive portion NC and a second contact electrically connected to the second impurity conductive portion PC, and the contact CT may be disposed between a pair of gate structures GS in a first horizontal direction (X direction).

[0086] In some embodiments, each contact CT may have a double-layer structure including a metal buried layer 154 and a metal barrier film 152 surrounding the side and bottom surfaces of the metal buried layer 154. That is, the metal barrier film 152 may be disposed first so as to contact the third nanosheet N3 and a portion of the sacrificial insulating pattern 110S, and then the metal buried layer 154 may be disposed so as to cover the metal barrier film 152. In other embodiments, the metal barrier film 152 may be omitted, and the contact CT may have a layered structure of the metal buried layer 154.

[0087] Referring to FIG. 14, a bottom removal process may be performed to reduce the thickness of the substrate 101.

[0088] The underside removal process for reducing the thickness of the substrate 101 may include a process of exposing bottom surfaces of a pair of device isolation layers STI by alternately performing a grinding process and a wet etching process, so that after portions of the substrate 101 are removed, the underside of the substrate 101 is substantially flush with the undersides of the first well region NW and the second well region PW.

[0089] Also, referring to FIG. 1B, a backside power wiring structure BSPDN may be further formed on the underside of the substrate 101, and a connection structure such as a via contact for connecting the backside power wiring structure BSPDN to a lateral diode and / or nanosheet field effect transistor may be further formed.

[0090] Through the above-described manufacturing method, the semiconductor device 10 according to the technical idea of ​​the present invention has the effect of providing stable performance and improved reliability by using the first impurity conductive portion NC and the second impurity conductive portion PC in a lateral PN junction diode having a structure similar to that of a nanosheet field effect transistor.

[0091] 15 to 23 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the technical concept of the present invention.

[0092] Referring to FIG. 15, a substrate 101 having a first surface and a second surface facing each other can be prepared.

[0093] The substrate 101 may have a first surface corresponding to the top surface (or active surface) and a second surface corresponding to the bottom surface (or non-active surface).

[0094] Next, nanosheets NS and sacrificial insulating patterns 110S can be formed on the upper surface of the substrate 101 by alternately stacking them in the vertical direction (Z direction).

[0095] Each nanosheet NS may also be a semiconductor pattern. In some embodiments, the nanosheets NS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 spaced apart in the vertical direction (Z direction).

[0096] A sacrificial insulating pattern 110S may be formed between the nanosheets NS. In some embodiments, the length of the nanosheets NS along the first horizontal direction (X direction) and the length of the sacrificial insulating pattern 110S along the first horizontal direction (X direction) may be formed to be substantially the same.

[0097] Referring to FIG. 16, a pair of isolation layers STI may be formed on the exposed upper surface of the substrate 101 by etching a portion of the nanosheet NS and the sacrificial insulating pattern 110S.

[0098] The STI element isolation film is also a shallow element isolation film that extends from the upper surface of the substrate 101 to the interior of the substrate 101. The STI element isolation film may be formed to have a double-layer structure of an interface layer (not shown) and a buried insulating layer (not shown).

[0099] Referring to FIG. 17, a sacrificial material layer 130S surrounding both ends of the nanosheet NS and the sacrificial insulating pattern 110S, and a gate spacer 120 surrounding the sacrificial material layer 130S may be formed.

[0100] In some embodiments, the sacrificial material film 130S may be formed of, but is not limited to, polysilicon, and in some embodiments, the gate spacer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

[0101] Referring to FIG. 18, impurities of different conductivity types may be implanted into the nanosheet NS, the sacrificial insulating pattern 110S, and the substrate 101 through two ion implantation processes IIP.

[0102] First, a first conductivity type impurity (e.g., n-type impurity) may be implanted into the nanosheet NS, the sacrificial insulating pattern 110S, and a portion of the substrate 101. Then, a second conductivity type impurity (e.g., p-type impurity) may be implanted into another portion of the nanosheet NS, the sacrificial insulating pattern 110S, and the substrate 101.

[0103] The photomask (not shown) process for the ion implantation process IIP is obvious to those skilled in the art, so a detailed description thereof will be omitted here.

[0104] Referring to FIG. 19, a first impurity region NC2 and a second impurity region PC2 may be formed by a heat treatment process using the implanted impurities of different conductivity types.

[0105] In some embodiments, the vertical level of the top surfaces of the first impurity region NC2 and the second impurity region PC2 may be substantially the same as the vertical level of the top surface of the third nanosheet N3, and the vertical level of the bottom surfaces of the first impurity region NC2 and the second impurity region PC2 may be located within the substrate 101.

[0106] The sacrificial material film 130S (see FIG. 18) may then be removed, and the gate electrode 130 may be formed in the location where the sacrificial material film 130S (see FIG. 18) was removed. In some embodiments, the gate electrode 130 may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof.

[0107] This allows the formation of a pair of gate structures GS surrounding both ends of the nanosheet NS and the sacrificial insulating pattern 110S, respectively.

[0108] Referring to FIG. 20, an inter-gate insulating layer 140 may be formed to cover the pair of gate structures GS and nanosheets NS.

[0109] In some embodiments, the inter-gate insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

[0110] Referring to FIG. 21, a contact hole 140H may be formed to expose the first impurity region NC2 and the second impurity region PC2.

[0111] In some embodiments, a contact hole 140H may be formed by etching a portion of the uppermost layer of the inter-gate insulating layer 140, the third nanosheet N3, and the sacrificial insulating pattern 110S through a photolithography and etching process.

[0112] In another embodiment, the contact hole 140H may be formed by etching a portion of the inter-gate insulating layer 140 and the third nanosheet N3 through a photolithography and etching process. That is, unlike the illustrated example, the bottom surface of the contact hole 140H may be located inside the third nanosheet N3.

[0113] Referring to FIG. 22, a contact CT may be formed to fill the contact hole 140H (see FIG. 21).

[0114] The contact CT may include a first contact electrically connected to the first impurity region NC2 and a second contact electrically connected to the second impurity region PC2. Here, the contact CT may be disposed between a pair of gate structures GS in a first horizontal direction (X direction).

[0115] In some embodiments, each contact CT may have a double-layer structure including a metal buried layer 154 and a metal barrier film 152 surrounding the side and bottom surfaces of the metal buried layer 154. That is, the metal barrier film 152 may be disposed first so as to contact the third nanosheet N3 and a portion of the sacrificial insulating pattern 110S, and then the metal buried layer 154 may be disposed so as to cover the metal barrier film 152. In other embodiments, the metal barrier film 152 may be omitted, and the contact CT may have a layered structure of the metal buried layer 154.

[0116] Referring to FIG. 23, a bottom removal process may be performed to reduce the thickness of the substrate 101.

[0117] The bottom surface removal process for reducing the thickness of the substrate 101 may include a process of exposing bottom surfaces of a pair of device isolation layers STI by alternately performing a grinding process and a wet etching process. Thus, after portions of the substrate 101 are removed, the bottom surface of the substrate 101 is substantially flush with the bottom surfaces of the first impurity region NC2 and the second impurity region PC2.

[0118] Referring again to FIG. 2B, a backside power wiring structure BSPDN may be further formed on the underside of the substrate 101, and a connection structure such as a via contact for connecting the backside power wiring structure BSPDN to a lateral diode and / or nanosheet field effect transistor may be further formed.

[0119] Through the above-described manufacturing method, the semiconductor device 20 according to the technical idea of ​​the present invention has the effect of providing stable performance and improved reliability by using the first impurity region NC2 and the second impurity region PC2 in a lateral PN junction diode having a structure similar to that of a nanosheet field effect transistor.

[0120] FIG. 24 is a block diagram illustrating a system including a semiconductor device according to an embodiment of the inventive concept.

[0121] Referring to FIG. 24, the system 1000 includes a controller 1010 , an input / output device 1020 , a storage device 1030 , an interface 1040 , and a bus 1050 .

[0122] System 1000 may also be a mobile system or a system that transmits or transmits information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0123] The controller 1010 controls the execution of programs in the system 1000 and may be a microprocessor, digital signal processor, microcontroller, or similar device.

[0124] The input / output device 1020 can be used to input or output data to or from the system 1000. The system 1000 can be connected to an external device, such as a personal computer or a network, and exchange data with the external device using the input / output device 1020. The input / output device 1020 can be, for example, a touch screen, a touch pad, a keyboard, or a display.

[0125] The memory device 1030 may store data for the operation of the controller 1010 or store data processed by the controller 1010. The memory device 1030 may include any one of the semiconductor devices 10, 20, 30, 40, and 50 according to the technical concept of the present invention described above.

[0126] The interface 1040 is also a data transmission path between the system 1000 and external devices. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 can communicate with each other via a bus 1050.

[0127] Although the embodiments of the technical concept of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0128] 10, 20, 30, 40, 50 semiconductor elements 101 Substrate 110S Sacrificial Insulation Pattern 120 Gate spacer 130 gate electrode 140 Gate-to-gate insulating layer 152 Metal Barrier Film 154 Metal Buried Layer STI device isolation membrane NW First well region PW Second well region NC First impurity conductive part PC Second impurity conductive part NS nanosheet GS Gate Structure CT Contact

Claims

1. a substrate having a first surface and a second surface facing each other, and a pair of element isolation films penetrating the substrate; a first well region and a second well region disposed along a first horizontal direction in the substrate between the pair of device isolation films and in contact with each other; nanosheets and sacrificial insulating patterns alternately stacked vertically on the first well region and the second well region; a pair of inactive gate structures extending from both ends of the nanosheet and the sacrificial insulating pattern in a second horizontal direction perpendicular to the first horizontal direction and surrounding both ends of the nanosheet and the sacrificial insulating pattern, respectively; a first impurity conductive portion that penetrates the nanosheet and the sacrificial insulating pattern in the vertical direction on the first well region and is connected to the first well region; a second impurity conductive portion that penetrates the nanosheet and the sacrificial insulating pattern in the vertical direction on the second well region and is connected to the second well region; a first contact connected to an upper portion of the first impurity conductive portion; a second contact connected to an upper portion of the second impurity conductive portion; Semiconductor element.

2. no inactive gate structure is disposed on an interface where the first well region and the second well region contact each other in the first horizontal direction; 2. The semiconductor device according to claim 1 .

3. the first contact and the second contact are disposed between the pair of inactive gate structures in the first horizontal direction; 3. The semiconductor device according to claim 2.

4. the first impurity conductive portion and the second impurity conductive portion are regions in which the nanosheet and the sacrificial insulating pattern are doped with different conductivity type impurities; 2. The semiconductor device according to claim 1 .

5. the nanosheet located between the first impurity conductive portion and the second impurity conductive portion is a semiconductor pattern, and the sacrificial insulating pattern is an insulating pattern; 5. The semiconductor device according to claim 4.

6. a vertical level of the top surfaces of the first impurity conductive portion and the second impurity conductive portion is substantially the same as a vertical level of the top surface of the top semiconductor pattern of the nanosheet; a vertical level of the bottom surfaces of the first impurity conductive portion and the second impurity conductive portion is located between the first surface and the second surface of the substrate; 5. The semiconductor device according to claim 4.

7. a length of the nanosheet along the first horizontal direction and a length of the sacrificial insulating pattern along the first horizontal direction are substantially the same; 2. The semiconductor device according to claim 1 .

8. the first well region and the second well region are regions in which the substrate is doped with impurities of different conductivity types; the first well region and the second well region are in contact with each other to form a lateral diode; 2. The semiconductor device according to claim 1 .

9. the vertical level of the top surfaces of the first well region and the second well region is substantially the same as the first surface of the substrate; the vertical level of the bottom surfaces of the first well region and the second well region is substantially the same as the second surface of the substrate; 9. The semiconductor device according to claim 8.

10. the first impurity conductive portion and the first well region contain the same first conductivity type impurities; the second impurity conductive portion and the second well region contain the same second conductivity type impurities, the first conductivity type impurity and the second conductivity type impurity have opposite conductivity types; 2. The semiconductor device according to claim 1 .

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