Semiconductor device and manufacturing method of the same

Abstract

To provide a semiconductor device capable of shortening a lead terminal and a manufacturing method of the same.SOLUTION: A package 20 included in a semiconductor device of an embodiment includes: an upper surface 20a provided above a semiconductor chip 30; a lower surface 20b provided below the semiconductor chip; a side surface 20c from which a lead terminal protrudes; and a side surface 20f from which the lead terminal does not protrude. The side surface 20c has a first surface 20ca, a second surface 20cb, and a third surface 20cc. The first surface 20ca is continuous with the upper surface 20a of the package and is provided in an oblique direction with respect to the upper surface 20a of the package. The second surface 20cb is continuous with the first surface 20ca and is provided in a direction parallel to the upper surface 20a of the package. The third surface 20cc is continuous with the second surface 20cb and is provided in a direction orthogonal to the upper surface 20a of the package. A second side surface 20f is provided in an oblique direction with respect to the upper surface 20a of the package.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices including semiconductor packages with semiconductor chips mounted thereon are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-163325 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of shortening lead terminals and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip disposed above the lead frame, first lead terminals electrically connected to the semiconductor chip, and a package containing the semiconductor chip, a portion of the lead frame, and a portion of the first lead terminals. The package has a top surface disposed above the semiconductor chip, a bottom surface disposed below the semiconductor chip, a first side surface disposed between the top surface and the bottom surface and from which the first lead terminals protrude, and a second side surface disposed between the top surface and the bottom surface and from which the first lead terminals do not protrude. The first side surface has a first surface, a second surface, and a third surface, the first surface being continuous with the top surface of the package and extending obliquely relative to the top surface of the package, the second surface being continuous with the first surface and extending parallel to the top surface of the package, the third surface being continuous with the second surface and extending perpendicular to the top surface of the package, and the second side surface being extending obliquely relative to the top surface of the package. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a perspective view showing the outer shape of a semiconductor device according to an embodiment; [Figure 2] 1 is a top view of a semiconductor device according to an embodiment; [Figure 3] 1 is a first side view of a semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a second side view of the semiconductor device according to the embodiment. [Figure 5] 4 is an enlarged view of a portion A in the semiconductor device shown in FIG. [Figure 6] 5 is an enlarged view of a portion B in the semiconductor device shown in FIG. [Figure 7] FIG. 2 is a top view showing the structure inside the package of the semiconductor device according to the embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII of the semiconductor device shown in FIG. 7. [Figure 9] 9 is a cross-sectional view taken along line IX-IX of the semiconductor device shown in FIG. 7. [Figure 10] 8 is a cross-sectional view of the semiconductor device shown in FIG. 7 taken along line XX. [Figure 11] 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1 is a plan view of a lead frame prepared in a manufacturing process of a semiconductor device according to an embodiment; [Figure 13] 1A and 1B are a top view and a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment. [Figure 14] 1A and 1B are a top view and a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment. [Figure 15] 1A and 1B are a top view and a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment. [Figure 16] 1A and 1B are a top view and a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment. [Figure 17] 1A and 1B are a top view and a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment. [Figure 18] 1A and 1B are a top view and a cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment. [Figure 19] 1A and 1B are diagrams illustrating the layout of a part of a mold in a manufacturing process of a semiconductor device according to an embodiment. [Figure 20] 1 is a diagram showing dimensions of a package and lead terminals in a semiconductor device according to an embodiment; [Figure 21] 1 is a diagram showing dimensions of a package and lead terminals in a semiconductor device according to an embodiment; [Figure 22] FIG. 10 is a first side view of a semiconductor device according to a modified example of the embodiment. [Figure 23] FIG. 10 is a second side view of the semiconductor device according to the modified example of the embodiment. [Figure 24] 24 is an enlarged view of a portion C in the semiconductor device shown in FIG. 23. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numerals. Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0008] 1. Embodiment 1.1 Configuration of semiconductor device A semiconductor device 1 according to an embodiment will now be described. Fig. 1 is a perspective view showing the external shape of the semiconductor device 1 according to the embodiment. In Fig. 1 and the subsequent figures, the direction parallel to the top surface of the package 20 is referred to as the X direction, the direction parallel to the top surface of the package 20 and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the top surface of the package 20 (or the XY plane) is referred to as the Z direction.

[0009] The semiconductor device 1 includes a semiconductor package, such as a surface-mount SOP (Small Outline Package) that can be mounted on the mounting surface of a printed circuit board. The semiconductor device 1 includes a lead terminal (or a lead frame) 10, a package 20, and a semiconductor chip (or a semiconductor element) 30.

[0010] The lead terminals 10 are electrically connected to electrodes of the semiconductor chip 30. The lead terminals 10 are also terminals for connecting to the outside, for example, to a circuit provided on a printed circuit board. The lead terminals 10 may be part of a lead frame protruding from the package 20.

[0011] The package 20 includes the semiconductor chip 30, some of the lead terminals 10, and some of the lead frame. That is, the package 20 seals the semiconductor chip 30, some of the lead terminals 10, and some of the lead frame. The package 20 protects the semiconductor chip 30 from the external environment and also fixes the lead terminals 10, the lead frame, and the semiconductor chip 30.

[0012] The semiconductor chip 30 includes, for example, a MOS field effect transistor, and has a source, a drain, and a gate.

[0013] Next, the external shape of the semiconductor device 1 according to the embodiment will be described in detail. Fig. 2 is a top view of the semiconductor device 1 according to the embodiment. Fig. 3 is a first side view of the semiconductor device 1, and Fig. 4 is a second side view of the semiconductor device 1. Fig. 2 is a view of the semiconductor device 1 as seen in the Z direction, i.e., from above (or the top surface of) the package 20. Fig. 3 is a view of the semiconductor device 1 as seen in the X direction, and Fig. 4 is a view of the semiconductor device 1 as seen in the Y direction.

[0014] As shown in FIGS. 2, 3 and 4, the package 20 of the semiconductor device 1 has, for example, a substantially hexahedral shape and has an upper surface 20a, a lower surface 20b and four side surfaces 20c, 20d, 20e and 20f.

[0015] An upper surface 20a of the package 20 is provided above the semiconductor chip 30. A lower surface 20b of the package 20 is provided below the semiconductor chip 30. The upper surface 20a and the lower surface 20b are perpendicular to the Z direction and face each other.

[0016] The side surfaces 20c and 20d of the package 20 are provided between the top surface 20a and the bottom surface 20b. The side surfaces 20c and 20d are perpendicular to the Y direction, in other words, aligned along the X direction. The side surfaces 20c and 20d face each other. As shown in FIGS. 2 and 3, lead terminals 10 protrude from the side surfaces 20c and 20d. Burrs 20g, which are part of the package 20, are provided on the portions of the side surfaces 20c and 20d from which the lead terminals 10 do not protrude.

[0017] A plurality of lead terminals 10 and burrs 20g are provided on the side surface 20c. The lead terminals 10 are arranged at predetermined intervals in the X direction. The burrs 20g are provided adjacent to the lead terminals 10 on the side surface 20c. Furthermore, the burrs 20g are provided between the lead terminals 10.

[0018] Similarly, a plurality of lead terminals 10 and burrs 20g are provided on the side surface 20d. The lead terminals 10 are arranged at predetermined intervals in the X direction. The burrs 20g are provided adjacent to the lead terminals 10 on the side surface 20d and are also provided between the lead terminals 10.

[0019] The side surfaces 20e and 20f of the package 20 are provided between the top surface 20a and the bottom surface 20b. The side surfaces 20e and 20f are perpendicular to the X direction, in other words, aligned along the Y direction. The side surfaces 20e and 20f face each other. As shown in FIGS. 2 and 4, no lead terminals 10 protrude from the side surfaces 20e and 20f, and no burrs 20g are provided.

[0020] Next, details of the side surfaces 20c, 20d, 20e, and 20f of the package 20 will be described. Fig. 5 is an enlarged view of portion A in the semiconductor device 1 shown in Fig. 3, showing the detailed structure of the side surface 20c. Note that the structure of the side surface 20d is the same as that of the side surface 20c, and therefore will not be described here.

[0021] As described above, the lead terminal 10 protrudes from the side surface 20c of the package 20. Burrs 20g protrude from the side surface 20c on both sides of the lead terminal 10. The burrs 20g protrude from the side surface 20c and are provided adjacent to the lead terminal 10.

[0022] The side surface 20c of the package 20 has a surface 20ca, a surface 20cb, and a surface 20cc. The surface 20ca is continuous with the top surface 20a of the package 20 and is provided in a direction oblique to the top surface 20a of the package 20. The surface 20cb is continuous with the surface 20ca and is provided in a direction parallel to the top surface 20a of the package 20. The surface 20cc is continuous with the surface 20cb and is provided in a direction perpendicular to the top surface 20a of the package 20. The surface 20cb is the top surface of the burr 20g, and the surface 20cc is a side surface of the burr 20g. Furthermore, for example, the bottom surface 20b of the package 20 is substantially common to the bottom surface of the burr 20g.

[0023] In the Z direction, the position of the upper surface 20cb of the burr 20g coincides with the position of the upper surface of the lead terminal 10. In other words, the distance from the lower surface 20b of the package 20 to the upper surface 20cb of the burr 20g coincides with the distance from the lower surface 20b of the package 20 to the upper surface of the lead terminal 10. In the Z direction, the position of the lower surface 20b of the burr 20g coincides with the position of the lower surface of the lead terminal 10.

[0024] Fig. 6 is an enlarged view of portion B in the semiconductor device 1 shown in Fig. 4, showing the detailed structure of the side surface 20f. Note that the structure of the side surface 20e is the same as that of the side surface 20f, and therefore will not be described again.

[0025] As described above, the lead terminals 10 do not protrude from the side surface 20f of the package 20. Furthermore, the side surface 20f of the package 20 does not have any burrs 20g.

[0026] The side surface 20f of the package 20 is provided obliquely with respect to the top surface 20a of the package 20.

[0027] Next, the structure inside the package 20 of the semiconductor device 1 according to the embodiment will be described. FIG. 7 is a top view showing the structure inside the package 20 of the semiconductor device 1 according to the embodiment. FIG. 8 is a cross-sectional view of the semiconductor device 1 shown in FIG. 7 taken along line VIII-VIII. FIG. 9 is a cross-sectional view of the semiconductor device 1 shown in FIG. 7 taken along line IX-IX. FIG. 10 is a cross-sectional view of the semiconductor device 1 taken along line XX. FIG. 7 is a perspective view of the package 20 from above the semiconductor device 1 (i.e., in the Z direction). In FIG. 7, the package 20 is indicated by a dashed line. In addition, in FIGS. 7, 8, and 9, the lead terminals 10 are represented by 10a, 10b, and 10c according to the positions at which the lead terminals 10 are provided.

[0028] As shown in Figures 7 to 10, the semiconductor device 1 includes a lead frame 10 including a lead terminal 10a, a lead terminal 10b, a lead terminal 10c, a conductive layer 11, a conductive layer 12, a package 20, a semiconductor chip 30, a drain electrode layer 30a, a source electrode layer 30b, a gate electrode layer 30c, a bonding layer 31a, a bonding layer 31b, a bonding layer 31c, a bonding layer 32, and a bonding layer 33.

[0029] As shown in FIGS. 7 and 8, a bonding layer 31a is provided on the lead frame 10. A drain electrode layer 30a is provided on the bonding layer 31a. A semiconductor chip 30 is provided on the drain electrode layer 30a. A source electrode layer 30b is provided on the semiconductor chip 30. A bonding layer 31b is provided on the source electrode layer 30b. A bonding layer 32 is provided on the lead terminal 10b. Furthermore, a conductor layer 11 is provided on the bonding layers 31b and 32.

[0030] 7 and 9, a gate electrode layer 30c is provided on the semiconductor chip 30. A bonding layer 31c is provided on the gate electrode layer 30c. A bonding layer 33 is provided on the lead terminal 10c. Furthermore, a conductor layer 12 is provided on the bonding layers 31c and 33.

[0031] That is, as shown in FIGS. 7 to 10, a semiconductor chip 30 is provided on a lead frame 10 via a bonding layer 31a and a drain electrode layer 30a. A conductor layer 11 is provided on the semiconductor chip 30 via a source electrode layer 30b and a bonding layer 31b. A part of the conductor layer 11 is provided on a lead terminal 10b via a bonding layer 32. A conductor layer 12 is provided on the semiconductor chip 30 via a gate electrode layer 30c and a bonding layer 31c. A part of the conductor layer 12 is provided on a lead terminal 10c via a bonding layer 33.

[0032] The lead terminals 10a, 10b, and 10c of the semiconductor device 1 having the above structure are connected to the semiconductor chip 30 as follows.

[0033] The semiconductor chip 30 includes, for example, a MOS field effect transistor, and has a drain, a source, and a gate.

[0034] The lead terminal 10a is electrically connected to the drain of the semiconductor chip 30 via the bonding layer 31a and the drain electrode layer 30a. The lead terminal 10b is electrically connected to the source of the semiconductor chip 30 via the bonding layer 32, the conductor layer 11, the bonding layer 31b, and the source electrode layer 30b. Furthermore, the lead terminal 10c is electrically connected to the gate of the semiconductor chip 30 via the bonding layer 33, the conductor layer 12, the bonding layer 31c, and the gate electrode layer 30c.

[0035] Next, materials of the members constituting the semiconductor device 1 of the embodiment will be described.

[0036] The lead terminal (and lead frame) 10 includes a conductive material, for example, a metal such as copper or aluminum. The conductive layers 11 and 12 include a conductive material, for example, a metal such as copper or aluminum. The package 20 includes an insulator, for example, an insulating resin or ceramics. The burr 20g is a part of the package 20, and like the package 20, includes an insulator, for example, an insulating resin or ceramics. The thickness of the burr 20g is the same as the thickness of the lead terminal (or lead frame) 10. In other words, the thickness of the burr 20g in the Z direction is approximately the same as the thickness of the lead terminal (or lead frame) 10 in the Z direction.

[0037] The semiconductor chip 30 includes, for example, a MOS field effect transistor or an IGBT (Insulated Gate Bipolar Transistor). The semiconductor chip 30 includes, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) as a semiconductor material.

[0038] The drain electrode layer 30a, the source electrode layer 30b, and the gate electrode layer 30c include a metal such as aluminum, and the bonding layers 31a, 31b, 31c, 32, and 33 include a metal such as copper, silver, or tin.

[0039] 1.2 Semiconductor device manufacturing method Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Fig. 11 is a flowchart showing a method for manufacturing the semiconductor device 1 according to the embodiment. Fig. 12 is a plan view of a lead frame prepared in the manufacturing process of the semiconductor device 1. Figs. 13 to 18 are top views and cross-sectional views of the manufacturing process of the semiconductor device 1. The view shown in Fig. 12 is a view of the lead frame 100 as seen from above (i.e., in the Z direction). In Figs. 13 to 18, (a) shows a view of the lead frame 100 as seen from above, and (b) shows a cross section taken along line VIII-VIII in (a).

[0040] In the manufacturing process of the semiconductor device 1, a lead frame 100 as shown in FIG. 12 is prepared. The lead frame 100 is shown in a state before the semiconductor chip 30 is bonded thereto. The lead frame 100 has portions 100a, 100b, and 100c that become lead terminals, a portion 100d to which the semiconductor chip 30 is bonded, and portions 100e and 100f to which the conductive layers 11 and 12 are bonded. Note that FIG. 12 shows one lead frame 100 to which one semiconductor chip 30 is bonded, but in the manufacturing process, for example, a rectangular frame in which multiple lead frames 100 are arranged is prepared. Then, multiple semiconductor chips 30 are bonded to the multiple lead frames 100, respectively, and multiple semiconductor devices 1 are manufactured through other processes. The multiple semiconductor devices 1 are then cut into individual semiconductor devices 1.

[0041] The semiconductor device 1 is manufactured, for example, by the following steps.

[0042] 11 and 13, the semiconductor chip 30 is bonded (or placed) on the lead frame 100 (S1). Specifically, a bonding layer 31a and a drain electrode layer 30a are formed on the lead frame 100. Furthermore, the semiconductor chip 30 is bonded onto the drain electrode layer 30a. As a result, the semiconductor chip 30 is fixed onto the portion 100d of the lead frame 100. The drain of the semiconductor chip 30 is electrically connected to the portion 100d of the lead frame 100 via the drain electrode layer 30a and the bonding layer 31a.

[0043] Next, as shown in FIGS. 11 and 14, conductive layers 11 and 12 are bonded above the semiconductor chip 30 and above the lead frame 100 (S2). Specifically, a source electrode layer 30b and a bonding layer 31b, and a gate electrode layer 30c and a bonding layer 31c are formed on the semiconductor chip 30. Bonding layers 32 and 33 are formed on the lead frame 100. Furthermore, a conductive layer 11 is bonded on the bonding layers 31b and 32. Simultaneously or subsequently, a conductive layer 12 is bonded on the bonding layers 31c and 33. As a result, the conductive layers 11 and 12 are fixed on the semiconductor chip 30 and on portions 100e and 100f of the lead frame 100. The source of the semiconductor chip 30 is electrically connected to portion 100e of the lead frame 100 via the source electrode layer 30b, the bonding layer 31b, and the conductive layer 11. The gate of the semiconductor chip 30 is electrically connected to the portion 100f of the lead frame 100 via the gate electrode layer 30c, the bonding layer 31c, and the conductive layer 12.

[0044] 11 and 15, a package 20 is then formed around the semiconductor chip 30 on the lead frame 100 and around the conductive layers 11 and 12 (S3). As a result, the semiconductor chip 30 and the conductive layers 11 and 12 on the lead frame 100 are sealed with the package 20.

[0045] In the process of forming the package 20, for example, a resin sealing process is used in which the package 20 is formed by resin molding using a mold, and the semiconductor chip 30 and the conductor layers 11 and 12 are sealed with the package 20. Fig. 19 shows the arrangement of part of the mold in the resin sealing process.

[0046] The lead frame 100, the semiconductor chip 30, and the conductive layers 11 and 12 are sandwiched between two molds from above and below the lead frame 100, i.e., from the Z direction. Hereinafter, the lower mold will be referred to as the lower mold, and the upper mold will be referred to as the upper mold.

[0047] The lead frame 100, the semiconductor chip 30, and the conductive layers 11 and 12 are sandwiched between the lower and upper molds to form a cavity containing the lead frame 100, the semiconductor chip 30, and the conductive layers 11 and 12. Molten resin is poured into this cavity and solidified to form the package 20.

[0048] Here, as shown in FIG. 19 , for example, a portion (hereinafter, referred to as a lead guide) 40a of the lower mold (or upper mold) is provided on the side surfaces 20e and 20f of the package 20 in the X direction. The side surfaces 20e and 20f of the package 20 are surfaces from which the lead terminals 10 do not protrude. Because the lead guides 40a are provided on the side surfaces 20e and 20f, no burrs 20g are formed on the side surfaces 20e and 20f. The burrs 20g are part of the resin forming the package 20, and are formed by molding the resin so as to protrude from between the lower mold and the upper mold when the package 20 is molded. As described above, because the lead guides 40a are arranged on the side surfaces 20e and 20f, the resin does not protrude from between the lower mold and the upper mold, and no burrs are formed.

[0049] On the other hand, no lead guides are provided on the side surfaces 20c and 20d of the package 20 in the Y direction. The side surfaces 20c and 20d of the package 20 in the Y direction are surfaces from which the lead terminals 10 protrude. Since no lead guides are provided on the side surfaces 20c and 20d, burrs 20g are formed on the side surfaces 20c and 20d. Note that the portion 40b where no lead guides exist represents an opening through which resin flows when the package 20 is molded.

[0050] 11 and 16, burrs 20g formed on the side surfaces 20c and 20d of the package 20 in the Y direction are removed, for example, by a laser (S4). In this process, it is not possible to remove all the burrs from the side surfaces 20c and 20d of the package 20, and some burrs 20g remain.

[0051] 11 and 17, plating is then applied to the lead frame 100 that will become the lead terminal 10 (S5). Plating materials include, for example, metals such as silver, gold, nickel, and palladium.

[0052] 11 and 18, the plurality of continuous lead frames 100 are cut and separated into individual semiconductor devices 1 (S6). This completes the manufacturing process for the semiconductor device 1.

[0053] Next, dimensions of specific parts of the semiconductor device 1 of the embodiment will be described.

[0054] FIG. 20 is a top view of the semiconductor device 1 according to the embodiment, showing the dimensions of the package 20 and the lead terminals 10c.

[0055] The lead terminals 10 protrude from a side surface 20d of the package 20. Furthermore, burrs 20g are provided on parts of the side surface 20d where the lead terminals 10 do not protrude, i.e., between the lead terminals 10 and on both sides of the lead terminals 10 in the X direction.

[0056] The distance required between the end of the side surface 20d and the end of the lead terminal 10 to ensure the strength of the mold varies depending on the thickness of the lead terminal (or lead frame) 10 in the Z direction. When the thickness of the lead terminal 10 is thick, the distance needs to be longer, and when the thickness of the lead terminal 10 is thin, the distance can be shorter.

[0057] For example, if the thickness of the lead terminal 10 is 0.25 mm, as shown in FIG. 20, the distance between the end of the side surface 20d and the end of the lead terminal 10 can be set to 0.4 mm or less. This allows the length of the lead terminal 10 to be shortened. Note that if the thickness of the lead terminal is thicker than 0.25 mm, there is little demand for shortening the length of the lead terminal 10, and in many cases, priority is given to lengthening the lead terminal 10 to improve current-carrying capacity. Note that region 40c indicates the region that is punched out with a die to separate the lead terminals 10. The distance between the side surface 20c of the package 20 and the lead terminals 10 is also the same as described above.

[0058] 21 is a view of a portion of the semiconductor device 1 according to the embodiment viewed from below (i.e., the underside of the package 20), showing the dimensions of the package 20 and the lead terminals 10b. Fig. 21 is a see-through view of the package 20, showing the lead frame including the lead terminals 10b and the side surface 20d of the package 20 including the burrs 20g.

[0059] For example, if the thickness of the lead terminal (or lead frame) 10b in the Z direction is 0.25 mm, the distance between the end of the package 20 (or the end of the side surface 20d) and the end of the lead frame inside the package 20 is set to 0.2 mm or more, as shown in Fig. 21. Setting the distance to 0.2 mm or more makes it easy to fill the end of the lead frame with resin.

[0060] As described above, according to the embodiment, lead guides (i.e., parts of the mold) are not provided on the side surfaces 20c and 20d of the package 20 in the Y direction (i.e., the side surfaces from which the lead terminals 10 protrude), but are provided on the side surfaces 20e and 20f of the package 20 in the X direction (i.e., the side surfaces from which the lead terminals 10 do not protrude). This makes it possible to shorten the lead terminals 10 provided on the side surfaces 20c and 20d in the Y direction, i.e., to shorten the length from the side surface of the package 20 to the tip of the lead terminal 10. Furthermore, burrs provided on the side surfaces 20e and 20f of the package 20 can be reduced.

[0061] For example, when forming the package 20 with lead guides, the lead guides must be set to a certain size or larger to ensure their strength. Therefore, the size of the lead guide determines the minimum length of the lead terminals. However, when forming the package 20 without lead guides, there is no need to reserve an area for providing the lead guides, so the length of the lead terminals 10 can be shortened.

[0062] Furthermore, in the embodiment, the lead guides are provided on the side surfaces 20e and 20f from which the lead terminals 10 do not protrude, which reduces burrs formed on the side surfaces 20e and 20f of the package 20. This reduces the number of steps required to remove burrs in the manufacturing process.

[0063] Furthermore, in the embodiment, since no lead guides are provided on the side surfaces 20c and 20d from which the lead terminals 10 protrude, the package 20 can be formed even when the distance between the lead terminals is narrow. That is, the package 20 can be formed even when the product specifications call for a narrow pitch (or narrow dimensions) between the lead terminals such that a lead guide cannot be arranged between one lead terminal and the next.

[0064] As described above, according to the embodiment, the lead terminal 10 can be shortened, and further, burrs on the package 20 can be reduced.

[0065] 2. Variations Next, a semiconductor device 1 according to a modification of the embodiment will be described. In the modification, the shape of the side surfaces 20e and 20f of the package 20 differs from the shape shown in Fig. 4. In the modification, differences from the above-described embodiment will be mainly described.

[0066] Fig. 22 is a side view of the semiconductor device 1 of the modified example as seen from the X direction. Fig. 23 is a side view of the semiconductor device 1 of the modified example as seen from the Y direction.

[0067] 23, the side surface 20e of the package 20 has a surface 20ea and a surface 20eb. The surfaces 20ea and 20eb form a "L" shape between the upper surface 20a and the lower surface 20b of the package 20.

[0068] Similarly, the side surface 20f of the package 20 has a surface 20fa and a surface 20fb. The surfaces 20fa and 20fb form a "L" shape between the top surface 20a and the bottom surface 20b of the package 20. The side surfaces 20c and 20d of the package 20 are the same as those in the above-described embodiment.

[0069] Next, details of the side surfaces 20e and 20f of the package 20 will be described. Fig. 24 is an enlarged view of a portion C in the semiconductor device 1 shown in Fig. 23, showing the detailed structure of the side surface 20f. Note that the structure of the side surface 20e is the same as that of the side surface 20f, and therefore will not be described again.

[0070] As described above, the side surface 20f of the package 20 has the surface 20fa and the surface 20fb. The surface 20fa is continuous with the top surface 20a of the package 20 and is provided in a first oblique direction with respect to the top surface 20a of the package 20. The surface 20fb is continuous with the surface 20fa and is provided in a second oblique direction with respect to the top surface 20a of the package 20 that is different from the first oblique direction.

[0071] In other words, when viewed from the Y direction (or from the side surface 20c side), the surface 20fa is provided in a diagonal direction downward to the right with respect to the top surface 20a of the package 20, from the top surface 20a of the package 20 to the position (or height) of the top surface of the lead terminal 10 (or burr 20g). The surface 20fb is provided in a diagonal direction upward to the right with respect to the top surface 20a of the package 20, from the position of the top surface of the lead terminal 10 to the bottom surface 20b of the package 20.

[0072] Similarly, when viewed from the Y direction (or from the side surface 20c side), the surface 20ea extends from the top surface 20a of the package 20 to the position (or height) of the top surface of the lead terminal 10 (or burr 20g) in a diagonal direction that rises to the right relative to the top surface 20a of the package 20. The surface 20eb extends from the position of the top surface of the lead terminal 10 to the bottom surface 20b of the package 20 in a diagonal direction that falls to the right relative to the top surface 20a of the package 20.

[0073] 3.Other In the above-described embodiment and modified examples, the semiconductor chip 30 includes a MOS field effect transistor (i.e., a MOSFET), but the semiconductor chip 30 may include an active element such as an IGBT (Insulated Gate Bipolar Transistor) or a diode. The number and shapes of the lead terminals and members included in the semiconductor device 1 can be changed as appropriate depending on the elements included in the semiconductor chip 30.

[0074] In this specification, the term "connected" refers to a direct connection between multiple components (or elements) or an electrical connection between multiple components, and does not exclude, for example, the presence of another component between the two connected components.

[0075] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0076] 1...semiconductor device, 10...lead terminal (or lead frame), 10a...lead terminal, 10b...lead terminal, 10c...lead terminal, 11...conductor layer, 12...conductor layer, 20...package, 20a...upper surface, 20b...lower surface, 20c...side surface, 20ca...surface, 20cb...surface (or upper surface), 20cc...surface, 20d...side surface, 20e...side surface, 20ea...surface, 20eb...surface, 20f...side surface, 20fa...surface, 20fb...surface, 20g...burrs, 30...semiconductor chip, 30a...drain electrode layer, 30b...source electrode layer, 30c...gate electrode layer, 31a...bonding layer, 31b...bonding layer, 31c...bonding layer, 32...bonding layer, 33...bonding layer, 40a...lead guide, 100...lead frame.

Claims

1. A lead frame; a semiconductor chip provided above the lead frame; a first lead terminal electrically connected to the semiconductor chip; a package including the semiconductor chip, a portion of the lead frame, and a portion of the first lead terminal; Equipped with the package has an upper surface provided above the semiconductor chip, a lower surface provided below the semiconductor chip, a first side surface provided between the upper surface and the lower surface and from which the first lead terminals protrude, and a second side surface provided between the upper surface and the lower surface and from which the first lead terminals do not protrude, the first side surface has a first surface, a second surface, and a third surface; the first surface is continuous with the top surface of the package and is provided in a diagonal direction with respect to the top surface of the package, the second surface is continuous with the first surface and is provided in a direction parallel to the top surface of the package, the third surface is continuous with the second surface and is provided in a direction perpendicular to the top surface of the package, The second side surface is provided obliquely with respect to the top surface of the package.

2. the package has a first portion protruding from the first side surface and disposed adjacent to the first lead terminal; The semiconductor device according to claim 1 , wherein a top surface of the first portion corresponds to the second surface, and a side surface of the first portion corresponds to the third surface.

3. 2. The semiconductor device according to claim 1, wherein the second surface of the first side surface is positioned at the same position as the upper surface of the first lead terminal in a direction perpendicular to the upper surface of the package.

4. 2. The semiconductor device according to claim 1, wherein the distance from the lower surface of the package to the second surface of the first side surface is equal to the distance from the lower surface of the package to the upper surface of the first lead terminal.

5. further comprising a plurality of lead terminals including the first lead terminal; The plurality of lead terminals are arranged at intervals on the first side surface, The semiconductor device according to claim 2 , wherein the first portion is provided between the plurality of lead terminals.

6. a second lead terminal electrically connected to the semiconductor chip; the package has a third side face provided between the upper surface and the lower surface of the package and from which the second lead terminal protrudes, and a fourth side face provided between the upper surface and the lower surface and from which the second lead terminal does not protrude, the third side surface has a fourth surface, a fifth surface, and a sixth surface; the fourth surface is continuous with the top surface of the package and is provided in a diagonal direction with respect to the top surface of the package, the fifth surface is continuous with the fourth surface and is provided in a direction parallel to the top surface of the package, the sixth surface is continuous with the fifth surface and is provided in a direction perpendicular to the top surface of the package, The semiconductor device according to claim 1 , wherein the fourth side surface is provided in an oblique direction with respect to the top surface of the package.

7. The semiconductor device according to claim 6 , wherein the third side surface is disposed so as to face the first side surface, and the fourth side surface is disposed so as to face the third side surface.

8. 2. The semiconductor device according to claim 1, wherein the package seals the semiconductor chip on the lead frame.

9. The semiconductor device according to claim 2 , wherein the package and the first portion of the package include a resin.

10. The second side surface is a first oblique direction with respect to the top surface of the package, the first oblique direction being perpendicular to the top surface of the package and extending from the top surface of the package to a position of the top surface of the first portion; 3. The semiconductor device according to claim 2, wherein the first portion is provided from the position of the upper surface of the first portion to the lower surface of the package in a second oblique direction different from the first oblique direction with respect to the upper surface of the package.

11. placing a semiconductor chip above a lead frame; providing a conductive layer connecting the lead frame and the semiconductor chip; forming a package including the semiconductor chip and the conductive layer using a mold; Equipped with In the step of forming the package, the package is formed to have an upper surface above the semiconductor chip, a lower surface below the semiconductor chip, a first side surface between the upper surface and the lower surface from which the lead frame protrudes, and a second side surface between the upper surface and the lower surface from which the lead frame does not protrude, A method for manufacturing a semiconductor device in which, when forming the package, a part of the mold is placed on the second side of the package and a part of the mold is not placed on the first side of the package.

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